1 /*
2 * Hardware modules present on the DRA7xx chips
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley
7 * Benoit Cousson
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
20 #include <linux/io.h>
21 #include <linux/platform_data/gpio-omap.h>
22 #include <linux/power/smartreflex.h>
23 #include <linux/i2c-omap.h>
25 #include <linux/omap-dma.h>
26 #include <linux/platform_data/spi-omap2-mcspi.h>
27 #include <linux/platform_data/asoc-ti-mcbsp.h>
28 #include <linux/platform_data/iommu-omap.h>
29 #include <plat/dmtimer.h>
31 #include "omap_hwmod.h"
32 #include "omap_hwmod_common_data.h"
33 #include "cm1_7xx.h"
34 #include "cm2_7xx.h"
35 #include "prm7xx.h"
36 #include "i2c.h"
37 #include "mmc.h"
38 #include "wd_timer.h"
39 #include "soc.h"
41 /* Base offset for all DRA7XX interrupts external to MPUSS */
42 #define DRA7XX_IRQ_GIC_START 32
44 /* Base offset for all DRA7XX dma requests */
45 #define DRA7XX_DMA_REQ_START 1
48 /*
49 * IP blocks
50 */
52 /*
53 * 'l3' class
54 * instance(s): l3_instr, l3_main_1, l3_main_2
55 */
56 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
57 .name = "l3",
58 };
60 /* l3_instr */
61 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
62 .name = "l3_instr",
63 .class = &dra7xx_l3_hwmod_class,
64 .clkdm_name = "l3instr_clkdm",
65 .prcm = {
66 .omap4 = {
67 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
68 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
69 .modulemode = MODULEMODE_HWCTRL,
70 },
71 },
72 };
74 /* l3_main_1 */
75 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
76 .name = "l3_main_1",
77 .class = &dra7xx_l3_hwmod_class,
78 .clkdm_name = "l3main1_clkdm",
79 .prcm = {
80 .omap4 = {
81 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
82 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
83 },
84 },
85 };
87 /* l3_main_2 */
88 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
89 .name = "l3_main_2",
90 .class = &dra7xx_l3_hwmod_class,
91 .clkdm_name = "l3instr_clkdm",
92 .prcm = {
93 .omap4 = {
94 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
95 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
96 .modulemode = MODULEMODE_HWCTRL,
97 },
98 },
99 };
101 /*
102 * 'l4' class
103 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
104 */
105 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
106 .name = "l4",
107 };
109 /* l4_cfg */
110 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
111 .name = "l4_cfg",
112 .class = &dra7xx_l4_hwmod_class,
113 .clkdm_name = "l4cfg_clkdm",
114 .prcm = {
115 .omap4 = {
116 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
117 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
118 },
119 },
120 };
122 /* l4_per1 */
123 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
124 .name = "l4_per1",
125 .class = &dra7xx_l4_hwmod_class,
126 .clkdm_name = "l4per_clkdm",
127 .prcm = {
128 .omap4 = {
129 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
130 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
131 },
132 },
133 };
135 /* l4_per2 */
136 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
137 .name = "l4_per2",
138 .class = &dra7xx_l4_hwmod_class,
139 .clkdm_name = "l4per2_clkdm",
140 .prcm = {
141 .omap4 = {
142 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
143 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
144 },
145 },
146 };
148 /* l4_per3 */
149 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
150 .name = "l4_per3",
151 .class = &dra7xx_l4_hwmod_class,
152 .clkdm_name = "l4per3_clkdm",
153 .prcm = {
154 .omap4 = {
155 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
156 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
157 },
158 },
159 };
161 /* l4_wkup */
162 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
163 .name = "l4_wkup",
164 .class = &dra7xx_l4_hwmod_class,
165 .clkdm_name = "wkupaon_clkdm",
166 .prcm = {
167 .omap4 = {
168 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
169 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
170 },
171 },
172 };
174 /*
175 * 'atl' class
176 *
177 */
179 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
180 .name = "atl",
181 };
183 /* atl */
184 static struct omap_hwmod dra7xx_atl_hwmod = {
185 .name = "atl",
186 .class = &dra7xx_atl_hwmod_class,
187 .clkdm_name = "atl_clkdm",
188 .main_clk = "atl_gfclk_mux",
189 .prcm = {
190 .omap4 = {
191 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
192 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
193 .modulemode = MODULEMODE_SWCTRL,
194 },
195 },
196 };
198 /*
199 * 'bb2d' class
200 *
201 */
203 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
204 .name = "bb2d",
205 };
207 /* bb2d */
208 static struct omap_hwmod dra7xx_bb2d_hwmod = {
209 .name = "bb2d",
210 .class = &dra7xx_bb2d_hwmod_class,
211 .clkdm_name = "dss_clkdm",
212 .main_clk = "dpll_core_h24x2_ck",
213 .prcm = {
214 .omap4 = {
215 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
216 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
217 .modulemode = MODULEMODE_SWCTRL,
218 },
219 },
220 };
222 /*
223 * 'counter' class
224 *
225 */
227 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
228 .rev_offs = 0x0000,
229 .sysc_offs = 0x0010,
230 .sysc_flags = SYSC_HAS_SIDLEMODE,
231 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
232 SIDLE_SMART_WKUP),
233 .sysc_fields = &omap_hwmod_sysc_type1,
234 };
236 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
237 .name = "counter",
238 .sysc = &dra7xx_counter_sysc,
239 };
241 /* counter_32k */
242 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
243 .name = "counter_32k",
244 .class = &dra7xx_counter_hwmod_class,
245 .clkdm_name = "wkupaon_clkdm",
246 .flags = HWMOD_SWSUP_SIDLE,
247 .main_clk = "wkupaon_iclk_mux",
248 .prcm = {
249 .omap4 = {
250 .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
251 .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
252 },
253 },
254 };
256 /*
257 * 'ctrl_module' class
258 *
259 */
261 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
262 .name = "ctrl_module",
263 };
265 /* ctrl_module_wkup */
266 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
267 .name = "ctrl_module_wkup",
268 .class = &dra7xx_ctrl_module_hwmod_class,
269 .clkdm_name = "wkupaon_clkdm",
270 .prcm = {
271 .omap4 = {
272 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
273 },
274 },
275 };
277 /*
278 * 'dcan' class
279 *
280 */
282 static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
283 .name = "dcan",
284 };
286 /* dcan1 */
287 static struct omap_hwmod dra7xx_dcan1_hwmod = {
288 .name = "dcan1",
289 .class = &dra7xx_dcan_hwmod_class,
290 .clkdm_name = "wkupaon_clkdm",
291 .main_clk = "dcan1_sys_clk_mux",
292 .prcm = {
293 .omap4 = {
294 .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
295 .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
296 .modulemode = MODULEMODE_SWCTRL,
297 },
298 },
299 };
301 /* dcan2 */
302 static struct omap_hwmod dra7xx_dcan2_hwmod = {
303 .name = "dcan2",
304 .class = &dra7xx_dcan_hwmod_class,
305 .clkdm_name = "l4per2_clkdm",
306 .main_clk = "sys_clkin1",
307 .prcm = {
308 .omap4 = {
309 .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
310 .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
311 .modulemode = MODULEMODE_SWCTRL,
312 },
313 },
314 };
316 /*
317 * 'dma' class
318 *
319 */
321 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
322 .rev_offs = 0x0000,
323 .sysc_offs = 0x002c,
324 .syss_offs = 0x0028,
325 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
326 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
327 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
328 SYSS_HAS_RESET_STATUS),
329 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
330 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
331 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
332 .sysc_fields = &omap_hwmod_sysc_type1,
333 };
335 static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
336 .name = "dma",
337 .sysc = &dra7xx_dma_sysc,
338 };
340 /* dma dev_attr */
341 static struct omap_dma_dev_attr dma_dev_attr = {
342 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
343 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
344 .lch_count = 32,
345 };
347 /* dma_system */
348 static struct omap_hwmod dra7xx_dma_system_hwmod = {
349 .name = "dma_system",
350 .class = &dra7xx_dma_hwmod_class,
351 .clkdm_name = "dma_clkdm",
352 .main_clk = "l3_iclk_div",
353 .prcm = {
354 .omap4 = {
355 .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
356 .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
357 },
358 },
359 .dev_attr = &dma_dev_attr,
360 };
362 /*
363 * 'dsp' class
364 * dsp sub-system
365 */
367 static struct omap_hwmod_class dra7xx_dsp_hwmod_class = {
368 .name = "dsp",
369 };
371 static struct omap_hwmod_rst_info dra7xx_dsp_resets[] = {
372 { .name = "dsp", .rst_shift = 0 },
373 };
375 /* dsp1 processor */
376 static struct omap_hwmod dra7xx_dsp1_hwmod = {
377 .name = "dsp1",
378 .class = &dra7xx_dsp_hwmod_class,
379 .clkdm_name = "dsp1_clkdm",
380 .rst_lines = dra7xx_dsp_resets,
381 .rst_lines_cnt = ARRAY_SIZE(dra7xx_dsp_resets),
382 .main_clk = "dpll_dsp_m2_ck",
383 .prcm = {
384 .omap4 = {
385 .clkctrl_offs = DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET,
386 .rstctrl_offs = DRA7XX_RM_DSP1_RSTCTRL_OFFSET,
387 .context_offs = DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET,
388 },
389 },
390 };
392 /* dsp2 processor */
393 static struct omap_hwmod dra7xx_dsp2_hwmod = {
394 .name = "dsp2",
395 .class = &dra7xx_dsp_hwmod_class,
396 .clkdm_name = "dsp2_clkdm",
397 .rst_lines = dra7xx_dsp_resets,
398 .rst_lines_cnt = ARRAY_SIZE(dra7xx_dsp_resets),
399 .main_clk = "dpll_dsp_m2_ck",
400 .prcm = {
401 .omap4 = {
402 .clkctrl_offs = DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET,
403 .rstctrl_offs = DRA7XX_RM_DSP2_RSTCTRL_OFFSET,
404 .context_offs = DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET,
405 },
406 },
407 };
409 /*
410 * 'dss' class
411 *
412 */
414 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
415 .rev_offs = 0x0000,
416 .syss_offs = 0x0014,
417 .sysc_flags = SYSS_HAS_RESET_STATUS,
418 };
420 static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
421 .name = "dss",
422 .sysc = &dra7xx_dss_sysc,
423 .reset = omap_dss_reset,
424 };
426 /* dss */
427 static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
428 { .dma_req = 75 + DRA7XX_DMA_REQ_START },
429 { .dma_req = -1 }
430 };
432 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
433 { .role = "dss_clk", .clk = "dss_dss_clk" },
434 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
435 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
436 { .role = "video2_clk", .clk = "dss_video2_clk" },
437 { .role = "video1_clk", .clk = "dss_video1_clk" },
438 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
439 };
441 static struct omap_hwmod dra7xx_dss_hwmod = {
442 .name = "dss_core",
443 .class = &dra7xx_dss_hwmod_class,
444 .clkdm_name = "dss_clkdm",
445 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
446 .sdma_reqs = dra7xx_dss_sdma_reqs,
447 .main_clk = "dss_dss_clk",
448 .prcm = {
449 .omap4 = {
450 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
451 .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
452 .modulemode = MODULEMODE_SWCTRL,
453 },
454 },
455 .opt_clks = dss_opt_clks,
456 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
457 };
459 /*
460 * 'dispc' class
461 * display controller
462 */
464 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
465 .rev_offs = 0x0000,
466 .sysc_offs = 0x0010,
467 .syss_offs = 0x0014,
468 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
469 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
470 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
471 SYSS_HAS_RESET_STATUS),
472 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
473 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
474 .sysc_fields = &omap_hwmod_sysc_type1,
475 };
477 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
478 .name = "dispc",
479 .sysc = &dra7xx_dispc_sysc,
480 };
482 /* dss_dispc */
483 /* dss_dispc dev_attr */
484 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
485 .has_framedonetv_irq = 1,
486 .manager_count = 4,
487 };
489 static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
490 .name = "dss_dispc",
491 .class = &dra7xx_dispc_hwmod_class,
492 .clkdm_name = "dss_clkdm",
493 .main_clk = "dss_dss_clk",
494 .prcm = {
495 .omap4 = {
496 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
497 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
498 },
499 },
500 .dev_attr = &dss_dispc_dev_attr,
501 };
503 /*
504 * 'hdmi' class
505 * hdmi controller
506 */
508 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
509 .rev_offs = 0x0000,
510 .sysc_offs = 0x0010,
511 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
512 SYSC_HAS_SOFTRESET),
513 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
514 SIDLE_SMART_WKUP),
515 .sysc_fields = &omap_hwmod_sysc_type2,
516 };
518 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
519 .name = "hdmi",
520 .sysc = &dra7xx_hdmi_sysc,
521 };
523 /* dss_hdmi */
525 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
526 { .role = "sys_clk", .clk = "dss_hdmi_clk" },
527 };
529 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
530 .name = "dss_hdmi",
531 .class = &dra7xx_hdmi_hwmod_class,
532 .clkdm_name = "dss_clkdm",
533 .main_clk = "dss_48mhz_clk",
534 .prcm = {
535 .omap4 = {
536 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
537 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
538 },
539 },
540 .opt_clks = dss_hdmi_opt_clks,
541 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
542 };
544 /* AES (the 'P' (public) device) */
545 static struct omap_hwmod_class_sysconfig dra7xx_aes_sysc = {
546 .rev_offs = 0x0080,
547 .sysc_offs = 0x0084,
548 .syss_offs = 0x0088,
549 .sysc_flags = SYSS_HAS_RESET_STATUS,
550 };
552 static struct omap_hwmod_class dra7xx_aes_hwmod_class = {
553 .name = "aes",
554 .sysc = &dra7xx_aes_sysc,
555 .rev = 2,
556 };
558 /* AES */
559 static struct omap_hwmod dra7xx_aes_hwmod = {
560 .name = "aes",
561 .class = &dra7xx_aes_hwmod_class,
562 .clkdm_name = "l4sec_clkdm",
563 .main_clk = "l3_iclk_div",
564 .prcm = {
565 .omap4 = {
566 .clkctrl_offs = DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET,
567 .context_offs = DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET,
568 .modulemode = MODULEMODE_HWCTRL,
569 },
570 },
571 };
573 /* sha0 HIB2 (the 'P' (public) device) */
574 static struct omap_hwmod_class_sysconfig dra7xx_sha0_sysc = {
575 .rev_offs = 0x100,
576 .sysc_offs = 0x110,
577 .syss_offs = 0x114,
578 .sysc_flags = SYSS_HAS_RESET_STATUS,
579 };
581 static struct omap_hwmod_class dra7xx_sha0_hwmod_class = {
582 .name = "sham",
583 .sysc = &dra7xx_sha0_sysc,
584 .rev = 2,
585 };
587 struct omap_hwmod dra7xx_sha0_hwmod = {
588 .name = "sham",
589 .class = &dra7xx_sha0_hwmod_class,
590 .clkdm_name = "l4sec_clkdm",
591 .main_clk = "l3_iclk_div",
592 .prcm = {
593 .omap4 = {
594 .clkctrl_offs = DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
595 .context_offs = DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
596 .modulemode = MODULEMODE_HWCTRL,
597 },
598 },
599 };
601 /*
602 * 'elm' class
603 *
604 */
606 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
607 .rev_offs = 0x0000,
608 .sysc_offs = 0x0010,
609 .syss_offs = 0x0014,
610 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
611 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
612 SYSS_HAS_RESET_STATUS),
613 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
614 SIDLE_SMART_WKUP),
615 .sysc_fields = &omap_hwmod_sysc_type1,
616 };
618 static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
619 .name = "elm",
620 .sysc = &dra7xx_elm_sysc,
621 };
623 /* elm */
625 static struct omap_hwmod dra7xx_elm_hwmod = {
626 .name = "elm",
627 .class = &dra7xx_elm_hwmod_class,
628 .clkdm_name = "l4per_clkdm",
629 .main_clk = "l3_iclk_div",
630 .prcm = {
631 .omap4 = {
632 .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
633 .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
634 },
635 },
636 };
638 /*
639 * 'gpio' class
640 *
641 */
643 static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
644 .rev_offs = 0x0000,
645 .sysc_offs = 0x0010,
646 .syss_offs = 0x0114,
647 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
648 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
649 SYSS_HAS_RESET_STATUS),
650 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
651 SIDLE_SMART_WKUP),
652 .sysc_fields = &omap_hwmod_sysc_type1,
653 };
655 static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
656 .name = "gpio",
657 .sysc = &dra7xx_gpio_sysc,
658 .rev = 2,
659 };
661 /* gpio dev_attr */
662 static struct omap_gpio_dev_attr gpio_dev_attr = {
663 .bank_width = 32,
664 .dbck_flag = true,
665 };
667 /* gpio1 */
668 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
669 { .role = "dbclk", .clk = "gpio1_dbclk" },
670 };
672 static struct omap_hwmod dra7xx_gpio1_hwmod = {
673 .name = "gpio1",
674 .class = &dra7xx_gpio_hwmod_class,
675 .clkdm_name = "wkupaon_clkdm",
676 .main_clk = "wkupaon_iclk_mux",
677 .prcm = {
678 .omap4 = {
679 .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
680 .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
681 .modulemode = MODULEMODE_HWCTRL,
682 },
683 },
684 .opt_clks = gpio1_opt_clks,
685 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
686 .dev_attr = &gpio_dev_attr,
687 };
689 /* gpio2 */
690 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
691 { .role = "dbclk", .clk = "gpio2_dbclk" },
692 };
694 static struct omap_hwmod dra7xx_gpio2_hwmod = {
695 .name = "gpio2",
696 .class = &dra7xx_gpio_hwmod_class,
697 .clkdm_name = "l4per_clkdm",
698 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
699 .main_clk = "l3_iclk_div",
700 .prcm = {
701 .omap4 = {
702 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
703 .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
704 .modulemode = MODULEMODE_HWCTRL,
705 },
706 },
707 .opt_clks = gpio2_opt_clks,
708 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
709 .dev_attr = &gpio_dev_attr,
710 };
712 /* gpio3 */
713 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
714 { .role = "dbclk", .clk = "gpio3_dbclk" },
715 };
717 static struct omap_hwmod dra7xx_gpio3_hwmod = {
718 .name = "gpio3",
719 .class = &dra7xx_gpio_hwmod_class,
720 .clkdm_name = "l4per_clkdm",
721 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
722 .main_clk = "l3_iclk_div",
723 .prcm = {
724 .omap4 = {
725 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
726 .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
727 .modulemode = MODULEMODE_HWCTRL,
728 },
729 },
730 .opt_clks = gpio3_opt_clks,
731 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
732 .dev_attr = &gpio_dev_attr,
733 };
735 /* gpio4 */
736 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
737 { .role = "dbclk", .clk = "gpio4_dbclk" },
738 };
740 static struct omap_hwmod dra7xx_gpio4_hwmod = {
741 .name = "gpio4",
742 .class = &dra7xx_gpio_hwmod_class,
743 .clkdm_name = "l4per_clkdm",
744 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
745 .main_clk = "l3_iclk_div",
746 .prcm = {
747 .omap4 = {
748 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
749 .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
750 .modulemode = MODULEMODE_HWCTRL,
751 },
752 },
753 .opt_clks = gpio4_opt_clks,
754 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
755 .dev_attr = &gpio_dev_attr,
756 };
758 /* gpio5 */
759 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
760 { .role = "dbclk", .clk = "gpio5_dbclk" },
761 };
763 static struct omap_hwmod dra7xx_gpio5_hwmod = {
764 .name = "gpio5",
765 .class = &dra7xx_gpio_hwmod_class,
766 .clkdm_name = "l4per_clkdm",
767 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
768 .main_clk = "l3_iclk_div",
769 .prcm = {
770 .omap4 = {
771 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
772 .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
773 .modulemode = MODULEMODE_HWCTRL,
774 },
775 },
776 .opt_clks = gpio5_opt_clks,
777 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
778 .dev_attr = &gpio_dev_attr,
779 };
781 /* gpio6 */
782 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
783 { .role = "dbclk", .clk = "gpio6_dbclk" },
784 };
786 static struct omap_hwmod dra7xx_gpio6_hwmod = {
787 .name = "gpio6",
788 .class = &dra7xx_gpio_hwmod_class,
789 .clkdm_name = "l4per_clkdm",
790 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
791 .main_clk = "l3_iclk_div",
792 .prcm = {
793 .omap4 = {
794 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
795 .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
796 .modulemode = MODULEMODE_HWCTRL,
797 },
798 },
799 .opt_clks = gpio6_opt_clks,
800 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
801 .dev_attr = &gpio_dev_attr,
802 };
804 /* gpio7 */
805 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
806 { .role = "dbclk", .clk = "gpio7_dbclk" },
807 };
809 static struct omap_hwmod dra7xx_gpio7_hwmod = {
810 .name = "gpio7",
811 .class = &dra7xx_gpio_hwmod_class,
812 .clkdm_name = "l4per_clkdm",
813 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
814 .main_clk = "l3_iclk_div",
815 .prcm = {
816 .omap4 = {
817 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
818 .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
819 .modulemode = MODULEMODE_HWCTRL,
820 },
821 },
822 .opt_clks = gpio7_opt_clks,
823 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
824 .dev_attr = &gpio_dev_attr,
825 };
827 /* gpio8 */
828 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
829 { .role = "dbclk", .clk = "gpio8_dbclk" },
830 };
832 static struct omap_hwmod dra7xx_gpio8_hwmod = {
833 .name = "gpio8",
834 .class = &dra7xx_gpio_hwmod_class,
835 .clkdm_name = "l4per_clkdm",
836 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
837 .main_clk = "l3_iclk_div",
838 .prcm = {
839 .omap4 = {
840 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
841 .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
842 .modulemode = MODULEMODE_HWCTRL,
843 },
844 },
845 .opt_clks = gpio8_opt_clks,
846 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
847 .dev_attr = &gpio_dev_attr,
848 };
850 /*
851 * 'gpmc' class
852 *
853 */
855 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
856 .rev_offs = 0x0000,
857 .sysc_offs = 0x0010,
858 .syss_offs = 0x0014,
859 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
860 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
861 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
862 SIDLE_SMART_WKUP),
863 .sysc_fields = &omap_hwmod_sysc_type1,
864 };
866 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
867 .name = "gpmc",
868 .sysc = &dra7xx_gpmc_sysc,
869 };
871 /* gpmc */
873 static struct omap_hwmod dra7xx_gpmc_hwmod = {
874 .name = "gpmc",
875 .class = &dra7xx_gpmc_hwmod_class,
876 .clkdm_name = "l3main1_clkdm",
877 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
878 .main_clk = "l3_iclk_div",
879 .prcm = {
880 .omap4 = {
881 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
882 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
883 .modulemode = MODULEMODE_HWCTRL,
884 },
885 },
886 };
888 /*
889 * 'hdq1w' class
890 *
891 */
893 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
894 .rev_offs = 0x0000,
895 .sysc_offs = 0x0014,
896 .syss_offs = 0x0018,
897 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
898 SYSS_HAS_RESET_STATUS),
899 .sysc_fields = &omap_hwmod_sysc_type1,
900 };
902 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
903 .name = "hdq1w",
904 .sysc = &dra7xx_hdq1w_sysc,
905 };
907 /* hdq1w */
909 static struct omap_hwmod dra7xx_hdq1w_hwmod = {
910 .name = "hdq1w",
911 .class = &dra7xx_hdq1w_hwmod_class,
912 .clkdm_name = "l4per_clkdm",
913 .flags = HWMOD_INIT_NO_RESET,
914 .main_clk = "func_12m_fclk",
915 .prcm = {
916 .omap4 = {
917 .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
918 .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
919 .modulemode = MODULEMODE_SWCTRL,
920 },
921 },
922 };
924 /*
925 * 'i2c' class
926 *
927 */
929 static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
930 .sysc_offs = 0x0010,
931 .syss_offs = 0x0090,
932 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
933 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
934 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
935 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
936 SIDLE_SMART_WKUP),
937 .clockact = CLOCKACT_TEST_ICLK,
938 .sysc_fields = &omap_hwmod_sysc_type1,
939 };
941 static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
942 .name = "i2c",
943 .sysc = &dra7xx_i2c_sysc,
944 .reset = &omap_i2c_reset,
945 .rev = OMAP_I2C_IP_VERSION_2,
946 };
948 /* i2c dev_attr */
949 static struct omap_i2c_dev_attr i2c_dev_attr = {
950 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
951 };
953 /* i2c1 */
954 static struct omap_hwmod dra7xx_i2c1_hwmod = {
955 .name = "i2c1",
956 .class = &dra7xx_i2c_hwmod_class,
957 .clkdm_name = "l4per_clkdm",
958 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
959 .main_clk = "func_96m_fclk",
960 .prcm = {
961 .omap4 = {
962 .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
963 .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
964 .modulemode = MODULEMODE_SWCTRL,
965 },
966 },
967 .dev_attr = &i2c_dev_attr,
968 };
970 /* i2c2 */
971 static struct omap_hwmod dra7xx_i2c2_hwmod = {
972 .name = "i2c2",
973 .class = &dra7xx_i2c_hwmod_class,
974 .clkdm_name = "l4per_clkdm",
975 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
976 .main_clk = "func_96m_fclk",
977 .prcm = {
978 .omap4 = {
979 .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
980 .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
981 .modulemode = MODULEMODE_SWCTRL,
982 },
983 },
984 .dev_attr = &i2c_dev_attr,
985 };
987 /* i2c3 */
988 static struct omap_hwmod dra7xx_i2c3_hwmod = {
989 .name = "i2c3",
990 .class = &dra7xx_i2c_hwmod_class,
991 .clkdm_name = "l4per_clkdm",
992 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
993 .main_clk = "func_96m_fclk",
994 .prcm = {
995 .omap4 = {
996 .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
997 .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
998 .modulemode = MODULEMODE_SWCTRL,
999 },
1000 },
1001 .dev_attr = &i2c_dev_attr,
1002 };
1004 /* i2c4 */
1005 static struct omap_hwmod dra7xx_i2c4_hwmod = {
1006 .name = "i2c4",
1007 .class = &dra7xx_i2c_hwmod_class,
1008 .clkdm_name = "l4per_clkdm",
1009 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1010 .main_clk = "func_96m_fclk",
1011 .prcm = {
1012 .omap4 = {
1013 .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1014 .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
1015 .modulemode = MODULEMODE_SWCTRL,
1016 },
1017 },
1018 .dev_attr = &i2c_dev_attr,
1019 };
1021 /* i2c5 */
1022 static struct omap_hwmod dra7xx_i2c5_hwmod = {
1023 .name = "i2c5",
1024 .class = &dra7xx_i2c_hwmod_class,
1025 .clkdm_name = "ipu_clkdm",
1026 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1027 .main_clk = "func_96m_fclk",
1028 .prcm = {
1029 .omap4 = {
1030 .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
1031 .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
1032 .modulemode = MODULEMODE_SWCTRL,
1033 },
1034 },
1035 .dev_attr = &i2c_dev_attr,
1036 };
1038 /*
1039 * 'ipu' class
1040 * imaging processor unit
1041 */
1043 static struct omap_hwmod_class dra7xx_ipu_hwmod_class = {
1044 .name = "ipu",
1045 };
1047 static struct omap_hwmod_rst_info dra7xx_ipu_resets[] = {
1048 { .name = "cpu0", .rst_shift = 0 },
1049 { .name = "cpu1", .rst_shift = 1 },
1050 };
1052 /* ipu1 processor */
1053 static struct omap_hwmod dra7xx_ipu1_hwmod = {
1054 .name = "ipu1",
1055 .class = &dra7xx_ipu_hwmod_class,
1056 .clkdm_name = "ipu1_clkdm",
1057 .rst_lines = dra7xx_ipu_resets,
1058 .rst_lines_cnt = ARRAY_SIZE(dra7xx_ipu_resets),
1059 .main_clk = "ipu1_gfclk_mux",
1060 .prcm = {
1061 .omap4 = {
1062 .clkctrl_offs = DRA7XX_CM_IPU1_IPU1_CLKCTRL_OFFSET,
1063 .rstctrl_offs = DRA7XX_RM_IPU1_RSTCTRL_OFFSET,
1064 .context_offs = DRA7XX_RM_IPU1_IPU1_CONTEXT_OFFSET,
1065 },
1066 },
1067 };
1069 /* ipu2 processor */
1070 static struct omap_hwmod dra7xx_ipu2_hwmod = {
1071 .name = "ipu2",
1072 .class = &dra7xx_ipu_hwmod_class,
1073 .clkdm_name = "ipu2_clkdm",
1074 .rst_lines = dra7xx_ipu_resets,
1075 .rst_lines_cnt = ARRAY_SIZE(dra7xx_ipu_resets),
1076 .main_clk = "dpll_core_h22x2_ck",
1077 .prcm = {
1078 .omap4 = {
1079 .clkctrl_offs = DRA7XX_CM_IPU2_IPU2_CLKCTRL_OFFSET,
1080 .rstctrl_offs = DRA7XX_RM_IPU2_RSTCTRL_OFFSET,
1081 .context_offs = DRA7XX_RM_IPU2_IPU2_CONTEXT_OFFSET,
1082 },
1083 },
1084 };
1086 /*
1087 * 'mailbox' class
1088 *
1089 */
1091 static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
1092 .rev_offs = 0x0000,
1093 .sysc_offs = 0x0010,
1094 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1095 SYSC_HAS_SOFTRESET),
1096 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1097 .sysc_fields = &omap_hwmod_sysc_type2,
1098 };
1100 static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
1101 .name = "mailbox",
1102 .sysc = &dra7xx_mailbox_sysc,
1103 };
1105 /* mailbox1 */
1106 static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1107 .name = "mailbox1",
1108 .class = &dra7xx_mailbox_hwmod_class,
1109 .clkdm_name = "l4cfg_clkdm",
1110 .prcm = {
1111 .omap4 = {
1112 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1113 .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1114 },
1115 },
1116 };
1118 /* mailbox2 */
1119 static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1120 .name = "mailbox2",
1121 .class = &dra7xx_mailbox_hwmod_class,
1122 .clkdm_name = "l4cfg_clkdm",
1123 .prcm = {
1124 .omap4 = {
1125 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1126 .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1127 },
1128 },
1129 };
1131 /* mailbox3 */
1132 static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1133 .name = "mailbox3",
1134 .class = &dra7xx_mailbox_hwmod_class,
1135 .clkdm_name = "l4cfg_clkdm",
1136 .prcm = {
1137 .omap4 = {
1138 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1139 .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1140 },
1141 },
1142 };
1144 /* mailbox4 */
1145 static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1146 .name = "mailbox4",
1147 .class = &dra7xx_mailbox_hwmod_class,
1148 .clkdm_name = "l4cfg_clkdm",
1149 .prcm = {
1150 .omap4 = {
1151 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1152 .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1153 },
1154 },
1155 };
1157 /* mailbox5 */
1158 static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1159 .name = "mailbox5",
1160 .class = &dra7xx_mailbox_hwmod_class,
1161 .clkdm_name = "l4cfg_clkdm",
1162 .prcm = {
1163 .omap4 = {
1164 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1165 .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1166 },
1167 },
1168 };
1170 /* mailbox6 */
1171 static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1172 .name = "mailbox6",
1173 .class = &dra7xx_mailbox_hwmod_class,
1174 .clkdm_name = "l4cfg_clkdm",
1175 .prcm = {
1176 .omap4 = {
1177 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1178 .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1179 },
1180 },
1181 };
1183 /* mailbox7 */
1184 static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1185 .name = "mailbox7",
1186 .class = &dra7xx_mailbox_hwmod_class,
1187 .clkdm_name = "l4cfg_clkdm",
1188 .prcm = {
1189 .omap4 = {
1190 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1191 .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1192 },
1193 },
1194 };
1196 /* mailbox8 */
1197 static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1198 .name = "mailbox8",
1199 .class = &dra7xx_mailbox_hwmod_class,
1200 .clkdm_name = "l4cfg_clkdm",
1201 .prcm = {
1202 .omap4 = {
1203 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1204 .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1205 },
1206 },
1207 };
1209 /* mailbox9 */
1210 static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1211 .name = "mailbox9",
1212 .class = &dra7xx_mailbox_hwmod_class,
1213 .clkdm_name = "l4cfg_clkdm",
1214 .prcm = {
1215 .omap4 = {
1216 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1217 .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1218 },
1219 },
1220 };
1222 /* mailbox10 */
1223 static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1224 .name = "mailbox10",
1225 .class = &dra7xx_mailbox_hwmod_class,
1226 .clkdm_name = "l4cfg_clkdm",
1227 .prcm = {
1228 .omap4 = {
1229 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1230 .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1231 },
1232 },
1233 };
1235 /* mailbox11 */
1236 static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1237 .name = "mailbox11",
1238 .class = &dra7xx_mailbox_hwmod_class,
1239 .clkdm_name = "l4cfg_clkdm",
1240 .prcm = {
1241 .omap4 = {
1242 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1243 .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1244 },
1245 },
1246 };
1248 /* mailbox12 */
1249 static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1250 .name = "mailbox12",
1251 .class = &dra7xx_mailbox_hwmod_class,
1252 .clkdm_name = "l4cfg_clkdm",
1253 .prcm = {
1254 .omap4 = {
1255 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1256 .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1257 },
1258 },
1259 };
1261 /* mailbox13 */
1262 static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1263 .name = "mailbox13",
1264 .class = &dra7xx_mailbox_hwmod_class,
1265 .clkdm_name = "l4cfg_clkdm",
1266 .prcm = {
1267 .omap4 = {
1268 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1269 .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1270 },
1271 },
1272 };
1274 /*
1275 * 'mcspi' class
1276 *
1277 */
1279 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1280 .rev_offs = 0x0000,
1281 .sysc_offs = 0x0010,
1282 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1283 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1284 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1285 SIDLE_SMART_WKUP),
1286 .sysc_fields = &omap_hwmod_sysc_type2,
1287 };
1289 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1290 .name = "mcspi",
1291 .sysc = &dra7xx_mcspi_sysc,
1292 .rev = OMAP4_MCSPI_REV,
1293 };
1295 /* mcspi1 */
1296 /* mcspi1 dev_attr */
1297 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1298 .num_chipselect = 4,
1299 };
1301 static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1302 .name = "mcspi1",
1303 .class = &dra7xx_mcspi_hwmod_class,
1304 .clkdm_name = "l4per_clkdm",
1305 .main_clk = "func_48m_fclk",
1306 .prcm = {
1307 .omap4 = {
1308 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1309 .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1310 .modulemode = MODULEMODE_SWCTRL,
1311 },
1312 },
1313 .dev_attr = &mcspi1_dev_attr,
1314 };
1316 /* mcspi2 */
1317 /* mcspi2 dev_attr */
1318 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1319 .num_chipselect = 2,
1320 };
1322 static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1323 .name = "mcspi2",
1324 .class = &dra7xx_mcspi_hwmod_class,
1325 .clkdm_name = "l4per_clkdm",
1326 .main_clk = "func_48m_fclk",
1327 .prcm = {
1328 .omap4 = {
1329 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1330 .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1331 .modulemode = MODULEMODE_SWCTRL,
1332 },
1333 },
1334 .dev_attr = &mcspi2_dev_attr,
1335 };
1337 /* mcspi3 */
1338 /* mcspi3 dev_attr */
1339 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1340 .num_chipselect = 2,
1341 };
1343 static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1344 .name = "mcspi3",
1345 .class = &dra7xx_mcspi_hwmod_class,
1346 .clkdm_name = "l4per_clkdm",
1347 .main_clk = "func_48m_fclk",
1348 .prcm = {
1349 .omap4 = {
1350 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1351 .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1352 .modulemode = MODULEMODE_SWCTRL,
1353 },
1354 },
1355 .dev_attr = &mcspi3_dev_attr,
1356 };
1358 /* mcspi4 */
1359 /* mcspi4 dev_attr */
1360 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1361 .num_chipselect = 1,
1362 };
1364 static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1365 .name = "mcspi4",
1366 .class = &dra7xx_mcspi_hwmod_class,
1367 .clkdm_name = "l4per_clkdm",
1368 .main_clk = "func_48m_fclk",
1369 .prcm = {
1370 .omap4 = {
1371 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1372 .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1373 .modulemode = MODULEMODE_SWCTRL,
1374 },
1375 },
1376 .dev_attr = &mcspi4_dev_attr,
1377 };
1379 /*
1380 * 'mmc' class
1381 *
1382 */
1384 static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1385 .rev_offs = 0x0000,
1386 .sysc_offs = 0x0010,
1387 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1388 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1389 SYSC_HAS_SOFTRESET),
1390 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1391 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1392 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1393 .sysc_fields = &omap_hwmod_sysc_type2,
1394 };
1396 static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1397 .name = "mmc",
1398 .sysc = &dra7xx_mmc_sysc,
1399 };
1401 /* mmc1 */
1402 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1403 { .role = "clk32k", .clk = "mmc1_clk32k" },
1404 };
1406 /* mmc1 dev_attr */
1407 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1408 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1409 };
1411 static struct omap_hwmod dra7xx_mmc1_hwmod = {
1412 .name = "mmc1",
1413 .class = &dra7xx_mmc_hwmod_class,
1414 .clkdm_name = "l3init_clkdm",
1415 .main_clk = "mmc1_fclk_div",
1416 .prcm = {
1417 .omap4 = {
1418 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1419 .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1420 .modulemode = MODULEMODE_SWCTRL,
1421 },
1422 },
1423 .opt_clks = mmc1_opt_clks,
1424 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1425 .dev_attr = &mmc1_dev_attr,
1426 };
1428 /* mmc2 */
1429 static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1430 { .role = "clk32k", .clk = "mmc2_clk32k" },
1431 };
1433 static struct omap_hwmod dra7xx_mmc2_hwmod = {
1434 .name = "mmc2",
1435 .class = &dra7xx_mmc_hwmod_class,
1436 .clkdm_name = "l3init_clkdm",
1437 .main_clk = "mmc2_fclk_div",
1438 .prcm = {
1439 .omap4 = {
1440 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1441 .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1442 .modulemode = MODULEMODE_SWCTRL,
1443 },
1444 },
1445 .opt_clks = mmc2_opt_clks,
1446 .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks),
1447 };
1449 /* mmc3 */
1450 static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1451 { .role = "clk32k", .clk = "mmc3_clk32k" },
1452 };
1454 static struct omap_hwmod dra7xx_mmc3_hwmod = {
1455 .name = "mmc3",
1456 .class = &dra7xx_mmc_hwmod_class,
1457 .clkdm_name = "l4per_clkdm",
1458 .main_clk = "mmc3_gfclk_div",
1459 .prcm = {
1460 .omap4 = {
1461 .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1462 .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1463 .modulemode = MODULEMODE_SWCTRL,
1464 },
1465 },
1466 .opt_clks = mmc3_opt_clks,
1467 .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks),
1468 };
1470 /* mmc4 */
1471 static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1472 { .role = "clk32k", .clk = "mmc4_clk32k" },
1473 };
1475 static struct omap_hwmod dra7xx_mmc4_hwmod = {
1476 .name = "mmc4",
1477 .class = &dra7xx_mmc_hwmod_class,
1478 .clkdm_name = "l4per_clkdm",
1479 .main_clk = "mmc4_gfclk_div",
1480 .prcm = {
1481 .omap4 = {
1482 .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1483 .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1484 .modulemode = MODULEMODE_SWCTRL,
1485 },
1486 },
1487 .opt_clks = mmc4_opt_clks,
1488 .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks),
1489 };
1491 /*
1492 * 'mmu' class
1493 * The memory management unit performs virtual to physical address translation
1494 * for its requestors.
1495 */
1497 static struct omap_hwmod_class_sysconfig dra7xx_mmu_sysc = {
1498 .rev_offs = 0x0000,
1499 .sysc_offs = 0x0010,
1500 .syss_offs = 0x0014,
1501 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1502 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1503 SYSS_HAS_RESET_STATUS),
1504 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1505 .sysc_fields = &omap_hwmod_sysc_type1,
1506 };
1508 static struct omap_hwmod_class dra7xx_mmu_hwmod_class = {
1509 .name = "mmu",
1510 .sysc = &dra7xx_mmu_sysc,
1511 };
1513 /* DSP MMUs */
1514 static struct omap_hwmod_rst_info dra7xx_mmu_dsp_resets[] = {
1515 { .name = "mmu_cache", .rst_shift = 1 },
1516 };
1518 /* mmu0 - dsp1 */
1519 static struct omap_hwmod dra7xx_mmu0_dsp1_hwmod = {
1520 .name = "mmu0_dsp1",
1521 .class = &dra7xx_mmu_hwmod_class,
1522 .clkdm_name = "dsp1_clkdm",
1523 .rst_lines = dra7xx_mmu_dsp_resets,
1524 .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_dsp_resets),
1525 .main_clk = "dpll_dsp_m2_ck",
1526 .prcm = {
1527 .omap4 = {
1528 .clkctrl_offs = DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET,
1529 .rstctrl_offs = DRA7XX_RM_DSP1_RSTCTRL_OFFSET,
1530 .context_offs = DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET,
1531 .modulemode = MODULEMODE_HWCTRL,
1532 },
1533 },
1534 };
1536 /* mmu1 - dsp1 */
1537 static struct omap_hwmod dra7xx_mmu1_dsp1_hwmod = {
1538 .name = "mmu1_dsp1",
1539 .class = &dra7xx_mmu_hwmod_class,
1540 .clkdm_name = "dsp1_clkdm",
1541 .rst_lines = dra7xx_mmu_dsp_resets,
1542 .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_dsp_resets),
1543 .main_clk = "dpll_dsp_m2_ck",
1544 .prcm = {
1545 .omap4 = {
1546 .clkctrl_offs = DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET,
1547 .rstctrl_offs = DRA7XX_RM_DSP1_RSTCTRL_OFFSET,
1548 .context_offs = DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET,
1549 .modulemode = MODULEMODE_HWCTRL,
1550 },
1551 },
1552 };
1554 /* mmu0 - dsp2 */
1555 static struct omap_hwmod dra7xx_mmu0_dsp2_hwmod = {
1556 .name = "mmu0_dsp2",
1557 .class = &dra7xx_mmu_hwmod_class,
1558 .clkdm_name = "dsp2_clkdm",
1559 .rst_lines = dra7xx_mmu_dsp_resets,
1560 .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_dsp_resets),
1561 .main_clk = "dpll_dsp_m2_ck",
1562 .prcm = {
1563 .omap4 = {
1564 .clkctrl_offs = DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET,
1565 .rstctrl_offs = DRA7XX_RM_DSP2_RSTCTRL_OFFSET,
1566 .context_offs = DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET,
1567 .modulemode = MODULEMODE_HWCTRL,
1568 },
1569 },
1570 };
1572 /* mmu1 - dsp2 */
1573 static struct omap_hwmod dra7xx_mmu1_dsp2_hwmod = {
1574 .name = "mmu1_dsp2",
1575 .class = &dra7xx_mmu_hwmod_class,
1576 .clkdm_name = "dsp2_clkdm",
1577 .rst_lines = dra7xx_mmu_dsp_resets,
1578 .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_dsp_resets),
1579 .main_clk = "dpll_dsp_m2_ck",
1580 .prcm = {
1581 .omap4 = {
1582 .clkctrl_offs = DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET,
1583 .rstctrl_offs = DRA7XX_RM_DSP2_RSTCTRL_OFFSET,
1584 .context_offs = DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET,
1585 .modulemode = MODULEMODE_HWCTRL,
1586 },
1587 },
1588 };
1590 /* IPU MMUs */
1591 static struct omap_hwmod_rst_info dra7xx_mmu_ipu_resets[] = {
1592 { .name = "mmu_cache", .rst_shift = 2 },
1593 };
1595 /* mmu ipu1 */
1596 static struct omap_hwmod dra7xx_mmu_ipu1_hwmod = {
1597 .name = "mmu_ipu1",
1598 .class = &dra7xx_mmu_hwmod_class,
1599 .clkdm_name = "ipu1_clkdm",
1600 .rst_lines = dra7xx_mmu_ipu_resets,
1601 .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_ipu_resets),
1602 .main_clk = "ipu1_gfclk_mux",
1603 .prcm = {
1604 .omap4 = {
1605 .clkctrl_offs = DRA7XX_CM_IPU1_IPU1_CLKCTRL_OFFSET,
1606 .rstctrl_offs = DRA7XX_RM_IPU1_RSTCTRL_OFFSET,
1607 .context_offs = DRA7XX_RM_IPU1_IPU1_CONTEXT_OFFSET,
1608 .modulemode = MODULEMODE_HWCTRL,
1609 },
1610 },
1611 };
1613 /* mmu ipu2 */
1614 static struct omap_hwmod dra7xx_mmu_ipu2_hwmod = {
1615 .name = "mmu_ipu2",
1616 .class = &dra7xx_mmu_hwmod_class,
1617 .clkdm_name = "ipu2_clkdm",
1618 .rst_lines = dra7xx_mmu_ipu_resets,
1619 .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_ipu_resets),
1620 .main_clk = "dpll_core_h22x2_ck",
1621 .prcm = {
1622 .omap4 = {
1623 .clkctrl_offs = DRA7XX_CM_IPU2_IPU2_CLKCTRL_OFFSET,
1624 .rstctrl_offs = DRA7XX_RM_IPU2_RSTCTRL_OFFSET,
1625 .context_offs = DRA7XX_RM_IPU2_IPU2_CONTEXT_OFFSET,
1626 .modulemode = MODULEMODE_HWCTRL,
1627 },
1628 },
1629 };
1631 /*
1632 * 'mpu' class
1633 *
1634 */
1636 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1637 .name = "mpu",
1638 };
1640 /* mpu */
1641 static struct omap_hwmod dra7xx_mpu_hwmod = {
1642 .name = "mpu",
1643 .class = &dra7xx_mpu_hwmod_class,
1644 .clkdm_name = "mpu_clkdm",
1645 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1646 .main_clk = "dpll_mpu_m2_ck",
1647 .prcm = {
1648 .omap4 = {
1649 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1650 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1651 },
1652 },
1653 };
1655 /*
1656 * 'ocp2scp' class
1657 *
1658 */
1660 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1661 .rev_offs = 0x0000,
1662 .sysc_offs = 0x0010,
1663 .syss_offs = 0x0014,
1664 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1665 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1666 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1667 SIDLE_SMART_WKUP),
1668 .sysc_fields = &omap_hwmod_sysc_type1,
1669 };
1671 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1672 .name = "ocp2scp",
1673 .sysc = &dra7xx_ocp2scp_sysc,
1674 };
1676 /* ocp2scp1 */
1677 static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1678 .name = "ocp2scp1",
1679 .class = &dra7xx_ocp2scp_hwmod_class,
1680 .clkdm_name = "l3init_clkdm",
1681 .main_clk = "l4_root_clk_div",
1682 .prcm = {
1683 .omap4 = {
1684 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1685 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1686 .modulemode = MODULEMODE_HWCTRL,
1687 },
1688 },
1689 };
1692 /*
1693 * 'pru-icss' class
1694 * Programmable Real-Time Unit and Industrial Communication Subsystem
1695 */
1696 static struct omap_hwmod_class dra7xx_pruss_hwmod_class = {
1697 .name = "pruss",
1698 };
1700 /* pru-icss1 */
1701 static struct omap_hwmod dra7xx_pruss1_hwmod = {
1702 .name = "pruss1",
1703 .class = &dra7xx_pruss_hwmod_class,
1704 .clkdm_name = "l4per2_clkdm",
1705 .prcm = {
1706 .omap4 = {
1707 .clkctrl_offs = DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL_OFFSET,
1708 .context_offs = DRA7XX_RM_L4PER2_PRUSS1_CONTEXT_OFFSET,
1709 .modulemode = MODULEMODE_SWCTRL,
1710 },
1711 },
1712 };
1714 /* pru-icss2 */
1715 static struct omap_hwmod dra7xx_pruss2_hwmod = {
1716 .name = "pruss2",
1717 .class = &dra7xx_pruss_hwmod_class,
1718 .clkdm_name = "l4per2_clkdm",
1719 .prcm = {
1720 .omap4 = {
1721 .clkctrl_offs = DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL_OFFSET,
1722 .context_offs = DRA7XX_RM_L4PER2_PRUSS2_CONTEXT_OFFSET,
1723 .modulemode = MODULEMODE_SWCTRL,
1724 },
1725 },
1726 };
1728 /*
1729 * 'qspi' class
1730 *
1731 */
1733 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1734 .sysc_offs = 0x0010,
1735 .sysc_flags = SYSC_HAS_SIDLEMODE,
1736 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1737 SIDLE_SMART_WKUP),
1738 .sysc_fields = &omap_hwmod_sysc_type2,
1739 };
1741 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1742 .name = "qspi",
1743 .sysc = &dra7xx_qspi_sysc,
1744 };
1746 /* qspi */
1747 static struct omap_hwmod dra7xx_qspi_hwmod = {
1748 .name = "qspi",
1749 .class = &dra7xx_qspi_hwmod_class,
1750 .clkdm_name = "l4per2_clkdm",
1751 .main_clk = "qspi_gfclk_div",
1752 .prcm = {
1753 .omap4 = {
1754 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1755 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1756 .modulemode = MODULEMODE_SWCTRL,
1757 },
1758 },
1759 };
1761 /*
1762 * 'rtcss' class
1763 *
1764 */
1765 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
1766 .sysc_offs = 0x0078,
1767 .sysc_flags = SYSC_HAS_SIDLEMODE,
1768 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1769 SIDLE_SMART_WKUP),
1770 .sysc_fields = &omap_hwmod_sysc_type3,
1771 };
1773 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
1774 .name = "rtcss",
1775 .sysc = &dra7xx_rtcss_sysc,
1776 };
1778 /* rtcss */
1779 static struct omap_hwmod dra7xx_rtcss_hwmod = {
1780 .name = "rtcss",
1781 .class = &dra7xx_rtcss_hwmod_class,
1782 .clkdm_name = "rtc_clkdm",
1783 .main_clk = "sys_32k_ck",
1784 .prcm = {
1785 .omap4 = {
1786 .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
1787 .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
1788 .modulemode = MODULEMODE_SWCTRL,
1789 },
1790 },
1791 };
1793 /*
1794 * 'sata' class
1795 *
1796 */
1798 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
1799 .sysc_offs = 0x0000,
1800 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1801 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1802 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1803 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1804 .sysc_fields = &omap_hwmod_sysc_type2,
1805 };
1807 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
1808 .name = "sata",
1809 .sysc = &dra7xx_sata_sysc,
1810 };
1812 /* sata */
1813 static struct omap_hwmod_opt_clk sata_opt_clks[] = {
1814 { .role = "ref_clk", .clk = "sata_ref_clk" },
1815 };
1817 static struct omap_hwmod dra7xx_sata_hwmod = {
1818 .name = "sata",
1819 .class = &dra7xx_sata_hwmod_class,
1820 .clkdm_name = "l3init_clkdm",
1821 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1822 .main_clk = "func_48m_fclk",
1823 .prcm = {
1824 .omap4 = {
1825 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
1826 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
1827 .modulemode = MODULEMODE_SWCTRL,
1828 },
1829 },
1830 .opt_clks = sata_opt_clks,
1831 .opt_clks_cnt = ARRAY_SIZE(sata_opt_clks),
1832 };
1834 /*
1835 * 'smartreflex' class
1836 *
1837 */
1839 /* The IP is not compliant to type1 / type2 scheme */
1840 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
1841 .sidle_shift = 24,
1842 .enwkup_shift = 26,
1843 };
1845 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
1846 .sysc_offs = 0x0038,
1847 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1848 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1849 SIDLE_SMART_WKUP),
1850 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
1851 };
1853 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
1854 .name = "smartreflex",
1855 .sysc = &dra7xx_smartreflex_sysc,
1856 .rev = 2,
1857 };
1859 /* smartreflex_core */
1860 /* smartreflex_core dev_attr */
1861 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
1862 .sensor_voltdm_name = "core",
1863 };
1865 static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
1866 .name = "smartreflex_core",
1867 .class = &dra7xx_smartreflex_hwmod_class,
1868 .clkdm_name = "coreaon_clkdm",
1869 .main_clk = "wkupaon_iclk_mux",
1870 .prcm = {
1871 .omap4 = {
1872 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
1873 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
1874 .modulemode = MODULEMODE_SWCTRL,
1875 },
1876 },
1877 .dev_attr = &smartreflex_core_dev_attr,
1878 };
1880 /* smartreflex_mpu */
1881 /* smartreflex_mpu dev_attr */
1882 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
1883 .sensor_voltdm_name = "mpu",
1884 };
1886 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
1887 .name = "smartreflex_mpu",
1888 .class = &dra7xx_smartreflex_hwmod_class,
1889 .clkdm_name = "coreaon_clkdm",
1890 .main_clk = "wkupaon_iclk_mux",
1891 .prcm = {
1892 .omap4 = {
1893 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
1894 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
1895 .modulemode = MODULEMODE_SWCTRL,
1896 },
1897 },
1898 .dev_attr = &smartreflex_mpu_dev_attr,
1899 };
1901 /*
1902 * 'spinlock' class
1903 *
1904 */
1906 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
1907 .rev_offs = 0x0000,
1908 .sysc_offs = 0x0010,
1909 .syss_offs = 0x0014,
1910 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1911 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1912 SYSS_HAS_RESET_STATUS),
1913 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1914 .sysc_fields = &omap_hwmod_sysc_type1,
1915 };
1917 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
1918 .name = "spinlock",
1919 .sysc = &dra7xx_spinlock_sysc,
1920 };
1922 /* spinlock */
1923 static struct omap_hwmod dra7xx_spinlock_hwmod = {
1924 .name = "spinlock",
1925 .class = &dra7xx_spinlock_hwmod_class,
1926 .clkdm_name = "l4cfg_clkdm",
1927 .main_clk = "l3_iclk_div",
1928 .prcm = {
1929 .omap4 = {
1930 .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
1931 .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1932 },
1933 },
1934 };
1936 /*
1937 * 'timer' class
1938 *
1939 * This class contains several variants: ['timer_1ms', 'timer_secure',
1940 * 'timer']
1941 */
1943 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
1944 .rev_offs = 0x0000,
1945 .sysc_offs = 0x0010,
1946 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1947 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1948 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1949 SIDLE_SMART_WKUP),
1950 .sysc_fields = &omap_hwmod_sysc_type2,
1951 };
1953 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
1954 .name = "timer",
1955 .sysc = &dra7xx_timer_1ms_sysc,
1956 };
1958 static struct omap_hwmod_class_sysconfig dra7xx_timer_secure_sysc = {
1959 .rev_offs = 0x0000,
1960 .sysc_offs = 0x0010,
1961 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1962 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1963 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1964 SIDLE_SMART_WKUP),
1965 .sysc_fields = &omap_hwmod_sysc_type2,
1966 };
1968 static struct omap_hwmod_class dra7xx_timer_secure_hwmod_class = {
1969 .name = "timer",
1970 .sysc = &dra7xx_timer_secure_sysc,
1971 };
1973 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
1974 .rev_offs = 0x0000,
1975 .sysc_offs = 0x0010,
1976 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1977 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1978 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1979 SIDLE_SMART_WKUP),
1980 .sysc_fields = &omap_hwmod_sysc_type2,
1981 };
1983 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
1984 .name = "timer",
1985 .sysc = &dra7xx_timer_sysc,
1986 };
1988 /* timer1 */
1989 static struct omap_hwmod dra7xx_timer1_hwmod = {
1990 .name = "timer1",
1991 .class = &dra7xx_timer_1ms_hwmod_class,
1992 .clkdm_name = "wkupaon_clkdm",
1993 .main_clk = "timer1_gfclk_mux",
1994 .prcm = {
1995 .omap4 = {
1996 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1997 .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1998 .modulemode = MODULEMODE_SWCTRL,
1999 },
2000 },
2001 };
2003 /* timer2 */
2004 static struct omap_hwmod dra7xx_timer2_hwmod = {
2005 .name = "timer2",
2006 .class = &dra7xx_timer_1ms_hwmod_class,
2007 .clkdm_name = "l4per_clkdm",
2008 .main_clk = "timer2_gfclk_mux",
2009 .prcm = {
2010 .omap4 = {
2011 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
2012 .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
2013 .modulemode = MODULEMODE_SWCTRL,
2014 },
2015 },
2016 };
2018 /* timer3 */
2019 static struct omap_hwmod dra7xx_timer3_hwmod = {
2020 .name = "timer3",
2021 .class = &dra7xx_timer_hwmod_class,
2022 .clkdm_name = "l4per_clkdm",
2023 .main_clk = "timer3_gfclk_mux",
2024 .prcm = {
2025 .omap4 = {
2026 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
2027 .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
2028 .modulemode = MODULEMODE_SWCTRL,
2029 },
2030 },
2031 };
2033 /* timer4 */
2034 static struct omap_hwmod dra7xx_timer4_hwmod = {
2035 .name = "timer4",
2036 .class = &dra7xx_timer_secure_hwmod_class,
2037 .clkdm_name = "l4per_clkdm",
2038 .main_clk = "timer4_gfclk_mux",
2039 .prcm = {
2040 .omap4 = {
2041 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
2042 .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
2043 .modulemode = MODULEMODE_SWCTRL,
2044 },
2045 },
2046 };
2048 /* timer5 */
2049 static struct omap_hwmod dra7xx_timer5_hwmod = {
2050 .name = "timer5",
2051 .class = &dra7xx_timer_hwmod_class,
2052 .clkdm_name = "ipu_clkdm",
2053 .main_clk = "timer5_gfclk_mux",
2054 .prcm = {
2055 .omap4 = {
2056 .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
2057 .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
2058 .modulemode = MODULEMODE_SWCTRL,
2059 },
2060 },
2061 };
2063 /* timer6 */
2064 static struct omap_hwmod dra7xx_timer6_hwmod = {
2065 .name = "timer6",
2066 .class = &dra7xx_timer_hwmod_class,
2067 .clkdm_name = "ipu_clkdm",
2068 .main_clk = "timer6_gfclk_mux",
2069 .prcm = {
2070 .omap4 = {
2071 .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
2072 .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
2073 .modulemode = MODULEMODE_SWCTRL,
2074 },
2075 },
2076 };
2078 /* timer7 */
2079 static struct omap_hwmod dra7xx_timer7_hwmod = {
2080 .name = "timer7",
2081 .class = &dra7xx_timer_hwmod_class,
2082 .clkdm_name = "ipu_clkdm",
2083 .main_clk = "timer7_gfclk_mux",
2084 .prcm = {
2085 .omap4 = {
2086 .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
2087 .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
2088 .modulemode = MODULEMODE_SWCTRL,
2089 },
2090 },
2091 };
2093 /* timer8 */
2094 static struct omap_hwmod dra7xx_timer8_hwmod = {
2095 .name = "timer8",
2096 .class = &dra7xx_timer_hwmod_class,
2097 .clkdm_name = "ipu_clkdm",
2098 .main_clk = "timer8_gfclk_mux",
2099 .prcm = {
2100 .omap4 = {
2101 .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
2102 .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
2103 .modulemode = MODULEMODE_SWCTRL,
2104 },
2105 },
2106 };
2108 /* timer9 */
2109 static struct omap_hwmod dra7xx_timer9_hwmod = {
2110 .name = "timer9",
2111 .class = &dra7xx_timer_hwmod_class,
2112 .clkdm_name = "l4per_clkdm",
2113 .main_clk = "timer9_gfclk_mux",
2114 .prcm = {
2115 .omap4 = {
2116 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
2117 .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
2118 .modulemode = MODULEMODE_SWCTRL,
2119 },
2120 },
2121 };
2123 /* timer10 */
2124 static struct omap_hwmod dra7xx_timer10_hwmod = {
2125 .name = "timer10",
2126 .class = &dra7xx_timer_1ms_hwmod_class,
2127 .clkdm_name = "l4per_clkdm",
2128 .main_clk = "timer10_gfclk_mux",
2129 .prcm = {
2130 .omap4 = {
2131 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
2132 .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
2133 .modulemode = MODULEMODE_SWCTRL,
2134 },
2135 },
2136 };
2138 /* timer11 */
2139 static struct omap_hwmod dra7xx_timer11_hwmod = {
2140 .name = "timer11",
2141 .class = &dra7xx_timer_hwmod_class,
2142 .clkdm_name = "l4per_clkdm",
2143 .main_clk = "timer11_gfclk_mux",
2144 .prcm = {
2145 .omap4 = {
2146 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
2147 .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
2148 .modulemode = MODULEMODE_SWCTRL,
2149 },
2150 },
2151 };
2153 /*
2154 * 'uart' class
2155 *
2156 */
2158 static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
2159 .rev_offs = 0x0050,
2160 .sysc_offs = 0x0054,
2161 .syss_offs = 0x0058,
2162 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2163 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2164 SYSS_HAS_RESET_STATUS),
2165 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2166 SIDLE_SMART_WKUP),
2167 .sysc_fields = &omap_hwmod_sysc_type1,
2168 };
2170 static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
2171 .name = "uart",
2172 .sysc = &dra7xx_uart_sysc,
2173 };
2175 /* uart1 */
2176 static struct omap_hwmod dra7xx_uart1_hwmod = {
2177 .name = "uart1",
2178 .class = &dra7xx_uart_hwmod_class,
2179 .clkdm_name = "l4per_clkdm",
2180 .main_clk = "uart1_gfclk_mux",
2181 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
2182 .prcm = {
2183 .omap4 = {
2184 .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
2185 .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
2186 .modulemode = MODULEMODE_SWCTRL,
2187 },
2188 },
2189 };
2191 /* uart2 */
2192 static struct omap_hwmod dra7xx_uart2_hwmod = {
2193 .name = "uart2",
2194 .class = &dra7xx_uart_hwmod_class,
2195 .clkdm_name = "l4per_clkdm",
2196 .main_clk = "uart2_gfclk_mux",
2197 .flags = HWMOD_SWSUP_SIDLE_ACT,
2198 .prcm = {
2199 .omap4 = {
2200 .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
2201 .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
2202 .modulemode = MODULEMODE_SWCTRL,
2203 },
2204 },
2205 };
2207 /* uart3 */
2208 static struct omap_hwmod dra7xx_uart3_hwmod = {
2209 .name = "uart3",
2210 .class = &dra7xx_uart_hwmod_class,
2211 .clkdm_name = "l4per_clkdm",
2212 .main_clk = "uart3_gfclk_mux",
2213 .flags = HWMOD_SWSUP_SIDLE_ACT,
2214 .prcm = {
2215 .omap4 = {
2216 .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
2217 .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
2218 .modulemode = MODULEMODE_SWCTRL,
2219 },
2220 },
2221 };
2223 /* uart4 */
2224 static struct omap_hwmod dra7xx_uart4_hwmod = {
2225 .name = "uart4",
2226 .class = &dra7xx_uart_hwmod_class,
2227 .clkdm_name = "l4per_clkdm",
2228 .main_clk = "uart4_gfclk_mux",
2229 .flags = HWMOD_SWSUP_SIDLE_ACT,
2230 .prcm = {
2231 .omap4 = {
2232 .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
2233 .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
2234 .modulemode = MODULEMODE_SWCTRL,
2235 },
2236 },
2237 };
2239 /* uart5 */
2240 static struct omap_hwmod dra7xx_uart5_hwmod = {
2241 .name = "uart5",
2242 .class = &dra7xx_uart_hwmod_class,
2243 .clkdm_name = "l4per_clkdm",
2244 .main_clk = "uart5_gfclk_mux",
2245 .flags = HWMOD_SWSUP_SIDLE_ACT,
2246 .prcm = {
2247 .omap4 = {
2248 .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
2249 .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
2250 .modulemode = MODULEMODE_SWCTRL,
2251 },
2252 },
2253 };
2255 /* uart6 */
2256 static struct omap_hwmod dra7xx_uart6_hwmod = {
2257 .name = "uart6",
2258 .class = &dra7xx_uart_hwmod_class,
2259 .clkdm_name = "ipu_clkdm",
2260 .main_clk = "uart6_gfclk_mux",
2261 .flags = HWMOD_SWSUP_SIDLE_ACT,
2262 .prcm = {
2263 .omap4 = {
2264 .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
2265 .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
2266 .modulemode = MODULEMODE_SWCTRL,
2267 },
2268 },
2269 };
2271 /* DES (the 'P' (public) device) */
2272 static struct omap_hwmod_class_sysconfig dra7xx_des_sysc = {
2273 .rev_offs = 0x0030,
2274 .sysc_offs = 0x0034,
2275 .syss_offs = 0x0038,
2276 .sysc_flags = SYSS_HAS_RESET_STATUS,
2277 };
2279 static struct omap_hwmod_class dra7xx_des_hwmod_class = {
2280 .name = "des",
2281 .sysc = &dra7xx_des_sysc,
2282 };
2284 /* DES */
2285 static struct omap_hwmod dra7xx_des_hwmod = {
2286 .name = "des",
2287 .class = &dra7xx_des_hwmod_class,
2288 .clkdm_name = "l4sec_clkdm",
2289 .main_clk = "l3_iclk_div",
2290 .prcm = {
2291 .omap4 = {
2292 .clkctrl_offs = DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
2293 .context_offs = DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
2294 .modulemode = MODULEMODE_HWCTRL,
2295 },
2296 },
2297 };
2299 /* rng */
2300 static struct omap_hwmod_class_sysconfig dra7xx_rng_sysc = {
2301 .rev_offs = 0x1fe0,
2302 .sysc_offs = 0x1fe4,
2303 .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
2304 .idlemodes = SIDLE_FORCE | SIDLE_NO,
2305 .sysc_fields = &omap_hwmod_sysc_type1,
2306 };
2308 static struct omap_hwmod_class dra7xx_rng_hwmod_class = {
2309 .name = "rng",
2310 .sysc = &dra7xx_rng_sysc,
2311 };
2313 static struct omap_hwmod dra7xx_rng_hwmod = {
2314 .name = "rng",
2315 .class = &dra7xx_rng_hwmod_class,
2316 .flags = HWMOD_SWSUP_SIDLE,
2317 .clkdm_name = "l4sec_clkdm",
2318 .prcm = {
2319 .omap4 = {
2320 .clkctrl_offs = DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET,
2321 .context_offs = DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET,
2322 .modulemode = MODULEMODE_HWCTRL,
2323 },
2324 },
2325 };
2327 /*
2328 * 'usb_otg_ss' class
2329 *
2330 */
2332 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
2333 .name = "usb_otg_ss",
2334 };
2336 /* usb_otg_ss1 */
2337 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
2338 { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
2339 };
2341 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
2342 .name = "usb_otg_ss1",
2343 .class = &dra7xx_usb_otg_ss_hwmod_class,
2344 .clkdm_name = "l3init_clkdm",
2345 .main_clk = "dpll_core_h13x2_ck",
2346 .prcm = {
2347 .omap4 = {
2348 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
2349 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
2350 .modulemode = MODULEMODE_HWCTRL,
2351 },
2352 },
2353 .opt_clks = usb_otg_ss1_opt_clks,
2354 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
2355 };
2357 /* usb_otg_ss2 */
2358 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
2359 { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
2360 };
2362 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
2363 .name = "usb_otg_ss2",
2364 .class = &dra7xx_usb_otg_ss_hwmod_class,
2365 .clkdm_name = "l3init_clkdm",
2366 .main_clk = "dpll_core_h13x2_ck",
2367 .prcm = {
2368 .omap4 = {
2369 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
2370 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
2371 .modulemode = MODULEMODE_HWCTRL,
2372 },
2373 },
2374 .opt_clks = usb_otg_ss2_opt_clks,
2375 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
2376 };
2378 /* usb_otg_ss3 */
2379 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
2380 .name = "usb_otg_ss3",
2381 .class = &dra7xx_usb_otg_ss_hwmod_class,
2382 .clkdm_name = "l3init_clkdm",
2383 .main_clk = "dpll_core_h13x2_ck",
2384 .prcm = {
2385 .omap4 = {
2386 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
2387 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
2388 .modulemode = MODULEMODE_HWCTRL,
2389 },
2390 },
2391 };
2393 /* usb_otg_ss4 */
2394 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
2395 .name = "usb_otg_ss4",
2396 .class = &dra7xx_usb_otg_ss_hwmod_class,
2397 .clkdm_name = "l3init_clkdm",
2398 .main_clk = "dpll_core_h13x2_ck",
2399 .prcm = {
2400 .omap4 = {
2401 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
2402 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
2403 .modulemode = MODULEMODE_HWCTRL,
2404 },
2405 },
2406 };
2408 /*
2409 * 'vcp' class
2410 *
2411 */
2413 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
2414 .name = "vcp",
2415 };
2417 /* vcp1 */
2418 static struct omap_hwmod dra7xx_vcp1_hwmod = {
2419 .name = "vcp1",
2420 .class = &dra7xx_vcp_hwmod_class,
2421 .clkdm_name = "l3main1_clkdm",
2422 .main_clk = "l3_iclk_div",
2423 .prcm = {
2424 .omap4 = {
2425 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
2426 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
2427 },
2428 },
2429 };
2431 /* vcp2 */
2432 static struct omap_hwmod dra7xx_vcp2_hwmod = {
2433 .name = "vcp2",
2434 .class = &dra7xx_vcp_hwmod_class,
2435 .clkdm_name = "l3main1_clkdm",
2436 .main_clk = "l3_iclk_div",
2437 .prcm = {
2438 .omap4 = {
2439 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
2440 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
2441 },
2442 },
2443 };
2445 /*
2446 * 'wd_timer' class
2447 *
2448 */
2450 static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
2451 .rev_offs = 0x0000,
2452 .sysc_offs = 0x0010,
2453 .syss_offs = 0x0014,
2454 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2455 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2456 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2457 SIDLE_SMART_WKUP),
2458 .sysc_fields = &omap_hwmod_sysc_type1,
2459 };
2461 static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
2462 .name = "wd_timer",
2463 .sysc = &dra7xx_wd_timer_sysc,
2464 .pre_shutdown = &omap2_wd_timer_disable,
2465 .reset = &omap2_wd_timer_reset,
2466 };
2468 /* wd_timer2 */
2469 static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
2470 .name = "wd_timer2",
2471 .class = &dra7xx_wd_timer_hwmod_class,
2472 .clkdm_name = "wkupaon_clkdm",
2473 .main_clk = "sys_32k_ck",
2474 .prcm = {
2475 .omap4 = {
2476 .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
2477 .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
2478 .modulemode = MODULEMODE_SWCTRL,
2479 },
2480 },
2481 };
2484 /*
2485 * Interfaces
2486 */
2488 /* l3_main_2 -> l3_instr */
2489 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
2490 .master = &dra7xx_l3_main_2_hwmod,
2491 .slave = &dra7xx_l3_instr_hwmod,
2492 .clk = "l3_iclk_div",
2493 .user = OCP_USER_MPU | OCP_USER_SDMA,
2494 };
2496 /* l4_cfg -> l3_main_1 */
2497 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
2498 .master = &dra7xx_l4_cfg_hwmod,
2499 .slave = &dra7xx_l3_main_1_hwmod,
2500 .clk = "l3_iclk_div",
2501 .user = OCP_USER_MPU | OCP_USER_SDMA,
2502 };
2504 /* mpu -> l3_main_1 */
2505 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
2506 .master = &dra7xx_mpu_hwmod,
2507 .slave = &dra7xx_l3_main_1_hwmod,
2508 .clk = "l3_iclk_div",
2509 .user = OCP_USER_MPU,
2510 };
2512 /* l3_main_1 -> l3_main_2 */
2513 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
2514 .master = &dra7xx_l3_main_1_hwmod,
2515 .slave = &dra7xx_l3_main_2_hwmod,
2516 .clk = "l3_iclk_div",
2517 .user = OCP_USER_MPU,
2518 };
2520 /* l4_cfg -> l3_main_2 */
2521 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
2522 .master = &dra7xx_l4_cfg_hwmod,
2523 .slave = &dra7xx_l3_main_2_hwmod,
2524 .clk = "l3_iclk_div",
2525 .user = OCP_USER_MPU | OCP_USER_SDMA,
2526 };
2528 /* l3_main_1 -> l4_cfg */
2529 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
2530 .master = &dra7xx_l3_main_1_hwmod,
2531 .slave = &dra7xx_l4_cfg_hwmod,
2532 .clk = "l3_iclk_div",
2533 .user = OCP_USER_MPU | OCP_USER_SDMA,
2534 };
2536 /* l3_main_1 -> mmu0_dsp1 */
2537 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu0_dsp1 = {
2538 .master = &dra7xx_l3_main_1_hwmod,
2539 .slave = &dra7xx_mmu0_dsp1_hwmod,
2540 .clk = "l3_iclk_div",
2541 .user = OCP_USER_MPU | OCP_USER_SDMA,
2542 };
2544 /* l3_main_1 -> mmu1_dsp1 */
2545 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu1_dsp1 = {
2546 .master = &dra7xx_l3_main_1_hwmod,
2547 .slave = &dra7xx_mmu1_dsp1_hwmod,
2548 .clk = "l3_iclk_div",
2549 .user = OCP_USER_MPU | OCP_USER_SDMA,
2550 };
2552 /* l3_main_1 -> mmu0_dsp2 */
2553 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu0_dsp2 = {
2554 .master = &dra7xx_l3_main_1_hwmod,
2555 .slave = &dra7xx_mmu0_dsp2_hwmod,
2556 .clk = "l3_iclk_div",
2557 .user = OCP_USER_MPU | OCP_USER_SDMA,
2558 };
2560 /* l3_main_1 -> mmu1_dsp2 */
2561 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu1_dsp2 = {
2562 .master = &dra7xx_l3_main_1_hwmod,
2563 .slave = &dra7xx_mmu1_dsp2_hwmod,
2564 .clk = "l3_iclk_div",
2565 .user = OCP_USER_MPU | OCP_USER_SDMA,
2566 };
2568 /* l3_main_1 -> mmu_ipu1 */
2569 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu_ipu1 = {
2570 .master = &dra7xx_l3_main_1_hwmod,
2571 .slave = &dra7xx_mmu_ipu1_hwmod,
2572 .clk = "l3_iclk_div",
2573 .user = OCP_USER_MPU | OCP_USER_SDMA,
2574 };
2576 /* l3_main_1 -> mmu_ipu2 */
2577 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu_ipu2 = {
2578 .master = &dra7xx_l3_main_1_hwmod,
2579 .slave = &dra7xx_mmu_ipu2_hwmod,
2580 .clk = "l3_iclk_div",
2581 .user = OCP_USER_MPU | OCP_USER_SDMA,
2582 };
2584 /* l3_main_1 -> l4_per1 */
2585 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
2586 .master = &dra7xx_l3_main_1_hwmod,
2587 .slave = &dra7xx_l4_per1_hwmod,
2588 .clk = "l3_iclk_div",
2589 .user = OCP_USER_MPU | OCP_USER_SDMA,
2590 };
2592 /* l3_main_1 -> l4_per2 */
2593 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
2594 .master = &dra7xx_l3_main_1_hwmod,
2595 .slave = &dra7xx_l4_per2_hwmod,
2596 .clk = "l3_iclk_div",
2597 .user = OCP_USER_MPU | OCP_USER_SDMA,
2598 };
2600 /* l3_main_1 -> l4_per3 */
2601 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
2602 .master = &dra7xx_l3_main_1_hwmod,
2603 .slave = &dra7xx_l4_per3_hwmod,
2604 .clk = "l3_iclk_div",
2605 .user = OCP_USER_MPU | OCP_USER_SDMA,
2606 };
2608 /* l3_main_1 -> l4_wkup */
2609 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
2610 .master = &dra7xx_l3_main_1_hwmod,
2611 .slave = &dra7xx_l4_wkup_hwmod,
2612 .clk = "wkupaon_iclk_mux",
2613 .user = OCP_USER_MPU | OCP_USER_SDMA,
2614 };
2616 /* l4_per2 -> atl */
2617 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
2618 .master = &dra7xx_l4_per2_hwmod,
2619 .slave = &dra7xx_atl_hwmod,
2620 .clk = "l3_iclk_div",
2621 .user = OCP_USER_MPU | OCP_USER_SDMA,
2622 };
2624 /* l3_main_1 -> bb2d */
2625 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
2626 .master = &dra7xx_l3_main_1_hwmod,
2627 .slave = &dra7xx_bb2d_hwmod,
2628 .clk = "l3_iclk_div",
2629 .user = OCP_USER_MPU | OCP_USER_SDMA,
2630 };
2632 /* l4_wkup -> counter_32k */
2633 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
2634 .master = &dra7xx_l4_wkup_hwmod,
2635 .slave = &dra7xx_counter_32k_hwmod,
2636 .clk = "wkupaon_iclk_mux",
2637 .user = OCP_USER_MPU | OCP_USER_SDMA,
2638 };
2640 /* l4_wkup -> ctrl_module_wkup */
2641 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
2642 .master = &dra7xx_l4_wkup_hwmod,
2643 .slave = &dra7xx_ctrl_module_wkup_hwmod,
2644 .clk = "wkupaon_iclk_mux",
2645 .user = OCP_USER_MPU | OCP_USER_SDMA,
2646 };
2648 /* l4_wkup -> dcan1 */
2649 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2650 .master = &dra7xx_l4_wkup_hwmod,
2651 .slave = &dra7xx_dcan1_hwmod,
2652 .clk = "wkupaon_iclk_mux",
2653 .user = OCP_USER_MPU | OCP_USER_SDMA,
2654 };
2656 /* l4_per2 -> dcan2 */
2657 static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2658 .master = &dra7xx_l4_per2_hwmod,
2659 .slave = &dra7xx_dcan2_hwmod,
2660 .clk = "l3_iclk_div",
2661 .user = OCP_USER_MPU | OCP_USER_SDMA,
2662 };
2664 static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
2665 {
2666 .pa_start = 0x4a056000,
2667 .pa_end = 0x4a056fff,
2668 .flags = ADDR_TYPE_RT
2669 },
2670 { }
2671 };
2673 /* l4_cfg -> dma_system */
2674 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
2675 .master = &dra7xx_l4_cfg_hwmod,
2676 .slave = &dra7xx_dma_system_hwmod,
2677 .clk = "l3_iclk_div",
2678 .addr = dra7xx_dma_system_addrs,
2679 .user = OCP_USER_MPU | OCP_USER_SDMA,
2680 };
2682 /* dsp1 -> l3_main_1 */
2683 static struct omap_hwmod_ocp_if dra7xx_dsp1__l3_main_1 = {
2684 .master = &dra7xx_dsp1_hwmod,
2685 .slave = &dra7xx_l3_main_1_hwmod,
2686 .clk = "l3_iclk_div",
2687 .user = OCP_USER_MPU | OCP_USER_SDMA,
2688 };
2690 /* dsp2 -> l3_main_1 */
2691 static struct omap_hwmod_ocp_if dra7xx_dsp2__l3_main_1 = {
2692 .master = &dra7xx_dsp2_hwmod,
2693 .slave = &dra7xx_l3_main_1_hwmod,
2694 .clk = "l3_iclk_div",
2695 .user = OCP_USER_MPU | OCP_USER_SDMA,
2696 };
2698 static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
2699 {
2700 .name = "family",
2701 .pa_start = 0x58000000,
2702 .pa_end = 0x5800007f,
2703 .flags = ADDR_TYPE_RT
2704 },
2705 };
2707 /* l3_main_1 -> dss */
2708 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
2709 .master = &dra7xx_l3_main_1_hwmod,
2710 .slave = &dra7xx_dss_hwmod,
2711 .clk = "l3_iclk_div",
2712 .addr = dra7xx_dss_addrs,
2713 .user = OCP_USER_MPU | OCP_USER_SDMA,
2714 };
2716 static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = {
2717 {
2718 .name = "dispc",
2719 .pa_start = 0x58001000,
2720 .pa_end = 0x58001fff,
2721 .flags = ADDR_TYPE_RT
2722 },
2723 };
2725 /* l3_main_1 -> dispc */
2726 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
2727 .master = &dra7xx_l3_main_1_hwmod,
2728 .slave = &dra7xx_dss_dispc_hwmod,
2729 .clk = "l3_iclk_div",
2730 .addr = dra7xx_dss_dispc_addrs,
2731 .user = OCP_USER_MPU | OCP_USER_SDMA,
2732 };
2734 static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = {
2735 {
2736 .name = "hdmi_wp",
2737 .pa_start = 0x58040000,
2738 .pa_end = 0x580400ff,
2739 .flags = ADDR_TYPE_RT
2740 },
2741 { }
2742 };
2744 /* l3_main_1 -> dispc */
2745 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
2746 .master = &dra7xx_l3_main_1_hwmod,
2747 .slave = &dra7xx_dss_hdmi_hwmod,
2748 .clk = "l3_iclk_div",
2749 .addr = dra7xx_dss_hdmi_addrs,
2750 .user = OCP_USER_MPU | OCP_USER_SDMA,
2751 };
2753 /* l3_main_1 -> aes */
2754 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes = {
2755 .master = &dra7xx_l3_main_1_hwmod,
2756 .slave = &dra7xx_aes_hwmod,
2757 .clk = "l3_iclk_div",
2758 .user = OCP_USER_MPU | OCP_USER_SDMA,
2759 };
2761 /* l3_main_1 -> sha0 */
2762 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__sha0 = {
2763 .master = &dra7xx_l3_main_1_hwmod,
2764 .slave = &dra7xx_sha0_hwmod,
2765 .clk = "l3_iclk_div",
2766 .user = OCP_USER_MPU | OCP_USER_SDMA,
2767 };
2769 static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = {
2770 {
2771 .pa_start = 0x48078000,
2772 .pa_end = 0x48078fff,
2773 .flags = ADDR_TYPE_RT
2774 },
2775 { }
2776 };
2778 /* l4_per1 -> elm */
2779 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
2780 .master = &dra7xx_l4_per1_hwmod,
2781 .slave = &dra7xx_elm_hwmod,
2782 .clk = "l3_iclk_div",
2783 .addr = dra7xx_elm_addrs,
2784 .user = OCP_USER_MPU | OCP_USER_SDMA,
2785 };
2787 /* l4_wkup -> gpio1 */
2788 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
2789 .master = &dra7xx_l4_wkup_hwmod,
2790 .slave = &dra7xx_gpio1_hwmod,
2791 .clk = "wkupaon_iclk_mux",
2792 .user = OCP_USER_MPU | OCP_USER_SDMA,
2793 };
2795 /* l4_per1 -> gpio2 */
2796 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
2797 .master = &dra7xx_l4_per1_hwmod,
2798 .slave = &dra7xx_gpio2_hwmod,
2799 .clk = "l3_iclk_div",
2800 .user = OCP_USER_MPU | OCP_USER_SDMA,
2801 };
2803 /* l4_per1 -> gpio3 */
2804 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
2805 .master = &dra7xx_l4_per1_hwmod,
2806 .slave = &dra7xx_gpio3_hwmod,
2807 .clk = "l3_iclk_div",
2808 .user = OCP_USER_MPU | OCP_USER_SDMA,
2809 };
2811 /* l4_per1 -> gpio4 */
2812 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
2813 .master = &dra7xx_l4_per1_hwmod,
2814 .slave = &dra7xx_gpio4_hwmod,
2815 .clk = "l3_iclk_div",
2816 .user = OCP_USER_MPU | OCP_USER_SDMA,
2817 };
2819 /* l4_per1 -> gpio5 */
2820 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
2821 .master = &dra7xx_l4_per1_hwmod,
2822 .slave = &dra7xx_gpio5_hwmod,
2823 .clk = "l3_iclk_div",
2824 .user = OCP_USER_MPU | OCP_USER_SDMA,
2825 };
2827 /* l4_per1 -> gpio6 */
2828 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
2829 .master = &dra7xx_l4_per1_hwmod,
2830 .slave = &dra7xx_gpio6_hwmod,
2831 .clk = "l3_iclk_div",
2832 .user = OCP_USER_MPU | OCP_USER_SDMA,
2833 };
2835 /* l4_per1 -> gpio7 */
2836 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
2837 .master = &dra7xx_l4_per1_hwmod,
2838 .slave = &dra7xx_gpio7_hwmod,
2839 .clk = "l3_iclk_div",
2840 .user = OCP_USER_MPU | OCP_USER_SDMA,
2841 };
2843 /* l4_per1 -> gpio8 */
2844 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
2845 .master = &dra7xx_l4_per1_hwmod,
2846 .slave = &dra7xx_gpio8_hwmod,
2847 .clk = "l3_iclk_div",
2848 .user = OCP_USER_MPU | OCP_USER_SDMA,
2849 };
2851 static struct omap_hwmod_addr_space dra7xx_gpmc_addrs[] = {
2852 {
2853 .pa_start = 0x50000000,
2854 .pa_end = 0x500003ff,
2855 .flags = ADDR_TYPE_RT
2856 },
2857 { }
2858 };
2860 /* l3_main_1 -> gpmc */
2861 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
2862 .master = &dra7xx_l3_main_1_hwmod,
2863 .slave = &dra7xx_gpmc_hwmod,
2864 .clk = "l3_iclk_div",
2865 .addr = dra7xx_gpmc_addrs,
2866 .user = OCP_USER_MPU | OCP_USER_SDMA,
2867 };
2869 static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
2870 {
2871 .pa_start = 0x480b2000,
2872 .pa_end = 0x480b201f,
2873 .flags = ADDR_TYPE_RT
2874 },
2875 { }
2876 };
2878 /* l4_per1 -> hdq1w */
2879 static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
2880 .master = &dra7xx_l4_per1_hwmod,
2881 .slave = &dra7xx_hdq1w_hwmod,
2882 .clk = "l3_iclk_div",
2883 .addr = dra7xx_hdq1w_addrs,
2884 .user = OCP_USER_MPU | OCP_USER_SDMA,
2885 };
2887 /* l4_per1 -> i2c1 */
2888 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
2889 .master = &dra7xx_l4_per1_hwmod,
2890 .slave = &dra7xx_i2c1_hwmod,
2891 .clk = "l3_iclk_div",
2892 .user = OCP_USER_MPU | OCP_USER_SDMA,
2893 };
2895 /* l4_per1 -> i2c2 */
2896 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
2897 .master = &dra7xx_l4_per1_hwmod,
2898 .slave = &dra7xx_i2c2_hwmod,
2899 .clk = "l3_iclk_div",
2900 .user = OCP_USER_MPU | OCP_USER_SDMA,
2901 };
2903 /* l4_per1 -> i2c3 */
2904 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
2905 .master = &dra7xx_l4_per1_hwmod,
2906 .slave = &dra7xx_i2c3_hwmod,
2907 .clk = "l3_iclk_div",
2908 .user = OCP_USER_MPU | OCP_USER_SDMA,
2909 };
2911 /* l4_per1 -> i2c4 */
2912 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
2913 .master = &dra7xx_l4_per1_hwmod,
2914 .slave = &dra7xx_i2c4_hwmod,
2915 .clk = "l3_iclk_div",
2916 .user = OCP_USER_MPU | OCP_USER_SDMA,
2917 };
2919 /* l4_per1 -> i2c5 */
2920 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
2921 .master = &dra7xx_l4_per1_hwmod,
2922 .slave = &dra7xx_i2c5_hwmod,
2923 .clk = "l3_iclk_div",
2924 .user = OCP_USER_MPU | OCP_USER_SDMA,
2925 };
2927 /* ipu1 -> l3_main_1 */
2928 static struct omap_hwmod_ocp_if dra7xx_ipu1__l3_main_1 = {
2929 .master = &dra7xx_ipu1_hwmod,
2930 .slave = &dra7xx_l3_main_1_hwmod,
2931 .clk = "l3_iclk_div",
2932 .user = OCP_USER_MPU | OCP_USER_SDMA,
2933 };
2935 /* ipu2 -> l3_main_1 */
2936 static struct omap_hwmod_ocp_if dra7xx_ipu2__l3_main_1 = {
2937 .master = &dra7xx_ipu2_hwmod,
2938 .slave = &dra7xx_l3_main_1_hwmod,
2939 .clk = "l3_iclk_div",
2940 .user = OCP_USER_MPU | OCP_USER_SDMA,
2941 };
2943 /* l4_cfg -> mailbox1 */
2944 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
2945 .master = &dra7xx_l4_cfg_hwmod,
2946 .slave = &dra7xx_mailbox1_hwmod,
2947 .clk = "l3_iclk_div",
2948 .user = OCP_USER_MPU | OCP_USER_SDMA,
2949 };
2951 /* l4_per3 -> mailbox2 */
2952 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
2953 .master = &dra7xx_l4_per3_hwmod,
2954 .slave = &dra7xx_mailbox2_hwmod,
2955 .clk = "l3_iclk_div",
2956 .user = OCP_USER_MPU | OCP_USER_SDMA,
2957 };
2959 /* l4_per3 -> mailbox3 */
2960 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
2961 .master = &dra7xx_l4_per3_hwmod,
2962 .slave = &dra7xx_mailbox3_hwmod,
2963 .clk = "l3_iclk_div",
2964 .user = OCP_USER_MPU | OCP_USER_SDMA,
2965 };
2967 /* l4_per3 -> mailbox4 */
2968 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
2969 .master = &dra7xx_l4_per3_hwmod,
2970 .slave = &dra7xx_mailbox4_hwmod,
2971 .clk = "l3_iclk_div",
2972 .user = OCP_USER_MPU | OCP_USER_SDMA,
2973 };
2975 /* l4_per3 -> mailbox5 */
2976 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
2977 .master = &dra7xx_l4_per3_hwmod,
2978 .slave = &dra7xx_mailbox5_hwmod,
2979 .clk = "l3_iclk_div",
2980 .user = OCP_USER_MPU | OCP_USER_SDMA,
2981 };
2983 /* l4_per3 -> mailbox6 */
2984 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
2985 .master = &dra7xx_l4_per3_hwmod,
2986 .slave = &dra7xx_mailbox6_hwmod,
2987 .clk = "l3_iclk_div",
2988 .user = OCP_USER_MPU | OCP_USER_SDMA,
2989 };
2991 /* l4_per3 -> mailbox7 */
2992 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
2993 .master = &dra7xx_l4_per3_hwmod,
2994 .slave = &dra7xx_mailbox7_hwmod,
2995 .clk = "l3_iclk_div",
2996 .user = OCP_USER_MPU | OCP_USER_SDMA,
2997 };
2999 /* l4_per3 -> mailbox8 */
3000 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
3001 .master = &dra7xx_l4_per3_hwmod,
3002 .slave = &dra7xx_mailbox8_hwmod,
3003 .clk = "l3_iclk_div",
3004 .user = OCP_USER_MPU | OCP_USER_SDMA,
3005 };
3007 /* l4_per3 -> mailbox9 */
3008 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
3009 .master = &dra7xx_l4_per3_hwmod,
3010 .slave = &dra7xx_mailbox9_hwmod,
3011 .clk = "l3_iclk_div",
3012 .user = OCP_USER_MPU | OCP_USER_SDMA,
3013 };
3015 /* l4_per3 -> mailbox10 */
3016 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
3017 .master = &dra7xx_l4_per3_hwmod,
3018 .slave = &dra7xx_mailbox10_hwmod,
3019 .clk = "l3_iclk_div",
3020 .user = OCP_USER_MPU | OCP_USER_SDMA,
3021 };
3023 /* l4_per3 -> mailbox11 */
3024 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
3025 .master = &dra7xx_l4_per3_hwmod,
3026 .slave = &dra7xx_mailbox11_hwmod,
3027 .clk = "l3_iclk_div",
3028 .user = OCP_USER_MPU | OCP_USER_SDMA,
3029 };
3031 /* l4_per3 -> mailbox12 */
3032 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
3033 .master = &dra7xx_l4_per3_hwmod,
3034 .slave = &dra7xx_mailbox12_hwmod,
3035 .clk = "l3_iclk_div",
3036 .user = OCP_USER_MPU | OCP_USER_SDMA,
3037 };
3039 /* l4_per3 -> mailbox13 */
3040 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
3041 .master = &dra7xx_l4_per3_hwmod,
3042 .slave = &dra7xx_mailbox13_hwmod,
3043 .clk = "l3_iclk_div",
3044 .user = OCP_USER_MPU | OCP_USER_SDMA,
3045 };
3047 /* l4_per1 -> mcspi1 */
3048 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
3049 .master = &dra7xx_l4_per1_hwmod,
3050 .slave = &dra7xx_mcspi1_hwmod,
3051 .clk = "l3_iclk_div",
3052 .user = OCP_USER_MPU | OCP_USER_SDMA,
3053 };
3055 /* l4_per1 -> mcspi2 */
3056 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
3057 .master = &dra7xx_l4_per1_hwmod,
3058 .slave = &dra7xx_mcspi2_hwmod,
3059 .clk = "l3_iclk_div",
3060 .user = OCP_USER_MPU | OCP_USER_SDMA,
3061 };
3063 /* l4_per1 -> mcspi3 */
3064 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
3065 .master = &dra7xx_l4_per1_hwmod,
3066 .slave = &dra7xx_mcspi3_hwmod,
3067 .clk = "l3_iclk_div",
3068 .user = OCP_USER_MPU | OCP_USER_SDMA,
3069 };
3071 /* l4_per1 -> mcspi4 */
3072 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
3073 .master = &dra7xx_l4_per1_hwmod,
3074 .slave = &dra7xx_mcspi4_hwmod,
3075 .clk = "l3_iclk_div",
3076 .user = OCP_USER_MPU | OCP_USER_SDMA,
3077 };
3079 /* l4_per1 -> mmc1 */
3080 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
3081 .master = &dra7xx_l4_per1_hwmod,
3082 .slave = &dra7xx_mmc1_hwmod,
3083 .clk = "l3_iclk_div",
3084 .user = OCP_USER_MPU | OCP_USER_SDMA,
3085 };
3087 /* l4_per1 -> mmc2 */
3088 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
3089 .master = &dra7xx_l4_per1_hwmod,
3090 .slave = &dra7xx_mmc2_hwmod,
3091 .clk = "l3_iclk_div",
3092 .user = OCP_USER_MPU | OCP_USER_SDMA,
3093 };
3095 /* l4_per1 -> mmc3 */
3096 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
3097 .master = &dra7xx_l4_per1_hwmod,
3098 .slave = &dra7xx_mmc3_hwmod,
3099 .clk = "l3_iclk_div",
3100 .user = OCP_USER_MPU | OCP_USER_SDMA,
3101 };
3103 /* l4_per1 -> mmc4 */
3104 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
3105 .master = &dra7xx_l4_per1_hwmod,
3106 .slave = &dra7xx_mmc4_hwmod,
3107 .clk = "l3_iclk_div",
3108 .user = OCP_USER_MPU | OCP_USER_SDMA,
3109 };
3111 /* l4_cfg -> mpu */
3112 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
3113 .master = &dra7xx_l4_cfg_hwmod,
3114 .slave = &dra7xx_mpu_hwmod,
3115 .clk = "l3_iclk_div",
3116 .user = OCP_USER_MPU | OCP_USER_SDMA,
3117 };
3119 /* l4_cfg -> ocp2scp1 */
3120 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
3121 .master = &dra7xx_l4_cfg_hwmod,
3122 .slave = &dra7xx_ocp2scp1_hwmod,
3123 .clk = "l4_root_clk_div",
3124 .user = OCP_USER_MPU | OCP_USER_SDMA,
3125 };
3127 /* l4_cfg -> pruss1 */
3128 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pruss1 = {
3129 .master = &dra7xx_l4_cfg_hwmod,
3130 .slave = &dra7xx_pruss1_hwmod,
3131 .clk = "dpll_gmac_h13x2_ck",
3132 .user = OCP_USER_MPU | OCP_USER_SDMA,
3133 };
3135 /* l4_cfg -> pruss2 */
3136 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pruss2 = {
3137 .master = &dra7xx_l4_cfg_hwmod,
3138 .slave = &dra7xx_pruss2_hwmod,
3139 .clk = "dpll_gmac_h13x2_ck",
3140 .user = OCP_USER_MPU | OCP_USER_SDMA,
3141 };
3143 static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
3144 {
3145 .pa_start = 0x4b300000,
3146 .pa_end = 0x4b30007f,
3147 .flags = ADDR_TYPE_RT
3148 },
3149 { }
3150 };
3152 /* l3_main_1 -> qspi */
3153 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
3154 .master = &dra7xx_l3_main_1_hwmod,
3155 .slave = &dra7xx_qspi_hwmod,
3156 .clk = "l3_iclk_div",
3157 .addr = dra7xx_qspi_addrs,
3158 .user = OCP_USER_MPU | OCP_USER_SDMA,
3159 };
3161 /* l4_per3 -> rtcss */
3162 static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
3163 .master = &dra7xx_l4_per3_hwmod,
3164 .slave = &dra7xx_rtcss_hwmod,
3165 .clk = "l4_root_clk_div",
3166 .user = OCP_USER_MPU | OCP_USER_SDMA,
3167 };
3169 static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
3170 {
3171 .name = "sysc",
3172 .pa_start = 0x4a141100,
3173 .pa_end = 0x4a141107,
3174 .flags = ADDR_TYPE_RT
3175 },
3176 { }
3177 };
3179 /* l4_cfg -> sata */
3180 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
3181 .master = &dra7xx_l4_cfg_hwmod,
3182 .slave = &dra7xx_sata_hwmod,
3183 .clk = "l3_iclk_div",
3184 .addr = dra7xx_sata_addrs,
3185 .user = OCP_USER_MPU | OCP_USER_SDMA,
3186 };
3188 static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
3189 {
3190 .pa_start = 0x4a0dd000,
3191 .pa_end = 0x4a0dd07f,
3192 .flags = ADDR_TYPE_RT
3193 },
3194 { }
3195 };
3197 /* l4_cfg -> smartreflex_core */
3198 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
3199 .master = &dra7xx_l4_cfg_hwmod,
3200 .slave = &dra7xx_smartreflex_core_hwmod,
3201 .clk = "l4_root_clk_div",
3202 .addr = dra7xx_smartreflex_core_addrs,
3203 .user = OCP_USER_MPU | OCP_USER_SDMA,
3204 };
3206 static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
3207 {
3208 .pa_start = 0x4a0d9000,
3209 .pa_end = 0x4a0d907f,
3210 .flags = ADDR_TYPE_RT
3211 },
3212 { }
3213 };
3215 /* l4_cfg -> smartreflex_mpu */
3216 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
3217 .master = &dra7xx_l4_cfg_hwmod,
3218 .slave = &dra7xx_smartreflex_mpu_hwmod,
3219 .clk = "l4_root_clk_div",
3220 .addr = dra7xx_smartreflex_mpu_addrs,
3221 .user = OCP_USER_MPU | OCP_USER_SDMA,
3222 };
3224 static struct omap_hwmod_addr_space dra7xx_spinlock_addrs[] = {
3225 {
3226 .pa_start = 0x4a0f6000,
3227 .pa_end = 0x4a0f6fff,
3228 .flags = ADDR_TYPE_RT
3229 },
3230 { }
3231 };
3233 /* l4_cfg -> spinlock */
3234 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
3235 .master = &dra7xx_l4_cfg_hwmod,
3236 .slave = &dra7xx_spinlock_hwmod,
3237 .clk = "l3_iclk_div",
3238 .addr = dra7xx_spinlock_addrs,
3239 .user = OCP_USER_MPU | OCP_USER_SDMA,
3240 };
3242 /* l4_wkup -> timer1 */
3243 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
3244 .master = &dra7xx_l4_wkup_hwmod,
3245 .slave = &dra7xx_timer1_hwmod,
3246 .clk = "wkupaon_iclk_mux",
3247 .user = OCP_USER_MPU | OCP_USER_SDMA,
3248 };
3250 /* l4_per1 -> timer2 */
3251 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
3252 .master = &dra7xx_l4_per1_hwmod,
3253 .slave = &dra7xx_timer2_hwmod,
3254 .clk = "l3_iclk_div",
3255 .user = OCP_USER_MPU | OCP_USER_SDMA,
3256 };
3258 /* l4_per1 -> timer3 */
3259 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
3260 .master = &dra7xx_l4_per1_hwmod,
3261 .slave = &dra7xx_timer3_hwmod,
3262 .clk = "l3_iclk_div",
3263 .user = OCP_USER_MPU | OCP_USER_SDMA,
3264 };
3266 /* l4_per1 -> timer4 */
3267 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
3268 .master = &dra7xx_l4_per1_hwmod,
3269 .slave = &dra7xx_timer4_hwmod,
3270 .clk = "l3_iclk_div",
3271 .user = OCP_USER_MPU | OCP_USER_SDMA,
3272 };
3274 /* l4_per3 -> timer5 */
3275 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
3276 .master = &dra7xx_l4_per3_hwmod,
3277 .slave = &dra7xx_timer5_hwmod,
3278 .clk = "l3_iclk_div",
3279 .user = OCP_USER_MPU | OCP_USER_SDMA,
3280 };
3282 /* l4_per3 -> timer6 */
3283 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
3284 .master = &dra7xx_l4_per3_hwmod,
3285 .slave = &dra7xx_timer6_hwmod,
3286 .clk = "l3_iclk_div",
3287 .user = OCP_USER_MPU | OCP_USER_SDMA,
3288 };
3290 /* l4_per3 -> timer7 */
3291 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
3292 .master = &dra7xx_l4_per3_hwmod,
3293 .slave = &dra7xx_timer7_hwmod,
3294 .clk = "l3_iclk_div",
3295 .user = OCP_USER_MPU | OCP_USER_SDMA,
3296 };
3298 /* l4_per3 -> timer8 */
3299 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
3300 .master = &dra7xx_l4_per3_hwmod,
3301 .slave = &dra7xx_timer8_hwmod,
3302 .clk = "l3_iclk_div",
3303 .user = OCP_USER_MPU | OCP_USER_SDMA,
3304 };
3306 /* l4_per1 -> timer9 */
3307 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
3308 .master = &dra7xx_l4_per1_hwmod,
3309 .slave = &dra7xx_timer9_hwmod,
3310 .clk = "l3_iclk_div",
3311 .user = OCP_USER_MPU | OCP_USER_SDMA,
3312 };
3314 /* l4_per1 -> timer10 */
3315 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
3316 .master = &dra7xx_l4_per1_hwmod,
3317 .slave = &dra7xx_timer10_hwmod,
3318 .clk = "l3_iclk_div",
3319 .user = OCP_USER_MPU | OCP_USER_SDMA,
3320 };
3322 /* l4_per1 -> timer11 */
3323 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
3324 .master = &dra7xx_l4_per1_hwmod,
3325 .slave = &dra7xx_timer11_hwmod,
3326 .clk = "l3_iclk_div",
3327 .user = OCP_USER_MPU | OCP_USER_SDMA,
3328 };
3330 /* l4_per1 -> uart1 */
3331 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
3332 .master = &dra7xx_l4_per1_hwmod,
3333 .slave = &dra7xx_uart1_hwmod,
3334 .clk = "l3_iclk_div",
3335 .user = OCP_USER_MPU | OCP_USER_SDMA,
3336 };
3338 /* l4_per1 -> uart2 */
3339 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
3340 .master = &dra7xx_l4_per1_hwmod,
3341 .slave = &dra7xx_uart2_hwmod,
3342 .clk = "l3_iclk_div",
3343 .user = OCP_USER_MPU | OCP_USER_SDMA,
3344 };
3346 /* l4_per1 -> uart3 */
3347 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
3348 .master = &dra7xx_l4_per1_hwmod,
3349 .slave = &dra7xx_uart3_hwmod,
3350 .clk = "l3_iclk_div",
3351 .user = OCP_USER_MPU | OCP_USER_SDMA,
3352 };
3354 /* l4_per1 -> uart4 */
3355 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
3356 .master = &dra7xx_l4_per1_hwmod,
3357 .slave = &dra7xx_uart4_hwmod,
3358 .clk = "l3_iclk_div",
3359 .user = OCP_USER_MPU | OCP_USER_SDMA,
3360 };
3362 /* l4_per1 -> uart5 */
3363 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
3364 .master = &dra7xx_l4_per1_hwmod,
3365 .slave = &dra7xx_uart5_hwmod,
3366 .clk = "l3_iclk_div",
3367 .user = OCP_USER_MPU | OCP_USER_SDMA,
3368 };
3370 /* l4_per1 -> uart6 */
3371 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
3372 .master = &dra7xx_l4_per1_hwmod,
3373 .slave = &dra7xx_uart6_hwmod,
3374 .clk = "l3_iclk_div",
3375 .user = OCP_USER_MPU | OCP_USER_SDMA,
3376 };
3378 /* l4_per1 -> des */
3379 static struct omap_hwmod_ocp_if dra7xx_l4_per1__des = {
3380 .master = &dra7xx_l4_per1_hwmod,
3381 .slave = &dra7xx_des_hwmod,
3382 .clk = "l3_iclk_div",
3383 .user = OCP_USER_MPU | OCP_USER_SDMA,
3384 };
3386 /* l4_per1 -> rng */
3387 static struct omap_hwmod_ocp_if dra7xx_l4_per1__rng = {
3388 .master = &dra7xx_l4_per1_hwmod,
3389 .slave = &dra7xx_rng_hwmod,
3390 .user = OCP_USER_MPU,
3391 };
3393 /* l4_per3 -> usb_otg_ss1 */
3394 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
3395 .master = &dra7xx_l4_per3_hwmod,
3396 .slave = &dra7xx_usb_otg_ss1_hwmod,
3397 .clk = "dpll_core_h13x2_ck",
3398 .user = OCP_USER_MPU | OCP_USER_SDMA,
3399 };
3401 /* l4_per3 -> usb_otg_ss2 */
3402 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
3403 .master = &dra7xx_l4_per3_hwmod,
3404 .slave = &dra7xx_usb_otg_ss2_hwmod,
3405 .clk = "dpll_core_h13x2_ck",
3406 .user = OCP_USER_MPU | OCP_USER_SDMA,
3407 };
3409 /* l4_per3 -> usb_otg_ss3 */
3410 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
3411 .master = &dra7xx_l4_per3_hwmod,
3412 .slave = &dra7xx_usb_otg_ss3_hwmod,
3413 .clk = "dpll_core_h13x2_ck",
3414 .user = OCP_USER_MPU | OCP_USER_SDMA,
3415 };
3417 /* l4_per3 -> usb_otg_ss4 */
3418 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
3419 .master = &dra7xx_l4_per3_hwmod,
3420 .slave = &dra7xx_usb_otg_ss4_hwmod,
3421 .clk = "dpll_core_h13x2_ck",
3422 .user = OCP_USER_MPU | OCP_USER_SDMA,
3423 };
3425 /* l3_main_1 -> vcp1 */
3426 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
3427 .master = &dra7xx_l3_main_1_hwmod,
3428 .slave = &dra7xx_vcp1_hwmod,
3429 .clk = "l3_iclk_div",
3430 .user = OCP_USER_MPU | OCP_USER_SDMA,
3431 };
3433 /* l4_per2 -> vcp1 */
3434 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
3435 .master = &dra7xx_l4_per2_hwmod,
3436 .slave = &dra7xx_vcp1_hwmod,
3437 .clk = "l3_iclk_div",
3438 .user = OCP_USER_MPU | OCP_USER_SDMA,
3439 };
3441 /* l3_main_1 -> vcp2 */
3442 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
3443 .master = &dra7xx_l3_main_1_hwmod,
3444 .slave = &dra7xx_vcp2_hwmod,
3445 .clk = "l3_iclk_div",
3446 .user = OCP_USER_MPU | OCP_USER_SDMA,
3447 };
3449 /* l4_per2 -> vcp2 */
3450 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
3451 .master = &dra7xx_l4_per2_hwmod,
3452 .slave = &dra7xx_vcp2_hwmod,
3453 .clk = "l3_iclk_div",
3454 .user = OCP_USER_MPU | OCP_USER_SDMA,
3455 };
3457 /* l4_wkup -> wd_timer2 */
3458 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
3459 .master = &dra7xx_l4_wkup_hwmod,
3460 .slave = &dra7xx_wd_timer2_hwmod,
3461 .clk = "wkupaon_iclk_mux",
3462 .user = OCP_USER_MPU | OCP_USER_SDMA,
3463 };
3465 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
3466 &dra7xx_l3_main_2__l3_instr,
3467 &dra7xx_l4_cfg__l3_main_1,
3468 &dra7xx_mpu__l3_main_1,
3469 &dra7xx_l3_main_1__l3_main_2,
3470 &dra7xx_l4_cfg__l3_main_2,
3471 &dra7xx_l3_main_1__l4_cfg,
3472 &dra7xx_l3_main_1__l4_per1,
3473 &dra7xx_l3_main_1__l4_per2,
3474 &dra7xx_l3_main_1__l4_per3,
3475 &dra7xx_l3_main_1__l4_wkup,
3476 &dra7xx_l4_per2__atl,
3477 &dra7xx_l3_main_1__bb2d,
3478 &dra7xx_l4_wkup__counter_32k,
3479 &dra7xx_l4_wkup__ctrl_module_wkup,
3480 &dra7xx_l4_wkup__dcan1,
3481 &dra7xx_l4_per2__dcan2,
3482 &dra7xx_l4_cfg__dma_system,
3483 &dra7xx_l3_main_1__dss,
3484 &dra7xx_l3_main_1__dispc,
3485 &dra7xx_dsp1__l3_main_1,
3486 &dra7xx_l3_main_1__hdmi,
3487 &dra7xx_l3_main_1__aes,
3488 &dra7xx_l3_main_1__sha0,
3489 &dra7xx_l4_per1__elm,
3490 &dra7xx_l4_wkup__gpio1,
3491 &dra7xx_l4_per1__gpio2,
3492 &dra7xx_l4_per1__gpio3,
3493 &dra7xx_l4_per1__gpio4,
3494 &dra7xx_l4_per1__gpio5,
3495 &dra7xx_l4_per1__gpio6,
3496 &dra7xx_l4_per1__gpio7,
3497 &dra7xx_l4_per1__gpio8,
3498 &dra7xx_l3_main_1__gpmc,
3499 &dra7xx_l4_per1__hdq1w,
3500 &dra7xx_l4_per1__i2c1,
3501 &dra7xx_l4_per1__i2c2,
3502 &dra7xx_l4_per1__i2c3,
3503 &dra7xx_l4_per1__i2c4,
3504 &dra7xx_l4_per1__i2c5,
3505 &dra7xx_ipu1__l3_main_1,
3506 &dra7xx_ipu2__l3_main_1,
3507 &dra7xx_l4_cfg__mailbox1,
3508 &dra7xx_l4_per3__mailbox2,
3509 &dra7xx_l4_per3__mailbox3,
3510 &dra7xx_l4_per3__mailbox4,
3511 &dra7xx_l4_per3__mailbox5,
3512 &dra7xx_l4_per3__mailbox6,
3513 &dra7xx_l4_per3__mailbox7,
3514 &dra7xx_l4_per3__mailbox8,
3515 &dra7xx_l4_per3__mailbox9,
3516 &dra7xx_l4_per3__mailbox10,
3517 &dra7xx_l4_per3__mailbox11,
3518 &dra7xx_l4_per3__mailbox12,
3519 &dra7xx_l4_per3__mailbox13,
3520 &dra7xx_l4_per1__mcspi1,
3521 &dra7xx_l4_per1__mcspi2,
3522 &dra7xx_l4_per1__mcspi3,
3523 &dra7xx_l4_per1__mcspi4,
3524 &dra7xx_l4_per1__mmc1,
3525 &dra7xx_l4_per1__mmc2,
3526 &dra7xx_l4_per1__mmc3,
3527 &dra7xx_l4_per1__mmc4,
3528 &dra7xx_l3_main_1__mmu0_dsp1,
3529 &dra7xx_l3_main_1__mmu1_dsp1,
3530 &dra7xx_l3_main_1__mmu_ipu1,
3531 &dra7xx_l3_main_1__mmu_ipu2,
3532 &dra7xx_l4_cfg__mpu,
3533 &dra7xx_l4_cfg__ocp2scp1,
3534 &dra7xx_l4_cfg__pruss1, /* AM57xx only */
3535 &dra7xx_l4_cfg__pruss2, /* AM57xx only */
3536 &dra7xx_l3_main_1__qspi,
3537 &dra7xx_l4_per3__rtcss,
3538 &dra7xx_l4_cfg__sata,
3539 &dra7xx_l4_cfg__smartreflex_core,
3540 &dra7xx_l4_cfg__smartreflex_mpu,
3541 &dra7xx_l4_cfg__spinlock,
3542 &dra7xx_l4_wkup__timer1,
3543 &dra7xx_l4_per1__timer2,
3544 &dra7xx_l4_per1__timer3,
3545 &dra7xx_l4_per1__timer4,
3546 &dra7xx_l4_per3__timer5,
3547 &dra7xx_l4_per3__timer6,
3548 &dra7xx_l4_per3__timer7,
3549 &dra7xx_l4_per3__timer8,
3550 &dra7xx_l4_per1__timer9,
3551 &dra7xx_l4_per1__timer10,
3552 &dra7xx_l4_per1__timer11,
3553 &dra7xx_l4_per1__uart1,
3554 &dra7xx_l4_per1__uart2,
3555 &dra7xx_l4_per1__uart3,
3556 &dra7xx_l4_per1__uart4,
3557 &dra7xx_l4_per1__uart5,
3558 &dra7xx_l4_per1__uart6,
3559 &dra7xx_l4_per1__des,
3560 &dra7xx_l4_per1__rng,
3561 &dra7xx_l4_per3__usb_otg_ss1,
3562 &dra7xx_l4_per3__usb_otg_ss2,
3563 &dra7xx_l4_per3__usb_otg_ss3,
3564 &dra7xx_l3_main_1__vcp1,
3565 &dra7xx_l4_per2__vcp1,
3566 &dra7xx_l3_main_1__vcp2,
3567 &dra7xx_l4_per2__vcp2,
3568 &dra7xx_l4_wkup__wd_timer2,
3569 NULL,
3570 };
3572 static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
3573 &dra7xx_l4_per3__usb_otg_ss4,
3574 &dra7xx_l3_main_1__mmu0_dsp2,
3575 &dra7xx_l3_main_1__mmu1_dsp2,
3576 &dra7xx_dsp2__l3_main_1,
3577 NULL,
3578 };
3580 static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
3581 NULL,
3582 };
3584 int __init dra7xx_hwmod_init(void)
3585 {
3586 int ret;
3588 omap_hwmod_init();
3589 ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
3591 if (!ret && soc_is_dra74x())
3592 return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
3593 else if (!ret && soc_is_dra72x())
3594 return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
3596 return ret;
3597 }