Merge remote-tracking branch 'origin/omaplfb' into p-ti-android-3.8.y-video
[android-sdk/kernel-video.git] / arch / arm / mach-omap2 / omap_hwmod_7xx_data.c
1 /*
2  * Hardware modules present on the DRA7xx chips
3  *
4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5  *
6  * Paul Walmsley
7  * Benoit Cousson
8  *
9  * This file is automatically generated from the OMAP hardware databases.
10  * We respectfully ask that any modifications to this file be coordinated
11  * with the public linux-omap@vger.kernel.org mailing list and the
12  * authors above to ensure that the autogeneration scripts are kept
13  * up-to-date with the file contents.
14  *
15  * This program is free software; you can redistribute it and/or modify
16  * it under the terms of the GNU General Public License version 2 as
17  * published by the Free Software Foundation.
18  */
20 #include <linux/io.h>
21 #include <linux/platform_data/gpio-omap.h>
22 #include <linux/power/smartreflex.h>
23 #include <linux/platform_data/omap_ocp2scp.h>
24 #include <linux/i2c-omap.h>
26 #include <linux/omap-dma.h>
27 #include <linux/platform_data/spi-omap2-mcspi.h>
28 #include <linux/platform_data/asoc-ti-mcbsp.h>
29 #include <plat/dmtimer.h>
31 #include "omap_hwmod.h"
32 #include "omap_hwmod_common_data.h"
33 #include "cm1_7xx.h"
34 #include "cm2_7xx.h"
35 #include "prm7xx.h"
36 #include "prm-regbits-7xx.h"
37 #include "i2c.h"
38 #include "mmc.h"
39 #include "wd_timer.h"
41 /* Base offset for all DRA7XX interrupts external to MPUSS */
42 #define DRA7XX_IRQ_GIC_START    32
44 /* Base offset for all DRA7XX dma requests */
45 #define DRA7XX_DMA_REQ_START    1
48 /*
49  * IP blocks
50  */
52 /*
53  * 'dmm' class
54  * instance(s): dmm
55  */
56 static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
57         .name   = "dmm",
58 };
60 /* dmm */
61 static struct omap_hwmod_irq_info dra7xx_dmm_irqs[] = {
62         { .irq = 113 + DRA7XX_IRQ_GIC_START },
63         { .irq = -1 }
64 };
66 static struct omap_hwmod dra7xx_dmm_hwmod = {
67         .name           = "dmm",
68         .class          = &dra7xx_dmm_hwmod_class,
69         .clkdm_name     = "emif_clkdm",
70         .mpu_irqs       = dra7xx_dmm_irqs,
71         .prcm = {
72                 .omap4 = {
73                         .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
74                         .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
75                 },
76         },
77 };
79 /*
80  * 'emif_ocp_fw' class
81  * instance(s): emif_ocp_fw
82  */
83 static struct omap_hwmod_class dra7xx_emif_ocp_fw_hwmod_class = {
84         .name   = "emif_ocp_fw",
85 };
87 /* emif_ocp_fw */
88 static struct omap_hwmod dra7xx_emif_ocp_fw_hwmod = {
89         .name           = "emif_ocp_fw",
90         .class          = &dra7xx_emif_ocp_fw_hwmod_class,
91         .clkdm_name     = "emif_clkdm",
92         .prcm = {
93                 .omap4 = {
94                         .clkctrl_offs = DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET,
95                         .context_offs = DRA7XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET,
96                 },
97         },
98 };
100 /*
101  * 'l3' class
102  * instance(s): l3_instr, l3_main_1, l3_main_2
103  */
104 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
105         .name   = "l3",
106 };
108 /* l3_instr */
109 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
110         .name           = "l3_instr",
111         .class          = &dra7xx_l3_hwmod_class,
112         .clkdm_name     = "l3instr_clkdm",
113         .prcm = {
114                 .omap4 = {
115                         .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
116                         .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
117                         .modulemode   = MODULEMODE_HWCTRL,
118                 },
119         },
120 };
122 /* l3_main_1 */
123 static struct omap_hwmod_irq_info dra7xx_l3_main_1_irqs[] = {
124         { .name = "dbg_err", .irq = 9 + DRA7XX_IRQ_GIC_START },
125         { .name = "app_err", .irq = 10 + DRA7XX_IRQ_GIC_START },
126         { .name = "stat_alarm", .irq = 16 + DRA7XX_IRQ_GIC_START },
127         { .irq = -1 }
128 };
130 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
131         .name           = "l3_main_1",
132         .class          = &dra7xx_l3_hwmod_class,
133         .clkdm_name     = "l3main1_clkdm",
134         .mpu_irqs       = dra7xx_l3_main_1_irqs,
135         .prcm = {
136                 .omap4 = {
137                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
138                         .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
139                 },
140         },
141 };
143 /* l3_main_2 */
144 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
145         .name           = "l3_main_2",
146         .class          = &dra7xx_l3_hwmod_class,
147         .clkdm_name     = "l3instr_clkdm",
148         .prcm = {
149                 .omap4 = {
150                         .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
151                         .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
152                         .modulemode   = MODULEMODE_HWCTRL,
153                 },
154         },
155 };
157 /*
158  * 'l4' class
159  * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
160  */
161 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
162         .name   = "l4",
163 };
165 /* l4_cfg */
166 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
167         .name           = "l4_cfg",
168         .class          = &dra7xx_l4_hwmod_class,
169         .clkdm_name     = "l4cfg_clkdm",
170         .prcm = {
171                 .omap4 = {
172                         .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
173                         .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
174                 },
175         },
176 };
178 /* l4_per1 */
179 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
180         .name           = "l4_per1",
181         .class          = &dra7xx_l4_hwmod_class,
182         .clkdm_name     = "l4per_clkdm",
183         .prcm = {
184                 .omap4 = {
185                         .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
186                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
187                 },
188         },
189 };
191 /* l4_per2 */
192 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
193         .name           = "l4_per2",
194         .class          = &dra7xx_l4_hwmod_class,
195         .clkdm_name     = "l4per2_clkdm",
196         .prcm = {
197                 .omap4 = {
198                         .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
199                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
200                 },
201         },
202 };
204 /* l4_per3 */
205 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
206         .name           = "l4_per3",
207         .class          = &dra7xx_l4_hwmod_class,
208         .clkdm_name     = "l4per3_clkdm",
209         .prcm = {
210                 .omap4 = {
211                         .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
212                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
213                 },
214         },
215 };
217 /* l4_wkup */
218 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
219         .name           = "l4_wkup",
220         .class          = &dra7xx_l4_hwmod_class,
221         .clkdm_name     = "wkupaon_clkdm",
222         .prcm = {
223                 .omap4 = {
224                         .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
225                         .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
226                 },
227         },
228 };
230 /*
231  * 'mpu_bus' class
232  * instance(s): mpu_private
233  */
234 static struct omap_hwmod_class dra7xx_mpu_bus_hwmod_class = {
235         .name   = "mpu_bus",
236 };
238 /* mpu_private */
239 static struct omap_hwmod dra7xx_mpu_private_hwmod = {
240         .name           = "mpu_private",
241         .class          = &dra7xx_mpu_bus_hwmod_class,
242         .clkdm_name     = "mpu_clkdm",
243         .prcm = {
244                 .omap4 = {
245                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
246                 },
247         },
248 };
250 /*
251  * 'ocp_wp_noc' class
252  * instance(s): ocp_wp_noc
253  */
254 static struct omap_hwmod_class dra7xx_ocp_wp_noc_hwmod_class = {
255         .name   = "ocp_wp_noc",
256 };
258 /* ocp_wp_noc */
259 static struct omap_hwmod dra7xx_ocp_wp_noc_hwmod = {
260         .name           = "ocp_wp_noc",
261         .class          = &dra7xx_ocp_wp_noc_hwmod_class,
262         .clkdm_name     = "l3instr_clkdm",
263         .prcm = {
264                 .omap4 = {
265                         .clkctrl_offs = DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET,
266                         .context_offs = DRA7XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET,
267                         .modulemode   = MODULEMODE_HWCTRL,
268                 },
269         },
270 };
272 /*
273  * 'atl' class
274  *
275  */
277 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
278         .name   = "atl",
279 };
281 /* atl */
282 static struct omap_hwmod dra7xx_atl_hwmod = {
283         .name           = "atl",
284         .class          = &dra7xx_atl_hwmod_class,
285         .clkdm_name     = "atl_clkdm",
286         .main_clk       = "atl_gfclk_mux",
287         .prcm = {
288                 .omap4 = {
289                         .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
290                         .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
291                         .modulemode   = MODULEMODE_SWCTRL,
292                 },
293         },
294 };
296 /*
297  * 'bb2d' class
298  *
299  */
301 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
302         .name   = "bb2d",
303 };
305 /* bb2d */
306 static struct omap_hwmod_irq_info dra7xx_bb2d_irqs[] = {
307         { .irq = 125 + DRA7XX_IRQ_GIC_START },
308         { .irq = -1 }
309 };
311 static struct omap_hwmod dra7xx_bb2d_hwmod = {
312         .name           = "bb2d",
313         .class          = &dra7xx_bb2d_hwmod_class,
314         .clkdm_name     = "dss_clkdm",
315         .mpu_irqs       = dra7xx_bb2d_irqs,
316         .main_clk       = "dpll_core_h24x2_ck",
317         .prcm = {
318                 .omap4 = {
319                         .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
320                         .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
321                         .modulemode   = MODULEMODE_SWCTRL,
322                 },
323         },
324 };
326 /*
327  * 'counter' class
328  *
329  */
331 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
332         .rev_offs       = 0x0000,
333         .sysc_offs      = 0x0010,
334         .sysc_flags     = SYSC_HAS_SIDLEMODE,
335         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
336                            SIDLE_SMART_WKUP),
337         .sysc_fields    = &omap_hwmod_sysc_type1,
338 };
340 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
341         .name   = "counter",
342         .sysc   = &dra7xx_counter_sysc,
343 };
345 /* counter_32k */
346 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
347         .name           = "counter_32k",
348         .class          = &dra7xx_counter_hwmod_class,
349         .clkdm_name     = "wkupaon_clkdm",
350         .flags          = HWMOD_SWSUP_SIDLE,
351         .main_clk       = "wkupaon_iclk_mux",
352         .prcm = {
353                 .omap4 = {
354                         .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
355                         .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
356                 },
357         },
358 };
360 /*
361  * 'ctrl_module' class
362  *
363  */
365 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
366         .name   = "ctrl_module",
367 };
369 /* ctrl_module_wkup */
370 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
371         .name           = "ctrl_module_wkup",
372         .class          = &dra7xx_ctrl_module_hwmod_class,
373         .clkdm_name     = "wkupaon_clkdm",
374         .prcm = {
375                 .omap4 = {
376                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
377                 },
378         },
379 };
381 /*
382  * 'dcan' class
383  *
384  */
386 static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
387         .name   = "dcan",
388 };
390 /* dcan1 */
391 static struct omap_hwmod dra7xx_dcan1_hwmod = {
392         .name           = "dcan1",
393         .class          = &dra7xx_dcan_hwmod_class,
394         .clkdm_name     = "wkupaon_clkdm",
395         .main_clk       = "dcan1_sys_clk_mux",
396         .prcm = {
397                 .omap4 = {
398                         .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
399                         .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
400                         .modulemode   = MODULEMODE_SWCTRL,
401                 },
402         },
403 };
405 /* dcan2 */
406 static struct omap_hwmod dra7xx_dcan2_hwmod = {
407         .name           = "dcan2",
408         .class          = &dra7xx_dcan_hwmod_class,
409         .clkdm_name     = "l4per2_clkdm",
410         .main_clk       = "sys_clkin1",
411         .prcm = {
412                 .omap4 = {
413                         .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
414                         .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
415                         .modulemode   = MODULEMODE_SWCTRL,
416                 },
417         },
418 };
420 /*
421  * 'dma' class
422  *
423  */
425 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
426         .rev_offs       = 0x0000,
427         .sysc_offs      = 0x002c,
428         .syss_offs      = 0x0028,
429         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
430                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
431                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
432                            SYSS_HAS_RESET_STATUS),
433         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
434                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
435                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
436         .sysc_fields    = &omap_hwmod_sysc_type1,
437 };
439 static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
440         .name   = "dma",
441         .sysc   = &dra7xx_dma_sysc,
442 };
444 /* dma dev_attr */
445 static struct omap_dma_dev_attr dma_dev_attr = {
446         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
447                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
448         .lch_count      = 32,
449 };
451 /* dma_system */
452 static struct omap_hwmod_irq_info dra7xx_dma_system_irqs[] = {
453         { .name = "0", .irq = 12 + DRA7XX_IRQ_GIC_START },
454         { .name = "1", .irq = 13 + DRA7XX_IRQ_GIC_START },
455         { .name = "2", .irq = 14 + DRA7XX_IRQ_GIC_START },
456         { .name = "3", .irq = 15 + DRA7XX_IRQ_GIC_START },
457         { .irq = -1 }
458 };
460 static struct omap_hwmod dra7xx_dma_system_hwmod = {
461         .name           = "dma_system",
462         .class          = &dra7xx_dma_hwmod_class,
463         .clkdm_name     = "dma_clkdm",
464         .mpu_irqs       = dra7xx_dma_system_irqs,
465         .main_clk       = "l3_iclk_div",
466         .prcm = {
467                 .omap4 = {
468                         .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
469                         .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
470                 },
471         },
472         .dev_attr       = &dma_dev_attr,
473 };
475 /*
476  * 'dss' class
477  *
478  */
480 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
481         .rev_offs       = 0x0000,
482         .syss_offs      = 0x0014,
483         .sysc_flags     = SYSS_HAS_RESET_STATUS,
484 };
486 static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
487         .name   = "dss",
488         .sysc   = &dra7xx_dss_sysc,
489         .reset  = omap_dss_reset,
490 };
492 /* dss */
493 static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
494         { .dma_req = 75 + DRA7XX_DMA_REQ_START },
495         { .dma_req = -1 }
496 };
498 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
499         { .role = "dss_clk", .clk = "dss_dss_clk" },
500         { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
501         { .role = "32khz_clk", .clk = "dss_32khz_clk" },
502         { .role = "video2_clk", .clk = "dss_video2_clk" },
503         { .role = "video1_clk", .clk = "dss_video1_clk" },
504         { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
505 };
507 static struct omap_hwmod dra7xx_dss_hwmod = {
508         .name           = "dss_core",
509         .class          = &dra7xx_dss_hwmod_class,
510         .clkdm_name     = "dss_clkdm",
511         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
512         .sdma_reqs      = dra7xx_dss_sdma_reqs,
513         .main_clk       = "dss_dss_clk",
514         .prcm = {
515                 .omap4 = {
516                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
517                         .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
518                         .modulemode   = MODULEMODE_SWCTRL,
519                 },
520         },
521         .opt_clks       = dss_opt_clks,
522         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
523 };
525 /*
526  * 'dispc' class
527  * display controller
528  */
530 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
531         .rev_offs       = 0x0000,
532         .sysc_offs      = 0x0010,
533         .syss_offs      = 0x0014,
534         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
535                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
536                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
537                            SYSS_HAS_RESET_STATUS),
538         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
539                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
540         .sysc_fields    = &omap_hwmod_sysc_type1,
541 };
543 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
544         .name   = "dispc",
545         .sysc   = &dra7xx_dispc_sysc,
546 };
548 /* dss_dispc */
549 static struct omap_hwmod_irq_info dra7xx_dss_dispc_irqs[] = {
550         { .irq = 25 + DRA7XX_IRQ_GIC_START },
551         { .irq = -1 }
552 };
554 static struct omap_hwmod_dma_info dra7xx_dss_dispc_sdma_reqs[] = {
555         { .dma_req = 5 + DRA7XX_DMA_REQ_START },
556         { .dma_req = -1 }
557 };
559 /* dss_dispc dev_attr */
560 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
561         .has_framedonetv_irq    = 1,
562         .manager_count          = 4,
563 };
565 static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
566         .name           = "dss_dispc",
567         .class          = &dra7xx_dispc_hwmod_class,
568         .clkdm_name     = "dss_clkdm",
569         .mpu_irqs       = dra7xx_dss_dispc_irqs,
570         .sdma_reqs      = dra7xx_dss_dispc_sdma_reqs,
571         .main_clk       = "dss_dss_clk",
572         .prcm = {
573                 .omap4 = {
574                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
575                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
576                 },
577         },
578         .dev_attr       = &dss_dispc_dev_attr,
579 };
581 /*
582  * 'hdmi' class
583  * hdmi controller
584  */
586 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
587         .rev_offs       = 0x0000,
588         .sysc_offs      = 0x0010,
589         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
590                            SYSC_HAS_SOFTRESET),
591         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
592                            SIDLE_SMART_WKUP),
593         .sysc_fields    = &omap_hwmod_sysc_type2,
594 };
596 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
597         .name   = "hdmi",
598         .sysc   = &dra7xx_hdmi_sysc,
599 };
601 /* dss_hdmi */
602 static struct omap_hwmod_irq_info dra7xx_dss_hdmi_irqs[] = {
603         { .irq = 101 + DRA7XX_IRQ_GIC_START },
604         { .irq = -1 }
605 };
607 static struct omap_hwmod_dma_info dra7xx_dss_hdmi_sdma_reqs[] = {
608         { .dma_req = 75 + DRA7XX_DMA_REQ_START },
609         { .dma_req = -1 }
610 };
612 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
613         { .role = "sys_clk", .clk = "dss_hdmi_clk" },
614 };
616 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
617         .name           = "dss_hdmi",
618         .class          = &dra7xx_hdmi_hwmod_class,
619         .clkdm_name     = "dss_clkdm",
620         .mpu_irqs       = dra7xx_dss_hdmi_irqs,
621         .sdma_reqs      = dra7xx_dss_hdmi_sdma_reqs,
622         .main_clk       = "dss_48mhz_clk",
623         .prcm = {
624                 .omap4 = {
625                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
626                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
627                 },
628         },
629         .opt_clks       = dss_hdmi_opt_clks,
630         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
631 };
633 /*
634  * 'elm' class
635  *
636  */
638 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
639         .rev_offs       = 0x0000,
640         .sysc_offs      = 0x0010,
641         .syss_offs      = 0x0014,
642         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
643                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
644                            SYSS_HAS_RESET_STATUS),
645         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
646                            SIDLE_SMART_WKUP),
647         .sysc_fields    = &omap_hwmod_sysc_type1,
648 };
650 static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
651         .name   = "elm",
652         .sysc   = &dra7xx_elm_sysc,
653 };
655 /* elm */
656 static struct omap_hwmod_irq_info dra7xx_elm_irqs[] = {
657         { .irq = 4 + DRA7XX_IRQ_GIC_START },
658         { .irq = -1 }
659 };
661 static struct omap_hwmod dra7xx_elm_hwmod = {
662         .name           = "elm",
663         .class          = &dra7xx_elm_hwmod_class,
664         .clkdm_name     = "l4per_clkdm",
665         .mpu_irqs       = dra7xx_elm_irqs,
666         .main_clk       = "l3_iclk_div",
667         .prcm = {
668                 .omap4 = {
669                         .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
670                         .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
671                 },
672         },
673 };
675 /*
676  * 'emif' class
677  *
678  */
680 static struct omap_hwmod_class_sysconfig dra7xx_emif_sysc = {
681         .rev_offs       = 0x0000,
682 };
684 static struct omap_hwmod_class dra7xx_emif_hwmod_class = {
685         .name   = "emif",
686         .sysc   = &dra7xx_emif_sysc,
687 };
689 /* emif1 */
690 static struct omap_hwmod_irq_info dra7xx_emif1_irqs[] = {
691         { .irq = 110 + DRA7XX_IRQ_GIC_START },
692         { .irq = -1 }
693 };
695 static struct omap_hwmod dra7xx_emif1_hwmod = {
696         .name           = "emif1",
697         .class          = &dra7xx_emif_hwmod_class,
698         .clkdm_name     = "emif_clkdm",
699         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
700         .mpu_irqs       = dra7xx_emif1_irqs,
701         .main_clk       = "dpll_ddr_h11x2_ck",
702         .prcm = {
703                 .omap4 = {
704                         .clkctrl_offs = DRA7XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
705                         .context_offs = DRA7XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
706                         .modulemode   = MODULEMODE_HWCTRL,
707                 },
708         },
709 };
711 /* emif2 */
712 static struct omap_hwmod_irq_info dra7xx_emif2_irqs[] = {
713         { .irq = 111 + DRA7XX_IRQ_GIC_START },
714         { .irq = -1 }
715 };
717 static struct omap_hwmod dra7xx_emif2_hwmod = {
718         .name           = "emif2",
719         .class          = &dra7xx_emif_hwmod_class,
720         .clkdm_name     = "emif_clkdm",
721         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
722         .mpu_irqs       = dra7xx_emif2_irqs,
723         .main_clk       = "dpll_ddr_h11x2_ck",
724         .prcm = {
725                 .omap4 = {
726                         .clkctrl_offs = DRA7XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
727                         .context_offs = DRA7XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
728                         .modulemode   = MODULEMODE_HWCTRL,
729                 },
730         },
731 };
733 /*
734  * 'gpio' class
735  *
736  */
738 static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
739         .rev_offs       = 0x0000,
740         .sysc_offs      = 0x0010,
741         .syss_offs      = 0x0114,
742         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
743                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
744                            SYSS_HAS_RESET_STATUS),
745         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
746                            SIDLE_SMART_WKUP),
747         .sysc_fields    = &omap_hwmod_sysc_type1,
748 };
750 static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
751         .name   = "gpio",
752         .sysc   = &dra7xx_gpio_sysc,
753         .rev    = 2,
754 };
756 /* gpio dev_attr */
757 static struct omap_gpio_dev_attr gpio_dev_attr = {
758         .bank_width     = 32,
759         .dbck_flag      = true,
760 };
762 /* gpio1 */
763 static struct omap_hwmod_irq_info dra7xx_gpio1_irqs[] = {
764         { .irq = 29 + DRA7XX_IRQ_GIC_START },
765         { .irq = -1 }
766 };
768 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
769         { .role = "dbclk", .clk = "gpio1_dbclk" },
770 };
772 static struct omap_hwmod dra7xx_gpio1_hwmod = {
773         .name           = "gpio1",
774         .class          = &dra7xx_gpio_hwmod_class,
775         .clkdm_name     = "wkupaon_clkdm",
776         .mpu_irqs       = dra7xx_gpio1_irqs,
777         .main_clk       = "wkupaon_iclk_mux",
778         .prcm = {
779                 .omap4 = {
780                         .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
781                         .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
782                         .modulemode   = MODULEMODE_HWCTRL,
783                 },
784         },
785         .opt_clks       = gpio1_opt_clks,
786         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
787         .dev_attr       = &gpio_dev_attr,
788 };
790 /* gpio2 */
791 static struct omap_hwmod_irq_info dra7xx_gpio2_irqs[] = {
792         { .irq = 30 + DRA7XX_IRQ_GIC_START },
793         { .irq = -1 }
794 };
796 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
797         { .role = "dbclk", .clk = "gpio2_dbclk" },
798 };
800 static struct omap_hwmod dra7xx_gpio2_hwmod = {
801         .name           = "gpio2",
802         .class          = &dra7xx_gpio_hwmod_class,
803         .clkdm_name     = "l4per_clkdm",
804         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
805         .mpu_irqs       = dra7xx_gpio2_irqs,
806         .main_clk       = "l3_iclk_div",
807         .prcm = {
808                 .omap4 = {
809                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
810                         .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
811                         .modulemode   = MODULEMODE_HWCTRL,
812                 },
813         },
814         .opt_clks       = gpio2_opt_clks,
815         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
816         .dev_attr       = &gpio_dev_attr,
817 };
819 /* gpio3 */
820 static struct omap_hwmod_irq_info dra7xx_gpio3_irqs[] = {
821         { .irq = 31 + DRA7XX_IRQ_GIC_START },
822         { .irq = -1 }
823 };
825 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
826         { .role = "dbclk", .clk = "gpio3_dbclk" },
827 };
829 static struct omap_hwmod dra7xx_gpio3_hwmod = {
830         .name           = "gpio3",
831         .class          = &dra7xx_gpio_hwmod_class,
832         .clkdm_name     = "l4per_clkdm",
833         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
834         .mpu_irqs       = dra7xx_gpio3_irqs,
835         .main_clk       = "l3_iclk_div",
836         .prcm = {
837                 .omap4 = {
838                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
839                         .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
840                         .modulemode   = MODULEMODE_HWCTRL,
841                 },
842         },
843         .opt_clks       = gpio3_opt_clks,
844         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
845         .dev_attr       = &gpio_dev_attr,
846 };
848 /* gpio4 */
849 static struct omap_hwmod_irq_info dra7xx_gpio4_irqs[] = {
850         { .irq = 32 + DRA7XX_IRQ_GIC_START },
851         { .irq = -1 }
852 };
854 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
855         { .role = "dbclk", .clk = "gpio4_dbclk" },
856 };
858 static struct omap_hwmod dra7xx_gpio4_hwmod = {
859         .name           = "gpio4",
860         .class          = &dra7xx_gpio_hwmod_class,
861         .clkdm_name     = "l4per_clkdm",
862         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
863         .mpu_irqs       = dra7xx_gpio4_irqs,
864         .main_clk       = "l3_iclk_div",
865         .prcm = {
866                 .omap4 = {
867                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
868                         .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
869                         .modulemode   = MODULEMODE_HWCTRL,
870                 },
871         },
872         .opt_clks       = gpio4_opt_clks,
873         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
874         .dev_attr       = &gpio_dev_attr,
875 };
877 /* gpio5 */
878 static struct omap_hwmod_irq_info dra7xx_gpio5_irqs[] = {
879         { .irq = 33 + DRA7XX_IRQ_GIC_START },
880         { .irq = -1 }
881 };
883 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
884         { .role = "dbclk", .clk = "gpio5_dbclk" },
885 };
887 static struct omap_hwmod dra7xx_gpio5_hwmod = {
888         .name           = "gpio5",
889         .class          = &dra7xx_gpio_hwmod_class,
890         .clkdm_name     = "l4per_clkdm",
891         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
892         .mpu_irqs       = dra7xx_gpio5_irqs,
893         .main_clk       = "l3_iclk_div",
894         .prcm = {
895                 .omap4 = {
896                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
897                         .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
898                         .modulemode   = MODULEMODE_HWCTRL,
899                 },
900         },
901         .opt_clks       = gpio5_opt_clks,
902         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
903         .dev_attr       = &gpio_dev_attr,
904 };
906 /* gpio6 */
907 static struct omap_hwmod_irq_info dra7xx_gpio6_irqs[] = {
908         { .irq = 34 + DRA7XX_IRQ_GIC_START },
909         { .irq = -1 }
910 };
912 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
913         { .role = "dbclk", .clk = "gpio6_dbclk" },
914 };
916 static struct omap_hwmod dra7xx_gpio6_hwmod = {
917         .name           = "gpio6",
918         .class          = &dra7xx_gpio_hwmod_class,
919         .clkdm_name     = "l4per_clkdm",
920         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
921         .mpu_irqs       = dra7xx_gpio6_irqs,
922         .main_clk       = "l3_iclk_div",
923         .prcm = {
924                 .omap4 = {
925                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
926                         .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
927                         .modulemode   = MODULEMODE_HWCTRL,
928                 },
929         },
930         .opt_clks       = gpio6_opt_clks,
931         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
932         .dev_attr       = &gpio_dev_attr,
933 };
935 /* gpio7 */
936 static struct omap_hwmod_irq_info dra7xx_gpio7_irqs[] = {
937         { .irq = 35 + DRA7XX_IRQ_GIC_START },
938         { .irq = -1 }
939 };
941 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
942         { .role = "dbclk", .clk = "gpio7_dbclk" },
943 };
945 static struct omap_hwmod dra7xx_gpio7_hwmod = {
946         .name           = "gpio7",
947         .class          = &dra7xx_gpio_hwmod_class,
948         .clkdm_name     = "l4per_clkdm",
949         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
950         .mpu_irqs       = dra7xx_gpio7_irqs,
951         .main_clk       = "l3_iclk_div",
952         .prcm = {
953                 .omap4 = {
954                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
955                         .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
956                         .modulemode   = MODULEMODE_HWCTRL,
957                 },
958         },
959         .opt_clks       = gpio7_opt_clks,
960         .opt_clks_cnt   = ARRAY_SIZE(gpio7_opt_clks),
961         .dev_attr       = &gpio_dev_attr,
962 };
964 /* gpio8 */
965 static struct omap_hwmod_irq_info dra7xx_gpio8_irqs[] = {
966         { .irq = 121 + DRA7XX_IRQ_GIC_START },
967         { .irq = -1 }
968 };
970 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
971         { .role = "dbclk", .clk = "gpio8_dbclk" },
972 };
974 static struct omap_hwmod dra7xx_gpio8_hwmod = {
975         .name           = "gpio8",
976         .class          = &dra7xx_gpio_hwmod_class,
977         .clkdm_name     = "l4per_clkdm",
978         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
979         .mpu_irqs       = dra7xx_gpio8_irqs,
980         .main_clk       = "l3_iclk_div",
981         .prcm = {
982                 .omap4 = {
983                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
984                         .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
985                         .modulemode   = MODULEMODE_HWCTRL,
986                 },
987         },
988         .opt_clks       = gpio8_opt_clks,
989         .opt_clks_cnt   = ARRAY_SIZE(gpio8_opt_clks),
990         .dev_attr       = &gpio_dev_attr,
991 };
993 /*
994  * 'gpmc' class
995  *
996  */
998 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
999         .rev_offs       = 0x0000,
1000         .sysc_offs      = 0x0010,
1001         .syss_offs      = 0x0014,
1002         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1003                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1004         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1005                            SIDLE_SMART_WKUP),
1006         .sysc_fields    = &omap_hwmod_sysc_type1,
1007 };
1009 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
1010         .name   = "gpmc",
1011         .sysc   = &dra7xx_gpmc_sysc,
1012 };
1014 /* gpmc */
1015 static struct omap_hwmod_irq_info dra7xx_gpmc_irqs[] = {
1016         { .irq = 20 + DRA7XX_IRQ_GIC_START },
1017         { .irq = -1 }
1018 };
1020 static struct omap_hwmod_dma_info dra7xx_gpmc_sdma_reqs[] = {
1021         { .dma_req = 3 + DRA7XX_DMA_REQ_START },
1022         { .dma_req = -1 }
1023 };
1025 static struct omap_hwmod dra7xx_gpmc_hwmod = {
1026         .name           = "gpmc",
1027         .class          = &dra7xx_gpmc_hwmod_class,
1028         .clkdm_name     = "l3main1_clkdm",
1029         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1030         .mpu_irqs       = dra7xx_gpmc_irqs,
1031         .sdma_reqs      = dra7xx_gpmc_sdma_reqs,
1032         .main_clk       = "l3_iclk_div",
1033         .prcm = {
1034                 .omap4 = {
1035                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
1036                         .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
1037                         .modulemode   = MODULEMODE_HWCTRL,
1038                 },
1039         },
1040 };
1042 /*
1043  * 'gpu' class
1044  * 2d/3d graphics accelerator
1045  */
1047 static struct omap_hwmod_class_sysconfig dra7xx_gpu_sysc = {
1048         .rev_offs       = 0x0000,
1049         .sysc_offs      = 0x0010,
1050         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1051         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1052                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1053                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1054         .sysc_fields    = &omap_hwmod_sysc_type2,
1055 };
1057 static struct omap_hwmod_class dra7xx_gpu_hwmod_class = {
1058         .name   = "gpu",
1059         .sysc   = &dra7xx_gpu_sysc,
1060 };
1062 /* gpu */
1063 static struct omap_hwmod_irq_info dra7xx_gpu_irqs[] = {
1064         { .irq = 21 + DRA7XX_IRQ_GIC_START },
1065         { .irq = -1 }
1066 };
1068 static struct omap_hwmod dra7xx_gpu_hwmod = {
1069         .name           = "gpu",
1070         .class          = &dra7xx_gpu_hwmod_class,
1071         .clkdm_name     = "gpu_clkdm",
1072         .mpu_irqs       = dra7xx_gpu_irqs,
1073         .main_clk       = "gpu_core_gclk_mux",
1074         .prcm = {
1075                 .omap4 = {
1076                         .clkctrl_offs = DRA7XX_CM_GPU_GPU_CLKCTRL_OFFSET,
1077                         .context_offs = DRA7XX_RM_GPU_GPU_CONTEXT_OFFSET,
1078                         .modulemode   = MODULEMODE_SWCTRL,
1079                 },
1080         },
1081 };
1083 /*
1084  * 'hdq1w' class
1085  *
1086  */
1088 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
1089         .rev_offs       = 0x0000,
1090         .sysc_offs      = 0x0014,
1091         .syss_offs      = 0x0018,
1092         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1093                            SYSS_HAS_RESET_STATUS),
1094         .sysc_fields    = &omap_hwmod_sysc_type1,
1095 };
1097 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
1098         .name   = "hdq1w",
1099         .sysc   = &dra7xx_hdq1w_sysc,
1100 };
1102 /* hdq1w */
1103 static struct omap_hwmod_irq_info dra7xx_hdq1w_irqs[] = {
1104         { .irq = 58 + DRA7XX_IRQ_GIC_START },
1105         { .irq = -1 }
1106 };
1108 static struct omap_hwmod dra7xx_hdq1w_hwmod = {
1109         .name           = "hdq1w",
1110         .class          = &dra7xx_hdq1w_hwmod_class,
1111         .clkdm_name     = "l4per_clkdm",
1112         .flags          = HWMOD_INIT_NO_RESET,
1113         .mpu_irqs       = dra7xx_hdq1w_irqs,
1114         .main_clk       = "func_12m_fclk",
1115         .prcm = {
1116                 .omap4 = {
1117                         .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1118                         .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1119                         .modulemode   = MODULEMODE_SWCTRL,
1120                 },
1121         },
1122 };
1124 /*
1125  * 'i2c' class
1126  *
1127  */
1129 static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
1130         .sysc_offs      = 0x0010,
1131         .syss_offs      = 0x0090,
1132         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1133                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1134                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1135         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1136                            SIDLE_SMART_WKUP),
1137         .clockact       = CLOCKACT_TEST_ICLK,
1138         .sysc_fields    = &omap_hwmod_sysc_type1,
1139 };
1141 static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
1142         .name   = "i2c",
1143         .sysc   = &dra7xx_i2c_sysc,
1144         .reset  = &omap_i2c_reset,
1145         .rev    = OMAP_I2C_IP_VERSION_2,
1146 };
1148 /* i2c dev_attr */
1149 static struct omap_i2c_dev_attr i2c_dev_attr = {
1150         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1151 };
1153 /* i2c1 */
1154 static struct omap_hwmod_irq_info dra7xx_i2c1_irqs[] = {
1155         { .irq = 56 + DRA7XX_IRQ_GIC_START },
1156         { .irq = -1 }
1157 };
1159 static struct omap_hwmod_dma_info dra7xx_i2c1_sdma_reqs[] = {
1160         { .name = "27", .dma_req = 26 + DRA7XX_DMA_REQ_START },
1161         { .name = "28", .dma_req = 27 + DRA7XX_DMA_REQ_START },
1162         { .dma_req = -1 }
1163 };
1165 static struct omap_hwmod dra7xx_i2c1_hwmod = {
1166         .name           = "i2c1",
1167         .class          = &dra7xx_i2c_hwmod_class,
1168         .clkdm_name     = "l4per_clkdm",
1169         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1170         .mpu_irqs       = dra7xx_i2c1_irqs,
1171         .sdma_reqs      = dra7xx_i2c1_sdma_reqs,
1172         .main_clk       = "func_96m_fclk",
1173         .prcm = {
1174                 .omap4 = {
1175                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1176                         .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
1177                         .modulemode   = MODULEMODE_SWCTRL,
1178                 },
1179         },
1180         .dev_attr       = &i2c_dev_attr,
1181 };
1183 /* i2c2 */
1184 static struct omap_hwmod_irq_info dra7xx_i2c2_irqs[] = {
1185         { .irq = 57 + DRA7XX_IRQ_GIC_START },
1186         { .irq = -1 }
1187 };
1189 static struct omap_hwmod_dma_info dra7xx_i2c2_sdma_reqs[] = {
1190         { .name = "29", .dma_req = 28 + DRA7XX_DMA_REQ_START },
1191         { .name = "30", .dma_req = 29 + DRA7XX_DMA_REQ_START },
1192         { .dma_req = -1 }
1193 };
1195 static struct omap_hwmod dra7xx_i2c2_hwmod = {
1196         .name           = "i2c2",
1197         .class          = &dra7xx_i2c_hwmod_class,
1198         .clkdm_name     = "l4per_clkdm",
1199         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1200         .mpu_irqs       = dra7xx_i2c2_irqs,
1201         .sdma_reqs      = dra7xx_i2c2_sdma_reqs,
1202         .main_clk       = "func_96m_fclk",
1203         .prcm = {
1204                 .omap4 = {
1205                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1206                         .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
1207                         .modulemode   = MODULEMODE_SWCTRL,
1208                 },
1209         },
1210         .dev_attr       = &i2c_dev_attr,
1211 };
1213 /* i2c3 */
1214 static struct omap_hwmod_irq_info dra7xx_i2c3_irqs[] = {
1215         { .irq = 61 + DRA7XX_IRQ_GIC_START },
1216         { .irq = -1 }
1217 };
1219 static struct omap_hwmod_dma_info dra7xx_i2c3_sdma_reqs[] = {
1220         { .name = "25", .dma_req = 24 + DRA7XX_DMA_REQ_START },
1221         { .name = "26", .dma_req = 25 + DRA7XX_DMA_REQ_START },
1222         { .dma_req = -1 }
1223 };
1225 static struct omap_hwmod dra7xx_i2c3_hwmod = {
1226         .name           = "i2c3",
1227         .class          = &dra7xx_i2c_hwmod_class,
1228         .clkdm_name     = "l4per_clkdm",
1229         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1230         .mpu_irqs       = dra7xx_i2c3_irqs,
1231         .sdma_reqs      = dra7xx_i2c3_sdma_reqs,
1232         .main_clk       = "func_96m_fclk",
1233         .prcm = {
1234                 .omap4 = {
1235                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1236                         .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
1237                         .modulemode   = MODULEMODE_SWCTRL,
1238                 },
1239         },
1240         .dev_attr       = &i2c_dev_attr,
1241 };
1243 /* i2c4 */
1244 static struct omap_hwmod_irq_info dra7xx_i2c4_irqs[] = {
1245         { .irq = 62 + DRA7XX_IRQ_GIC_START },
1246         { .irq = -1 }
1247 };
1249 static struct omap_hwmod_dma_info dra7xx_i2c4_sdma_reqs[] = {
1250         { .name = "124", .dma_req = 123 + DRA7XX_DMA_REQ_START },
1251         { .name = "125", .dma_req = 124 + DRA7XX_DMA_REQ_START },
1252         { .dma_req = -1 }
1253 };
1255 static struct omap_hwmod dra7xx_i2c4_hwmod = {
1256         .name           = "i2c4",
1257         .class          = &dra7xx_i2c_hwmod_class,
1258         .clkdm_name     = "l4per_clkdm",
1259         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1260         .mpu_irqs       = dra7xx_i2c4_irqs,
1261         .sdma_reqs      = dra7xx_i2c4_sdma_reqs,
1262         .main_clk       = "func_96m_fclk",
1263         .prcm = {
1264                 .omap4 = {
1265                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1266                         .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
1267                         .modulemode   = MODULEMODE_SWCTRL,
1268                 },
1269         },
1270         .dev_attr       = &i2c_dev_attr,
1271 };
1273 /* i2c5 */
1274 static struct omap_hwmod_irq_info dra7xx_i2c5_irqs[] = {
1275         { .irq = 60 + DRA7XX_IRQ_GIC_START },
1276         { .irq = -1 }
1277 };
1279 static struct omap_hwmod dra7xx_i2c5_hwmod = {
1280         .name           = "i2c5",
1281         .class          = &dra7xx_i2c_hwmod_class,
1282         .clkdm_name     = "ipu_clkdm",
1283         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1284         .mpu_irqs       = dra7xx_i2c5_irqs,
1285         .main_clk       = "func_96m_fclk",
1286         .prcm = {
1287                 .omap4 = {
1288                         .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
1289                         .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
1290                         .modulemode   = MODULEMODE_SWCTRL,
1291                 },
1292         },
1293         .dev_attr       = &i2c_dev_attr,
1294 };
1296 /*
1297  * 'mailbox' class
1298  *
1299  */
1301 static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
1302         .rev_offs       = 0x0000,
1303         .sysc_offs      = 0x0010,
1304         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1305                            SYSC_HAS_SOFTRESET),
1306         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1307                            SIDLE_SMART_WKUP),
1308         .sysc_fields    = &omap_hwmod_sysc_type2,
1309 };
1311 static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
1312         .name   = "mailbox",
1313         .sysc   = &dra7xx_mailbox_sysc,
1314 };
1316 /* mailbox1 */
1317 static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1318         .name           = "mailbox1",
1319         .class          = &dra7xx_mailbox_hwmod_class,
1320         .clkdm_name     = "l4cfg_clkdm",
1321         .main_clk       = "l3_iclk_div",
1322         .prcm = {
1323                 .omap4 = {
1324                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1325                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1326                 },
1327         },
1328 };
1330 /* mailbox2 */
1331 static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1332         .name           = "mailbox2",
1333         .class          = &dra7xx_mailbox_hwmod_class,
1334         .clkdm_name     = "l4cfg_clkdm",
1335         .main_clk       = "l3_iclk_div",
1336         .prcm = {
1337                 .omap4 = {
1338                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1339                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1340                 },
1341         },
1342 };
1344 /* mailbox3 */
1345 static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1346         .name           = "mailbox3",
1347         .class          = &dra7xx_mailbox_hwmod_class,
1348         .clkdm_name     = "l4cfg_clkdm",
1349         .main_clk       = "l3_iclk_div",
1350         .prcm = {
1351                 .omap4 = {
1352                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1353                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1354                 },
1355         },
1356 };
1358 /* mailbox4 */
1359 static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1360         .name           = "mailbox4",
1361         .class          = &dra7xx_mailbox_hwmod_class,
1362         .clkdm_name     = "l4cfg_clkdm",
1363         .main_clk       = "l3_iclk_div",
1364         .prcm = {
1365                 .omap4 = {
1366                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1367                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1368                 },
1369         },
1370 };
1372 /* mailbox5 */
1373 static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1374         .name           = "mailbox5",
1375         .class          = &dra7xx_mailbox_hwmod_class,
1376         .clkdm_name     = "l4cfg_clkdm",
1377         .main_clk       = "l3_iclk_div",
1378         .prcm = {
1379                 .omap4 = {
1380                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1381                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1382                 },
1383         },
1384 };
1386 /* mailbox6 */
1387 static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1388         .name           = "mailbox6",
1389         .class          = &dra7xx_mailbox_hwmod_class,
1390         .clkdm_name     = "l4cfg_clkdm",
1391         .main_clk       = "l3_iclk_div",
1392         .prcm = {
1393                 .omap4 = {
1394                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1395                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1396                 },
1397         },
1398 };
1400 /* mailbox7 */
1401 static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1402         .name           = "mailbox7",
1403         .class          = &dra7xx_mailbox_hwmod_class,
1404         .clkdm_name     = "l4cfg_clkdm",
1405         .main_clk       = "l3_iclk_div",
1406         .prcm = {
1407                 .omap4 = {
1408                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1409                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1410                 },
1411         },
1412 };
1414 /* mailbox8 */
1415 static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1416         .name           = "mailbox8",
1417         .class          = &dra7xx_mailbox_hwmod_class,
1418         .clkdm_name     = "l4cfg_clkdm",
1419         .main_clk       = "l3_iclk_div",
1420         .prcm = {
1421                 .omap4 = {
1422                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1423                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1424                 },
1425         },
1426 };
1428 /* mailbox9 */
1429 static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1430         .name           = "mailbox9",
1431         .class          = &dra7xx_mailbox_hwmod_class,
1432         .clkdm_name     = "l4cfg_clkdm",
1433         .main_clk       = "l3_iclk_div",
1434         .prcm = {
1435                 .omap4 = {
1436                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1437                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1438                 },
1439         },
1440 };
1442 /* mailbox10 */
1443 static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1444         .name           = "mailbox10",
1445         .class          = &dra7xx_mailbox_hwmod_class,
1446         .clkdm_name     = "l4cfg_clkdm",
1447         .main_clk       = "l3_iclk_div",
1448         .prcm = {
1449                 .omap4 = {
1450                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1451                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1452                 },
1453         },
1454 };
1456 /* mailbox11 */
1457 static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1458         .name           = "mailbox11",
1459         .class          = &dra7xx_mailbox_hwmod_class,
1460         .clkdm_name     = "l4cfg_clkdm",
1461         .main_clk       = "l3_iclk_div",
1462         .prcm = {
1463                 .omap4 = {
1464                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1465                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1466                 },
1467         },
1468 };
1470 /* mailbox12 */
1471 static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1472         .name           = "mailbox12",
1473         .class          = &dra7xx_mailbox_hwmod_class,
1474         .clkdm_name     = "l4cfg_clkdm",
1475         .main_clk       = "l3_iclk_div",
1476         .prcm = {
1477                 .omap4 = {
1478                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1479                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1480                 },
1481         },
1482 };
1484 /* mailbox13 */
1485 static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1486         .name           = "mailbox13",
1487         .class          = &dra7xx_mailbox_hwmod_class,
1488         .clkdm_name     = "l4cfg_clkdm",
1489         .main_clk       = "l3_iclk_div",
1490         .prcm = {
1491                 .omap4 = {
1492                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1493                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1494                 },
1495         },
1496 };
1498 /*
1499  * 'mcasp' class
1500  *
1501  */
1503 static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc = {
1504         .sysc_offs      = 0x0004,
1505         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1506         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1507         .sysc_fields    = &omap_hwmod_sysc_type3,
1508 };
1510 static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
1511         .name   = "mcasp",
1512         .sysc   = &dra7xx_mcasp_sysc,
1513 };
1515 /* mcasp1 */
1516 static struct omap_hwmod dra7xx_mcasp1_hwmod = {
1517         .name           = "mcasp1",
1518         .class          = &dra7xx_mcasp_hwmod_class,
1519         .clkdm_name     = "ipu_clkdm",
1520         .main_clk       = "mcasp1_ahclkx_mux",
1521         .prcm = {
1522                 .omap4 = {
1523                         .clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET,
1524                         .context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET,
1525                         .modulemode   = MODULEMODE_SWCTRL,
1526                 },
1527         },
1528 };
1530 /* mcasp2 */
1531 static struct omap_hwmod dra7xx_mcasp2_hwmod = {
1532         .name           = "mcasp2",
1533         .class          = &dra7xx_mcasp_hwmod_class,
1534         .clkdm_name     = "l4per2_clkdm",
1535         .main_clk       = "mcasp2_ahclkr_mux",
1536         .prcm = {
1537                 .omap4 = {
1538                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,
1539                         .context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
1540                         .modulemode   = MODULEMODE_SWCTRL,
1541                 },
1542         },
1543 };
1545 /* mcasp3 */
1546 static struct omap_hwmod dra7xx_mcasp3_hwmod = {
1547         .name           = "mcasp3",
1548         .class          = &dra7xx_mcasp_hwmod_class,
1549         .clkdm_name     = "l4per2_clkdm",
1550         .main_clk       = "mcasp3_ahclkx_mux",
1551         .prcm = {
1552                 .omap4 = {
1553                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET,
1554                         .context_offs = DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET,
1555                         .modulemode   = MODULEMODE_SWCTRL,
1556                 },
1557         },
1558 };
1560 /* mcasp4 */
1561 static struct omap_hwmod dra7xx_mcasp4_hwmod = {
1562         .name           = "mcasp4",
1563         .class          = &dra7xx_mcasp_hwmod_class,
1564         .clkdm_name     = "l4per2_clkdm",
1565         .main_clk       = "mcasp4_ahclkx_mux",
1566         .prcm = {
1567                 .omap4 = {
1568                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET,
1569                         .context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET,
1570                         .modulemode   = MODULEMODE_SWCTRL,
1571                 },
1572         },
1573 };
1575 /* mcasp5 */
1576 static struct omap_hwmod dra7xx_mcasp5_hwmod = {
1577         .name           = "mcasp5",
1578         .class          = &dra7xx_mcasp_hwmod_class,
1579         .clkdm_name     = "l4per2_clkdm",
1580         .main_clk       = "mcasp5_ahclkx_mux",
1581         .prcm = {
1582                 .omap4 = {
1583                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET,
1584                         .context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET,
1585                         .modulemode   = MODULEMODE_SWCTRL,
1586                 },
1587         },
1588 };
1590 /* mcasp6 */
1591 static struct omap_hwmod dra7xx_mcasp6_hwmod = {
1592         .name           = "mcasp6",
1593         .class          = &dra7xx_mcasp_hwmod_class,
1594         .clkdm_name     = "l4per2_clkdm",
1595         .main_clk       = "mcasp6_ahclkx_mux",
1596         .prcm = {
1597                 .omap4 = {
1598                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,
1599                         .context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
1600                         .modulemode   = MODULEMODE_SWCTRL,
1601                 },
1602         },
1603 };
1605 /* mcasp7 */
1606 static struct omap_hwmod dra7xx_mcasp7_hwmod = {
1607         .name           = "mcasp7",
1608         .class          = &dra7xx_mcasp_hwmod_class,
1609         .clkdm_name     = "l4per2_clkdm",
1610         .main_clk       = "mcasp7_ahclkx_mux",
1611         .prcm = {
1612                 .omap4 = {
1613                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET,
1614                         .context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,
1615                         .modulemode   = MODULEMODE_SWCTRL,
1616                 },
1617         },
1618 };
1620 /* mcasp8 */
1621 static struct omap_hwmod dra7xx_mcasp8_hwmod = {
1622         .name           = "mcasp8",
1623         .class          = &dra7xx_mcasp_hwmod_class,
1624         .clkdm_name     = "l4per2_clkdm",
1625         .main_clk       = "mcasp8_ahclk_mux",
1626         .prcm = {
1627                 .omap4 = {
1628                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,
1629                         .context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
1630                         .modulemode   = MODULEMODE_SWCTRL,
1631                 },
1632         },
1633 };
1635 /*
1636  * 'mcspi' class
1637  *
1638  */
1640 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1641         .rev_offs       = 0x0000,
1642         .sysc_offs      = 0x0010,
1643         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1644                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1645         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1646                            SIDLE_SMART_WKUP),
1647         .sysc_fields    = &omap_hwmod_sysc_type2,
1648 };
1650 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1651         .name   = "mcspi",
1652         .sysc   = &dra7xx_mcspi_sysc,
1653         .rev    = OMAP4_MCSPI_REV,
1654 };
1656 /* mcspi1 */
1657 static struct omap_hwmod_irq_info dra7xx_mcspi1_irqs[] = {
1658         { .irq = 65 + DRA7XX_IRQ_GIC_START },
1659         { .irq = -1 }
1660 };
1662 static struct omap_hwmod_dma_info dra7xx_mcspi1_sdma_reqs[] = {
1663         { .name = "35", .dma_req = 34 + DRA7XX_DMA_REQ_START },
1664         { .name = "36", .dma_req = 35 + DRA7XX_DMA_REQ_START },
1665         { .name = "37", .dma_req = 36 + DRA7XX_DMA_REQ_START },
1666         { .name = "38", .dma_req = 37 + DRA7XX_DMA_REQ_START },
1667         { .name = "39", .dma_req = 38 + DRA7XX_DMA_REQ_START },
1668         { .name = "40", .dma_req = 39 + DRA7XX_DMA_REQ_START },
1669         { .name = "41", .dma_req = 40 + DRA7XX_DMA_REQ_START },
1670         { .name = "42", .dma_req = 41 + DRA7XX_DMA_REQ_START },
1671         { .dma_req = -1 }
1672 };
1674 /* mcspi1 dev_attr */
1675 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1676         .num_chipselect = 4,
1677 };
1679 static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1680         .name           = "mcspi1",
1681         .class          = &dra7xx_mcspi_hwmod_class,
1682         .clkdm_name     = "l4per_clkdm",
1683         .mpu_irqs       = dra7xx_mcspi1_irqs,
1684         .sdma_reqs      = dra7xx_mcspi1_sdma_reqs,
1685         .main_clk       = "func_48m_fclk",
1686         .prcm = {
1687                 .omap4 = {
1688                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1689                         .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1690                         .modulemode   = MODULEMODE_SWCTRL,
1691                 },
1692         },
1693         .dev_attr       = &mcspi1_dev_attr,
1694 };
1696 /* mcspi2 */
1697 static struct omap_hwmod_irq_info dra7xx_mcspi2_irqs[] = {
1698         { .irq = 66 + DRA7XX_IRQ_GIC_START },
1699         { .irq = -1 }
1700 };
1702 static struct omap_hwmod_dma_info dra7xx_mcspi2_sdma_reqs[] = {
1703         { .name = "43", .dma_req = 42 + DRA7XX_DMA_REQ_START },
1704         { .name = "44", .dma_req = 43 + DRA7XX_DMA_REQ_START },
1705         { .name = "45", .dma_req = 44 + DRA7XX_DMA_REQ_START },
1706         { .name = "46", .dma_req = 45 + DRA7XX_DMA_REQ_START },
1707         { .dma_req = -1 }
1708 };
1710 /* mcspi2 dev_attr */
1711 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1712         .num_chipselect = 2,
1713 };
1715 static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1716         .name           = "mcspi2",
1717         .class          = &dra7xx_mcspi_hwmod_class,
1718         .clkdm_name     = "l4per_clkdm",
1719         .mpu_irqs       = dra7xx_mcspi2_irqs,
1720         .sdma_reqs      = dra7xx_mcspi2_sdma_reqs,
1721         .main_clk       = "func_48m_fclk",
1722         .prcm = {
1723                 .omap4 = {
1724                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1725                         .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1726                         .modulemode   = MODULEMODE_SWCTRL,
1727                 },
1728         },
1729         .dev_attr       = &mcspi2_dev_attr,
1730 };
1732 /* mcspi3 */
1733 static struct omap_hwmod_irq_info dra7xx_mcspi3_irqs[] = {
1734         { .irq = 91 + DRA7XX_IRQ_GIC_START },
1735         { .irq = -1 }
1736 };
1738 static struct omap_hwmod_dma_info dra7xx_mcspi3_sdma_reqs[] = {
1739         { .name = "15", .dma_req = 14 + DRA7XX_DMA_REQ_START },
1740         { .name = "16", .dma_req = 15 + DRA7XX_DMA_REQ_START },
1741         { .name = "23", .dma_req = 22 + DRA7XX_DMA_REQ_START },
1742         { .name = "24", .dma_req = 23 + DRA7XX_DMA_REQ_START },
1743         { .dma_req = -1 }
1744 };
1746 /* mcspi3 dev_attr */
1747 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1748         .num_chipselect = 2,
1749 };
1751 static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1752         .name           = "mcspi3",
1753         .class          = &dra7xx_mcspi_hwmod_class,
1754         .clkdm_name     = "l4per_clkdm",
1755         .mpu_irqs       = dra7xx_mcspi3_irqs,
1756         .sdma_reqs      = dra7xx_mcspi3_sdma_reqs,
1757         .main_clk       = "func_48m_fclk",
1758         .prcm = {
1759                 .omap4 = {
1760                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1761                         .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1762                         .modulemode   = MODULEMODE_SWCTRL,
1763                 },
1764         },
1765         .dev_attr       = &mcspi3_dev_attr,
1766 };
1768 /* mcspi4 */
1769 static struct omap_hwmod_irq_info dra7xx_mcspi4_irqs[] = {
1770         { .irq = 48 + DRA7XX_IRQ_GIC_START },
1771         { .irq = -1 }
1772 };
1774 static struct omap_hwmod_dma_info dra7xx_mcspi4_sdma_reqs[] = {
1775         { .name = "70", .dma_req = 69 + DRA7XX_DMA_REQ_START },
1776         { .name = "71", .dma_req = 70 + DRA7XX_DMA_REQ_START },
1777         { .dma_req = -1 }
1778 };
1780 /* mcspi4 dev_attr */
1781 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1782         .num_chipselect = 1,
1783 };
1785 static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1786         .name           = "mcspi4",
1787         .class          = &dra7xx_mcspi_hwmod_class,
1788         .clkdm_name     = "l4per_clkdm",
1789         .mpu_irqs       = dra7xx_mcspi4_irqs,
1790         .sdma_reqs      = dra7xx_mcspi4_sdma_reqs,
1791         .main_clk       = "func_48m_fclk",
1792         .prcm = {
1793                 .omap4 = {
1794                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1795                         .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1796                         .modulemode   = MODULEMODE_SWCTRL,
1797                 },
1798         },
1799         .dev_attr       = &mcspi4_dev_attr,
1800 };
1802 /*
1803  * 'mmc' class
1804  *
1805  */
1807 static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1808         .rev_offs       = 0x0000,
1809         .sysc_offs      = 0x0010,
1810         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1811                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1812                            SYSC_HAS_SOFTRESET),
1813         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1814                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1815                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1816         .sysc_fields    = &omap_hwmod_sysc_type2,
1817 };
1819 static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1820         .name   = "mmc",
1821         .sysc   = &dra7xx_mmc_sysc,
1822 };
1824 /* mmc1 */
1825 static struct omap_hwmod_irq_info dra7xx_mmc1_irqs[] = {
1826         { .irq = 83 + DRA7XX_IRQ_GIC_START },
1827         { .irq = -1 }
1828 };
1830 static struct omap_hwmod_dma_info dra7xx_mmc1_sdma_reqs[] = {
1831         { .name = "tx", .dma_req = 60 + DRA7XX_DMA_REQ_START },
1832         { .name = "rx", .dma_req = 61 + DRA7XX_DMA_REQ_START },
1833         { .dma_req = -1 }
1834 };
1836 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1837         { .role = "clk32k", .clk = "mmc1_clk32k" },
1838 };
1840 /* mmc1 dev_attr */
1841 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1842         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1843 };
1845 static struct omap_hwmod dra7xx_mmc1_hwmod = {
1846         .name           = "mmc1",
1847         .class          = &dra7xx_mmc_hwmod_class,
1848         .clkdm_name     = "l3init_clkdm",
1849         .mpu_irqs       = dra7xx_mmc1_irqs,
1850         .sdma_reqs      = dra7xx_mmc1_sdma_reqs,
1851         .main_clk       = "mmc1_fclk_div",
1852         .prcm = {
1853                 .omap4 = {
1854                         .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1855                         .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1856                         .modulemode   = MODULEMODE_SWCTRL,
1857                 },
1858         },
1859         .opt_clks       = mmc1_opt_clks,
1860         .opt_clks_cnt   = ARRAY_SIZE(mmc1_opt_clks),
1861         .dev_attr       = &mmc1_dev_attr,
1862 };
1864 /* mmc2 */
1865 static struct omap_hwmod_irq_info dra7xx_mmc2_irqs[] = {
1866         { .irq = 86 + DRA7XX_IRQ_GIC_START },
1867         { .irq = -1 }
1868 };
1870 static struct omap_hwmod_dma_info dra7xx_mmc2_sdma_reqs[] = {
1871         { .name = "tx", .dma_req = 46 + DRA7XX_DMA_REQ_START },
1872         { .name = "rx", .dma_req = 47 + DRA7XX_DMA_REQ_START },
1873         { .dma_req = -1 }
1874 };
1876 static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1877         { .role = "clk32k", .clk = "mmc2_clk32k" },
1878 };
1880 static struct omap_hwmod dra7xx_mmc2_hwmod = {
1881         .name           = "mmc2",
1882         .class          = &dra7xx_mmc_hwmod_class,
1883         .clkdm_name     = "l3init_clkdm",
1884         .mpu_irqs       = dra7xx_mmc2_irqs,
1885         .sdma_reqs      = dra7xx_mmc2_sdma_reqs,
1886         .main_clk       = "mmc2_fclk_div",
1887         .prcm = {
1888                 .omap4 = {
1889                         .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1890                         .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1891                         .modulemode   = MODULEMODE_SWCTRL,
1892                 },
1893         },
1894         .opt_clks       = mmc2_opt_clks,
1895         .opt_clks_cnt   = ARRAY_SIZE(mmc2_opt_clks),
1896 };
1898 /* mmc3 */
1899 static struct omap_hwmod_irq_info dra7xx_mmc3_irqs[] = {
1900         { .irq = 94 + DRA7XX_IRQ_GIC_START },
1901         { .irq = -1 }
1902 };
1904 static struct omap_hwmod_dma_info dra7xx_mmc3_sdma_reqs[] = {
1905         { .name = "77", .dma_req = 76 + DRA7XX_DMA_REQ_START },
1906         { .name = "78", .dma_req = 77 + DRA7XX_DMA_REQ_START },
1907         { .dma_req = -1 }
1908 };
1910 static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1911         { .role = "clk32k", .clk = "mmc3_clk32k" },
1912 };
1914 static struct omap_hwmod dra7xx_mmc3_hwmod = {
1915         .name           = "mmc3",
1916         .class          = &dra7xx_mmc_hwmod_class,
1917         .clkdm_name     = "l4per_clkdm",
1918         .mpu_irqs       = dra7xx_mmc3_irqs,
1919         .sdma_reqs      = dra7xx_mmc3_sdma_reqs,
1920         .main_clk       = "mmc3_gfclk_div",
1921         .prcm = {
1922                 .omap4 = {
1923                         .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1924                         .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1925                         .modulemode   = MODULEMODE_SWCTRL,
1926                 },
1927         },
1928         .opt_clks       = mmc3_opt_clks,
1929         .opt_clks_cnt   = ARRAY_SIZE(mmc3_opt_clks),
1930 };
1932 /* mmc4 */
1933 static struct omap_hwmod_irq_info dra7xx_mmc4_irqs[] = {
1934         { .irq = 96 + DRA7XX_IRQ_GIC_START },
1935         { .irq = -1 }
1936 };
1938 static struct omap_hwmod_dma_info dra7xx_mmc4_sdma_reqs[] = {
1939         { .name = "57", .dma_req = 56 + DRA7XX_DMA_REQ_START },
1940         { .name = "58", .dma_req = 57 + DRA7XX_DMA_REQ_START },
1941         { .dma_req = -1 }
1942 };
1944 static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1945         { .role = "clk32k", .clk = "mmc4_clk32k" },
1946 };
1948 static struct omap_hwmod dra7xx_mmc4_hwmod = {
1949         .name           = "mmc4",
1950         .class          = &dra7xx_mmc_hwmod_class,
1951         .clkdm_name     = "l4per_clkdm",
1952         .mpu_irqs       = dra7xx_mmc4_irqs,
1953         .sdma_reqs      = dra7xx_mmc4_sdma_reqs,
1954         .main_clk       = "mmc4_gfclk_div",
1955         .prcm = {
1956                 .omap4 = {
1957                         .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1958                         .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1959                         .modulemode   = MODULEMODE_SWCTRL,
1960                 },
1961         },
1962         .opt_clks       = mmc4_opt_clks,
1963         .opt_clks_cnt   = ARRAY_SIZE(mmc4_opt_clks),
1964 };
1966 /*
1967  * 'mpu' class
1968  *
1969  */
1971 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1972         .name   = "mpu",
1973 };
1975 /* mpu */
1976 static struct omap_hwmod_irq_info dra7xx_mpu_irqs[] = {
1977         { .irq = 132 + DRA7XX_IRQ_GIC_START },
1978         { .irq = -1 }
1979 };
1981 static struct omap_hwmod dra7xx_mpu_hwmod = {
1982         .name           = "mpu",
1983         .class          = &dra7xx_mpu_hwmod_class,
1984         .clkdm_name     = "mpu_clkdm",
1985         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1986         .mpu_irqs       = dra7xx_mpu_irqs,
1987         .main_clk       = "dpll_mpu_m2_ck",
1988         .prcm = {
1989                 .omap4 = {
1990                         .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1991                         .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1992                 },
1993         },
1994 };
1996 /*
1997  * 'ocmc_ram' class
1998  *
1999  */
2001 static struct omap_hwmod_class dra7xx_ocmc_ram_hwmod_class = {
2002         .name   = "ocmc_ram",
2003 };
2005 /* ocmc_ram1 */
2006 static struct omap_hwmod dra7xx_ocmc_ram1_hwmod = {
2007         .name           = "ocmc_ram1",
2008         .class          = &dra7xx_ocmc_ram_hwmod_class,
2009         .clkdm_name     = "l3main1_clkdm",
2010         .main_clk       = "l3_iclk_div",
2011         .prcm = {
2012                 .omap4 = {
2013                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL_OFFSET,
2014                         .context_offs = DRA7XX_RM_L3MAIN1_OCMC_RAM1_CONTEXT_OFFSET,
2015                 },
2016         },
2017 };
2019 /* ocmc_ram2 */
2020 static struct omap_hwmod dra7xx_ocmc_ram2_hwmod = {
2021         .name           = "ocmc_ram2",
2022         .class          = &dra7xx_ocmc_ram_hwmod_class,
2023         .clkdm_name     = "l3main1_clkdm",
2024         .main_clk       = "l3_iclk_div",
2025         .prcm = {
2026                 .omap4 = {
2027                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL_OFFSET,
2028                         .context_offs = DRA7XX_RM_L3MAIN1_OCMC_RAM2_CONTEXT_OFFSET,
2029                 },
2030         },
2031 };
2033 /* ocmc_ram3 */
2034 static struct omap_hwmod dra7xx_ocmc_ram3_hwmod = {
2035         .name           = "ocmc_ram3",
2036         .class          = &dra7xx_ocmc_ram_hwmod_class,
2037         .clkdm_name     = "l3main1_clkdm",
2038         .main_clk       = "l3_iclk_div",
2039         .prcm = {
2040                 .omap4 = {
2041                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL_OFFSET,
2042                         .context_offs = DRA7XX_RM_L3MAIN1_OCMC_RAM3_CONTEXT_OFFSET,
2043                 },
2044         },
2045 };
2047 /*
2048  * 'ocmc_rom' class
2049  *
2050  */
2052 static struct omap_hwmod_class dra7xx_ocmc_rom_hwmod_class = {
2053         .name   = "ocmc_rom",
2054 };
2056 /* ocmc_rom */
2057 static struct omap_hwmod dra7xx_ocmc_rom_hwmod = {
2058         .name           = "ocmc_rom",
2059         .class          = &dra7xx_ocmc_rom_hwmod_class,
2060         .clkdm_name     = "l3main1_clkdm",
2061         .main_clk       = "l3_iclk_div",
2062         .prcm = {
2063                 .omap4 = {
2064                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL_OFFSET,
2065                         .context_offs = DRA7XX_RM_L3MAIN1_OCMC_ROM_CONTEXT_OFFSET,
2066                 },
2067         },
2068 };
2070 /*
2071  * 'ocp2scp' class
2072  *
2073  */
2075 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
2076         .rev_offs       = 0x0000,
2077         .sysc_offs      = 0x0010,
2078         .syss_offs      = 0x0014,
2079         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2080                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2081         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2082                            SIDLE_SMART_WKUP),
2083         .sysc_fields    = &omap_hwmod_sysc_type1,
2084 };
2086 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
2087         .name   = "ocp2scp",
2088         .sysc   = &dra7xx_ocp2scp_sysc,
2089 };
2091 /* ocp2scp1 */
2092 static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
2093         .name           = "ocp2scp1",
2094         .class          = &dra7xx_ocp2scp_hwmod_class,
2095         .clkdm_name     = "l3init_clkdm",
2096         .main_clk       = "l4_root_clk_div",
2097         .prcm = {
2098                 .omap4 = {
2099                         .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
2100                         .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
2101                         .modulemode   = MODULEMODE_HWCTRL,
2102                 },
2103         },
2104 };
2106 /*
2107  * 'pruss' class
2108  *
2109  */
2111 static struct omap_hwmod_class dra7xx_pruss_hwmod_class = {
2112         .name   = "pruss",
2113 };
2115 /* pruss1 */
2116 static struct omap_hwmod dra7xx_pruss1_hwmod = {
2117         .name           = "pruss1",
2118         .class          = &dra7xx_pruss_hwmod_class,
2119         .clkdm_name     = "l4per2_clkdm",
2120         .main_clk       = "dpll_per_m2x2_ck",
2121         .prcm = {
2122                 .omap4 = {
2123                         .clkctrl_offs = DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL_OFFSET,
2124                         .context_offs = DRA7XX_RM_L4PER2_PRUSS1_CONTEXT_OFFSET,
2125                         .modulemode   = MODULEMODE_SWCTRL,
2126                 },
2127         },
2128 };
2130 /* pruss2 */
2131 static struct omap_hwmod dra7xx_pruss2_hwmod = {
2132         .name           = "pruss2",
2133         .class          = &dra7xx_pruss_hwmod_class,
2134         .clkdm_name     = "l4per2_clkdm",
2135         .main_clk       = "dpll_per_m2x2_ck",
2136         .prcm = {
2137                 .omap4 = {
2138                         .clkctrl_offs = DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL_OFFSET,
2139                         .context_offs = DRA7XX_RM_L4PER2_PRUSS2_CONTEXT_OFFSET,
2140                         .modulemode   = MODULEMODE_SWCTRL,
2141                 },
2142         },
2143 };
2145 /*
2146  * 'pwmss' class
2147  *
2148  */
2150 static struct omap_hwmod_class dra7xx_pwmss_hwmod_class = {
2151         .name   = "pwmss",
2152 };
2154 /* pwmss1 */
2155 static struct omap_hwmod dra7xx_pwmss1_hwmod = {
2156         .name           = "pwmss1",
2157         .class          = &dra7xx_pwmss_hwmod_class,
2158         .clkdm_name     = "l4per2_clkdm",
2159         .main_clk       = "l3_iclk_div",
2160         .prcm = {
2161                 .omap4 = {
2162                         .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET,
2163                         .context_offs = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET,
2164                         .modulemode   = MODULEMODE_SWCTRL,
2165                 },
2166         },
2167 };
2169 /* pwmss2 */
2170 static struct omap_hwmod dra7xx_pwmss2_hwmod = {
2171         .name           = "pwmss2",
2172         .class          = &dra7xx_pwmss_hwmod_class,
2173         .clkdm_name     = "l4per2_clkdm",
2174         .main_clk       = "l3_iclk_div",
2175         .prcm = {
2176                 .omap4 = {
2177                         .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET,
2178                         .context_offs = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET,
2179                         .modulemode   = MODULEMODE_SWCTRL,
2180                 },
2181         },
2182 };
2184 /* pwmss3 */
2185 static struct omap_hwmod dra7xx_pwmss3_hwmod = {
2186         .name           = "pwmss3",
2187         .class          = &dra7xx_pwmss_hwmod_class,
2188         .clkdm_name     = "l4per2_clkdm",
2189         .main_clk       = "l3_iclk_div",
2190         .prcm = {
2191                 .omap4 = {
2192                         .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET,
2193                         .context_offs = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET,
2194                         .modulemode   = MODULEMODE_SWCTRL,
2195                 },
2196         },
2197 };
2199 /*
2200  * 'qspi' class
2201  *
2202  */
2204 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
2205         .sysc_offs      = 0x0010,
2206         .sysc_flags     = SYSC_HAS_SIDLEMODE,
2207         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2208                            SIDLE_SMART_WKUP),
2209         .sysc_fields    = &omap_hwmod_sysc_type2,
2210 };
2212 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
2213         .name   = "qspi",
2214         .sysc   = &dra7xx_qspi_sysc,
2215 };
2217 /* qspi */
2218 static struct omap_hwmod dra7xx_qspi_hwmod = {
2219         .name           = "qspi",
2220         .class          = &dra7xx_qspi_hwmod_class,
2221         .clkdm_name     = "l4per2_clkdm",
2222         .main_clk       = "qspi_gfclk_div",
2223         .prcm = {
2224                 .omap4 = {
2225                         .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
2226                         .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
2227                         .modulemode   = MODULEMODE_SWCTRL,
2228                 },
2229         },
2230 };
2232 /*
2233  * 'rtcss' class
2234  *
2235  */
2237 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
2238         .sysc_offs      = 0x0078,
2239         .sysc_flags     = SYSC_HAS_SIDLEMODE,
2240         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2241         .sysc_fields    = &omap_hwmod_sysc_type3,
2242 };
2244 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
2245         .name   = "rtcss",
2246         .sysc   = &dra7xx_rtcss_sysc,
2247 };
2249 /* rtcss */
2250 static struct omap_hwmod dra7xx_rtcss_hwmod = {
2251         .name           = "rtcss",
2252         .class          = &dra7xx_rtcss_hwmod_class,
2253         .clkdm_name     = "rtc_clkdm",
2254         .main_clk       = "sys_32k_ck",
2255         .prcm = {
2256                 .omap4 = {
2257                         .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
2258                         .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
2259                         .modulemode   = MODULEMODE_SWCTRL,
2260                 },
2261         },
2262 };
2264 /*
2265  * 'sata' class
2266  *
2267  */
2269 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
2270         .sysc_offs      = 0x0000,
2271         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
2272         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2273                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2274                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2275         .sysc_fields    = &omap_hwmod_sysc_type2,
2276 };
2278 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
2279         .name   = "sata",
2280         .sysc   = &dra7xx_sata_sysc,
2281 };
2283 /* sata */
2284 static struct omap_hwmod_irq_info dra7xx_sata_irqs[] = {
2285         { .irq = 54 + DRA7XX_IRQ_GIC_START },
2286         { .irq = -1 }
2287 };
2289 static struct omap_hwmod_opt_clk sata_opt_clks[] = {
2290         { .role = "ref_clk", .clk = "sata_ref_clk" },
2291 };
2293 static struct omap_hwmod dra7xx_sata_hwmod = {
2294         .name           = "sata",
2295         .class          = &dra7xx_sata_hwmod_class,
2296         .clkdm_name     = "l3init_clkdm",
2297         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2298         .mpu_irqs       = dra7xx_sata_irqs,
2299         .main_clk       = "func_48m_fclk",
2300         .prcm = {
2301                 .omap4 = {
2302                         .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
2303                         .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
2304                         .modulemode   = MODULEMODE_SWCTRL,
2305                 },
2306         },
2307         .opt_clks       = sata_opt_clks,
2308         .opt_clks_cnt   = ARRAY_SIZE(sata_opt_clks),
2309 };
2311 /*
2312  * 'smartreflex' class
2313  *
2314  */
2316 /* The IP is not compliant to type1 / type2 scheme */
2317 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2318         .sidle_shift    = 24,
2319         .enwkup_shift   = 26,
2320 };
2322 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
2323         .sysc_offs      = 0x0038,
2324         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2325         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2326                            SIDLE_SMART_WKUP),
2327         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2328 };
2330 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
2331         .name   = "smartreflex",
2332         .sysc   = &dra7xx_smartreflex_sysc,
2333         .rev    = 2,
2334 };
2336 /* smartreflex_core */
2337 static struct omap_hwmod_irq_info dra7xx_smartreflex_core_irqs[] = {
2338         { .irq = 19 + DRA7XX_IRQ_GIC_START },
2339         { .irq = -1 }
2340 };
2342 /* smartreflex_core dev_attr */
2343 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2344         .sensor_voltdm_name     = "core",
2345 };
2347 static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
2348         .name           = "smartreflex_core",
2349         .class          = &dra7xx_smartreflex_hwmod_class,
2350         .clkdm_name     = "coreaon_clkdm",
2351         .mpu_irqs       = dra7xx_smartreflex_core_irqs,
2352         .main_clk       = "wkupaon_iclk_mux",
2353         .prcm = {
2354                 .omap4 = {
2355                         .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
2356                         .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
2357                         .modulemode   = MODULEMODE_SWCTRL,
2358                 },
2359         },
2360         .dev_attr       = &smartreflex_core_dev_attr,
2361 };
2363 /* smartreflex_dspeve */
2364 static struct omap_hwmod dra7xx_smartreflex_dspeve_hwmod = {
2365         .name           = "smartreflex_dspeve",
2366         .class          = &dra7xx_smartreflex_hwmod_class,
2367         .clkdm_name     = "coreaon_clkdm",
2368         .main_clk       = "wkupaon_iclk_mux",
2369         .prcm = {
2370                 .omap4 = {
2371                         .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL_OFFSET,
2372                         .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_DSPEVE_CONTEXT_OFFSET,
2373                         .modulemode   = MODULEMODE_SWCTRL,
2374                 },
2375         },
2376 };
2378 /* smartreflex_gpu */
2379 static struct omap_hwmod dra7xx_smartreflex_gpu_hwmod = {
2380         .name           = "smartreflex_gpu",
2381         .class          = &dra7xx_smartreflex_hwmod_class,
2382         .clkdm_name     = "coreaon_clkdm",
2383         .main_clk       = "wkupaon_iclk_mux",
2384         .prcm = {
2385                 .omap4 = {
2386                         .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL_OFFSET,
2387                         .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_GPU_CONTEXT_OFFSET,
2388                         .modulemode   = MODULEMODE_SWCTRL,
2389                 },
2390         },
2391 };
2393 /* smartreflex_mpu */
2394 static struct omap_hwmod_irq_info dra7xx_smartreflex_mpu_irqs[] = {
2395         { .irq = 18 + DRA7XX_IRQ_GIC_START },
2396         { .irq = -1 }
2397 };
2399 /* smartreflex_mpu dev_attr */
2400 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2401         .sensor_voltdm_name     = "mpu",
2402 };
2404 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
2405         .name           = "smartreflex_mpu",
2406         .class          = &dra7xx_smartreflex_hwmod_class,
2407         .clkdm_name     = "coreaon_clkdm",
2408         .mpu_irqs       = dra7xx_smartreflex_mpu_irqs,
2409         .main_clk       = "wkupaon_iclk_mux",
2410         .prcm = {
2411                 .omap4 = {
2412                         .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
2413                         .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
2414                         .modulemode   = MODULEMODE_SWCTRL,
2415                 },
2416         },
2417         .dev_attr       = &smartreflex_mpu_dev_attr,
2418 };
2420 /*
2421  * 'spare' class
2422  *
2423  */
2425 static struct omap_hwmod_class dra7xx_spare_hwmod_class = {
2426         .name   = "spare",
2427 };
2429 /* spare_cme */
2430 static struct omap_hwmod dra7xx_spare_cme_hwmod = {
2431         .name           = "spare_cme",
2432         .class          = &dra7xx_spare_hwmod_class,
2433         .clkdm_name     = "l3main1_clkdm",
2434         .main_clk       = "l4_root_clk_div",
2435         .prcm = {
2436                 .omap4 = {
2437                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL_OFFSET,
2438                         .context_offs = DRA7XX_RM_L3MAIN1_SPARE_CME_CONTEXT_OFFSET,
2439                 },
2440         },
2441 };
2443 /* spare_icm */
2444 static struct omap_hwmod dra7xx_spare_icm_hwmod = {
2445         .name           = "spare_icm",
2446         .class          = &dra7xx_spare_hwmod_class,
2447         .clkdm_name     = "l3main1_clkdm",
2448         .main_clk       = "l4_root_clk_div",
2449         .prcm = {
2450                 .omap4 = {
2451                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL_OFFSET,
2452                         .context_offs = DRA7XX_RM_L3MAIN1_SPARE_ICM_CONTEXT_OFFSET,
2453                 },
2454         },
2455 };
2457 /* spare_iva2 */
2458 static struct omap_hwmod dra7xx_spare_iva2_hwmod = {
2459         .name           = "spare_iva2",
2460         .class          = &dra7xx_spare_hwmod_class,
2461         .clkdm_name     = "l3main1_clkdm",
2462         .main_clk       = "l3_iclk_div",
2463         .prcm = {
2464                 .omap4 = {
2465                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL_OFFSET,
2466                         .context_offs = DRA7XX_RM_L3MAIN1_SPARE_IVA2_CONTEXT_OFFSET,
2467                 },
2468         },
2469 };
2471 /* spare_safety1 */
2472 static struct omap_hwmod dra7xx_spare_safety1_hwmod = {
2473         .name           = "spare_safety1",
2474         .class          = &dra7xx_spare_hwmod_class,
2475         .clkdm_name     = "wkupaon_clkdm",
2476         .main_clk       = "wkupaon_iclk_mux",
2477         .prcm = {
2478                 .omap4 = {
2479                         .clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL_OFFSET,
2480                         .context_offs = DRA7XX_RM_WKUPAON_SPARE_SAFETY1_CONTEXT_OFFSET,
2481                 },
2482         },
2483 };
2485 /* spare_safety2 */
2486 static struct omap_hwmod dra7xx_spare_safety2_hwmod = {
2487         .name           = "spare_safety2",
2488         .class          = &dra7xx_spare_hwmod_class,
2489         .clkdm_name     = "wkupaon_clkdm",
2490         .main_clk       = "wkupaon_iclk_mux",
2491         .prcm = {
2492                 .omap4 = {
2493                         .clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL_OFFSET,
2494                         .context_offs = DRA7XX_RM_WKUPAON_SPARE_SAFETY2_CONTEXT_OFFSET,
2495                 },
2496         },
2497 };
2499 /* spare_safety3 */
2500 static struct omap_hwmod dra7xx_spare_safety3_hwmod = {
2501         .name           = "spare_safety3",
2502         .class          = &dra7xx_spare_hwmod_class,
2503         .clkdm_name     = "wkupaon_clkdm",
2504         .main_clk       = "wkupaon_iclk_mux",
2505         .prcm = {
2506                 .omap4 = {
2507                         .clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL_OFFSET,
2508                         .context_offs = DRA7XX_RM_WKUPAON_SPARE_SAFETY3_CONTEXT_OFFSET,
2509                 },
2510         },
2511 };
2513 /* spare_safety4 */
2514 static struct omap_hwmod dra7xx_spare_safety4_hwmod = {
2515         .name           = "spare_safety4",
2516         .class          = &dra7xx_spare_hwmod_class,
2517         .clkdm_name     = "wkupaon_clkdm",
2518         .main_clk       = "wkupaon_iclk_mux",
2519         .prcm = {
2520                 .omap4 = {
2521                         .clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL_OFFSET,
2522                         .context_offs = DRA7XX_RM_WKUPAON_SPARE_SAFETY4_CONTEXT_OFFSET,
2523                 },
2524         },
2525 };
2527 /* spare_unknown2 */
2528 static struct omap_hwmod dra7xx_spare_unknown2_hwmod = {
2529         .name           = "spare_unknown2",
2530         .class          = &dra7xx_spare_hwmod_class,
2531         .clkdm_name     = "wkupaon_clkdm",
2532         .main_clk       = "wkupaon_iclk_mux",
2533         .prcm = {
2534                 .omap4 = {
2535                         .clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL_OFFSET,
2536                         .context_offs = DRA7XX_RM_WKUPAON_SPARE_UNKNOWN2_CONTEXT_OFFSET,
2537                 },
2538         },
2539 };
2541 /* spare_unknown3 */
2542 static struct omap_hwmod dra7xx_spare_unknown3_hwmod = {
2543         .name           = "spare_unknown3",
2544         .class          = &dra7xx_spare_hwmod_class,
2545         .clkdm_name     = "wkupaon_clkdm",
2546         .main_clk       = "wkupaon_iclk_mux",
2547         .prcm = {
2548                 .omap4 = {
2549                         .clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL_OFFSET,
2550                         .context_offs = DRA7XX_RM_WKUPAON_SPARE_UNKNOWN3_CONTEXT_OFFSET,
2551                 },
2552         },
2553 };
2555 /* spare_unknown4 */
2556 static struct omap_hwmod dra7xx_spare_unknown4_hwmod = {
2557         .name           = "spare_unknown4",
2558         .class          = &dra7xx_spare_hwmod_class,
2559         .clkdm_name     = "l3main1_clkdm",
2560         .main_clk       = "l4_root_clk_div",
2561         .prcm = {
2562                 .omap4 = {
2563                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL_OFFSET,
2564                         .context_offs = DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN4_CONTEXT_OFFSET,
2565                 },
2566         },
2567 };
2569 /* spare_unknown5 */
2570 static struct omap_hwmod dra7xx_spare_unknown5_hwmod = {
2571         .name           = "spare_unknown5",
2572         .class          = &dra7xx_spare_hwmod_class,
2573         .clkdm_name     = "l3main1_clkdm",
2574         .main_clk       = "l4_root_clk_div",
2575         .prcm = {
2576                 .omap4 = {
2577                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL_OFFSET,
2578                         .context_offs = DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN5_CONTEXT_OFFSET,
2579                 },
2580         },
2581 };
2583 /* spare_unknown6 */
2584 static struct omap_hwmod dra7xx_spare_unknown6_hwmod = {
2585         .name           = "spare_unknown6",
2586         .class          = &dra7xx_spare_hwmod_class,
2587         .clkdm_name     = "l3main1_clkdm",
2588         .main_clk       = "l4_root_clk_div",
2589         .prcm = {
2590                 .omap4 = {
2591                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL_OFFSET,
2592                         .context_offs = DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN6_CONTEXT_OFFSET,
2593                 },
2594         },
2595 };
2597 /* spare_videopll1 */
2598 static struct omap_hwmod dra7xx_spare_videopll1_hwmod = {
2599         .name           = "spare_videopll1",
2600         .class          = &dra7xx_spare_hwmod_class,
2601         .clkdm_name     = "l3main1_clkdm",
2602         .main_clk       = "l4_root_clk_div",
2603         .prcm = {
2604                 .omap4 = {
2605                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL_OFFSET,
2606                         .context_offs = DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL1_CONTEXT_OFFSET,
2607                 },
2608         },
2609 };
2611 /* spare_videopll2 */
2612 static struct omap_hwmod dra7xx_spare_videopll2_hwmod = {
2613         .name           = "spare_videopll2",
2614         .class          = &dra7xx_spare_hwmod_class,
2615         .clkdm_name     = "l3main1_clkdm",
2616         .main_clk       = "l4_root_clk_div",
2617         .prcm = {
2618                 .omap4 = {
2619                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL_OFFSET,
2620                         .context_offs = DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL2_CONTEXT_OFFSET,
2621                 },
2622         },
2623 };
2625 /* spare_videopll3 */
2626 static struct omap_hwmod dra7xx_spare_videopll3_hwmod = {
2627         .name           = "spare_videopll3",
2628         .class          = &dra7xx_spare_hwmod_class,
2629         .clkdm_name     = "l3main1_clkdm",
2630         .main_clk       = "l4_root_clk_div",
2631         .prcm = {
2632                 .omap4 = {
2633                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL_OFFSET,
2634                         .context_offs = DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL3_CONTEXT_OFFSET,
2635                 },
2636         },
2637 };
2639 /*
2640  * 'spare_sata2' class
2641  *
2642  */
2644 static struct omap_hwmod_class dra7xx_spare_sata2_hwmod_class = {
2645         .name   = "spare_sata2",
2646 };
2648 /* spare_sata2 */
2649 static struct omap_hwmod dra7xx_spare_sata2_hwmod = {
2650         .name           = "spare_sata2",
2651         .class          = &dra7xx_spare_sata2_hwmod_class,
2652         .clkdm_name     = "l3main1_clkdm",
2653         .main_clk       = "l4_root_clk_div",
2654         .prcm = {
2655                 .omap4 = {
2656                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL_OFFSET,
2657                         .context_offs = DRA7XX_RM_L3MAIN1_SPARE_SATA2_CONTEXT_OFFSET,
2658                 },
2659         },
2660 };
2662 /*
2663  * 'spare_smartreflex' class
2664  *
2665  */
2667 static struct omap_hwmod_class dra7xx_spare_smartreflex_hwmod_class = {
2668         .name   = "spare_smartreflex",
2669 };
2671 /* spare_smartreflex_rtc */
2672 static struct omap_hwmod dra7xx_spare_smartreflex_rtc_hwmod = {
2673         .name           = "spare_smartreflex_rtc",
2674         .class          = &dra7xx_spare_smartreflex_hwmod_class,
2675         .clkdm_name     = "l4cfg_clkdm",
2676         .main_clk       = "l4_root_clk_div",
2677         .prcm = {
2678                 .omap4 = {
2679                         .clkctrl_offs = DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL_OFFSET,
2680                         .context_offs = DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_RTC_CONTEXT_OFFSET,
2681                 },
2682         },
2683 };
2685 /* spare_smartreflex_sdram */
2686 static struct omap_hwmod dra7xx_spare_smartreflex_sdram_hwmod = {
2687         .name           = "spare_smartreflex_sdram",
2688         .class          = &dra7xx_spare_smartreflex_hwmod_class,
2689         .clkdm_name     = "l4cfg_clkdm",
2690         .main_clk       = "l4_root_clk_div",
2691         .prcm = {
2692                 .omap4 = {
2693                         .clkctrl_offs = DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL_OFFSET,
2694                         .context_offs = DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CONTEXT_OFFSET,
2695                 },
2696         },
2697 };
2699 /* spare_smartreflex_wkup */
2700 static struct omap_hwmod dra7xx_spare_smartreflex_wkup_hwmod = {
2701         .name           = "spare_smartreflex_wkup",
2702         .class          = &dra7xx_spare_smartreflex_hwmod_class,
2703         .clkdm_name     = "l4cfg_clkdm",
2704         .main_clk       = "l4_root_clk_div",
2705         .prcm = {
2706                 .omap4 = {
2707                         .clkctrl_offs = DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL_OFFSET,
2708                         .context_offs = DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_WKUP_CONTEXT_OFFSET,
2709                 },
2710         },
2711 };
2713 /*
2714  * 'spinlock' class
2715  *
2716  */
2718 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
2719         .rev_offs       = 0x0000,
2720         .sysc_offs      = 0x0010,
2721         .syss_offs      = 0x0014,
2722         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2723                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2724                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2725         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2726                            SIDLE_SMART_WKUP),
2727         .sysc_fields    = &omap_hwmod_sysc_type1,
2728 };
2730 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
2731         .name   = "spinlock",
2732         .sysc   = &dra7xx_spinlock_sysc,
2733 };
2735 /* spinlock */
2736 static struct omap_hwmod dra7xx_spinlock_hwmod = {
2737         .name           = "spinlock",
2738         .class          = &dra7xx_spinlock_hwmod_class,
2739         .clkdm_name     = "l4cfg_clkdm",
2740         .main_clk       = "l3_iclk_div",
2741         .prcm = {
2742                 .omap4 = {
2743                         .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
2744                         .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
2745                 },
2746         },
2747 };
2749 /*
2750  * 'timer' class
2751  *
2752  * This class contains several variants: ['timer_1ms', 'timer_secure',
2753  * 'timer']
2754  */
2756 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
2757         .rev_offs       = 0x0000,
2758         .sysc_offs      = 0x0010,
2759         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2760                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2761         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2762                            SIDLE_SMART_WKUP),
2763         .sysc_fields    = &omap_hwmod_sysc_type2,
2764 };
2766 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
2767         .name   = "timer",
2768         .sysc   = &dra7xx_timer_1ms_sysc,
2769 };
2771 static struct omap_hwmod_class_sysconfig dra7xx_timer_secure_sysc = {
2772         .rev_offs       = 0x0000,
2773         .sysc_offs      = 0x0010,
2774         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2775                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2776         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2777                            SIDLE_SMART_WKUP),
2778         .sysc_fields    = &omap_hwmod_sysc_type2,
2779 };
2781 static struct omap_hwmod_class dra7xx_timer_secure_hwmod_class = {
2782         .name   = "timer",
2783         .sysc   = &dra7xx_timer_secure_sysc,
2784 };
2786 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
2787         .rev_offs       = 0x0000,
2788         .sysc_offs      = 0x0010,
2789         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2790                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2791         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2792                            SIDLE_SMART_WKUP),
2793         .sysc_fields    = &omap_hwmod_sysc_type2,
2794 };
2796 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
2797         .name   = "timer",
2798         .sysc   = &dra7xx_timer_sysc,
2799 };
2801 /* timer1 */
2802 static struct omap_hwmod_irq_info dra7xx_timer1_irqs[] = {
2803         { .irq = 37 + DRA7XX_IRQ_GIC_START },
2804         { .irq = -1 }
2805 };
2807 static struct omap_hwmod dra7xx_timer1_hwmod = {
2808         .name           = "timer1",
2809         .class          = &dra7xx_timer_1ms_hwmod_class,
2810         .clkdm_name     = "wkupaon_clkdm",
2811         .mpu_irqs       = dra7xx_timer1_irqs,
2812         .main_clk       = "timer1_gfclk_mux",
2813         .prcm = {
2814                 .omap4 = {
2815                         .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
2816                         .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
2817                         .modulemode   = MODULEMODE_SWCTRL,
2818                 },
2819         },
2820 };
2822 /* timer2 */
2823 static struct omap_hwmod_irq_info dra7xx_timer2_irqs[] = {
2824         { .irq = 38 + DRA7XX_IRQ_GIC_START },
2825         { .irq = -1 }
2826 };
2828 static struct omap_hwmod dra7xx_timer2_hwmod = {
2829         .name           = "timer2",
2830         .class          = &dra7xx_timer_1ms_hwmod_class,
2831         .clkdm_name     = "l4per_clkdm",
2832         .mpu_irqs       = dra7xx_timer2_irqs,
2833         .main_clk       = "timer2_gfclk_mux",
2834         .prcm = {
2835                 .omap4 = {
2836                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
2837                         .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
2838                         .modulemode   = MODULEMODE_SWCTRL,
2839                 },
2840         },
2841 };
2843 /* timer3 */
2844 static struct omap_hwmod_irq_info dra7xx_timer3_irqs[] = {
2845         { .irq = 39 + DRA7XX_IRQ_GIC_START },
2846         { .irq = -1 }
2847 };
2849 static struct omap_hwmod dra7xx_timer3_hwmod = {
2850         .name           = "timer3",
2851         .class          = &dra7xx_timer_hwmod_class,
2852         .clkdm_name     = "l4per_clkdm",
2853         .mpu_irqs       = dra7xx_timer3_irqs,
2854         .main_clk       = "timer3_gfclk_mux",
2855         .prcm = {
2856                 .omap4 = {
2857                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
2858                         .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
2859                         .modulemode   = MODULEMODE_SWCTRL,
2860                 },
2861         },
2862 };
2864 /* timer4 */
2865 static struct omap_hwmod_irq_info dra7xx_timer4_irqs[] = {
2866         { .irq = 40 + DRA7XX_IRQ_GIC_START },
2867         { .irq = -1 }
2868 };
2870 static struct omap_hwmod dra7xx_timer4_hwmod = {
2871         .name           = "timer4",
2872         .class          = &dra7xx_timer_secure_hwmod_class,
2873         .clkdm_name     = "l4per_clkdm",
2874         .mpu_irqs       = dra7xx_timer4_irqs,
2875         .main_clk       = "timer4_gfclk_mux",
2876         .prcm = {
2877                 .omap4 = {
2878                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
2879                         .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
2880                         .modulemode   = MODULEMODE_SWCTRL,
2881                 },
2882         },
2883 };
2885 /* timer5 */
2886 static struct omap_hwmod_irq_info dra7xx_timer5_irqs[] = {
2887         { .irq = 41 + DRA7XX_IRQ_GIC_START },
2888         { .irq = -1 }
2889 };
2891 static struct omap_hwmod dra7xx_timer5_hwmod = {
2892         .name           = "timer5",
2893         .class          = &dra7xx_timer_hwmod_class,
2894         .clkdm_name     = "ipu_clkdm",
2895         .mpu_irqs       = dra7xx_timer5_irqs,
2896         .main_clk       = "timer5_gfclk_mux",
2897         .prcm = {
2898                 .omap4 = {
2899                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
2900                         .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
2901                         .modulemode   = MODULEMODE_SWCTRL,
2902                 },
2903         },
2904 };
2906 /* timer6 */
2907 static struct omap_hwmod_irq_info dra7xx_timer6_irqs[] = {
2908         { .irq = 42 + DRA7XX_IRQ_GIC_START },
2909         { .irq = -1 }
2910 };
2912 static struct omap_hwmod dra7xx_timer6_hwmod = {
2913         .name           = "timer6",
2914         .class          = &dra7xx_timer_hwmod_class,
2915         .clkdm_name     = "ipu_clkdm",
2916         .mpu_irqs       = dra7xx_timer6_irqs,
2917         .main_clk       = "timer6_gfclk_mux",
2918         .prcm = {
2919                 .omap4 = {
2920                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
2921                         .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
2922                         .modulemode   = MODULEMODE_SWCTRL,
2923                 },
2924         },
2925 };
2927 /* timer7 */
2928 static struct omap_hwmod_irq_info dra7xx_timer7_irqs[] = {
2929         { .irq = 43 + DRA7XX_IRQ_GIC_START },
2930         { .irq = -1 }
2931 };
2933 static struct omap_hwmod dra7xx_timer7_hwmod = {
2934         .name           = "timer7",
2935         .class          = &dra7xx_timer_hwmod_class,
2936         .clkdm_name     = "ipu_clkdm",
2937         .mpu_irqs       = dra7xx_timer7_irqs,
2938         .main_clk       = "timer7_gfclk_mux",
2939         .prcm = {
2940                 .omap4 = {
2941                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
2942                         .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
2943                         .modulemode   = MODULEMODE_SWCTRL,
2944                 },
2945         },
2946 };
2948 /* timer8 */
2949 static struct omap_hwmod_irq_info dra7xx_timer8_irqs[] = {
2950         { .irq = 44 + DRA7XX_IRQ_GIC_START },
2951         { .irq = -1 }
2952 };
2954 static struct omap_hwmod dra7xx_timer8_hwmod = {
2955         .name           = "timer8",
2956         .class          = &dra7xx_timer_hwmod_class,
2957         .clkdm_name     = "ipu_clkdm",
2958         .mpu_irqs       = dra7xx_timer8_irqs,
2959         .main_clk       = "timer8_gfclk_mux",
2960         .prcm = {
2961                 .omap4 = {
2962                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
2963                         .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
2964                         .modulemode   = MODULEMODE_SWCTRL,
2965                 },
2966         },
2967 };
2969 /* timer9 */
2970 static struct omap_hwmod_irq_info dra7xx_timer9_irqs[] = {
2971         { .irq = 45 + DRA7XX_IRQ_GIC_START },
2972         { .irq = -1 }
2973 };
2975 static struct omap_hwmod dra7xx_timer9_hwmod = {
2976         .name           = "timer9",
2977         .class          = &dra7xx_timer_hwmod_class,
2978         .clkdm_name     = "l4per_clkdm",
2979         .mpu_irqs       = dra7xx_timer9_irqs,
2980         .main_clk       = "timer9_gfclk_mux",
2981         .prcm = {
2982                 .omap4 = {
2983                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
2984                         .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
2985                         .modulemode   = MODULEMODE_SWCTRL,
2986                 },
2987         },
2988 };
2990 /* timer10 */
2991 static struct omap_hwmod_irq_info dra7xx_timer10_irqs[] = {
2992         { .irq = 46 + DRA7XX_IRQ_GIC_START },
2993         { .irq = -1 }
2994 };
2996 static struct omap_hwmod dra7xx_timer10_hwmod = {
2997         .name           = "timer10",
2998         .class          = &dra7xx_timer_1ms_hwmod_class,
2999         .clkdm_name     = "l4per_clkdm",
3000         .mpu_irqs       = dra7xx_timer10_irqs,
3001         .main_clk       = "timer10_gfclk_mux",
3002         .prcm = {
3003                 .omap4 = {
3004                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
3005                         .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
3006                         .modulemode   = MODULEMODE_SWCTRL,
3007                 },
3008         },
3009 };
3011 /* timer11 */
3012 static struct omap_hwmod_irq_info dra7xx_timer11_irqs[] = {
3013         { .irq = 47 + DRA7XX_IRQ_GIC_START },
3014         { .irq = -1 }
3015 };
3017 static struct omap_hwmod dra7xx_timer11_hwmod = {
3018         .name           = "timer11",
3019         .class          = &dra7xx_timer_hwmod_class,
3020         .clkdm_name     = "l4per_clkdm",
3021         .mpu_irqs       = dra7xx_timer11_irqs,
3022         .main_clk       = "timer11_gfclk_mux",
3023         .prcm = {
3024                 .omap4 = {
3025                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
3026                         .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
3027                         .modulemode   = MODULEMODE_SWCTRL,
3028                 },
3029         },
3030 };
3032 /* timer13 */
3033 static struct omap_hwmod dra7xx_timer13_hwmod = {
3034         .name           = "timer13",
3035         .class          = &dra7xx_timer_hwmod_class,
3036         .clkdm_name     = "l4per3_clkdm",
3037         .main_clk       = "timer13_gfclk_mux",
3038         .prcm = {
3039                 .omap4 = {
3040                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
3041                         .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
3042                         .modulemode   = MODULEMODE_SWCTRL,
3043                 },
3044         },
3045 };
3047 /* timer14 */
3048 static struct omap_hwmod dra7xx_timer14_hwmod = {
3049         .name           = "timer14",
3050         .class          = &dra7xx_timer_hwmod_class,
3051         .clkdm_name     = "l4per3_clkdm",
3052         .main_clk       = "timer14_gfclk_mux",
3053         .prcm = {
3054                 .omap4 = {
3055                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
3056                         .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
3057                         .modulemode   = MODULEMODE_SWCTRL,
3058                 },
3059         },
3060 };