29d7ee61f3caa33e6ea0251f7f5ce8b0bbe40daf
[android-sdk/kernel-video.git] / arch / arm / mach-omap2 / omap_hwmod_7xx_data.c
1 /*
2  * Hardware modules present on the DRA7xx chips
3  *
4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5  *
6  * Paul Walmsley
7  * Benoit Cousson
8  *
9  * This file is automatically generated from the OMAP hardware databases.
10  * We respectfully ask that any modifications to this file be coordinated
11  * with the public linux-omap@vger.kernel.org mailing list and the
12  * authors above to ensure that the autogeneration scripts are kept
13  * up-to-date with the file contents.
14  *
15  * This program is free software; you can redistribute it and/or modify
16  * it under the terms of the GNU General Public License version 2 as
17  * published by the Free Software Foundation.
18  */
20 #include <linux/io.h>
21 #include <linux/platform_data/gpio-omap.h>
22 #include <linux/power/smartreflex.h>
23 #include <linux/platform_data/omap_ocp2scp.h>
24 #include <linux/i2c-omap.h>
26 #include <linux/omap-dma.h>
27 #include <linux/platform_data/spi-omap2-mcspi.h>
28 #include <linux/platform_data/asoc-ti-mcbsp.h>
29 #include <plat/dmtimer.h>
31 #include "omap_hwmod.h"
32 #include "omap_hwmod_common_data.h"
33 #include "cm1_7xx.h"
34 #include "cm2_7xx.h"
35 #include "prm7xx.h"
36 #include "prm-regbits-7xx.h"
37 #include "i2c.h"
38 #include "mmc.h"
39 #include "wd_timer.h"
41 /* Base offset for all DRA7XX interrupts external to MPUSS */
42 #define DRA7XX_IRQ_GIC_START    32
44 /* Base offset for all DRA7XX dma requests */
45 #define DRA7XX_DMA_REQ_START    1
48 /*
49  * IP blocks
50  */
52 /*
53  * 'dmm' class
54  * instance(s): dmm
55  */
56 static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
57         .name   = "dmm",
58 };
60 /* dmm */
61 static struct omap_hwmod_irq_info dra7xx_dmm_irqs[] = {
62         { .irq = 113 + DRA7XX_IRQ_GIC_START },
63         { .irq = -1 }
64 };
66 static struct omap_hwmod dra7xx_dmm_hwmod = {
67         .name           = "dmm",
68         .class          = &dra7xx_dmm_hwmod_class,
69         .clkdm_name     = "emif_clkdm",
70         .mpu_irqs       = dra7xx_dmm_irqs,
71         .prcm = {
72                 .omap4 = {
73                         .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
74                         .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
75                 },
76         },
77 };
79 /*
80  * 'emif_ocp_fw' class
81  * instance(s): emif_ocp_fw
82  */
83 static struct omap_hwmod_class dra7xx_emif_ocp_fw_hwmod_class = {
84         .name   = "emif_ocp_fw",
85 };
87 /* emif_ocp_fw */
88 static struct omap_hwmod dra7xx_emif_ocp_fw_hwmod = {
89         .name           = "emif_ocp_fw",
90         .class          = &dra7xx_emif_ocp_fw_hwmod_class,
91         .clkdm_name     = "emif_clkdm",
92         .prcm = {
93                 .omap4 = {
94                         .clkctrl_offs = DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET,
95                         .context_offs = DRA7XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET,
96                 },
97         },
98 };
100 /*
101  * 'l3' class
102  * instance(s): l3_instr, l3_main_1, l3_main_2
103  */
104 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
105         .name   = "l3",
106 };
108 /* l3_instr */
109 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
110         .name           = "l3_instr",
111         .class          = &dra7xx_l3_hwmod_class,
112         .clkdm_name     = "l3instr_clkdm",
113         .prcm = {
114                 .omap4 = {
115                         .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
116                         .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
117                         .modulemode   = MODULEMODE_HWCTRL,
118                 },
119         },
120 };
122 /* l3_main_1 */
123 static struct omap_hwmod_irq_info dra7xx_l3_main_1_irqs[] = {
124         { .name = "dbg_err", .irq = 9 + DRA7XX_IRQ_GIC_START },
125         { .name = "app_err", .irq = 10 + DRA7XX_IRQ_GIC_START },
126         { .name = "stat_alarm", .irq = 16 + DRA7XX_IRQ_GIC_START },
127         { .irq = -1 }
128 };
130 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
131         .name           = "l3_main_1",
132         .class          = &dra7xx_l3_hwmod_class,
133         .clkdm_name     = "l3main1_clkdm",
134         .mpu_irqs       = dra7xx_l3_main_1_irqs,
135         .prcm = {
136                 .omap4 = {
137                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
138                         .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
139                 },
140         },
141 };
143 /* l3_main_2 */
144 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
145         .name           = "l3_main_2",
146         .class          = &dra7xx_l3_hwmod_class,
147         .clkdm_name     = "l3instr_clkdm",
148         .prcm = {
149                 .omap4 = {
150                         .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
151                         .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
152                         .modulemode   = MODULEMODE_HWCTRL,
153                 },
154         },
155 };
157 /*
158  * 'l4' class
159  * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
160  */
161 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
162         .name   = "l4",
163 };
165 /* l4_cfg */
166 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
167         .name           = "l4_cfg",
168         .class          = &dra7xx_l4_hwmod_class,
169         .clkdm_name     = "l4cfg_clkdm",
170         .prcm = {
171                 .omap4 = {
172                         .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
173                         .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
174                 },
175         },
176 };
178 /* l4_per1 */
179 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
180         .name           = "l4_per1",
181         .class          = &dra7xx_l4_hwmod_class,
182         .clkdm_name     = "l4per_clkdm",
183         .prcm = {
184                 .omap4 = {
185                         .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
186                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
187                 },
188         },
189 };
191 /* l4_per2 */
192 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
193         .name           = "l4_per2",
194         .class          = &dra7xx_l4_hwmod_class,
195         .clkdm_name     = "l4per2_clkdm",
196         .prcm = {
197                 .omap4 = {
198                         .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
199                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
200                 },
201         },
202 };
204 /* l4_per3 */
205 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
206         .name           = "l4_per3",
207         .class          = &dra7xx_l4_hwmod_class,
208         .clkdm_name     = "l4per3_clkdm",
209         .prcm = {
210                 .omap4 = {
211                         .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
212                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
213                 },
214         },
215 };
217 /* l4_wkup */
218 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
219         .name           = "l4_wkup",
220         .class          = &dra7xx_l4_hwmod_class,
221         .clkdm_name     = "wkupaon_clkdm",
222         .prcm = {
223                 .omap4 = {
224                         .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
225                         .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
226                 },
227         },
228 };
230 /*
231  * 'mpu_bus' class
232  * instance(s): mpu_private
233  */
234 static struct omap_hwmod_class dra7xx_mpu_bus_hwmod_class = {
235         .name   = "mpu_bus",
236 };
238 /* mpu_private */
239 static struct omap_hwmod dra7xx_mpu_private_hwmod = {
240         .name           = "mpu_private",
241         .class          = &dra7xx_mpu_bus_hwmod_class,
242         .clkdm_name     = "mpu_clkdm",
243         .prcm = {
244                 .omap4 = {
245                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
246                 },
247         },
248 };
250 /*
251  * 'ocp_wp_noc' class
252  * instance(s): ocp_wp_noc
253  */
254 static struct omap_hwmod_class dra7xx_ocp_wp_noc_hwmod_class = {
255         .name   = "ocp_wp_noc",
256 };
258 /* ocp_wp_noc */
259 static struct omap_hwmod dra7xx_ocp_wp_noc_hwmod = {
260         .name           = "ocp_wp_noc",
261         .class          = &dra7xx_ocp_wp_noc_hwmod_class,
262         .clkdm_name     = "l3instr_clkdm",
263         .prcm = {
264                 .omap4 = {
265                         .clkctrl_offs = DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET,
266                         .context_offs = DRA7XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET,
267                         .modulemode   = MODULEMODE_HWCTRL,
268                 },
269         },
270 };
272 /*
273  * 'atl' class
274  *
275  */
277 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
278         .name   = "atl",
279 };
281 /* atl */
282 static struct omap_hwmod dra7xx_atl_hwmod = {
283         .name           = "atl",
284         .class          = &dra7xx_atl_hwmod_class,
285         .clkdm_name     = "atl_clkdm",
286         .main_clk       = "atl_gfclk_mux",
287         .prcm = {
288                 .omap4 = {
289                         .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
290                         .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
291                         .modulemode   = MODULEMODE_SWCTRL,
292                 },
293         },
294 };
296 /*
297  * 'bb2d' class
298  *
299  */
301 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
302         .name   = "bb2d",
303 };
305 /* bb2d */
306 static struct omap_hwmod_irq_info dra7xx_bb2d_irqs[] = {
307         { .irq = 125 + DRA7XX_IRQ_GIC_START },
308         { .irq = -1 }
309 };
311 static struct omap_hwmod dra7xx_bb2d_hwmod = {
312         .name           = "bb2d",
313         .class          = &dra7xx_bb2d_hwmod_class,
314         .clkdm_name     = "dss_clkdm",
315         .mpu_irqs       = dra7xx_bb2d_irqs,
316         .main_clk       = "dpll_core_h24x2_ck",
317         .prcm = {
318                 .omap4 = {
319                         .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
320                         .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
321                         .modulemode   = MODULEMODE_SWCTRL,
322                 },
323         },
324 };
326 /*
327  * 'counter' class
328  *
329  */
331 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
332         .rev_offs       = 0x0000,
333         .sysc_offs      = 0x0010,
334         .sysc_flags     = SYSC_HAS_SIDLEMODE,
335         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
336                            SIDLE_SMART_WKUP),
337         .sysc_fields    = &omap_hwmod_sysc_type1,
338 };
340 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
341         .name   = "counter",
342         .sysc   = &dra7xx_counter_sysc,
343 };
345 /* counter_32k */
346 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
347         .name           = "counter_32k",
348         .class          = &dra7xx_counter_hwmod_class,
349         .clkdm_name     = "wkupaon_clkdm",
350         .flags          = HWMOD_SWSUP_SIDLE,
351         .main_clk       = "wkupaon_iclk_mux",
352         .prcm = {
353                 .omap4 = {
354                         .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
355                         .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
356                 },
357         },
358 };
360 /*
361  * 'ctrl_module' class
362  *
363  */
365 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
366         .name   = "ctrl_module",
367 };
369 /* ctrl_module_wkup */
370 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
371         .name           = "ctrl_module_wkup",
372         .class          = &dra7xx_ctrl_module_hwmod_class,
373         .clkdm_name     = "wkupaon_clkdm",
374         .prcm = {
375                 .omap4 = {
376                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
377                 },
378         },
379 };
381 /*
382  * 'dcan' class
383  *
384  */
386 static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
387         .name   = "dcan",
388 };
390 /* dcan1 */
391 static struct omap_hwmod dra7xx_dcan1_hwmod = {
392         .name           = "dcan1",
393         .class          = &dra7xx_dcan_hwmod_class,
394         .clkdm_name     = "wkupaon_clkdm",
395         .main_clk       = "dcan1_sys_clk_mux",
396         .prcm = {
397                 .omap4 = {
398                         .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
399                         .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
400                         .modulemode   = MODULEMODE_SWCTRL,
401                 },
402         },
403 };
405 /* dcan2 */
406 static struct omap_hwmod dra7xx_dcan2_hwmod = {
407         .name           = "dcan2",
408         .class          = &dra7xx_dcan_hwmod_class,
409         .clkdm_name     = "l4per2_clkdm",
410         .main_clk       = "sys_clkin1",
411         .prcm = {
412                 .omap4 = {
413                         .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
414                         .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
415                         .modulemode   = MODULEMODE_SWCTRL,
416                 },
417         },
418 };
420 /*
421  * 'dma' class
422  *
423  */
425 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
426         .rev_offs       = 0x0000,
427         .sysc_offs      = 0x002c,
428         .syss_offs      = 0x0028,
429         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
430                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
431                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
432                            SYSS_HAS_RESET_STATUS),
433         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
434                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
435                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
436         .sysc_fields    = &omap_hwmod_sysc_type1,
437 };
439 static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
440         .name   = "dma",
441         .sysc   = &dra7xx_dma_sysc,
442 };
444 /* dma dev_attr */
445 static struct omap_dma_dev_attr dma_dev_attr = {
446         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
447                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
448         .lch_count      = 32,
449 };
451 /* dma_system */
452 static struct omap_hwmod_irq_info dra7xx_dma_system_irqs[] = {
453         { .name = "0", .irq = 12 + DRA7XX_IRQ_GIC_START },
454         { .name = "1", .irq = 13 + DRA7XX_IRQ_GIC_START },
455         { .name = "2", .irq = 14 + DRA7XX_IRQ_GIC_START },
456         { .name = "3", .irq = 15 + DRA7XX_IRQ_GIC_START },
457         { .irq = -1 }
458 };
460 static struct omap_hwmod dra7xx_dma_system_hwmod = {
461         .name           = "dma_system",
462         .class          = &dra7xx_dma_hwmod_class,
463         .clkdm_name     = "dma_clkdm",
464         .mpu_irqs       = dra7xx_dma_system_irqs,
465         .main_clk       = "l3_iclk_div",
466         .prcm = {
467                 .omap4 = {
468                         .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
469                         .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
470                 },
471         },
472         .dev_attr       = &dma_dev_attr,
473 };
475 /*
476  * 'dss' class
477  *
478  */
480 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
481         .rev_offs       = 0x0000,
482         .syss_offs      = 0x0014,
483         .sysc_flags     = SYSS_HAS_RESET_STATUS,
484 };
486 static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
487         .name   = "dss",
488         .sysc   = &dra7xx_dss_sysc,
489         .reset  = omap_dss_reset,
490 };
492 /* dss */
493 static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
494         { .dma_req = 75 + DRA7XX_DMA_REQ_START },
495         { .dma_req = -1 }
496 };
498 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
499         { .role = "dss_clk", .clk = "dss_dss_clk" },
500         { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
501         { .role = "32khz_clk", .clk = "dss_32khz_clk" },
502         { .role = "video2_clk", .clk = "dss_video2_clk" },
503         { .role = "video1_clk", .clk = "dss_video1_clk" },
504         { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
505 };
507 static struct omap_hwmod dra7xx_dss_hwmod = {
508         .name           = "dss_core",
509         .class          = &dra7xx_dss_hwmod_class,
510         .clkdm_name     = "dss_clkdm",
511         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
512         .sdma_reqs      = dra7xx_dss_sdma_reqs,
513         .main_clk       = "dss_dss_clk",
514         .prcm = {
515                 .omap4 = {
516                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
517                         .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
518                         .modulemode   = MODULEMODE_SWCTRL,
519                 },
520         },
521         .opt_clks       = dss_opt_clks,
522         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
523 };
525 /*
526  * 'dispc' class
527  * display controller
528  */
530 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
531         .rev_offs       = 0x0000,
532         .sysc_offs      = 0x0010,
533         .syss_offs      = 0x0014,
534         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
535                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
536                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
537                            SYSS_HAS_RESET_STATUS),
538         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
539                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
540         .sysc_fields    = &omap_hwmod_sysc_type1,
541 };
543 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
544         .name   = "dispc",
545         .sysc   = &dra7xx_dispc_sysc,
546 };
548 /* dss_dispc */
549 static struct omap_hwmod_irq_info dra7xx_dss_dispc_irqs[] = {
550         { .irq = 25 + DRA7XX_IRQ_GIC_START },
551         { .irq = -1 }
552 };
554 static struct omap_hwmod_dma_info dra7xx_dss_dispc_sdma_reqs[] = {
555         { .dma_req = 5 + DRA7XX_DMA_REQ_START },
556         { .dma_req = -1 }
557 };
559 /* dss_dispc dev_attr */
560 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
561         .has_framedonetv_irq    = 1,
562         .manager_count          = 4,
563 };
565 static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
566         .name           = "dss_dispc",
567         .class          = &dra7xx_dispc_hwmod_class,
568         .clkdm_name     = "dss_clkdm",
569         .mpu_irqs       = dra7xx_dss_dispc_irqs,
570         .sdma_reqs      = dra7xx_dss_dispc_sdma_reqs,
571         .main_clk       = "dss_dss_clk",
572         .prcm = {
573                 .omap4 = {
574                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
575                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
576                 },
577         },
578         .dev_attr       = &dss_dispc_dev_attr,
579 };
581 /*
582  * 'hdmi' class
583  * hdmi controller
584  */
586 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
587         .rev_offs       = 0x0000,
588         .sysc_offs      = 0x0010,
589         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
590                            SYSC_HAS_SOFTRESET),
591         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
592                            SIDLE_SMART_WKUP),
593         .sysc_fields    = &omap_hwmod_sysc_type2,
594 };
596 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
597         .name   = "hdmi",
598         .sysc   = &dra7xx_hdmi_sysc,
599 };
601 /* dss_hdmi */
602 static struct omap_hwmod_irq_info dra7xx_dss_hdmi_irqs[] = {
603         { .irq = 101 + DRA7XX_IRQ_GIC_START },
604         { .irq = -1 }
605 };
607 static struct omap_hwmod_dma_info dra7xx_dss_hdmi_sdma_reqs[] = {
608         { .dma_req = 75 + DRA7XX_DMA_REQ_START },
609         { .dma_req = -1 }
610 };
612 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
613         { .role = "sys_clk", .clk = "dss_hdmi_clk" },
614 };
616 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
617         .name           = "dss_hdmi",
618         .class          = &dra7xx_hdmi_hwmod_class,
619         .clkdm_name     = "dss_clkdm",
620         .mpu_irqs       = dra7xx_dss_hdmi_irqs,
621         .sdma_reqs      = dra7xx_dss_hdmi_sdma_reqs,
622         .main_clk       = "dss_48mhz_clk",
623         .prcm = {
624                 .omap4 = {
625                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
626                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
627                 },
628         },
629         .opt_clks       = dss_hdmi_opt_clks,
630         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
631 };
633 /*
634  * 'elm' class
635  *
636  */
638 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
639         .rev_offs       = 0x0000,
640         .sysc_offs      = 0x0010,
641         .syss_offs      = 0x0014,
642         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
643                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
644                            SYSS_HAS_RESET_STATUS),
645         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
646                            SIDLE_SMART_WKUP),
647         .sysc_fields    = &omap_hwmod_sysc_type1,
648 };
650 static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
651         .name   = "elm",
652         .sysc   = &dra7xx_elm_sysc,
653 };
655 /* elm */
656 static struct omap_hwmod_irq_info dra7xx_elm_irqs[] = {
657         { .irq = 4 + DRA7XX_IRQ_GIC_START },
658         { .irq = -1 }
659 };
661 static struct omap_hwmod dra7xx_elm_hwmod = {
662         .name           = "elm",
663         .class          = &dra7xx_elm_hwmod_class,
664         .clkdm_name     = "l4per_clkdm",
665         .mpu_irqs       = dra7xx_elm_irqs,
666         .main_clk       = "l3_iclk_div",
667         .prcm = {
668                 .omap4 = {
669                         .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
670                         .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
671                 },
672         },
673 };
675 /*
676  * 'emif' class
677  *
678  */
680 static struct omap_hwmod_class_sysconfig dra7xx_emif_sysc = {
681         .rev_offs       = 0x0000,
682 };
684 static struct omap_hwmod_class dra7xx_emif_hwmod_class = {
685         .name   = "emif",
686         .sysc   = &dra7xx_emif_sysc,
687 };
689 /* emif1 */
690 static struct omap_hwmod_irq_info dra7xx_emif1_irqs[] = {
691         { .irq = 110 + DRA7XX_IRQ_GIC_START },
692         { .irq = -1 }
693 };
695 static struct omap_hwmod dra7xx_emif1_hwmod = {
696         .name           = "emif1",
697         .class          = &dra7xx_emif_hwmod_class,
698         .clkdm_name     = "emif_clkdm",
699         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
700         .mpu_irqs       = dra7xx_emif1_irqs,
701         .main_clk       = "dpll_ddr_h11x2_ck",
702         .prcm = {
703                 .omap4 = {
704                         .clkctrl_offs = DRA7XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
705                         .context_offs = DRA7XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
706                         .modulemode   = MODULEMODE_HWCTRL,
707                 },
708         },
709 };
711 /* emif2 */
712 static struct omap_hwmod_irq_info dra7xx_emif2_irqs[] = {
713         { .irq = 111 + DRA7XX_IRQ_GIC_START },
714         { .irq = -1 }
715 };
717 static struct omap_hwmod dra7xx_emif2_hwmod = {
718         .name           = "emif2",
719         .class          = &dra7xx_emif_hwmod_class,
720         .clkdm_name     = "emif_clkdm",
721         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
722         .mpu_irqs       = dra7xx_emif2_irqs,
723         .main_clk       = "dpll_ddr_h11x2_ck",
724         .prcm = {
725                 .omap4 = {
726                         .clkctrl_offs = DRA7XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
727                         .context_offs = DRA7XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
728                         .modulemode   = MODULEMODE_HWCTRL,
729                 },
730         },
731 };
733 /*
734  * 'gpio' class
735  *
736  */
738 static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
739         .rev_offs       = 0x0000,
740         .sysc_offs      = 0x0010,
741         .syss_offs      = 0x0114,
742         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
743                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
744                            SYSS_HAS_RESET_STATUS),
745         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
746                            SIDLE_SMART_WKUP),
747         .sysc_fields    = &omap_hwmod_sysc_type1,
748 };
750 static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
751         .name   = "gpio",
752         .sysc   = &dra7xx_gpio_sysc,
753         .rev    = 2,
754 };
756 /* gpio dev_attr */
757 static struct omap_gpio_dev_attr gpio_dev_attr = {
758         .bank_width     = 32,
759         .dbck_flag      = true,
760 };
762 /* gpio1 */
763 static struct omap_hwmod_irq_info dra7xx_gpio1_irqs[] = {
764         { .irq = 29 + DRA7XX_IRQ_GIC_START },
765         { .irq = -1 }
766 };
768 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
769         { .role = "dbclk", .clk = "gpio1_dbclk" },
770 };
772 static struct omap_hwmod dra7xx_gpio1_hwmod = {
773         .name           = "gpio1",
774         .class          = &dra7xx_gpio_hwmod_class,
775         .clkdm_name     = "wkupaon_clkdm",
776         .mpu_irqs       = dra7xx_gpio1_irqs,
777         .main_clk       = "wkupaon_iclk_mux",
778         .prcm = {
779                 .omap4 = {
780                         .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
781                         .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
782                         .modulemode   = MODULEMODE_HWCTRL,
783                 },
784         },
785         .opt_clks       = gpio1_opt_clks,
786         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
787         .dev_attr       = &gpio_dev_attr,
788 };
790 /* gpio2 */
791 static struct omap_hwmod_irq_info dra7xx_gpio2_irqs[] = {
792         { .irq = 30 + DRA7XX_IRQ_GIC_START },
793         { .irq = -1 }
794 };
796 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
797         { .role = "dbclk", .clk = "gpio2_dbclk" },
798 };
800 static struct omap_hwmod dra7xx_gpio2_hwmod = {
801         .name           = "gpio2",
802         .class          = &dra7xx_gpio_hwmod_class,
803         .clkdm_name     = "l4per_clkdm",
804         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
805         .mpu_irqs       = dra7xx_gpio2_irqs,
806         .main_clk       = "l3_iclk_div",
807         .prcm = {
808                 .omap4 = {
809                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
810                         .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
811                         .modulemode   = MODULEMODE_HWCTRL,
812                 },
813         },
814         .opt_clks       = gpio2_opt_clks,
815         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
816         .dev_attr       = &gpio_dev_attr,
817 };
819 /* gpio3 */
820 static struct omap_hwmod_irq_info dra7xx_gpio3_irqs[] = {
821         { .irq = 31 + DRA7XX_IRQ_GIC_START },
822         { .irq = -1 }
823 };
825 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
826         { .role = "dbclk", .clk = "gpio3_dbclk" },
827 };
829 static struct omap_hwmod dra7xx_gpio3_hwmod = {
830         .name           = "gpio3",
831         .class          = &dra7xx_gpio_hwmod_class,
832         .clkdm_name     = "l4per_clkdm",
833         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
834         .mpu_irqs       = dra7xx_gpio3_irqs,
835         .main_clk       = "l3_iclk_div",
836         .prcm = {
837                 .omap4 = {
838                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
839                         .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
840                         .modulemode   = MODULEMODE_HWCTRL,
841                 },
842         },
843         .opt_clks       = gpio3_opt_clks,
844         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
845         .dev_attr       = &gpio_dev_attr,
846 };
848 /* gpio4 */
849 static struct omap_hwmod_irq_info dra7xx_gpio4_irqs[] = {
850         { .irq = 32 + DRA7XX_IRQ_GIC_START },
851         { .irq = -1 }
852 };
854 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
855         { .role = "dbclk", .clk = "gpio4_dbclk" },
856 };
858 static struct omap_hwmod dra7xx_gpio4_hwmod = {
859         .name           = "gpio4",
860         .class          = &dra7xx_gpio_hwmod_class,
861         .clkdm_name     = "l4per_clkdm",
862         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
863         .mpu_irqs       = dra7xx_gpio4_irqs,
864         .main_clk       = "l3_iclk_div",
865         .prcm = {
866                 .omap4 = {
867                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
868                         .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
869                         .modulemode   = MODULEMODE_HWCTRL,
870                 },
871         },
872         .opt_clks       = gpio4_opt_clks,
873         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
874         .dev_attr       = &gpio_dev_attr,
875 };
877 /* gpio5 */
878 static struct omap_hwmod_irq_info dra7xx_gpio5_irqs[] = {
879         { .irq = 33 + DRA7XX_IRQ_GIC_START },
880         { .irq = -1 }
881 };
883 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
884         { .role = "dbclk", .clk = "gpio5_dbclk" },
885 };
887 static struct omap_hwmod dra7xx_gpio5_hwmod = {
888         .name           = "gpio5",
889         .class          = &dra7xx_gpio_hwmod_class,
890         .clkdm_name     = "l4per_clkdm",
891         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
892         .mpu_irqs       = dra7xx_gpio5_irqs,
893         .main_clk       = "l3_iclk_div",
894         .prcm = {
895                 .omap4 = {
896                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
897                         .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
898                         .modulemode   = MODULEMODE_HWCTRL,
899                 },
900         },
901         .opt_clks       = gpio5_opt_clks,
902         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
903         .dev_attr       = &gpio_dev_attr,
904 };
906 /* gpio6 */
907 static struct omap_hwmod_irq_info dra7xx_gpio6_irqs[] = {
908         { .irq = 34 + DRA7XX_IRQ_GIC_START },
909         { .irq = -1 }
910 };
912 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
913         { .role = "dbclk", .clk = "gpio6_dbclk" },
914 };
916 static struct omap_hwmod dra7xx_gpio6_hwmod = {
917         .name           = "gpio6",
918         .class          = &dra7xx_gpio_hwmod_class,
919         .clkdm_name     = "l4per_clkdm",
920         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
921         .mpu_irqs       = dra7xx_gpio6_irqs,
922         .main_clk       = "l3_iclk_div",
923         .prcm = {
924                 .omap4 = {
925                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
926                         .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
927                         .modulemode   = MODULEMODE_HWCTRL,
928                 },
929         },
930         .opt_clks       = gpio6_opt_clks,
931         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
932         .dev_attr       = &gpio_dev_attr,
933 };
935 /* gpio7 */
936 static struct omap_hwmod_irq_info dra7xx_gpio7_irqs[] = {
937         { .irq = 35 + DRA7XX_IRQ_GIC_START },
938         { .irq = -1 }
939 };
941 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
942         { .role = "dbclk", .clk = "gpio7_dbclk" },
943 };
945 static struct omap_hwmod dra7xx_gpio7_hwmod = {
946         .name           = "gpio7",
947         .class          = &dra7xx_gpio_hwmod_class,
948         .clkdm_name     = "l4per_clkdm",
949         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
950         .mpu_irqs       = dra7xx_gpio7_irqs,
951         .main_clk       = "l3_iclk_div",
952         .prcm = {
953                 .omap4 = {
954                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
955                         .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
956                         .modulemode   = MODULEMODE_HWCTRL,
957                 },
958         },
959         .opt_clks       = gpio7_opt_clks,
960         .opt_clks_cnt   = ARRAY_SIZE(gpio7_opt_clks),
961         .dev_attr       = &gpio_dev_attr,
962 };
964 /* gpio8 */
965 static struct omap_hwmod_irq_info dra7xx_gpio8_irqs[] = {
966         { .irq = 121 + DRA7XX_IRQ_GIC_START },
967         { .irq = -1 }
968 };
970 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
971         { .role = "dbclk", .clk = "gpio8_dbclk" },
972 };
974 static struct omap_hwmod dra7xx_gpio8_hwmod = {
975         .name           = "gpio8",
976         .class          = &dra7xx_gpio_hwmod_class,
977         .clkdm_name     = "l4per_clkdm",
978         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
979         .mpu_irqs       = dra7xx_gpio8_irqs,
980         .main_clk       = "l3_iclk_div",
981         .prcm = {
982                 .omap4 = {
983                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
984                         .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
985                         .modulemode   = MODULEMODE_HWCTRL,
986                 },
987         },
988         .opt_clks       = gpio8_opt_clks,
989         .opt_clks_cnt   = ARRAY_SIZE(gpio8_opt_clks),
990         .dev_attr       = &gpio_dev_attr,
991 };
993 /*
994  * 'gpmc' class
995  *
996  */
998 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
999         .rev_offs       = 0x0000,
1000         .sysc_offs      = 0x0010,
1001         .syss_offs      = 0x0014,
1002         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1003                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1004         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1005                            SIDLE_SMART_WKUP),
1006         .sysc_fields    = &omap_hwmod_sysc_type1,
1007 };
1009 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
1010         .name   = "gpmc",
1011         .sysc   = &dra7xx_gpmc_sysc,
1012 };
1014 /* gpmc */
1015 static struct omap_hwmod_irq_info dra7xx_gpmc_irqs[] = {
1016         { .irq = 20 + DRA7XX_IRQ_GIC_START },
1017         { .irq = -1 }
1018 };
1020 static struct omap_hwmod_dma_info dra7xx_gpmc_sdma_reqs[] = {
1021         { .dma_req = 3 + DRA7XX_DMA_REQ_START },
1022         { .dma_req = -1 }
1023 };
1025 static struct omap_hwmod dra7xx_gpmc_hwmod = {
1026         .name           = "gpmc",
1027         .class          = &dra7xx_gpmc_hwmod_class,
1028         .clkdm_name     = "l3main1_clkdm",
1029         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1030         .mpu_irqs       = dra7xx_gpmc_irqs,
1031         .sdma_reqs      = dra7xx_gpmc_sdma_reqs,
1032         .main_clk       = "l3_iclk_div",
1033         .prcm = {
1034                 .omap4 = {
1035                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
1036                         .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
1037                         .modulemode   = MODULEMODE_HWCTRL,
1038                 },
1039         },
1040 };
1042 /*
1043  * 'hdq1w' class
1044  *
1045  */
1047 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
1048         .rev_offs       = 0x0000,
1049         .sysc_offs      = 0x0014,
1050         .syss_offs      = 0x0018,
1051         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1052                            SYSS_HAS_RESET_STATUS),
1053         .sysc_fields    = &omap_hwmod_sysc_type1,
1054 };
1056 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
1057         .name   = "hdq1w",
1058         .sysc   = &dra7xx_hdq1w_sysc,
1059 };
1061 /* hdq1w */
1062 static struct omap_hwmod_irq_info dra7xx_hdq1w_irqs[] = {
1063         { .irq = 58 + DRA7XX_IRQ_GIC_START },
1064         { .irq = -1 }
1065 };
1067 static struct omap_hwmod dra7xx_hdq1w_hwmod = {
1068         .name           = "hdq1w",
1069         .class          = &dra7xx_hdq1w_hwmod_class,
1070         .clkdm_name     = "l4per_clkdm",
1071         .flags          = HWMOD_INIT_NO_RESET,
1072         .mpu_irqs       = dra7xx_hdq1w_irqs,
1073         .main_clk       = "func_12m_fclk",
1074         .prcm = {
1075                 .omap4 = {
1076                         .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1077                         .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1078                         .modulemode   = MODULEMODE_SWCTRL,
1079                 },
1080         },
1081 };
1083 /*
1084  * 'i2c' class
1085  *
1086  */
1088 static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
1089         .sysc_offs      = 0x0010,
1090         .syss_offs      = 0x0090,
1091         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1092                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1093                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1094         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1095                            SIDLE_SMART_WKUP),
1096         .clockact       = CLOCKACT_TEST_ICLK,
1097         .sysc_fields    = &omap_hwmod_sysc_type1,
1098 };
1100 static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
1101         .name   = "i2c",
1102         .sysc   = &dra7xx_i2c_sysc,
1103         .reset  = &omap_i2c_reset,
1104         .rev    = OMAP_I2C_IP_VERSION_2,
1105 };
1107 /* i2c dev_attr */
1108 static struct omap_i2c_dev_attr i2c_dev_attr = {
1109         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1110 };
1112 /* i2c1 */
1113 static struct omap_hwmod_irq_info dra7xx_i2c1_irqs[] = {
1114         { .irq = 56 + DRA7XX_IRQ_GIC_START },
1115         { .irq = -1 }
1116 };
1118 static struct omap_hwmod_dma_info dra7xx_i2c1_sdma_reqs[] = {
1119         { .name = "27", .dma_req = 26 + DRA7XX_DMA_REQ_START },
1120         { .name = "28", .dma_req = 27 + DRA7XX_DMA_REQ_START },
1121         { .dma_req = -1 }
1122 };
1124 static struct omap_hwmod dra7xx_i2c1_hwmod = {
1125         .name           = "i2c1",
1126         .class          = &dra7xx_i2c_hwmod_class,
1127         .clkdm_name     = "l4per_clkdm",
1128         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1129         .mpu_irqs       = dra7xx_i2c1_irqs,
1130         .sdma_reqs      = dra7xx_i2c1_sdma_reqs,
1131         .main_clk       = "func_96m_fclk",
1132         .prcm = {
1133                 .omap4 = {
1134                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1135                         .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
1136                         .modulemode   = MODULEMODE_SWCTRL,
1137                 },
1138         },
1139         .dev_attr       = &i2c_dev_attr,
1140 };
1142 /* i2c2 */
1143 static struct omap_hwmod_irq_info dra7xx_i2c2_irqs[] = {
1144         { .irq = 57 + DRA7XX_IRQ_GIC_START },
1145         { .irq = -1 }
1146 };
1148 static struct omap_hwmod_dma_info dra7xx_i2c2_sdma_reqs[] = {
1149         { .name = "29", .dma_req = 28 + DRA7XX_DMA_REQ_START },
1150         { .name = "30", .dma_req = 29 + DRA7XX_DMA_REQ_START },
1151         { .dma_req = -1 }
1152 };
1154 static struct omap_hwmod dra7xx_i2c2_hwmod = {
1155         .name           = "i2c2",
1156         .class          = &dra7xx_i2c_hwmod_class,
1157         .clkdm_name     = "l4per_clkdm",
1158         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1159         .mpu_irqs       = dra7xx_i2c2_irqs,
1160         .sdma_reqs      = dra7xx_i2c2_sdma_reqs,
1161         .main_clk       = "func_96m_fclk",
1162         .prcm = {
1163                 .omap4 = {
1164                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1165                         .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
1166                         .modulemode   = MODULEMODE_SWCTRL,
1167                 },
1168         },
1169         .dev_attr       = &i2c_dev_attr,
1170 };
1172 /* i2c3 */
1173 static struct omap_hwmod_irq_info dra7xx_i2c3_irqs[] = {
1174         { .irq = 61 + DRA7XX_IRQ_GIC_START },
1175         { .irq = -1 }
1176 };
1178 static struct omap_hwmod_dma_info dra7xx_i2c3_sdma_reqs[] = {
1179         { .name = "25", .dma_req = 24 + DRA7XX_DMA_REQ_START },
1180         { .name = "26", .dma_req = 25 + DRA7XX_DMA_REQ_START },
1181         { .dma_req = -1 }
1182 };
1184 static struct omap_hwmod dra7xx_i2c3_hwmod = {
1185         .name           = "i2c3",
1186         .class          = &dra7xx_i2c_hwmod_class,
1187         .clkdm_name     = "l4per_clkdm",
1188         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1189         .mpu_irqs       = dra7xx_i2c3_irqs,
1190         .sdma_reqs      = dra7xx_i2c3_sdma_reqs,
1191         .main_clk       = "func_96m_fclk",
1192         .prcm = {
1193                 .omap4 = {
1194                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1195                         .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
1196                         .modulemode   = MODULEMODE_SWCTRL,
1197                 },
1198         },
1199         .dev_attr       = &i2c_dev_attr,
1200 };
1202 /* i2c4 */
1203 static struct omap_hwmod_irq_info dra7xx_i2c4_irqs[] = {
1204         { .irq = 62 + DRA7XX_IRQ_GIC_START },
1205         { .irq = -1 }
1206 };
1208 static struct omap_hwmod_dma_info dra7xx_i2c4_sdma_reqs[] = {
1209         { .name = "124", .dma_req = 123 + DRA7XX_DMA_REQ_START },
1210         { .name = "125", .dma_req = 124 + DRA7XX_DMA_REQ_START },
1211         { .dma_req = -1 }
1212 };
1214 static struct omap_hwmod dra7xx_i2c4_hwmod = {
1215         .name           = "i2c4",
1216         .class          = &dra7xx_i2c_hwmod_class,
1217         .clkdm_name     = "l4per_clkdm",
1218         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1219         .mpu_irqs       = dra7xx_i2c4_irqs,
1220         .sdma_reqs      = dra7xx_i2c4_sdma_reqs,
1221         .main_clk       = "func_96m_fclk",
1222         .prcm = {
1223                 .omap4 = {
1224                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1225                         .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
1226                         .modulemode   = MODULEMODE_SWCTRL,
1227                 },
1228         },
1229         .dev_attr       = &i2c_dev_attr,
1230 };
1232 /* i2c5 */
1233 static struct omap_hwmod_irq_info dra7xx_i2c5_irqs[] = {
1234         { .irq = 60 + DRA7XX_IRQ_GIC_START },
1235         { .irq = -1 }
1236 };
1238 static struct omap_hwmod dra7xx_i2c5_hwmod = {
1239         .name           = "i2c5",
1240         .class          = &dra7xx_i2c_hwmod_class,
1241         .clkdm_name     = "ipu_clkdm",
1242         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1243         .mpu_irqs       = dra7xx_i2c5_irqs,
1244         .main_clk       = "func_96m_fclk",
1245         .prcm = {
1246                 .omap4 = {
1247                         .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
1248                         .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
1249                         .modulemode   = MODULEMODE_SWCTRL,
1250                 },
1251         },
1252         .dev_attr       = &i2c_dev_attr,
1253 };
1255 /*
1256  * 'mailbox' class
1257  *
1258  */
1260 static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
1261         .rev_offs       = 0x0000,
1262         .sysc_offs      = 0x0010,
1263         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1264                            SYSC_HAS_SOFTRESET),
1265         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1266                            SIDLE_SMART_WKUP),
1267         .sysc_fields    = &omap_hwmod_sysc_type2,
1268 };
1270 static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
1271         .name   = "mailbox",
1272         .sysc   = &dra7xx_mailbox_sysc,
1273 };
1275 /* mailbox1 */
1276 static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1277         .name           = "mailbox1",
1278         .class          = &dra7xx_mailbox_hwmod_class,
1279         .clkdm_name     = "l4cfg_clkdm",
1280         .main_clk       = "l3_iclk_div",
1281         .prcm = {
1282                 .omap4 = {
1283                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1284                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1285                 },
1286         },
1287 };
1289 /* mailbox2 */
1290 static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1291         .name           = "mailbox2",
1292         .class          = &dra7xx_mailbox_hwmod_class,
1293         .clkdm_name     = "l4cfg_clkdm",
1294         .main_clk       = "l3_iclk_div",
1295         .prcm = {
1296                 .omap4 = {
1297                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1298                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1299                 },
1300         },
1301 };
1303 /* mailbox3 */
1304 static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1305         .name           = "mailbox3",
1306         .class          = &dra7xx_mailbox_hwmod_class,
1307         .clkdm_name     = "l4cfg_clkdm",
1308         .main_clk       = "l3_iclk_div",
1309         .prcm = {
1310                 .omap4 = {
1311                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1312                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1313                 },
1314         },
1315 };
1317 /* mailbox4 */
1318 static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1319         .name           = "mailbox4",
1320         .class          = &dra7xx_mailbox_hwmod_class,
1321         .clkdm_name     = "l4cfg_clkdm",
1322         .main_clk       = "l3_iclk_div",
1323         .prcm = {
1324                 .omap4 = {
1325                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1326                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1327                 },
1328         },
1329 };
1331 /* mailbox5 */
1332 static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1333         .name           = "mailbox5",
1334         .class          = &dra7xx_mailbox_hwmod_class,
1335         .clkdm_name     = "l4cfg_clkdm",
1336         .main_clk       = "l3_iclk_div",
1337         .prcm = {
1338                 .omap4 = {
1339                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1340                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1341                 },
1342         },
1343 };
1345 /* mailbox6 */
1346 static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1347         .name           = "mailbox6",
1348         .class          = &dra7xx_mailbox_hwmod_class,
1349         .clkdm_name     = "l4cfg_clkdm",
1350         .main_clk       = "l3_iclk_div",
1351         .prcm = {
1352                 .omap4 = {
1353                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1354                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1355                 },
1356         },
1357 };
1359 /* mailbox7 */
1360 static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1361         .name           = "mailbox7",
1362         .class          = &dra7xx_mailbox_hwmod_class,
1363         .clkdm_name     = "l4cfg_clkdm",
1364         .main_clk       = "l3_iclk_div",
1365         .prcm = {
1366                 .omap4 = {
1367                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1368                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1369                 },
1370         },
1371 };
1373 /* mailbox8 */
1374 static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1375         .name           = "mailbox8",
1376         .class          = &dra7xx_mailbox_hwmod_class,
1377         .clkdm_name     = "l4cfg_clkdm",
1378         .main_clk       = "l3_iclk_div",
1379         .prcm = {
1380                 .omap4 = {
1381                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1382                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1383                 },
1384         },
1385 };
1387 /* mailbox9 */
1388 static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1389         .name           = "mailbox9",
1390         .class          = &dra7xx_mailbox_hwmod_class,
1391         .clkdm_name     = "l4cfg_clkdm",
1392         .main_clk       = "l3_iclk_div",
1393         .prcm = {
1394                 .omap4 = {
1395                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1396                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1397                 },
1398         },
1399 };
1401 /* mailbox10 */
1402 static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1403         .name           = "mailbox10",
1404         .class          = &dra7xx_mailbox_hwmod_class,
1405         .clkdm_name     = "l4cfg_clkdm",
1406         .main_clk       = "l3_iclk_div",
1407         .prcm = {
1408                 .omap4 = {
1409                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1410                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1411                 },
1412         },
1413 };
1415 /* mailbox11 */
1416 static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1417         .name           = "mailbox11",
1418         .class          = &dra7xx_mailbox_hwmod_class,
1419         .clkdm_name     = "l4cfg_clkdm",
1420         .main_clk       = "l3_iclk_div",
1421         .prcm = {
1422                 .omap4 = {
1423                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1424                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1425                 },
1426         },
1427 };
1429 /* mailbox12 */
1430 static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1431         .name           = "mailbox12",
1432         .class          = &dra7xx_mailbox_hwmod_class,
1433         .clkdm_name     = "l4cfg_clkdm",
1434         .main_clk       = "l3_iclk_div",
1435         .prcm = {
1436                 .omap4 = {
1437                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1438                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1439                 },
1440         },
1441 };
1443 /* mailbox13 */
1444 static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1445         .name           = "mailbox13",
1446         .class          = &dra7xx_mailbox_hwmod_class,
1447         .clkdm_name     = "l4cfg_clkdm",
1448         .main_clk       = "l3_iclk_div",
1449         .prcm = {
1450                 .omap4 = {
1451                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1452                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1453                 },
1454         },
1455 };
1457 /*
1458  * 'mcasp' class
1459  *
1460  */
1462 static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc = {
1463         .sysc_offs      = 0x0004,
1464         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1465         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1466         .sysc_fields    = &omap_hwmod_sysc_type3,
1467 };
1469 static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
1470         .name   = "mcasp",
1471         .sysc   = &dra7xx_mcasp_sysc,
1472 };
1474 /* mcasp1 */
1475 static struct omap_hwmod dra7xx_mcasp1_hwmod = {
1476         .name           = "mcasp1",
1477         .class          = &dra7xx_mcasp_hwmod_class,
1478         .clkdm_name     = "ipu_clkdm",
1479         .main_clk       = "mcasp1_ahclkx_mux",
1480         .prcm = {
1481                 .omap4 = {
1482                         .clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET,
1483                         .context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET,
1484                         .modulemode   = MODULEMODE_SWCTRL,
1485                 },
1486         },
1487 };
1489 /* mcasp2 */
1490 static struct omap_hwmod dra7xx_mcasp2_hwmod = {
1491         .name           = "mcasp2",
1492         .class          = &dra7xx_mcasp_hwmod_class,
1493         .clkdm_name     = "l4per2_clkdm",
1494         .main_clk       = "mcasp2_ahclkr_mux",
1495         .prcm = {
1496                 .omap4 = {
1497                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,
1498                         .context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
1499                         .modulemode   = MODULEMODE_SWCTRL,
1500                 },
1501         },
1502 };
1504 /* mcasp3 */
1505 static struct omap_hwmod dra7xx_mcasp3_hwmod = {
1506         .name           = "mcasp3",
1507         .class          = &dra7xx_mcasp_hwmod_class,
1508         .clkdm_name     = "l4per2_clkdm",
1509         .main_clk       = "mcasp3_ahclkx_mux",
1510         .prcm = {
1511                 .omap4 = {
1512                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET,
1513                         .context_offs = DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET,
1514                         .modulemode   = MODULEMODE_SWCTRL,
1515                 },
1516         },
1517 };
1519 /* mcasp4 */
1520 static struct omap_hwmod dra7xx_mcasp4_hwmod = {
1521         .name           = "mcasp4",
1522         .class          = &dra7xx_mcasp_hwmod_class,
1523         .clkdm_name     = "l4per2_clkdm",
1524         .main_clk       = "mcasp4_ahclkx_mux",
1525         .prcm = {
1526                 .omap4 = {
1527                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET,
1528                         .context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET,
1529                         .modulemode   = MODULEMODE_SWCTRL,
1530                 },
1531         },
1532 };
1534 /* mcasp5 */
1535 static struct omap_hwmod dra7xx_mcasp5_hwmod = {
1536         .name           = "mcasp5",
1537         .class          = &dra7xx_mcasp_hwmod_class,
1538         .clkdm_name     = "l4per2_clkdm",
1539         .main_clk       = "mcasp5_ahclkx_mux",
1540         .prcm = {
1541                 .omap4 = {
1542                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET,
1543                         .context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET,
1544                         .modulemode   = MODULEMODE_SWCTRL,
1545                 },
1546         },
1547 };
1549 /* mcasp6 */
1550 static struct omap_hwmod dra7xx_mcasp6_hwmod = {
1551         .name           = "mcasp6",
1552         .class          = &dra7xx_mcasp_hwmod_class,
1553         .clkdm_name     = "l4per2_clkdm",
1554         .main_clk       = "mcasp6_ahclkx_mux",
1555         .prcm = {
1556                 .omap4 = {
1557                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,
1558                         .context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
1559                         .modulemode   = MODULEMODE_SWCTRL,
1560                 },
1561         },
1562 };
1564 /* mcasp7 */
1565 static struct omap_hwmod dra7xx_mcasp7_hwmod = {
1566         .name           = "mcasp7",
1567         .class          = &dra7xx_mcasp_hwmod_class,
1568         .clkdm_name     = "l4per2_clkdm",
1569         .main_clk       = "mcasp7_ahclkx_mux",
1570         .prcm = {
1571                 .omap4 = {
1572                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET,
1573                         .context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,
1574                         .modulemode   = MODULEMODE_SWCTRL,
1575                 },
1576         },
1577 };
1579 /* mcasp8 */
1580 static struct omap_hwmod dra7xx_mcasp8_hwmod = {
1581         .name           = "mcasp8",
1582         .class          = &dra7xx_mcasp_hwmod_class,
1583         .clkdm_name     = "l4per2_clkdm",
1584         .main_clk       = "mcasp8_ahclk_mux",
1585         .prcm = {
1586                 .omap4 = {
1587                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,
1588                         .context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
1589                         .modulemode   = MODULEMODE_SWCTRL,
1590                 },
1591         },
1592 };
1594 /*
1595  * 'mcspi' class
1596  *
1597  */
1599 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1600         .rev_offs       = 0x0000,
1601         .sysc_offs      = 0x0010,
1602         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1603                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1604         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1605                            SIDLE_SMART_WKUP),
1606         .sysc_fields    = &omap_hwmod_sysc_type2,
1607 };
1609 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1610         .name   = "mcspi",
1611         .sysc   = &dra7xx_mcspi_sysc,
1612         .rev    = OMAP4_MCSPI_REV,
1613 };
1615 /* mcspi1 */
1616 static struct omap_hwmod_irq_info dra7xx_mcspi1_irqs[] = {
1617         { .irq = 65 + DRA7XX_IRQ_GIC_START },
1618         { .irq = -1 }
1619 };
1621 static struct omap_hwmod_dma_info dra7xx_mcspi1_sdma_reqs[] = {
1622         { .name = "35", .dma_req = 34 + DRA7XX_DMA_REQ_START },
1623         { .name = "36", .dma_req = 35 + DRA7XX_DMA_REQ_START },
1624         { .name = "37", .dma_req = 36 + DRA7XX_DMA_REQ_START },
1625         { .name = "38", .dma_req = 37 + DRA7XX_DMA_REQ_START },
1626         { .name = "39", .dma_req = 38 + DRA7XX_DMA_REQ_START },
1627         { .name = "40", .dma_req = 39 + DRA7XX_DMA_REQ_START },
1628         { .name = "41", .dma_req = 40 + DRA7XX_DMA_REQ_START },
1629         { .name = "42", .dma_req = 41 + DRA7XX_DMA_REQ_START },
1630         { .dma_req = -1 }
1631 };
1633 /* mcspi1 dev_attr */
1634 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1635         .num_chipselect = 4,
1636 };
1638 static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1639         .name           = "mcspi1",
1640         .class          = &dra7xx_mcspi_hwmod_class,
1641         .clkdm_name     = "l4per_clkdm",
1642         .mpu_irqs       = dra7xx_mcspi1_irqs,
1643         .sdma_reqs      = dra7xx_mcspi1_sdma_reqs,
1644         .main_clk       = "func_48m_fclk",
1645         .prcm = {
1646                 .omap4 = {
1647                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1648                         .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1649                         .modulemode   = MODULEMODE_SWCTRL,
1650                 },
1651         },
1652         .dev_attr       = &mcspi1_dev_attr,
1653 };
1655 /* mcspi2 */
1656 static struct omap_hwmod_irq_info dra7xx_mcspi2_irqs[] = {
1657         { .irq = 66 + DRA7XX_IRQ_GIC_START },
1658         { .irq = -1 }
1659 };
1661 static struct omap_hwmod_dma_info dra7xx_mcspi2_sdma_reqs[] = {
1662         { .name = "43", .dma_req = 42 + DRA7XX_DMA_REQ_START },
1663         { .name = "44", .dma_req = 43 + DRA7XX_DMA_REQ_START },
1664         { .name = "45", .dma_req = 44 + DRA7XX_DMA_REQ_START },
1665         { .name = "46", .dma_req = 45 + DRA7XX_DMA_REQ_START },
1666         { .dma_req = -1 }
1667 };
1669 /* mcspi2 dev_attr */
1670 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1671         .num_chipselect = 2,
1672 };
1674 static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1675         .name           = "mcspi2",
1676         .class          = &dra7xx_mcspi_hwmod_class,
1677         .clkdm_name     = "l4per_clkdm",
1678         .mpu_irqs       = dra7xx_mcspi2_irqs,
1679         .sdma_reqs      = dra7xx_mcspi2_sdma_reqs,
1680         .main_clk       = "func_48m_fclk",
1681         .prcm = {
1682                 .omap4 = {
1683                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1684                         .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1685                         .modulemode   = MODULEMODE_SWCTRL,
1686                 },
1687         },
1688         .dev_attr       = &mcspi2_dev_attr,
1689 };
1691 /* mcspi3 */
1692 static struct omap_hwmod_irq_info dra7xx_mcspi3_irqs[] = {
1693         { .irq = 91 + DRA7XX_IRQ_GIC_START },
1694         { .irq = -1 }
1695 };
1697 static struct omap_hwmod_dma_info dra7xx_mcspi3_sdma_reqs[] = {
1698         { .name = "15", .dma_req = 14 + DRA7XX_DMA_REQ_START },
1699         { .name = "16", .dma_req = 15 + DRA7XX_DMA_REQ_START },
1700         { .name = "23", .dma_req = 22 + DRA7XX_DMA_REQ_START },
1701         { .name = "24", .dma_req = 23 + DRA7XX_DMA_REQ_START },
1702         { .dma_req = -1 }
1703 };
1705 /* mcspi3 dev_attr */
1706 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1707         .num_chipselect = 2,
1708 };
1710 static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1711         .name           = "mcspi3",
1712         .class          = &dra7xx_mcspi_hwmod_class,
1713         .clkdm_name     = "l4per_clkdm",
1714         .mpu_irqs       = dra7xx_mcspi3_irqs,
1715         .sdma_reqs      = dra7xx_mcspi3_sdma_reqs,
1716         .main_clk       = "func_48m_fclk",
1717         .prcm = {
1718                 .omap4 = {
1719                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1720                         .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1721                         .modulemode   = MODULEMODE_SWCTRL,
1722                 },
1723         },
1724         .dev_attr       = &mcspi3_dev_attr,
1725 };
1727 /* mcspi4 */
1728 static struct omap_hwmod_irq_info dra7xx_mcspi4_irqs[] = {
1729         { .irq = 48 + DRA7XX_IRQ_GIC_START },
1730         { .irq = -1 }
1731 };
1733 static struct omap_hwmod_dma_info dra7xx_mcspi4_sdma_reqs[] = {
1734         { .name = "70", .dma_req = 69 + DRA7XX_DMA_REQ_START },
1735         { .name = "71", .dma_req = 70 + DRA7XX_DMA_REQ_START },
1736         { .dma_req = -1 }
1737 };
1739 /* mcspi4 dev_attr */
1740 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1741         .num_chipselect = 1,
1742 };
1744 static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1745         .name           = "mcspi4",
1746         .class          = &dra7xx_mcspi_hwmod_class,
1747         .clkdm_name     = "l4per_clkdm",
1748         .mpu_irqs       = dra7xx_mcspi4_irqs,
1749         .sdma_reqs      = dra7xx_mcspi4_sdma_reqs,
1750         .main_clk       = "func_48m_fclk",
1751         .prcm = {
1752                 .omap4 = {
1753                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1754                         .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1755                         .modulemode   = MODULEMODE_SWCTRL,
1756                 },
1757         },
1758         .dev_attr       = &mcspi4_dev_attr,
1759 };
1761 /*
1762  * 'mmc' class
1763  *
1764  */
1766 static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1767         .rev_offs       = 0x0000,
1768         .sysc_offs      = 0x0010,
1769         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1770                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1771                            SYSC_HAS_SOFTRESET),
1772         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1773                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1774                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1775         .sysc_fields    = &omap_hwmod_sysc_type2,
1776 };
1778 static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1779         .name   = "mmc",
1780         .sysc   = &dra7xx_mmc_sysc,
1781 };
1783 /* mmc1 */
1784 static struct omap_hwmod_irq_info dra7xx_mmc1_irqs[] = {
1785         { .irq = 83 + DRA7XX_IRQ_GIC_START },
1786         { .irq = -1 }
1787 };
1789 static struct omap_hwmod_dma_info dra7xx_mmc1_sdma_reqs[] = {
1790         { .name = "tx", .dma_req = 60 + DRA7XX_DMA_REQ_START },
1791         { .name = "rx", .dma_req = 61 + DRA7XX_DMA_REQ_START },
1792         { .dma_req = -1 }
1793 };
1795 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1796         { .role = "clk32k", .clk = "mmc1_clk32k" },
1797 };
1799 /* mmc1 dev_attr */
1800 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1801         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1802 };
1804 static struct omap_hwmod dra7xx_mmc1_hwmod = {
1805         .name           = "mmc1",
1806         .class          = &dra7xx_mmc_hwmod_class,
1807         .clkdm_name     = "l3init_clkdm",
1808         .mpu_irqs       = dra7xx_mmc1_irqs,
1809         .sdma_reqs      = dra7xx_mmc1_sdma_reqs,
1810         .main_clk       = "mmc1_fclk_div",
1811         .prcm = {
1812                 .omap4 = {
1813                         .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1814                         .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1815                         .modulemode   = MODULEMODE_SWCTRL,
1816                 },
1817         },
1818         .opt_clks       = mmc1_opt_clks,
1819         .opt_clks_cnt   = ARRAY_SIZE(mmc1_opt_clks),
1820         .dev_attr       = &mmc1_dev_attr,
1821 };
1823 /* mmc2 */
1824 static struct omap_hwmod_irq_info dra7xx_mmc2_irqs[] = {
1825         { .irq = 86 + DRA7XX_IRQ_GIC_START },
1826         { .irq = -1 }
1827 };
1829 static struct omap_hwmod_dma_info dra7xx_mmc2_sdma_reqs[] = {
1830         { .name = "tx", .dma_req = 46 + DRA7XX_DMA_REQ_START },
1831         { .name = "rx", .dma_req = 47 + DRA7XX_DMA_REQ_START },
1832         { .dma_req = -1 }
1833 };
1835 static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1836         { .role = "clk32k", .clk = "mmc2_clk32k" },
1837 };
1839 static struct omap_hwmod dra7xx_mmc2_hwmod = {
1840         .name           = "mmc2",
1841         .class          = &dra7xx_mmc_hwmod_class,
1842         .clkdm_name     = "l3init_clkdm",
1843         .mpu_irqs       = dra7xx_mmc2_irqs,
1844         .sdma_reqs      = dra7xx_mmc2_sdma_reqs,
1845         .main_clk       = "mmc2_fclk_div",
1846         .prcm = {
1847                 .omap4 = {
1848                         .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1849                         .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1850                         .modulemode   = MODULEMODE_SWCTRL,
1851                 },
1852         },
1853         .opt_clks       = mmc2_opt_clks,
1854         .opt_clks_cnt   = ARRAY_SIZE(mmc2_opt_clks),
1855 };
1857 /* mmc3 */
1858 static struct omap_hwmod_irq_info dra7xx_mmc3_irqs[] = {
1859         { .irq = 94 + DRA7XX_IRQ_GIC_START },
1860         { .irq = -1 }
1861 };
1863 static struct omap_hwmod_dma_info dra7xx_mmc3_sdma_reqs[] = {
1864         { .name = "77", .dma_req = 76 + DRA7XX_DMA_REQ_START },
1865         { .name = "78", .dma_req = 77 + DRA7XX_DMA_REQ_START },
1866         { .dma_req = -1 }
1867 };
1869 static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1870         { .role = "clk32k", .clk = "mmc3_clk32k" },
1871 };
1873 static struct omap_hwmod dra7xx_mmc3_hwmod = {
1874         .name           = "mmc3",
1875         .class          = &dra7xx_mmc_hwmod_class,
1876         .clkdm_name     = "l4per_clkdm",
1877         .mpu_irqs       = dra7xx_mmc3_irqs,
1878         .sdma_reqs      = dra7xx_mmc3_sdma_reqs,
1879         .main_clk       = "mmc3_gfclk_div",
1880         .prcm = {
1881                 .omap4 = {
1882                         .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1883                         .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1884                         .modulemode   = MODULEMODE_SWCTRL,
1885                 },
1886         },
1887         .opt_clks       = mmc3_opt_clks,
1888         .opt_clks_cnt   = ARRAY_SIZE(mmc3_opt_clks),
1889 };
1891 /* mmc4 */
1892 static struct omap_hwmod_irq_info dra7xx_mmc4_irqs[] = {
1893         { .irq = 96 + DRA7XX_IRQ_GIC_START },
1894         { .irq = -1 }
1895 };
1897 static struct omap_hwmod_dma_info dra7xx_mmc4_sdma_reqs[] = {
1898         { .name = "57", .dma_req = 56 + DRA7XX_DMA_REQ_START },
1899         { .name = "58", .dma_req = 57 + DRA7XX_DMA_REQ_START },
1900         { .dma_req = -1 }
1901 };
1903 static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1904         { .role = "clk32k", .clk = "mmc4_clk32k" },
1905 };
1907 static struct omap_hwmod dra7xx_mmc4_hwmod = {
1908         .name           = "mmc4",
1909         .class          = &dra7xx_mmc_hwmod_class,
1910         .clkdm_name     = "l4per_clkdm",
1911         .mpu_irqs       = dra7xx_mmc4_irqs,
1912         .sdma_reqs      = dra7xx_mmc4_sdma_reqs,
1913         .main_clk       = "mmc4_gfclk_div",
1914         .prcm = {
1915                 .omap4 = {
1916                         .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1917                         .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1918                         .modulemode   = MODULEMODE_SWCTRL,
1919                 },
1920         },
1921         .opt_clks       = mmc4_opt_clks,
1922         .opt_clks_cnt   = ARRAY_SIZE(mmc4_opt_clks),
1923 };
1925 /*
1926  * 'mpu' class
1927  *
1928  */
1930 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1931         .name   = "mpu",
1932 };
1934 /* mpu */
1935 static struct omap_hwmod_irq_info dra7xx_mpu_irqs[] = {
1936         { .irq = 132 + DRA7XX_IRQ_GIC_START },
1937         { .irq = -1 }
1938 };
1940 static struct omap_hwmod dra7xx_mpu_hwmod = {
1941         .name           = "mpu",
1942         .class          = &dra7xx_mpu_hwmod_class,
1943         .clkdm_name     = "mpu_clkdm",
1944         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1945         .mpu_irqs       = dra7xx_mpu_irqs,
1946         .main_clk       = "dpll_mpu_m2_ck",
1947         .prcm = {
1948                 .omap4 = {
1949                         .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1950                         .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1951                 },
1952         },
1953 };
1955 /*
1956  * 'ocmc_ram' class
1957  *
1958  */
1960 static struct omap_hwmod_class dra7xx_ocmc_ram_hwmod_class = {
1961         .name   = "ocmc_ram",
1962 };
1964 /* ocmc_ram1 */
1965 static struct omap_hwmod dra7xx_ocmc_ram1_hwmod = {
1966         .name           = "ocmc_ram1",
1967         .class          = &dra7xx_ocmc_ram_hwmod_class,
1968         .clkdm_name     = "l3main1_clkdm",
1969         .main_clk       = "l3_iclk_div",
1970         .prcm = {
1971                 .omap4 = {
1972                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL_OFFSET,
1973                         .context_offs = DRA7XX_RM_L3MAIN1_OCMC_RAM1_CONTEXT_OFFSET,
1974                 },
1975         },
1976 };
1978 /* ocmc_ram2 */
1979 static struct omap_hwmod dra7xx_ocmc_ram2_hwmod = {
1980         .name           = "ocmc_ram2",
1981         .class          = &dra7xx_ocmc_ram_hwmod_class,
1982         .clkdm_name     = "l3main1_clkdm",
1983         .main_clk       = "l3_iclk_div",
1984         .prcm = {
1985                 .omap4 = {
1986                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL_OFFSET,
1987                         .context_offs = DRA7XX_RM_L3MAIN1_OCMC_RAM2_CONTEXT_OFFSET,
1988                 },
1989         },
1990 };
1992 /* ocmc_ram3 */
1993 static struct omap_hwmod dra7xx_ocmc_ram3_hwmod = {
1994         .name           = "ocmc_ram3",
1995         .class          = &dra7xx_ocmc_ram_hwmod_class,
1996         .clkdm_name     = "l3main1_clkdm",
1997         .main_clk       = "l3_iclk_div",
1998         .prcm = {
1999                 .omap4 = {
2000                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL_OFFSET,
2001                         .context_offs = DRA7XX_RM_L3MAIN1_OCMC_RAM3_CONTEXT_OFFSET,
2002                 },
2003         },
2004 };
2006 /*
2007  * 'ocmc_rom' class
2008  *
2009  */
2011 static struct omap_hwmod_class dra7xx_ocmc_rom_hwmod_class = {
2012         .name   = "ocmc_rom",
2013 };
2015 /* ocmc_rom */
2016 static struct omap_hwmod dra7xx_ocmc_rom_hwmod = {
2017         .name           = "ocmc_rom",
2018         .class          = &dra7xx_ocmc_rom_hwmod_class,
2019         .clkdm_name     = "l3main1_clkdm",
2020         .main_clk       = "l3_iclk_div",
2021         .prcm = {
2022                 .omap4 = {
2023                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL_OFFSET,
2024                         .context_offs = DRA7XX_RM_L3MAIN1_OCMC_ROM_CONTEXT_OFFSET,
2025                 },
2026         },
2027 };
2029 /*
2030  * 'ocp2scp' class
2031  *
2032  */
2034 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
2035         .rev_offs       = 0x0000,
2036         .sysc_offs      = 0x0010,
2037         .syss_offs      = 0x0014,
2038         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2039                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2040         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2041                            SIDLE_SMART_WKUP),
2042         .sysc_fields    = &omap_hwmod_sysc_type1,
2043 };
2045 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
2046         .name   = "ocp2scp",
2047         .sysc   = &dra7xx_ocp2scp_sysc,
2048 };
2050 /* ocp2scp1 */
2051 static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
2052         .name           = "ocp2scp1",
2053         .class          = &dra7xx_ocp2scp_hwmod_class,
2054         .clkdm_name     = "l3init_clkdm",
2055         .main_clk       = "l4_root_clk_div",
2056         .prcm = {
2057                 .omap4 = {
2058                         .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
2059                         .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
2060                         .modulemode   = MODULEMODE_HWCTRL,
2061                 },
2062         },
2063 };
2065 /*
2066  * 'pruss' class
2067  *
2068  */
2070 static struct omap_hwmod_class dra7xx_pruss_hwmod_class = {
2071         .name   = "pruss",
2072 };
2074 /* pruss1 */
2075 static struct omap_hwmod dra7xx_pruss1_hwmod = {
2076         .name           = "pruss1",
2077         .class          = &dra7xx_pruss_hwmod_class,
2078         .clkdm_name     = "l4per2_clkdm",
2079         .main_clk       = "dpll_per_m2x2_ck",
2080         .prcm = {
2081                 .omap4 = {
2082                         .clkctrl_offs = DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL_OFFSET,
2083                         .context_offs = DRA7XX_RM_L4PER2_PRUSS1_CONTEXT_OFFSET,
2084                         .modulemode   = MODULEMODE_SWCTRL,
2085                 },
2086         },
2087 };
2089 /* pruss2 */
2090 static struct omap_hwmod dra7xx_pruss2_hwmod = {
2091         .name           = "pruss2",
2092         .class          = &dra7xx_pruss_hwmod_class,
2093         .clkdm_name     = "l4per2_clkdm",
2094         .main_clk       = "dpll_per_m2x2_ck",
2095         .prcm = {
2096                 .omap4 = {
2097                         .clkctrl_offs = DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL_OFFSET,
2098                         .context_offs = DRA7XX_RM_L4PER2_PRUSS2_CONTEXT_OFFSET,
2099                         .modulemode   = MODULEMODE_SWCTRL,
2100                 },
2101         },
2102 };
2104 /*
2105  * 'pwmss' class
2106  *
2107  */
2109 static struct omap_hwmod_class dra7xx_pwmss_hwmod_class = {
2110         .name   = "pwmss",
2111 };
2113 /* pwmss1 */
2114 static struct omap_hwmod dra7xx_pwmss1_hwmod = {
2115         .name           = "pwmss1",
2116         .class          = &dra7xx_pwmss_hwmod_class,
2117         .clkdm_name     = "l4per2_clkdm",
2118         .main_clk       = "l3_iclk_div",
2119         .prcm = {
2120                 .omap4 = {
2121                         .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET,
2122                         .context_offs = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET,
2123                         .modulemode   = MODULEMODE_SWCTRL,
2124                 },
2125         },
2126 };
2128 /* pwmss2 */
2129 static struct omap_hwmod dra7xx_pwmss2_hwmod = {
2130         .name           = "pwmss2",
2131         .class          = &dra7xx_pwmss_hwmod_class,
2132         .clkdm_name     = "l4per2_clkdm",
2133         .main_clk       = "l3_iclk_div",
2134         .prcm = {
2135                 .omap4 = {
2136                         .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET,
2137                         .context_offs = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET,
2138                         .modulemode   = MODULEMODE_SWCTRL,
2139                 },
2140         },
2141 };
2143 /* pwmss3 */
2144 static struct omap_hwmod dra7xx_pwmss3_hwmod = {
2145         .name           = "pwmss3",
2146         .class          = &dra7xx_pwmss_hwmod_class,
2147         .clkdm_name     = "l4per2_clkdm",
2148         .main_clk       = "l3_iclk_div",
2149         .prcm = {
2150                 .omap4 = {
2151                         .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET,
2152                         .context_offs = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET,
2153                         .modulemode   = MODULEMODE_SWCTRL,
2154                 },
2155         },
2156 };
2158 /*
2159  * 'qspi' class
2160  *
2161  */
2163 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
2164         .sysc_offs      = 0x0010,
2165         .sysc_flags     = SYSC_HAS_SIDLEMODE,
2166         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2167                            SIDLE_SMART_WKUP),
2168         .sysc_fields    = &omap_hwmod_sysc_type2,
2169 };
2171 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
2172         .name   = "qspi",
2173         .sysc   = &dra7xx_qspi_sysc,
2174 };
2176 /* qspi */
2177 static struct omap_hwmod dra7xx_qspi_hwmod = {
2178         .name           = "qspi",
2179         .class          = &dra7xx_qspi_hwmod_class,
2180         .clkdm_name     = "l4per2_clkdm",
2181         .main_clk       = "qspi_gfclk_div",
2182         .prcm = {
2183                 .omap4 = {
2184                         .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
2185                         .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
2186                         .modulemode   = MODULEMODE_SWCTRL,
2187                 },
2188         },
2189 };
2191 /*
2192  * 'rtcss' class
2193  *
2194  */
2196 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
2197         .sysc_offs      = 0x0078,
2198         .sysc_flags     = SYSC_HAS_SIDLEMODE,
2199         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2200         .sysc_fields    = &omap_hwmod_sysc_type3,
2201 };
2203 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
2204         .name   = "rtcss",
2205         .sysc   = &dra7xx_rtcss_sysc,
2206 };
2208 /* rtcss */
2209 static struct omap_hwmod dra7xx_rtcss_hwmod = {
2210         .name           = "rtcss",
2211         .class          = &dra7xx_rtcss_hwmod_class,
2212         .clkdm_name     = "rtc_clkdm",
2213         .main_clk       = "sys_32k_ck",
2214         .prcm = {
2215                 .omap4 = {
2216                         .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
2217                         .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
2218                         .modulemode   = MODULEMODE_SWCTRL,
2219                 },
2220         },
2221 };
2223 /*
2224  * 'sata' class
2225  *
2226  */
2228 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
2229         .sysc_offs      = 0x0000,
2230         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
2231         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2232                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2233                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2234         .sysc_fields    = &omap_hwmod_sysc_type2,
2235 };
2237 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
2238         .name   = "sata",
2239         .sysc   = &dra7xx_sata_sysc,
2240 };
2242 /* sata */
2243 static struct omap_hwmod_irq_info dra7xx_sata_irqs[] = {
2244         { .irq = 54 + DRA7XX_IRQ_GIC_START },
2245         { .irq = -1 }
2246 };
2248 static struct omap_hwmod_opt_clk sata_opt_clks[] = {
2249         { .role = "ref_clk", .clk = "sata_ref_clk" },
2250 };
2252 static struct omap_hwmod dra7xx_sata_hwmod = {
2253         .name           = "sata",
2254         .class          = &dra7xx_sata_hwmod_class,
2255         .clkdm_name     = "l3init_clkdm",
2256         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2257         .mpu_irqs       = dra7xx_sata_irqs,
2258         .main_clk       = "func_48m_fclk",
2259         .prcm = {
2260                 .omap4 = {
2261                         .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
2262                         .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
2263                         .modulemode   = MODULEMODE_SWCTRL,
2264                 },
2265         },
2266         .opt_clks       = sata_opt_clks,
2267         .opt_clks_cnt   = ARRAY_SIZE(sata_opt_clks),
2268 };
2270 /*
2271  * 'smartreflex' class
2272  *
2273  */
2275 /* The IP is not compliant to type1 / type2 scheme */
2276 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2277         .sidle_shift    = 24,
2278         .enwkup_shift   = 26,
2279 };
2281 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
2282         .sysc_offs      = 0x0038,
2283         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2284         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2285                            SIDLE_SMART_WKUP),
2286         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2287 };
2289 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
2290         .name   = "smartreflex",
2291         .sysc   = &dra7xx_smartreflex_sysc,
2292         .rev    = 2,
2293 };
2295 /* smartreflex_core */
2296 static struct omap_hwmod_irq_info dra7xx_smartreflex_core_irqs[] = {
2297         { .irq = 19 + DRA7XX_IRQ_GIC_START },
2298         { .irq = -1 }
2299 };
2301 /* smartreflex_core dev_attr */
2302 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2303         .sensor_voltdm_name     = "core",
2304 };
2306 static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
2307         .name           = "smartreflex_core",
2308         .class          = &dra7xx_smartreflex_hwmod_class,
2309         .clkdm_name     = "coreaon_clkdm",
2310         .mpu_irqs       = dra7xx_smartreflex_core_irqs,
2311         .main_clk       = "wkupaon_iclk_mux",
2312         .prcm = {
2313                 .omap4 = {
2314                         .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
2315                         .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
2316                         .modulemode   = MODULEMODE_SWCTRL,
2317                 },
2318         },
2319         .dev_attr       = &smartreflex_core_dev_attr,
2320 };
2322 /* smartreflex_dspeve */
2323 static struct omap_hwmod dra7xx_smartreflex_dspeve_hwmod = {
2324         .name           = "smartreflex_dspeve",
2325         .class          = &dra7xx_smartreflex_hwmod_class,
2326         .clkdm_name     = "coreaon_clkdm",
2327         .main_clk       = "wkupaon_iclk_mux",
2328         .prcm = {
2329                 .omap4 = {
2330                         .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL_OFFSET,
2331                         .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_DSPEVE_CONTEXT_OFFSET,
2332                         .modulemode   = MODULEMODE_SWCTRL,
2333                 },
2334         },
2335 };
2337 /* smartreflex_gpu */
2338 static struct omap_hwmod dra7xx_smartreflex_gpu_hwmod = {
2339         .name           = "smartreflex_gpu",
2340         .class          = &dra7xx_smartreflex_hwmod_class,
2341         .clkdm_name     = "coreaon_clkdm",
2342         .main_clk       = "wkupaon_iclk_mux",
2343         .prcm = {
2344                 .omap4 = {
2345                         .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL_OFFSET,
2346                         .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_GPU_CONTEXT_OFFSET,
2347                         .modulemode   = MODULEMODE_SWCTRL,
2348                 },
2349         },
2350 };
2352 /* smartreflex_mpu */
2353 static struct omap_hwmod_irq_info dra7xx_smartreflex_mpu_irqs[] = {
2354         { .irq = 18 + DRA7XX_IRQ_GIC_START },
2355         { .irq = -1 }
2356 };
2358 /* smartreflex_mpu dev_attr */
2359 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2360         .sensor_voltdm_name     = "mpu",
2361 };
2363 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
2364         .name           = "smartreflex_mpu",
2365         .class          = &dra7xx_smartreflex_hwmod_class,
2366         .clkdm_name     = "coreaon_clkdm",
2367         .mpu_irqs       = dra7xx_smartreflex_mpu_irqs,
2368         .main_clk       = "wkupaon_iclk_mux",
2369         .prcm = {
2370                 .omap4 = {
2371                         .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
2372                         .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
2373                         .modulemode   = MODULEMODE_SWCTRL,
2374                 },
2375         },
2376         .dev_attr       = &smartreflex_mpu_dev_attr,
2377 };
2379 /*
2380  * 'spare' class
2381  *
2382  */
2384 static struct omap_hwmod_class dra7xx_spare_hwmod_class = {
2385         .name   = "spare",
2386 };
2388 /* spare_cme */
2389 static struct omap_hwmod dra7xx_spare_cme_hwmod = {
2390         .name           = "spare_cme",
2391         .class          = &dra7xx_spare_hwmod_class,
2392         .clkdm_name     = "l3main1_clkdm",
2393         .main_clk       = "l4_root_clk_div",
2394         .prcm = {
2395                 .omap4 = {
2396                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL_OFFSET,
2397                         .context_offs = DRA7XX_RM_L3MAIN1_SPARE_CME_CONTEXT_OFFSET,
2398                 },
2399         },
2400 };
2402 /* spare_icm */
2403 static struct omap_hwmod dra7xx_spare_icm_hwmod = {
2404         .name           = "spare_icm",
2405         .class          = &dra7xx_spare_hwmod_class,
2406         .clkdm_name     = "l3main1_clkdm",
2407         .main_clk       = "l4_root_clk_div",
2408         .prcm = {
2409                 .omap4 = {
2410                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL_OFFSET,
2411                         .context_offs = DRA7XX_RM_L3MAIN1_SPARE_ICM_CONTEXT_OFFSET,
2412                 },
2413         },
2414 };
2416 /* spare_iva2 */
2417 static struct omap_hwmod dra7xx_spare_iva2_hwmod = {
2418         .name           = "spare_iva2",
2419         .class          = &dra7xx_spare_hwmod_class,
2420         .clkdm_name     = "l3main1_clkdm",
2421         .main_clk       = "l3_iclk_div",
2422         .prcm = {
2423                 .omap4 = {
2424                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL_OFFSET,
2425                         .context_offs = DRA7XX_RM_L3MAIN1_SPARE_IVA2_CONTEXT_OFFSET,
2426                 },
2427         },
2428 };
2430 /* spare_safety1 */
2431 static struct omap_hwmod dra7xx_spare_safety1_hwmod = {
2432         .name           = "spare_safety1",
2433         .class          = &dra7xx_spare_hwmod_class,
2434         .clkdm_name     = "wkupaon_clkdm",
2435         .main_clk       = "wkupaon_iclk_mux",
2436         .prcm = {
2437                 .omap4 = {
2438                         .clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL_OFFSET,
2439                         .context_offs = DRA7XX_RM_WKUPAON_SPARE_SAFETY1_CONTEXT_OFFSET,
2440                 },
2441         },
2442 };
2444 /* spare_safety2 */
2445 static struct omap_hwmod dra7xx_spare_safety2_hwmod = {
2446         .name           = "spare_safety2",
2447         .class          = &dra7xx_spare_hwmod_class,
2448         .clkdm_name     = "wkupaon_clkdm",
2449         .main_clk       = "wkupaon_iclk_mux",
2450         .prcm = {
2451                 .omap4 = {
2452                         .clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL_OFFSET,
2453                         .context_offs = DRA7XX_RM_WKUPAON_SPARE_SAFETY2_CONTEXT_OFFSET,
2454                 },
2455         },
2456 };
2458 /* spare_safety3 */
2459 static struct omap_hwmod dra7xx_spare_safety3_hwmod = {
2460         .name           = "spare_safety3",
2461         .class          = &dra7xx_spare_hwmod_class,
2462         .clkdm_name     = "wkupaon_clkdm",
2463         .main_clk       = "wkupaon_iclk_mux",
2464         .prcm = {
2465                 .omap4 = {
2466                         .clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL_OFFSET,
2467                         .context_offs = DRA7XX_RM_WKUPAON_SPARE_SAFETY3_CONTEXT_OFFSET,
2468                 },
2469         },
2470 };
2472 /* spare_safety4 */
2473 static struct omap_hwmod dra7xx_spare_safety4_hwmod = {
2474         .name           = "spare_safety4",
2475         .class          = &dra7xx_spare_hwmod_class,
2476         .clkdm_name     = "wkupaon_clkdm",
2477         .main_clk       = "wkupaon_iclk_mux",
2478         .prcm = {
2479                 .omap4 = {
2480                         .clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL_OFFSET,
2481                         .context_offs = DRA7XX_RM_WKUPAON_SPARE_SAFETY4_CONTEXT_OFFSET,
2482                 },
2483         },
2484 };
2486 /* spare_unknown2 */
2487 static struct omap_hwmod dra7xx_spare_unknown2_hwmod = {
2488         .name           = "spare_unknown2",
2489         .class          = &dra7xx_spare_hwmod_class,
2490         .clkdm_name     = "wkupaon_clkdm",
2491         .main_clk       = "wkupaon_iclk_mux",
2492         .prcm = {
2493                 .omap4 = {
2494                         .clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL_OFFSET,
2495                         .context_offs = DRA7XX_RM_WKUPAON_SPARE_UNKNOWN2_CONTEXT_OFFSET,
2496                 },
2497         },
2498 };
2500 /* spare_unknown3 */
2501 static struct omap_hwmod dra7xx_spare_unknown3_hwmod = {
2502         .name           = "spare_unknown3",
2503         .class          = &dra7xx_spare_hwmod_class,
2504         .clkdm_name     = "wkupaon_clkdm",
2505         .main_clk       = "wkupaon_iclk_mux",
2506         .prcm = {
2507                 .omap4 = {
2508                         .clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL_OFFSET,
2509                         .context_offs = DRA7XX_RM_WKUPAON_SPARE_UNKNOWN3_CONTEXT_OFFSET,
2510                 },
2511         },
2512 };
2514 /* spare_unknown4 */
2515 static struct omap_hwmod dra7xx_spare_unknown4_hwmod = {
2516         .name           = "spare_unknown4",
2517         .class          = &dra7xx_spare_hwmod_class,
2518         .clkdm_name     = "l3main1_clkdm",
2519         .main_clk       = "l4_root_clk_div",
2520         .prcm = {
2521                 .omap4 = {
2522                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL_OFFSET,
2523                         .context_offs = DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN4_CONTEXT_OFFSET,
2524                 },
2525         },
2526 };
2528 /* spare_unknown5 */
2529 static struct omap_hwmod dra7xx_spare_unknown5_hwmod = {
2530         .name           = "spare_unknown5",
2531         .class          = &dra7xx_spare_hwmod_class,
2532         .clkdm_name     = "l3main1_clkdm",
2533         .main_clk       = "l4_root_clk_div",
2534         .prcm = {
2535                 .omap4 = {
2536                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL_OFFSET,
2537                         .context_offs = DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN5_CONTEXT_OFFSET,
2538                 },
2539         },
2540 };
2542 /* spare_unknown6 */
2543 static struct omap_hwmod dra7xx_spare_unknown6_hwmod = {
2544         .name           = "spare_unknown6",
2545         .class          = &dra7xx_spare_hwmod_class,
2546         .clkdm_name     = "l3main1_clkdm",
2547         .main_clk       = "l4_root_clk_div",
2548         .prcm = {
2549                 .omap4 = {
2550                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL_OFFSET,
2551                         .context_offs = DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN6_CONTEXT_OFFSET,
2552                 },
2553         },
2554 };
2556 /* spare_videopll1 */
2557 static struct omap_hwmod dra7xx_spare_videopll1_hwmod = {
2558         .name           = "spare_videopll1",
2559         .class          = &dra7xx_spare_hwmod_class,
2560         .clkdm_name     = "l3main1_clkdm",
2561         .main_clk       = "l4_root_clk_div",
2562         .prcm = {
2563                 .omap4 = {
2564                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL_OFFSET,
2565                         .context_offs = DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL1_CONTEXT_OFFSET,
2566                 },
2567         },
2568 };
2570 /* spare_videopll2 */
2571 static struct omap_hwmod dra7xx_spare_videopll2_hwmod = {
2572         .name           = "spare_videopll2",
2573         .class          = &dra7xx_spare_hwmod_class,
2574         .clkdm_name     = "l3main1_clkdm",
2575         .main_clk       = "l4_root_clk_div",
2576         .prcm = {
2577                 .omap4 = {
2578                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL_OFFSET,
2579                         .context_offs = DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL2_CONTEXT_OFFSET,
2580                 },
2581         },
2582 };
2584 /* spare_videopll3 */
2585 static struct omap_hwmod dra7xx_spare_videopll3_hwmod = {
2586         .name           = "spare_videopll3",
2587         .class          = &dra7xx_spare_hwmod_class,
2588         .clkdm_name     = "l3main1_clkdm",
2589         .main_clk       = "l4_root_clk_div",
2590         .prcm = {
2591                 .omap4 = {
2592                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL_OFFSET,
2593                         .context_offs = DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL3_CONTEXT_OFFSET,
2594                 },
2595         },
2596 };
2598 /*
2599  * 'spare_sata2' class
2600  *
2601  */
2603 static struct omap_hwmod_class dra7xx_spare_sata2_hwmod_class = {
2604         .name   = "spare_sata2",
2605 };
2607 /* spare_sata2 */
2608 static struct omap_hwmod dra7xx_spare_sata2_hwmod = {
2609         .name           = "spare_sata2",
2610         .class          = &dra7xx_spare_sata2_hwmod_class,
2611         .clkdm_name     = "l3main1_clkdm",
2612         .main_clk       = "l4_root_clk_div",
2613         .prcm = {
2614                 .omap4 = {
2615                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL_OFFSET,
2616                         .context_offs = DRA7XX_RM_L3MAIN1_SPARE_SATA2_CONTEXT_OFFSET,
2617                 },
2618         },
2619 };
2621 /*
2622  * 'spare_smartreflex' class
2623  *
2624  */
2626 static struct omap_hwmod_class dra7xx_spare_smartreflex_hwmod_class = {
2627         .name   = "spare_smartreflex",
2628 };
2630 /* spare_smartreflex_rtc */
2631 static struct omap_hwmod dra7xx_spare_smartreflex_rtc_hwmod = {
2632         .name           = "spare_smartreflex_rtc",
2633         .class          = &dra7xx_spare_smartreflex_hwmod_class,
2634         .clkdm_name     = "l4cfg_clkdm",
2635         .main_clk       = "l4_root_clk_div",
2636         .prcm = {
2637                 .omap4 = {
2638                         .clkctrl_offs = DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL_OFFSET,
2639                         .context_offs = DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_RTC_CONTEXT_OFFSET,
2640                 },
2641         },
2642 };
2644 /* spare_smartreflex_sdram */
2645 static struct omap_hwmod dra7xx_spare_smartreflex_sdram_hwmod = {
2646         .name           = "spare_smartreflex_sdram",
2647         .class          = &dra7xx_spare_smartreflex_hwmod_class,
2648         .clkdm_name     = "l4cfg_clkdm",
2649         .main_clk       = "l4_root_clk_div",
2650         .prcm = {
2651                 .omap4 = {
2652                         .clkctrl_offs = DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL_OFFSET,
2653                         .context_offs = DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CONTEXT_OFFSET,
2654                 },
2655         },
2656 };
2658 /* spare_smartreflex_wkup */
2659 static struct omap_hwmod dra7xx_spare_smartreflex_wkup_hwmod = {
2660         .name           = "spare_smartreflex_wkup",
2661         .class          = &dra7xx_spare_smartreflex_hwmod_class,
2662         .clkdm_name     = "l4cfg_clkdm",
2663         .main_clk       = "l4_root_clk_div",
2664         .prcm = {
2665                 .omap4 = {
2666                         .clkctrl_offs = DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL_OFFSET,
2667                         .context_offs = DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_WKUP_CONTEXT_OFFSET,
2668                 },
2669         },
2670 };
2672 /*
2673  * 'spinlock' class
2674  *
2675  */
2677 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
2678         .rev_offs       = 0x0000,
2679         .sysc_offs      = 0x0010,
2680         .syss_offs      = 0x0014,
2681         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2682                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2683                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2684         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2685                            SIDLE_SMART_WKUP),
2686         .sysc_fields    = &omap_hwmod_sysc_type1,
2687 };
2689 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
2690         .name   = "spinlock",
2691         .sysc   = &dra7xx_spinlock_sysc,
2692 };
2694 /* spinlock */
2695 static struct omap_hwmod dra7xx_spinlock_hwmod = {
2696         .name           = "spinlock",
2697         .class          = &dra7xx_spinlock_hwmod_class,
2698         .clkdm_name     = "l4cfg_clkdm",
2699         .main_clk       = "l3_iclk_div",
2700         .prcm = {
2701                 .omap4 = {
2702                         .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
2703                         .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
2704                 },
2705         },
2706 };
2708 /*
2709  * 'timer' class
2710  *
2711  * This class contains several variants: ['timer_1ms', 'timer_secure',
2712  * 'timer']
2713  */
2715 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
2716         .rev_offs       = 0x0000,
2717         .sysc_offs      = 0x0010,
2718         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2719                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2720         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2721                            SIDLE_SMART_WKUP),
2722         .sysc_fields    = &omap_hwmod_sysc_type2,
2723 };
2725 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
2726         .name   = "timer",
2727         .sysc   = &dra7xx_timer_1ms_sysc,
2728 };
2730 static struct omap_hwmod_class_sysconfig dra7xx_timer_secure_sysc = {
2731         .rev_offs       = 0x0000,
2732         .sysc_offs      = 0x0010,
2733         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2734                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2735         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2736                            SIDLE_SMART_WKUP),
2737         .sysc_fields    = &omap_hwmod_sysc_type2,
2738 };
2740 static struct omap_hwmod_class dra7xx_timer_secure_hwmod_class = {
2741         .name   = "timer",
2742         .sysc   = &dra7xx_timer_secure_sysc,
2743 };
2745 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
2746         .rev_offs       = 0x0000,
2747         .sysc_offs      = 0x0010,
2748         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2749                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2750         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2751                            SIDLE_SMART_WKUP),
2752         .sysc_fields    = &omap_hwmod_sysc_type2,
2753 };
2755 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
2756         .name   = "timer",
2757         .sysc   = &dra7xx_timer_sysc,
2758 };
2760 /* timer1 */
2761 static struct omap_hwmod_irq_info dra7xx_timer1_irqs[] = {
2762         { .irq = 37 + DRA7XX_IRQ_GIC_START },
2763         { .irq = -1 }
2764 };
2766 static struct omap_hwmod dra7xx_timer1_hwmod = {
2767         .name           = "timer1",
2768         .class          = &dra7xx_timer_1ms_hwmod_class,
2769         .clkdm_name     = "wkupaon_clkdm",
2770         .mpu_irqs       = dra7xx_timer1_irqs,
2771         .main_clk       = "timer1_gfclk_mux",
2772         .prcm = {
2773                 .omap4 = {
2774                         .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
2775                         .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
2776                         .modulemode   = MODULEMODE_SWCTRL,
2777                 },
2778         },
2779 };
2781 /* timer2 */
2782 static struct omap_hwmod_irq_info dra7xx_timer2_irqs[] = {
2783         { .irq = 38 + DRA7XX_IRQ_GIC_START },
2784         { .irq = -1 }
2785 };
2787 static struct omap_hwmod dra7xx_timer2_hwmod = {
2788         .name           = "timer2",
2789         .class          = &dra7xx_timer_1ms_hwmod_class,
2790         .clkdm_name     = "l4per_clkdm",
2791         .mpu_irqs       = dra7xx_timer2_irqs,
2792         .main_clk       = "timer2_gfclk_mux",
2793         .prcm = {
2794                 .omap4 = {
2795                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
2796                         .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
2797                         .modulemode   = MODULEMODE_SWCTRL,
2798                 },
2799         },
2800 };
2802 /* timer3 */
2803 static struct omap_hwmod_irq_info dra7xx_timer3_irqs[] = {
2804         { .irq = 39 + DRA7XX_IRQ_GIC_START },
2805         { .irq = -1 }
2806 };
2808 static struct omap_hwmod dra7xx_timer3_hwmod = {
2809         .name           = "timer3",
2810         .class          = &dra7xx_timer_hwmod_class,
2811         .clkdm_name     = "l4per_clkdm",
2812         .mpu_irqs       = dra7xx_timer3_irqs,
2813         .main_clk       = "timer3_gfclk_mux",
2814         .prcm = {
2815                 .omap4 = {
2816                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
2817                         .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
2818                         .modulemode   = MODULEMODE_SWCTRL,
2819                 },
2820         },
2821 };
2823 /* timer4 */
2824 static struct omap_hwmod_irq_info dra7xx_timer4_irqs[] = {
2825         { .irq = 40 + DRA7XX_IRQ_GIC_START },
2826         { .irq = -1 }
2827 };
2829 static struct omap_hwmod dra7xx_timer4_hwmod = {
2830         .name           = "timer4",
2831         .class          = &dra7xx_timer_secure_hwmod_class,
2832         .clkdm_name     = "l4per_clkdm",
2833         .mpu_irqs       = dra7xx_timer4_irqs,
2834         .main_clk       = "timer4_gfclk_mux",
2835         .prcm = {
2836                 .omap4 = {
2837                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
2838                         .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
2839                         .modulemode   = MODULEMODE_SWCTRL,
2840                 },
2841         },
2842 };
2844 /* timer5 */
2845 static struct omap_hwmod_irq_info dra7xx_timer5_irqs[] = {
2846         { .irq = 41 + DRA7XX_IRQ_GIC_START },
2847         { .irq = -1 }
2848 };
2850 static struct omap_hwmod dra7xx_timer5_hwmod = {
2851         .name           = "timer5",
2852         .class          = &dra7xx_timer_hwmod_class,
2853         .clkdm_name     = "ipu_clkdm",
2854         .mpu_irqs       = dra7xx_timer5_irqs,
2855         .main_clk       = "timer5_gfclk_mux",
2856         .prcm = {
2857                 .omap4 = {
2858                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
2859                         .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
2860                         .modulemode   = MODULEMODE_SWCTRL,
2861                 },
2862         },
2863 };
2865 /* timer6 */
2866 static struct omap_hwmod_irq_info dra7xx_timer6_irqs[] = {
2867         { .irq = 42 + DRA7XX_IRQ_GIC_START },
2868         { .irq = -1 }
2869 };
2871 static struct omap_hwmod dra7xx_timer6_hwmod = {
2872         .name           = "timer6",
2873         .class          = &dra7xx_timer_hwmod_class,
2874         .clkdm_name     = "ipu_clkdm",
2875         .mpu_irqs       = dra7xx_timer6_irqs,
2876         .main_clk       = "timer6_gfclk_mux",
2877         .prcm = {
2878                 .omap4 = {
2879                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
2880                         .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
2881                         .modulemode   = MODULEMODE_SWCTRL,
2882                 },
2883         },
2884 };
2886 /* timer7 */
2887 static struct omap_hwmod_irq_info dra7xx_timer7_irqs[] = {
2888         { .irq = 43 + DRA7XX_IRQ_GIC_START },
2889         { .irq = -1 }
2890 };
2892 static struct omap_hwmod dra7xx_timer7_hwmod = {
2893         .name           = "timer7",
2894         .class          = &dra7xx_timer_hwmod_class,
2895         .clkdm_name     = "ipu_clkdm",
2896         .mpu_irqs       = dra7xx_timer7_irqs,
2897         .main_clk       = "timer7_gfclk_mux",
2898         .prcm = {
2899                 .omap4 = {
2900                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
2901                         .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
2902                         .modulemode   = MODULEMODE_SWCTRL,
2903                 },
2904         },
2905 };
2907 /* timer8 */
2908 static struct omap_hwmod_irq_info dra7xx_timer8_irqs[] = {
2909         { .irq = 44 + DRA7XX_IRQ_GIC_START },
2910         { .irq = -1 }
2911 };
2913 static struct omap_hwmod dra7xx_timer8_hwmod = {
2914         .name           = "timer8",
2915         .class          = &dra7xx_timer_hwmod_class,
2916         .clkdm_name     = "ipu_clkdm",
2917         .mpu_irqs       = dra7xx_timer8_irqs,
2918         .main_clk       = "timer8_gfclk_mux",
2919         .prcm = {
2920                 .omap4 = {
2921                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
2922                         .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
2923                         .modulemode   = MODULEMODE_SWCTRL,
2924                 },
2925         },
2926 };
2928 /* timer9 */
2929 static struct omap_hwmod_irq_info dra7xx_timer9_irqs[] = {
2930         { .irq = 45 + DRA7XX_IRQ_GIC_START },
2931         { .irq = -1 }
2932 };
2934 static struct omap_hwmod dra7xx_timer9_hwmod = {
2935         .name           = "timer9",
2936         .class          = &dra7xx_timer_hwmod_class,
2937         .clkdm_name     = "l4per_clkdm",
2938         .mpu_irqs       = dra7xx_timer9_irqs,
2939         .main_clk       = "timer9_gfclk_mux",
2940         .prcm = {
2941                 .omap4 = {
2942                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
2943                         .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
2944                         .modulemode   = MODULEMODE_SWCTRL,
2945                 },
2946         },
2947 };
2949 /* timer10 */
2950 static struct omap_hwmod_irq_info dra7xx_timer10_irqs[] = {
2951         { .irq = 46 + DRA7XX_IRQ_GIC_START },
2952         { .irq = -1 }
2953 };
2955 static struct omap_hwmod dra7xx_timer10_hwmod = {
2956         .name           = "timer10",
2957         .class          = &dra7xx_timer_1ms_hwmod_class,
2958         .clkdm_name     = "l4per_clkdm",
2959         .mpu_irqs       = dra7xx_timer10_irqs,
2960         .main_clk       = "timer10_gfclk_mux",
2961         .prcm = {
2962                 .omap4 = {
2963                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
2964                         .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
2965                         .modulemode   = MODULEMODE_SWCTRL,
2966                 },
2967         },
2968 };
2970 /* timer11 */
2971 static struct omap_hwmod_irq_info dra7xx_timer11_irqs[] = {
2972         { .irq = 47 + DRA7XX_IRQ_GIC_START },
2973         { .irq = -1 }
2974 };
2976 static struct omap_hwmod dra7xx_timer11_hwmod = {
2977         .name           = "timer11",
2978         .class          = &dra7xx_timer_hwmod_class,
2979         .clkdm_name     = "l4per_clkdm",
2980         .mpu_irqs       = dra7xx_timer11_irqs,
2981         .main_clk       = "timer11_gfclk_mux",
2982         .prcm = {
2983                 .omap4 = {
2984                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
2985                         .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
2986                         .modulemode   = MODULEMODE_SWCTRL,
2987                 },
2988         },
2989 };
2991 /* timer13 */
2992 static struct omap_hwmod dra7xx_timer13_hwmod = {
2993         .name           = "timer13",
2994         .class          = &dra7xx_timer_hwmod_class,
2995         .clkdm_name     = "l4per3_clkdm",
2996         .main_clk       = "timer13_gfclk_mux",
2997         .prcm = {
2998                 .omap4 = {
2999                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
3000                         .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
3001                         .modulemode   = MODULEMODE_SWCTRL,
3002                 },
3003         },
3004 };
3006 /* timer14 */
3007 static struct omap_hwmod dra7xx_timer14_hwmod = {
3008         .name           = "timer14",
3009         .class          = &dra7xx_timer_hwmod_class,
3010         .clkdm_name     = "l4per3_clkdm",
3011         .main_clk       = "timer14_gfclk_mux",
3012         .prcm = {
3013                 .omap4 = {
3014                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
3015                         .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
3016                         .modulemode   = MODULEMODE_SWCTRL,
3017                 },
3018         },
3019 };
3021 /* timer15 */
3022 static struct omap_hwmod dra7xx_timer15_hwmod = {
3023         .name           = "timer15",
3024         .class          = &dra7xx_timer_hwmod_class,
3025         .clkdm_name     = "l4per3_clkdm",
3026         .main_clk       = "timer15_gfclk_mux",
3027         .prcm = {
3028                 .omap4 = {
3029                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
3030                         .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
3031                         .modulemode   = MODULEMODE_SWCTRL,
3032                 },
3033         },
3034 };
3036 /* timer16 */
3037 static struct omap_hwmod dra7xx_timer16_hwmod = {
3038         .name           = "timer16",
3039         .class          = &dra7xx_timer_hwmod_class,
3040         .clkdm_name     = "l4per3_clkdm",
3041         .main_clk       = "timer16_gfclk_mux",
3042         .prcm = {
3043                 .omap4 = {
3044                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
3045                         .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
3046                         .modulemode   = MODULEMODE_SWCTRL,
3047                 },
3048         },
3049 };
3051 /*
3052  * 'uart' class
3053  *
3054  */
3056 static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
3057         .rev_offs       = 0x0050,
3058         .sysc_offs      = 0x0054,
3059         .syss_offs      = 0x0058,
3060         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3061                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3062                            SYSS_HAS_RESET_STATUS),
3063         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |