arm: dra7: hwmod: remove opt clks enable flag from hwmod
[android-sdk/kernel-video.git] / arch / arm / mach-omap2 / omap_hwmod_7xx_data.c
1 /*
2  * Hardware modules present on the DRA7xx chips
3  *
4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5  *
6  * Paul Walmsley
7  * Benoit Cousson
8  *
9  * This file is automatically generated from the OMAP hardware databases.
10  * We respectfully ask that any modifications to this file be coordinated
11  * with the public linux-omap@vger.kernel.org mailing list and the
12  * authors above to ensure that the autogeneration scripts are kept
13  * up-to-date with the file contents.
14  *
15  * This program is free software; you can redistribute it and/or modify
16  * it under the terms of the GNU General Public License version 2 as
17  * published by the Free Software Foundation.
18  */
20 #include <linux/io.h>
21 #include <linux/platform_data/gpio-omap.h>
22 #include <linux/power/smartreflex.h>
23 #include <linux/i2c-omap.h>
25 #include <linux/omap-dma.h>
26 #include <linux/platform_data/spi-omap2-mcspi.h>
27 #include <linux/platform_data/asoc-ti-mcbsp.h>
28 #include <linux/platform_data/iommu-omap.h>
29 #include <plat/dmtimer.h>
31 #include "omap_hwmod.h"
32 #include "omap_hwmod_common_data.h"
33 #include "cm1_7xx.h"
34 #include "cm2_7xx.h"
35 #include "prm7xx.h"
36 #include "i2c.h"
37 #include "mmc.h"
38 #include "wd_timer.h"
39 #include "soc.h"
41 /* Base offset for all DRA7XX interrupts external to MPUSS */
42 #define DRA7XX_IRQ_GIC_START    32
44 /* Base offset for all DRA7XX dma requests */
45 #define DRA7XX_DMA_REQ_START    1
48 /*
49  * IP blocks
50  */
52 /*
53  * 'dmm' class
54  * instance(s): dmm
55  */
56 static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
57         .name   = "dmm",
58 };
60 /* dmm */
61 static struct omap_hwmod dra7xx_dmm_hwmod = {
62         .name           = "dmm",
63         .class          = &dra7xx_dmm_hwmod_class,
64         .clkdm_name     = "emif_clkdm",
65         .prcm = {
66                 .omap4 = {
67                         .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
68                         .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
69                 },
70         },
71 };
73 /*
74  * 'emif_ocp_fw' class
75  * instance(s): emif_ocp_fw
76  */
77 static struct omap_hwmod_class dra7xx_emif_ocp_fw_hwmod_class = {
78         .name   = "emif_ocp_fw",
79 };
81 /* emif_ocp_fw */
82 static struct omap_hwmod dra7xx_emif_ocp_fw_hwmod = {
83         .name           = "emif_ocp_fw",
84         .class          = &dra7xx_emif_ocp_fw_hwmod_class,
85         .clkdm_name     = "emif_clkdm",
86         .prcm = {
87                 .omap4 = {
88                         .clkctrl_offs = DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET,
89                         .context_offs = DRA7XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET,
90                 },
91         },
92 };
94 /*
95  * 'l3' class
96  * instance(s): l3_instr, l3_main_1, l3_main_2
97  */
98 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
99         .name   = "l3",
100 };
102 /* l3_instr */
103 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
104         .name           = "l3_instr",
105         .class          = &dra7xx_l3_hwmod_class,
106         .clkdm_name     = "l3instr_clkdm",
107         .prcm = {
108                 .omap4 = {
109                         .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
110                         .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
111                         .modulemode   = MODULEMODE_HWCTRL,
112                 },
113         },
114 };
116 /* l3_main_1 */
117 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
118         .name           = "l3_main_1",
119         .class          = &dra7xx_l3_hwmod_class,
120         .clkdm_name     = "l3main1_clkdm",
121         .prcm = {
122                 .omap4 = {
123                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
124                         .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
125                 },
126         },
127 };
129 /* l3_main_2 */
130 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
131         .name           = "l3_main_2",
132         .class          = &dra7xx_l3_hwmod_class,
133         .clkdm_name     = "l3instr_clkdm",
134         .prcm = {
135                 .omap4 = {
136                         .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
137                         .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
138                         .modulemode   = MODULEMODE_HWCTRL,
139                 },
140         },
141 };
143 /*
144  * 'l4' class
145  * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
146  */
147 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
148         .name   = "l4",
149 };
151 /* l4_cfg */
152 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
153         .name           = "l4_cfg",
154         .class          = &dra7xx_l4_hwmod_class,
155         .clkdm_name     = "l4cfg_clkdm",
156         .prcm = {
157                 .omap4 = {
158                         .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
159                         .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
160                 },
161         },
162 };
164 /* l4_per1 */
165 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
166         .name           = "l4_per1",
167         .class          = &dra7xx_l4_hwmod_class,
168         .clkdm_name     = "l4per_clkdm",
169         .prcm = {
170                 .omap4 = {
171                         .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
172                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
173                 },
174         },
175 };
177 /* l4_per2 */
178 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
179         .name           = "l4_per2",
180         .class          = &dra7xx_l4_hwmod_class,
181         .clkdm_name     = "l4per2_clkdm",
182         .prcm = {
183                 .omap4 = {
184                         .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
185                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
186                 },
187         },
188 };
190 /* l4_per3 */
191 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
192         .name           = "l4_per3",
193         .class          = &dra7xx_l4_hwmod_class,
194         .clkdm_name     = "l4per3_clkdm",
195         .prcm = {
196                 .omap4 = {
197                         .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
198                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
199                 },
200         },
201 };
203 /* l4_wkup */
204 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
205         .name           = "l4_wkup",
206         .class          = &dra7xx_l4_hwmod_class,
207         .clkdm_name     = "wkupaon_clkdm",
208         .prcm = {
209                 .omap4 = {
210                         .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
211                         .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
212                 },
213         },
214 };
216 /*
217  * 'atl' class
218  *
219  */
221 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
222         .name   = "atl",
223 };
225 /* atl */
226 static struct omap_hwmod dra7xx_atl_hwmod = {
227         .name           = "atl",
228         .class          = &dra7xx_atl_hwmod_class,
229         .clkdm_name     = "atl_clkdm",
230         .main_clk       = "atl_gfclk_mux",
231         .lockdep_class  = HWMOD_LOCKDEP_SUBCLASS_CLASS1,
232         .prcm = {
233                 .omap4 = {
234                         .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
235                         .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
236                         .modulemode   = MODULEMODE_SWCTRL,
237                 },
238         },
239 };
241 /*
242  * 'bb2d' class
243  *
244  */
246 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
247         .name   = "bb2d",
248 };
250 /* bb2d */
251 static struct omap_hwmod dra7xx_bb2d_hwmod = {
252         .name           = "bb2d",
253         .class          = &dra7xx_bb2d_hwmod_class,
254         .clkdm_name     = "dss_clkdm",
255         .main_clk       = "dpll_core_h24x2_ck",
256         .prcm = {
257                 .omap4 = {
258                         .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
259                         .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
260                         .modulemode   = MODULEMODE_SWCTRL,
261                 },
262         },
263 };
265 /*
266  * 'vpe' class
267  *
268  */
270 static struct omap_hwmod_class_sysconfig dra7xx_vpe_sysc = {
271         .sysc_offs      = 0x0010,
272         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
273         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
274                            MSTANDBY_FORCE | MSTANDBY_NO |
275                            MSTANDBY_SMART),
276         .sysc_fields    = &omap_hwmod_sysc_type2,
277 };
279 static struct omap_hwmod_class dra7xx_vpe_hwmod_class = {
280         .name   = "vpe",
281         .sysc   = &dra7xx_vpe_sysc,
282 };
284 /* vpe */
285 static struct omap_hwmod dra7xx_vpe_hwmod = {
286         .name           = "vpe",
287         .class          = &dra7xx_vpe_hwmod_class,
288         .clkdm_name     = "vpe_clkdm",
289         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
290         .prcm = {
291                 .omap4 = {
292                         .clkctrl_offs = DRA7XX_CM_VPE_VPE_CLKCTRL_OFFSET,
293                         .context_offs = DRA7XX_RM_VPE_VPE_CONTEXT_OFFSET,
294                         .modulemode   = MODULEMODE_HWCTRL,
295                 },
296         },
297 };
299 /*
300  * 'vip' class
301  *
302  */
304 static struct omap_hwmod_class_sysconfig dra7xx_vip_sysc = {
305         .sysc_offs      = 0x0010,
306         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
307         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
308                            MSTANDBY_FORCE | MSTANDBY_NO |
309                            MSTANDBY_SMART),
310         .sysc_fields    = &omap_hwmod_sysc_type2,
311 };
313 static struct omap_hwmod_class dra7xx_vip_hwmod_class = {
314         .name   = "vip",
315         .sysc   = &dra7xx_vip_sysc,
316 };
318 /* vip1 */
319 static struct omap_hwmod dra7xx_vip1_hwmod = {
320         .name           = "vip1",
321         .class          = &dra7xx_vip_hwmod_class,
322         .clkdm_name     = "cam_clkdm",
323         .main_clk       = "vip1_gclk_mux",
324         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
325         .prcm = {
326                 .omap4 = {
327                         .clkctrl_offs = DRA7XX_CM_CAM_VIP1_CLKCTRL_OFFSET,
328                         .context_offs = DRA7XX_RM_CAM_VIP1_CONTEXT_OFFSET,
329                         .modulemode   = MODULEMODE_HWCTRL,
330                 },
331         },
332 };
334 /* vip2 */
335 static struct omap_hwmod dra7xx_vip2_hwmod = {
336         .name           = "vip2",
337         .class          = &dra7xx_vip_hwmod_class,
338         .clkdm_name     = "cam_clkdm",
339         .main_clk       = "vip2_gclk_mux",
340         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
341         .prcm = {
342                 .omap4 = {
343                         .clkctrl_offs = DRA7XX_CM_CAM_VIP2_CLKCTRL_OFFSET,
344                         .context_offs = DRA7XX_RM_CAM_VIP2_CONTEXT_OFFSET,
345                         .modulemode   = MODULEMODE_HWCTRL,
346                 },
347         },
348 };
350 /* vip3 */
351 static struct omap_hwmod dra7xx_vip3_hwmod = {
352         .name           = "vip3",
353         .class          = &dra7xx_vip_hwmod_class,
354         .clkdm_name     = "cam_clkdm",
355         .main_clk       = "vip3_gclk_mux",
356         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
357         .prcm = {
358                 .omap4 = {
359                         .clkctrl_offs = DRA7XX_CM_CAM_VIP3_CLKCTRL_OFFSET,
360                         .context_offs = DRA7XX_RM_CAM_VIP3_CONTEXT_OFFSET,
361                         .modulemode   = MODULEMODE_HWCTRL,
362                 },
363         },
364 };
366 /*
367  * 'cal' class
368  *
369  */
371 static struct omap_hwmod_class_sysconfig dra7xx_cal_sysc = {
372         .sysc_offs      = 0x0010,
373         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_RESET_STATUS |
374                            SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE),
375         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
376                            MSTANDBY_FORCE | MSTANDBY_NO),
377         .sysc_fields    = &omap_hwmod_sysc_type2,
378 };
380 static struct omap_hwmod_class dra7xx_cal_hwmod_class = {
381         .name   = "cal",
382         .sysc   = &dra7xx_cal_sysc,
383 };
385 /* cal */
386 static struct omap_hwmod dra7xx_cal_hwmod = {
387         .name           = "cal",
388         .class          = &dra7xx_cal_hwmod_class,
389         .clkdm_name     = "cam_clkdm",
390         .main_clk       = "vip2_gclk_mux",
391         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
392         .prcm = {
393                 .omap4 = {
394                         .clkctrl_offs = DRA7XX_CM_CAM_VIP2_CLKCTRL_OFFSET,
395                         .context_offs = DRA7XX_RM_CAM_VIP2_CONTEXT_OFFSET,
396                         .modulemode   = MODULEMODE_HWCTRL,
397                 },
398         },
399 };
401 /*
402  * 'counter' class
403  *
404  */
406 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
407         .rev_offs       = 0x0000,
408         .sysc_offs      = 0x0010,
409         .sysc_flags     = SYSC_HAS_SIDLEMODE,
410         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
411                            SIDLE_SMART_WKUP),
412         .sysc_fields    = &omap_hwmod_sysc_type1,
413 };
415 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
416         .name   = "counter",
417         .sysc   = &dra7xx_counter_sysc,
418 };
420 /* counter_32k */
421 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
422         .name           = "counter_32k",
423         .class          = &dra7xx_counter_hwmod_class,
424         .clkdm_name     = "wkupaon_clkdm",
425         .flags          = HWMOD_SWSUP_SIDLE,
426         .main_clk       = "wkupaon_iclk_mux",
427         .prcm = {
428                 .omap4 = {
429                         .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
430                         .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
431                 },
432         },
433 };
435 /*
436  * 'ctrl_module' class
437  *
438  */
440 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
441         .name   = "ctrl_module",
442 };
444 /* ctrl_module_wkup */
445 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
446         .name           = "ctrl_module_wkup",
447         .class          = &dra7xx_ctrl_module_hwmod_class,
448         .clkdm_name     = "wkupaon_clkdm",
449         .prcm = {
450                 .omap4 = {
451                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
452                 },
453         },
454 };
456 /*
457  * 'gmac' class
458  * cpsw/gmac sub system
459  */
460 static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
461         .rev_offs       = 0x0,
462         .sysc_offs      = 0x8,
463         .syss_offs      = 0x4,
464         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
465                            SYSS_HAS_RESET_STATUS),
466         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
467                            MSTANDBY_NO),
468         .sysc_fields    = &omap_hwmod_sysc_type3,
469 };
471 static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
472         .name           = "gmac",
473         .sysc           = &dra7xx_gmac_sysc,
474 };
476 static struct omap_hwmod dra7xx_gmac_hwmod = {
477         .name           = "gmac",
478         .class          = &dra7xx_gmac_hwmod_class,
479         .clkdm_name     = "gmac_clkdm",
480         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
481         .main_clk       = "dpll_gmac_ck",
482         .mpu_rt_idx     = 1,
483         .prcm           = {
484                 .omap4  = {
485                         .clkctrl_offs   = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
486                         .context_offs   = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
487                         .modulemode     = MODULEMODE_SWCTRL,
488                 },
489         },
490 };
492 /*
493  * 'mdio' class
494  */
495 static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
496         .name           = "davinci_mdio",
497 };
499 static struct omap_hwmod dra7xx_mdio_hwmod = {
500         .name           = "davinci_mdio",
501         .class          = &dra7xx_mdio_hwmod_class,
502         .clkdm_name     = "gmac_clkdm",
503         .main_clk       = "dpll_gmac_ck",
504 };
506 /*
507  * 'dcan' class
508  *
509  */
511 static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
512         .name   = "dcan",
513 };
515 /* dcan1 */
516 static struct omap_hwmod dra7xx_dcan1_hwmod = {
517         .name           = "dcan1",
518         .class          = &dra7xx_dcan_hwmod_class,
519         .clkdm_name     = "wkupaon_clkdm",
520         .prcm = {
521                 .omap4 = {
522                         .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
523                         .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
524                         .modulemode   = MODULEMODE_SWCTRL,
525                 },
526         },
527 };
529 /* dcan2 */
530 static struct omap_hwmod dra7xx_dcan2_hwmod = {
531         .name           = "dcan2",
532         .class          = &dra7xx_dcan_hwmod_class,
533         .clkdm_name     = "l4per2_clkdm",
534         .prcm = {
535                 .omap4 = {
536                         .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
537                         .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
538                         .modulemode   = MODULEMODE_SWCTRL,
539                 },
540         },
541 };
543 /* pwmss  */
544 static struct omap_hwmod_class_sysconfig dra7xx_epwmss_sysc = {
545         .rev_offs       = 0x0,
546         .sysc_offs      = 0x4,
547         .sysc_flags     = SYSC_HAS_SIDLEMODE | SYSC_HAS_RESET_STATUS,
548         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
549         .sysc_fields    = &omap_hwmod_sysc_type2,
550 };
552 struct omap_hwmod_class dra7xx_epwmss_hwmod_class = {
553         .name           = "epwmss",
554         .sysc           = &dra7xx_epwmss_sysc,
555 };
557 static struct omap_hwmod_class dra7xx_ecap_hwmod_class = {
558         .name           = "ecap",
559 };
561 static struct omap_hwmod_class dra7xx_eqep_hwmod_class = {
562         .name           = "eqep",
563 };
565 struct omap_hwmod_class dra7xx_ehrpwm_hwmod_class = {
566         .name           = "ehrpwm",
567 };
569 /* epwmss0 */
570 struct omap_hwmod dra7xx_epwmss0_hwmod = {
571         .name           = "epwmss0",
572         .class          = &dra7xx_epwmss_hwmod_class,
573         .clkdm_name     = "l4per2_clkdm",
574         .main_clk       = "l4_root_clk_div",
575         .prcm           = {
576                 .omap4  = {
577                         .modulemode     = MODULEMODE_SWCTRL,
578                         .clkctrl_offs   = DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET,
579                         .context_offs   = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET,
580                 },
581         },
582 };
584 /* ecap0 */
585 struct omap_hwmod dra7xx_ecap0_hwmod = {
586         .name           = "ecap0",
587         .class          = &dra7xx_ecap_hwmod_class,
588         .clkdm_name     = "l4per2_clkdm",
589         .main_clk       = "l4_root_clk_div",
590 };
592 /* eqep0 */
593 struct omap_hwmod dra7xx_eqep0_hwmod = {
594         .name           = "eqep0",
595         .class          = &dra7xx_eqep_hwmod_class,
596         .clkdm_name     = "l4per2_clkdm",
597         .main_clk       = "l4_root_clk_div",
598 };
600 /* ehrpwm0 */
601 struct omap_hwmod dra7xx_ehrpwm0_hwmod = {
602         .name           = "ehrpwm0",
603         .class          = &dra7xx_ehrpwm_hwmod_class,
604         .clkdm_name     = "l4per2_clkdm",
605         .main_clk       = "l4_root_clk_div",
606 };
608 /* epwmss1 */
609 struct omap_hwmod dra7xx_epwmss1_hwmod = {
610         .name           = "epwmss1",
611         .class          = &dra7xx_epwmss_hwmod_class,
612         .clkdm_name     = "l4per2_clkdm",
613         .main_clk       = "l4_root_clk_div",
614         .prcm           = {
615                 .omap4  = {
616                         .modulemode     = MODULEMODE_SWCTRL,
617                         .clkctrl_offs   = DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET,
618                         .context_offs   = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET,
619                 },
620         },
621 };
623 /* ecap1 */
624 struct omap_hwmod dra7xx_ecap1_hwmod = {
625         .name           = "ecap1",
626         .class          = &dra7xx_ecap_hwmod_class,
627         .clkdm_name     = "l4per2_clkdm",
628         .main_clk       = "l4_root_clk_div",
629 };
631 /* eqep1 */
632 struct omap_hwmod dra7xx_eqep1_hwmod = {
633         .name           = "eqep1",
634         .class          = &dra7xx_eqep_hwmod_class,
635         .clkdm_name     = "l4per2_clkdm",
636         .main_clk       = "l4_root_clk_div",
637 };
639 /* ehrpwm1 */
640 struct omap_hwmod dra7xx_ehrpwm1_hwmod = {
641         .name           = "ehrpwm1",
642         .class          = &dra7xx_ehrpwm_hwmod_class,
643         .clkdm_name     = "l4per2_clkdm",
644         .main_clk       = "l4_root_clk_div",
645 };
647 /* epwmss2 */
648 struct omap_hwmod dra7xx_epwmss2_hwmod = {
649         .name           = "epwmss2",
650         .class          = &dra7xx_epwmss_hwmod_class,
651         .clkdm_name     = "l4per2_clkdm",
652         .main_clk       = "l4_root_clk_div",
653         .prcm           = {
654                 .omap4  = {
655                         .modulemode     = MODULEMODE_SWCTRL,
656                         .clkctrl_offs   = DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET,
657                         .context_offs   = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET,
658                 },
659         },
660 };
662 /* ecap2 */
663 struct omap_hwmod dra7xx_ecap2_hwmod = {
664         .name           = "ecap2",
665         .class          = &dra7xx_ecap_hwmod_class,
666         .clkdm_name     = "l4per2_clkdm",
667         .main_clk       = "l4_root_clk_div",
668 };
670 /* eqep2 */
671 struct omap_hwmod dra7xx_eqep2_hwmod = {
672         .name           = "eqep2",
673         .class          = &dra7xx_eqep_hwmod_class,
674         .clkdm_name     = "l4per2_clkdm",
675         .main_clk       = "l4_root_clk_div",
676 };
678 /* ehrpwm2 */
679 struct omap_hwmod dra7xx_ehrpwm2_hwmod = {
680         .name           = "ehrpwm2",
681         .class          = &dra7xx_ehrpwm_hwmod_class,
682         .clkdm_name     = "l4per2_clkdm",
683         .main_clk       = "l4_root_clk_div",
684 };
686 /*
687  * 'dma' class
688  *
689  */
691 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
692         .rev_offs       = 0x0000,
693         .sysc_offs      = 0x002c,
694         .syss_offs      = 0x0028,
695         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
696                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
697                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
698                            SYSS_HAS_RESET_STATUS),
699         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
700                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
701                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
702         .sysc_fields    = &omap_hwmod_sysc_type1,
703 };
705 static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
706         .name   = "dma",
707         .sysc   = &dra7xx_dma_sysc,
708 };
710 /* dma dev_attr */
711 static struct omap_dma_dev_attr dma_dev_attr = {
712         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
713                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
714         .lch_count      = 32,
715 };
717 /* dma_system */
718 static struct omap_hwmod dra7xx_dma_system_hwmod = {
719         .name           = "dma_system",
720         .class          = &dra7xx_dma_hwmod_class,
721         .clkdm_name     = "dma_clkdm",
722         .main_clk       = "l3_iclk_div",
723         .prcm = {
724                 .omap4 = {
725                         .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
726                         .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
727                 },
728         },
729         .dev_attr       = &dma_dev_attr,
730 };
732 /* tpcc */
733 static struct omap_hwmod_class dra7xx_tpcc_hwmod_class = {
734         .name           = "tpcc",
735 };
737 struct omap_hwmod dra7xx_tpcc_hwmod = {
738         .name           = "tpcc",
739         .class          = &dra7xx_tpcc_hwmod_class,
740         .clkdm_name     = "l3main1_clkdm",
741         .main_clk       = "l3_iclk_div",
742         .prcm           = {
743                 .omap4  = {
744                         .modulemode     = MODULEMODE_SWCTRL,
745                 },
746         },
747 };
749 /* 'tptc' class */
750 static struct omap_hwmod_class dra7xx_tptc_hwmod_class = {
751         .name           = "tptc",
752 };
754 /* tptc0 */
755 struct omap_hwmod dra7xx_tptc0_hwmod = {
756         .name           = "tptc0",
757         .class          = &dra7xx_tptc_hwmod_class,
758         .clkdm_name     = "l3main1_clkdm",
759         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
760                           HWMOD_NEEDS_REIDLE,
761         .main_clk       = "l3_iclk_div",
762         .prcm           = {
763                 .omap4  = {
764                         .modulemode     = MODULEMODE_SWCTRL,
765                 },
766         },
767 };
769 /* tptc1 */
770 struct omap_hwmod dra7xx_tptc1_hwmod = {
771         .name           = "tptc1",
772         .class          = &dra7xx_tptc_hwmod_class,
773         .clkdm_name     = "l3main1_clkdm",
774         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
775                           HWMOD_NEEDS_REIDLE,
776         .main_clk       = "l3_iclk_div",
777         .prcm           = {
778                 .omap4  = {
779                         .modulemode     = MODULEMODE_SWCTRL,
780                 },
781         },
782 };
784 /* tptc2 */
785 struct omap_hwmod dra7xx_tptc2_hwmod = {
786         .name           = "tptc2",
787         .class          = &dra7xx_tptc_hwmod_class,
788         .clkdm_name     = "l3main1_clkdm",
789         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
790                           HWMOD_NEEDS_REIDLE,
791         .main_clk       = "l3_iclk_div",
792         .prcm           = {
793                 .omap4  = {
794                         .modulemode     = MODULEMODE_SWCTRL,
795                 },
796         },
797 };
799 /*
800  * 'dsp' class
801  * dsp sub-system
802  */
804 static struct omap_hwmod_class dra7xx_dsp_hwmod_class = {
805         .name   = "dsp",
806 };
808 static struct omap_hwmod_rst_info dra7xx_dsp_resets[] = {
809         { .name = "dsp", .rst_shift = 0 },
810 };
812 /* dsp1 processor */
813 static struct omap_hwmod dra7xx_dsp1_hwmod = {
814         .name           = "dsp1",
815         .class          = &dra7xx_dsp_hwmod_class,
816         .clkdm_name     = "dsp1_clkdm",
817         .rst_lines      = dra7xx_dsp_resets,
818         .rst_lines_cnt  = ARRAY_SIZE(dra7xx_dsp_resets),
819         .main_clk       = "dpll_dsp_m2_ck",
820         .prcm = {
821                 .omap4 = {
822                         .clkctrl_offs = DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET,
823                         .rstctrl_offs = DRA7XX_RM_DSP1_RSTCTRL_OFFSET,
824                         .context_offs = DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET,
825                 },
826         },
827 };
829 /* dsp2 processor */
830 static struct omap_hwmod dra7xx_dsp2_hwmod = {
831         .name           = "dsp2",
832         .class          = &dra7xx_dsp_hwmod_class,
833         .clkdm_name     = "dsp2_clkdm",
834         .rst_lines      = dra7xx_dsp_resets,
835         .rst_lines_cnt  = ARRAY_SIZE(dra7xx_dsp_resets),
836         .main_clk       = "dpll_dsp_m2_ck",
837         .prcm = {
838                 .omap4 = {
839                         .clkctrl_offs = DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET,
840                         .rstctrl_offs = DRA7XX_RM_DSP2_RSTCTRL_OFFSET,
841                         .context_offs = DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET,
842                 },
843         },
844 };
846 /*
847  * 'dss' class
848  *
849  */
851 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
852         .rev_offs       = 0x0000,
853         .syss_offs      = 0x0014,
854         .sysc_flags     = SYSS_HAS_RESET_STATUS,
855 };
857 static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
858         .name   = "dss",
859         .sysc   = &dra7xx_dss_sysc,
860         .reset  = omap_dss_reset,
861 };
863 /* dss */
864 static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
865         { .dma_req = 75 + DRA7XX_DMA_REQ_START },
866         { .dma_req = -1 }
867 };
869 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
870         { .role = "dss_clk", .clk = "dss_dss_clk" },
871         { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
872         { .role = "32khz_clk", .clk = "dss_32khz_clk" },
873         { .role = "video2_clk", .clk = "dss_video2_clk" },
874         { .role = "video1_clk", .clk = "dss_video1_clk" },
875         { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
876 };
878 static struct omap_hwmod dra7xx_dss_hwmod = {
879         .name           = "dss_core",
880         .class          = &dra7xx_dss_hwmod_class,
881         .clkdm_name     = "dss_clkdm",
882         .sdma_reqs      = dra7xx_dss_sdma_reqs,
883         .main_clk       = "dss_dss_clk",
884         .prcm = {
885                 .omap4 = {
886                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
887                         .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
888                         .modulemode   = MODULEMODE_SWCTRL,
889                 },
890         },
891         .opt_clks       = dss_opt_clks,
892         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
893 };
895 /*
896  * 'dispc' class
897  * display controller
898  */
900 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
901         .rev_offs       = 0x0000,
902         .sysc_offs      = 0x0010,
903         .syss_offs      = 0x0014,
904         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
905                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
906                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
907                            SYSS_HAS_RESET_STATUS),
908         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
909                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
910         .sysc_fields    = &omap_hwmod_sysc_type1,
911 };
913 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
914         .name   = "dispc",
915         .sysc   = &dra7xx_dispc_sysc,
916 };
918 /* dss_dispc */
919 /* dss_dispc dev_attr */
920 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
921         .has_framedonetv_irq    = 1,
922         .manager_count          = 4,
923 };
925 static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
926         .name           = "dss_dispc",
927         .class          = &dra7xx_dispc_hwmod_class,
928         .clkdm_name     = "dss_clkdm",
929         .main_clk       = "dss_dss_clk",
930         .prcm = {
931                 .omap4 = {
932                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
933                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
934                 },
935         },
936         .dev_attr       = &dss_dispc_dev_attr,
937         .parent_hwmod   = &dra7xx_dss_hwmod,
938 };
940 /*
941  * 'hdmi' class
942  * hdmi controller
943  */
945 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
946         .rev_offs       = 0x0000,
947         .sysc_offs      = 0x0010,
948         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
949                            SYSC_HAS_SOFTRESET),
950         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
951                            SIDLE_SMART_WKUP),
952         .sysc_fields    = &omap_hwmod_sysc_type2,
953 };
955 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
956         .name   = "hdmi",
957         .sysc   = &dra7xx_hdmi_sysc,
958 };
960 /* dss_hdmi */
962 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
963         { .role = "sys_clk", .clk = "dss_hdmi_clk" },
964 };
966 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
967         .name           = "dss_hdmi",
968         .class          = &dra7xx_hdmi_hwmod_class,
969         .clkdm_name     = "dss_clkdm",
970         .main_clk       = "dss_48mhz_clk",
971         .prcm = {
972                 .omap4 = {
973                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
974                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
975                 },
976         },
977         .opt_clks       = dss_hdmi_opt_clks,
978         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
979         .parent_hwmod   = &dra7xx_dss_hwmod,
980 };
982 /* AES (the 'P' (public) device) */
983 static struct omap_hwmod_class_sysconfig dra7xx_aes_sysc = {
984         .rev_offs       = 0x0080,
985         .sysc_offs      = 0x0084,
986         .syss_offs      = 0x0088,
987         .sysc_flags     = SYSS_HAS_RESET_STATUS,
988 };
990 static struct omap_hwmod_class dra7xx_aes_hwmod_class = {
991         .name   = "aes",
992         .sysc   = &dra7xx_aes_sysc,
993         .rev    = 2,
994 };
996 /* AES1 */
997 static struct omap_hwmod dra7xx_aes1_hwmod = {
998         .name           = "aes1",
999         .class          = &dra7xx_aes_hwmod_class,
1000         .clkdm_name     = "l4sec_clkdm",
1001         .main_clk       = "l3_iclk_div",
1002         .prcm = {
1003                 .omap4 = {
1004                         .clkctrl_offs = DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET,
1005                         .context_offs = DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET,
1006                         .modulemode   = MODULEMODE_HWCTRL,
1007                 },
1008         },
1009 };
1011 /* AES2 */
1012 static struct omap_hwmod dra7xx_aes2_hwmod = {
1013         .name           = "aes2",
1014         .class          = &dra7xx_aes_hwmod_class,
1015         .clkdm_name     = "l4sec_clkdm",
1016         .main_clk       = "l3_iclk_div",
1017         .prcm = {
1018                 .omap4 = {
1019                         .clkctrl_offs = DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET,
1020                         .context_offs = DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET,
1021                         .modulemode   = MODULEMODE_HWCTRL,
1022                 },
1023         },
1024 };
1026 /* sha0 HIB2 (the 'P' (public) device) */
1027 static struct omap_hwmod_class_sysconfig dra7xx_sha0_sysc = {
1028         .rev_offs       = 0x100,
1029         .sysc_offs      = 0x110,
1030         .syss_offs      = 0x114,
1031         .sysc_flags     = SYSS_HAS_RESET_STATUS,
1032 };
1034 static struct omap_hwmod_class dra7xx_sha0_hwmod_class = {
1035         .name           = "sham",
1036         .sysc           = &dra7xx_sha0_sysc,
1037         .rev            = 2,
1038 };
1040 struct omap_hwmod dra7xx_sha0_hwmod = {
1041         .name           = "sham",
1042         .class          = &dra7xx_sha0_hwmod_class,
1043         .clkdm_name     = "l4sec_clkdm",
1044         .main_clk       = "l3_iclk_div",
1045         .prcm           = {
1046                 .omap4 = {
1047                         .clkctrl_offs = DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
1048                         .context_offs = DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
1049                         .modulemode   = MODULEMODE_HWCTRL,
1050                 },
1051         },
1052 };
1054 /*
1055  * 'elm' class
1056  *
1057  */
1059 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
1060         .rev_offs       = 0x0000,
1061         .sysc_offs      = 0x0010,
1062         .syss_offs      = 0x0014,
1063         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1064                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1065                            SYSS_HAS_RESET_STATUS),
1066         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1067                            SIDLE_SMART_WKUP),
1068         .sysc_fields    = &omap_hwmod_sysc_type1,
1069 };
1071 static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
1072         .name   = "elm",
1073         .sysc   = &dra7xx_elm_sysc,
1074 };
1076 /* elm */
1078 static struct omap_hwmod dra7xx_elm_hwmod = {
1079         .name           = "elm",
1080         .class          = &dra7xx_elm_hwmod_class,
1081         .clkdm_name     = "l4per_clkdm",
1082         .main_clk       = "l3_iclk_div",
1083         .prcm = {
1084                 .omap4 = {
1085                         .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
1086                         .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
1087                 },
1088         },
1089 };
1091 /*
1092  * 'gpio' class
1093  *
1094  */
1096 static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
1097         .rev_offs       = 0x0000,
1098         .sysc_offs      = 0x0010,
1099         .syss_offs      = 0x0114,
1100         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1101                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1102                            SYSS_HAS_RESET_STATUS),
1103         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1104                            SIDLE_SMART_WKUP),
1105         .sysc_fields    = &omap_hwmod_sysc_type1,
1106 };
1108 static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
1109         .name   = "gpio",
1110         .sysc   = &dra7xx_gpio_sysc,
1111         .rev    = 2,
1112 };
1114 /* gpio dev_attr */
1115 static struct omap_gpio_dev_attr gpio_dev_attr = {
1116         .bank_width     = 32,
1117         .dbck_flag      = true,
1118 };
1120 /* gpio1 */
1121 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1122         { .role = "dbclk", .clk = "gpio1_dbclk" },
1123 };
1125 static struct omap_hwmod dra7xx_gpio1_hwmod = {
1126         .name           = "gpio1",
1127         .class          = &dra7xx_gpio_hwmod_class,
1128         .clkdm_name     = "wkupaon_clkdm",
1129         .main_clk       = "wkupaon_iclk_mux",
1130         .prcm = {
1131                 .omap4 = {
1132                         .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
1133                         .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
1134                         .modulemode   = MODULEMODE_HWCTRL,
1135                 },
1136         },
1137         .opt_clks       = gpio1_opt_clks,
1138         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1139         .dev_attr       = &gpio_dev_attr,
1140 };
1142 /* gpio2 */
1143 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1144         { .role = "dbclk", .clk = "gpio2_dbclk" },
1145 };
1147 static struct omap_hwmod dra7xx_gpio2_hwmod = {
1148         .name           = "gpio2",
1149         .class          = &dra7xx_gpio_hwmod_class,
1150         .clkdm_name     = "l4per_clkdm",
1151         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1152         .main_clk       = "l3_iclk_div",
1153         .prcm = {
1154                 .omap4 = {
1155                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1156                         .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1157                         .modulemode   = MODULEMODE_HWCTRL,
1158                 },
1159         },
1160         .opt_clks       = gpio2_opt_clks,
1161         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1162         .dev_attr       = &gpio_dev_attr,
1163 };
1165 /* gpio3 */
1166 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1167         { .role = "dbclk", .clk = "gpio3_dbclk" },
1168 };
1170 static struct omap_hwmod dra7xx_gpio3_hwmod = {
1171         .name           = "gpio3",
1172         .class          = &dra7xx_gpio_hwmod_class,
1173         .clkdm_name     = "l4per_clkdm",
1174         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1175         .main_clk       = "l3_iclk_div",
1176         .prcm = {
1177                 .omap4 = {
1178                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1179                         .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1180                         .modulemode   = MODULEMODE_HWCTRL,
1181                 },
1182         },
1183         .opt_clks       = gpio3_opt_clks,
1184         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1185         .dev_attr       = &gpio_dev_attr,
1186 };
1188 /* gpio4 */
1189 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1190         { .role = "dbclk", .clk = "gpio4_dbclk" },
1191 };
1193 static struct omap_hwmod dra7xx_gpio4_hwmod = {
1194         .name           = "gpio4",
1195         .class          = &dra7xx_gpio_hwmod_class,
1196         .clkdm_name     = "l4per_clkdm",
1197         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1198         .main_clk       = "l3_iclk_div",
1199         .prcm = {
1200                 .omap4 = {
1201                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1202                         .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1203                         .modulemode   = MODULEMODE_HWCTRL,
1204                 },
1205         },
1206         .opt_clks       = gpio4_opt_clks,
1207         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1208         .dev_attr       = &gpio_dev_attr,
1209 };
1211 /* gpio5 */
1212 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1213         { .role = "dbclk", .clk = "gpio5_dbclk" },
1214 };
1216 static struct omap_hwmod dra7xx_gpio5_hwmod = {
1217         .name           = "gpio5",
1218         .class          = &dra7xx_gpio_hwmod_class,
1219         .clkdm_name     = "l4per_clkdm",
1220         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1221         .main_clk       = "l3_iclk_div",
1222         .prcm = {
1223                 .omap4 = {
1224                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1225                         .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1226                         .modulemode   = MODULEMODE_HWCTRL,
1227                 },
1228         },
1229         .opt_clks       = gpio5_opt_clks,
1230         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1231         .dev_attr       = &gpio_dev_attr,
1232 };
1234 /* gpio6 */
1235 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1236         { .role = "dbclk", .clk = "gpio6_dbclk" },
1237 };
1239 static struct omap_hwmod dra7xx_gpio6_hwmod = {
1240         .name           = "gpio6",
1241         .class          = &dra7xx_gpio_hwmod_class,
1242         .clkdm_name     = "l4per_clkdm",
1243         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1244         .main_clk       = "l3_iclk_div",
1245         .prcm = {
1246                 .omap4 = {
1247                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1248                         .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1249                         .modulemode   = MODULEMODE_HWCTRL,
1250                 },
1251         },
1252         .opt_clks       = gpio6_opt_clks,
1253         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1254         .dev_attr       = &gpio_dev_attr,
1255 };
1257 /* gpio7 */
1258 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
1259         { .role = "dbclk", .clk = "gpio7_dbclk" },
1260 };
1262 static struct omap_hwmod dra7xx_gpio7_hwmod = {
1263         .name           = "gpio7",
1264         .class          = &dra7xx_gpio_hwmod_class,
1265         .clkdm_name     = "l4per_clkdm",
1266         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1267         .main_clk       = "l3_iclk_div",
1268         .prcm = {
1269                 .omap4 = {
1270                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
1271                         .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
1272                         .modulemode   = MODULEMODE_HWCTRL,
1273                 },
1274         },
1275         .opt_clks       = gpio7_opt_clks,
1276         .opt_clks_cnt   = ARRAY_SIZE(gpio7_opt_clks),
1277         .dev_attr       = &gpio_dev_attr,
1278 };
1280 /* gpio8 */
1281 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
1282         { .role = "dbclk", .clk = "gpio8_dbclk" },
1283 };
1285 static struct omap_hwmod dra7xx_gpio8_hwmod = {
1286         .name           = "gpio8",
1287         .class          = &dra7xx_gpio_hwmod_class,
1288         .clkdm_name     = "l4per_clkdm",
1289         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1290         .main_clk       = "l3_iclk_div",
1291         .prcm = {
1292                 .omap4 = {
1293                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
1294                         .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
1295                         .modulemode   = MODULEMODE_HWCTRL,
1296                 },
1297         },
1298         .opt_clks       = gpio8_opt_clks,
1299         .opt_clks_cnt   = ARRAY_SIZE(gpio8_opt_clks),
1300         .dev_attr       = &gpio_dev_attr,
1301 };
1303 /*
1304  * 'gpmc' class
1305  *
1306  */
1308 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
1309         .rev_offs       = 0x0000,
1310         .sysc_offs      = 0x0010,
1311         .syss_offs      = 0x0014,
1312         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1313                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1314         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
1315         .sysc_fields    = &omap_hwmod_sysc_type1,
1316 };
1318 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
1319         .name   = "gpmc",
1320         .sysc   = &dra7xx_gpmc_sysc,
1321 };
1323 /* gpmc */
1325 static struct omap_hwmod dra7xx_gpmc_hwmod = {
1326         .name           = "gpmc",
1327         .class          = &dra7xx_gpmc_hwmod_class,
1328         .clkdm_name     = "l3main1_clkdm",
1329         .main_clk       = "l3_iclk_div",
1330         .prcm = {
1331                 .omap4 = {
1332                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
1333                         .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
1334                         .modulemode   = MODULEMODE_HWCTRL,
1335                 },
1336         },
1337 };
1339 /*
1340  * 'gpu' class
1341  * 2d/3d graphics accelerator
1342  */
1344 static struct omap_hwmod_class_sysconfig dra7xx_gpu_sysc = {
1345         .rev_offs       = 0x0000,
1346         .sysc_offs      = 0x0010,
1347         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1348         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1349                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1350                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1351         .sysc_fields    = &omap_hwmod_sysc_type2,
1352 };
1354 static struct omap_hwmod_class dra7xx_gpu_hwmod_class = {
1355         .name   = "gpu",
1356         .sysc   = &dra7xx_gpu_sysc,
1357 };
1359 static struct omap_hwmod dra7xx_gpu_hwmod = {
1360         .name           = "gpu",
1361         .class          = &dra7xx_gpu_hwmod_class,
1362         .clkdm_name     = "gpu_clkdm",
1363         .main_clk       = "gpu_core_gclk_mux",
1364         .prcm = {
1365                 .omap4 = {
1366                         .clkctrl_offs = DRA7XX_CM_GPU_GPU_CLKCTRL_OFFSET,
1367                         .context_offs = DRA7XX_RM_GPU_GPU_CONTEXT_OFFSET,
1368                         .modulemode   = MODULEMODE_SWCTRL,
1369                 },
1370         },
1371 };
1373 /*
1374  * 'hdq1w' class
1375  *
1376  */
1378 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
1379         .rev_offs       = 0x0000,
1380         .sysc_offs      = 0x0014,
1381         .syss_offs      = 0x0018,
1382         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1383                            SYSS_HAS_RESET_STATUS),
1384         .sysc_fields    = &omap_hwmod_sysc_type1,
1385 };
1387 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
1388         .name   = "hdq1w",
1389         .sysc   = &dra7xx_hdq1w_sysc,
1390 };
1392 /* hdq1w */
1394 static struct omap_hwmod dra7xx_hdq1w_hwmod = {
1395         .name           = "hdq1w",
1396         .class          = &dra7xx_hdq1w_hwmod_class,
1397         .clkdm_name     = "l4per_clkdm",
1398         .flags          = HWMOD_INIT_NO_RESET,
1399         .main_clk       = "func_12m_fclk",
1400         .prcm = {
1401                 .omap4 = {
1402                         .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1403                         .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1404                         .modulemode   = MODULEMODE_SWCTRL,
1405                 },
1406         },
1407 };
1409 /*
1410  * 'i2c' class
1411  *
1412  */
1414 static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
1415         .sysc_offs      = 0x0010,
1416         .syss_offs      = 0x0090,
1417         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1418                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1419                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1420         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1421                            SIDLE_SMART_WKUP),
1422         .clockact       = CLOCKACT_TEST_ICLK,
1423         .sysc_fields    = &omap_hwmod_sysc_type1,
1424 };
1426 static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
1427         .name   = "i2c",
1428         .sysc   = &dra7xx_i2c_sysc,
1429         .reset  = &omap_i2c_reset,
1430         .rev    = OMAP_I2C_IP_VERSION_2,
1431 };
1433 /* i2c dev_attr */
1434 static struct omap_i2c_dev_attr i2c_dev_attr = {
1435         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1436 };
1438 /* i2c1 */
1439 static struct omap_hwmod dra7xx_i2c1_hwmod = {
1440         .name           = "i2c1",
1441         .class          = &dra7xx_i2c_hwmod_class,
1442         .clkdm_name     = "l4per_clkdm",
1443         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1444         .main_clk       = "func_96m_fclk",
1445         .prcm = {
1446                 .omap4 = {
1447                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1448                         .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
1449                         .modulemode   = MODULEMODE_SWCTRL,
1450                 },
1451         },
1452         .dev_attr       = &i2c_dev_attr,
1453 };
1455 /* i2c2 */
1456 static struct omap_hwmod dra7xx_i2c2_hwmod = {
1457         .name           = "i2c2",
1458         .class          = &dra7xx_i2c_hwmod_class,
1459         .clkdm_name     = "l4per_clkdm",
1460         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1461         .main_clk       = "func_96m_fclk",
1462         .prcm = {
1463                 .omap4 = {
1464                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1465                         .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
1466                         .modulemode   = MODULEMODE_SWCTRL,
1467                 },
1468         },
1469         .dev_attr       = &i2c_dev_attr,
1470 };
1472 /* i2c3 */
1473 static struct omap_hwmod dra7xx_i2c3_hwmod = {
1474         .name           = "i2c3",
1475         .class          = &dra7xx_i2c_hwmod_class,
1476         .clkdm_name     = "l4per_clkdm",
1477         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1478         .main_clk       = "func_96m_fclk",
1479         .prcm = {
1480                 .omap4 = {
1481                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1482                         .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
1483                         .modulemode   = MODULEMODE_SWCTRL,
1484                 },
1485         },
1486         .dev_attr       = &i2c_dev_attr,
1487 };
1489 /* i2c4 */
1490 static struct omap_hwmod dra7xx_i2c4_hwmod = {
1491         .name           = "i2c4",
1492         .class          = &dra7xx_i2c_hwmod_class,
1493         .clkdm_name     = "l4per_clkdm",
1494         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1495         .main_clk       = "func_96m_fclk",
1496         .prcm = {
1497                 .omap4 = {
1498                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1499                         .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
1500                         .modulemode   = MODULEMODE_SWCTRL,
1501                 },
1502         },
1503         .dev_attr       = &i2c_dev_attr,
1504 };
1506 /* i2c5 */
1507 static struct omap_hwmod dra7xx_i2c5_hwmod = {
1508         .name           = "i2c5",
1509         .class          = &dra7xx_i2c_hwmod_class,
1510         .clkdm_name     = "ipu_clkdm",
1511         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1512         .main_clk       = "func_96m_fclk",
1513         .prcm = {
1514                 .omap4 = {
1515                         .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
1516                         .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
1517                         .modulemode   = MODULEMODE_SWCTRL,
1518                 },
1519         },
1520         .dev_attr       = &i2c_dev_attr,
1521 };
1523 /*
1524  * 'ipu' class
1525  * imaging processor unit
1526  */
1528 static struct omap_hwmod_class dra7xx_ipu_hwmod_class = {
1529         .name   = "ipu",
1530 };
1532 static struct omap_hwmod_rst_info dra7xx_ipu_resets[] = {
1533         { .name = "cpu0", .rst_shift = 0 },
1534         { .name = "cpu1", .rst_shift = 1 },
1535 };
1537 /* ipu1 processor */
1538 static struct omap_hwmod dra7xx_ipu1_hwmod = {
1539         .name           = "ipu1",
1540         .class          = &dra7xx_ipu_hwmod_class,
1541         .clkdm_name     = "ipu1_clkdm",
1542         .rst_lines      = dra7xx_ipu_resets,
1543         .rst_lines_cnt  = ARRAY_SIZE(dra7xx_ipu_resets),
1544         .main_clk       = "ipu1_gfclk_mux",
1545         .prcm = {
1546                 .omap4 = {
1547                         .clkctrl_offs = DRA7XX_CM_IPU1_IPU1_CLKCTRL_OFFSET,
1548                         .rstctrl_offs = DRA7XX_RM_IPU1_RSTCTRL_OFFSET,
1549                         .context_offs = DRA7XX_RM_IPU1_IPU1_CONTEXT_OFFSET,
1550                 },
1551         },
1552 };
1554 /* ipu2 processor */
1555 static struct omap_hwmod dra7xx_ipu2_hwmod = {
1556         .name           = "ipu2",
1557         .class          = &dra7xx_ipu_hwmod_class,
1558         .clkdm_name     = "ipu2_clkdm",
1559         .rst_lines      = dra7xx_ipu_resets,
1560         .rst_lines_cnt  = ARRAY_SIZE(dra7xx_ipu_resets),
1561         .main_clk       = "dpll_core_h22x2_ck",
1562         .prcm = {
1563                 .omap4 = {
1564                         .clkctrl_offs = DRA7XX_CM_IPU2_IPU2_CLKCTRL_OFFSET,
1565                         .rstctrl_offs = DRA7XX_RM_IPU2_RSTCTRL_OFFSET,
1566                         .context_offs = DRA7XX_RM_IPU2_IPU2_CONTEXT_OFFSET,
1567                 },
1568         },
1569 };
1571 /*
1572  * 'mailbox' class
1573  *
1574  */
1576 static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
1577         .rev_offs       = 0x0000,
1578         .sysc_offs      = 0x0010,
1579         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1580                            SYSC_HAS_SOFTRESET),
1581         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1582         .sysc_fields    = &omap_hwmod_sysc_type2,
1583 };
1585 static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
1586         .name   = "mailbox",
1587         .sysc   = &dra7xx_mailbox_sysc,
1588 };
1590 /* mailbox1 */
1591 static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1592         .name           = "mailbox1",
1593         .class          = &dra7xx_mailbox_hwmod_class,
1594         .clkdm_name     = "l4cfg_clkdm",
1595         .prcm = {
1596                 .omap4 = {
1597                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1598                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1599                 },
1600         },
1601 };
1603 /* mailbox2 */
1604 static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1605         .name           = "mailbox2",
1606         .class          = &dra7xx_mailbox_hwmod_class,
1607         .clkdm_name     = "l4cfg_clkdm",
1608         .prcm = {
1609                 .omap4 = {
1610                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1611                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1612                 },
1613         },
1614 };
1616 /* mailbox3 */
1617 static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1618         .name           = "mailbox3",
1619         .class          = &dra7xx_mailbox_hwmod_class,
1620         .clkdm_name     = "l4cfg_clkdm",
1621         .prcm = {
1622                 .omap4 = {
1623                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1624                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1625                 },
1626         },
1627 };
1629 /* mailbox4 */
1630 static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1631         .name           = "mailbox4",
1632         .class          = &dra7xx_mailbox_hwmod_class,
1633         .clkdm_name     = "l4cfg_clkdm",
1634         .prcm = {
1635                 .omap4 = {
1636                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1637                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1638                 },
1639         },
1640 };
1642 /* mailbox5 */
1643 static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1644         .name           = "mailbox5",
1645         .class          = &dra7xx_mailbox_hwmod_class,
1646         .clkdm_name     = "l4cfg_clkdm",
1647         .prcm = {
1648                 .omap4 = {
1649                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1650                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1651                 },
1652         },
1653 };
1655 /* mailbox6 */
1656 static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1657         .name           = "mailbox6",
1658         .class          = &dra7xx_mailbox_hwmod_class,
1659         .clkdm_name     = "l4cfg_clkdm",
1660         .prcm = {
1661                 .omap4 = {
1662                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1663                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1664                 },
1665         },
1666 };
1668 /* mailbox7 */
1669 static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1670         .name           = "mailbox7",
1671         .class          = &dra7xx_mailbox_hwmod_class,
1672         .clkdm_name     = "l4cfg_clkdm",
1673         .prcm = {
1674                 .omap4 = {
1675                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1676                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1677                 },
1678         },
1679 };
1681 /* mailbox8 */
1682 static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1683         .name           = "mailbox8",
1684         .class          = &dra7xx_mailbox_hwmod_class,
1685         .clkdm_name     = "l4cfg_clkdm",
1686         .prcm = {
1687                 .omap4 = {
1688                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1689                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1690                 },
1691         },
1692 };
1694 /* mailbox9 */
1695 static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1696         .name           = "mailbox9",
1697         .class          = &dra7xx_mailbox_hwmod_class,
1698         .clkdm_name     = "l4cfg_clkdm",
1699         .prcm = {
1700                 .omap4 = {
1701                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1702                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1703                 },
1704         },
1705 };
1707 /* mailbox10 */
1708 static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1709         .name           = "mailbox10",
1710         .class          = &dra7xx_mailbox_hwmod_class,
1711         .clkdm_name     = "l4cfg_clkdm",
1712         .prcm = {
1713                 .omap4 = {
1714                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1715                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1716                 },
1717         },
1718 };
1720 /* mailbox11 */
1721 static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1722         .name           = "mailbox11",
1723         .class          = &dra7xx_mailbox_hwmod_class,
1724         .clkdm_name     = "l4cfg_clkdm",
1725         .prcm = {
1726                 .omap4 = {
1727                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1728                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1729                 },
1730         },
1731 };
1733 /* mailbox12 */
1734 static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1735         .name           = "mailbox12",
1736         .class          = &dra7xx_mailbox_hwmod_class,
1737         .clkdm_name     = "l4cfg_clkdm",
1738         .prcm = {
1739                 .omap4 = {
1740                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1741                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1742                 },
1743         },
1744 };
1746 /* mailbox13 */
1747 static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1748         .name           = "mailbox13",
1749         .class          = &dra7xx_mailbox_hwmod_class,
1750         .clkdm_name     = "l4cfg_clkdm",
1751         .prcm = {
1752                 .omap4 = {
1753                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1754                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1755                 },
1756         },
1757 };
1759 /*
1760  * 'mcspi' class
1761  *
1762  */
1764 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1765         .rev_offs       = 0x0000,
1766         .sysc_offs      = 0x0010,
1767         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1768                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1769         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1770                            SIDLE_SMART_WKUP),
1771         .sysc_fields    = &omap_hwmod_sysc_type2,
1772 };
1774 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1775         .name   = "mcspi",
1776         .sysc   = &dra7xx_mcspi_sysc,
1777         .rev    = OMAP4_MCSPI_REV,
1778 };
1780 /* mcspi1 */
1781 /* mcspi1 dev_attr */
1782 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1783         .num_chipselect = 4,
1784 };
1786 static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1787         .name           = "mcspi1",
1788         .class          = &dra7xx_mcspi_hwmod_class,
1789         .clkdm_name     = "l4per_clkdm",
1790         .main_clk       = "func_48m_fclk",
1791         .prcm = {
1792                 .omap4 = {
1793                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1794                         .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1795                         .modulemode   = MODULEMODE_SWCTRL,
1796                 },
1797         },
1798         .dev_attr       = &mcspi1_dev_attr,
1799 };
1801 /* mcspi2 */
1802 /* mcspi2 dev_attr */
1803 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1804         .num_chipselect = 2,
1805 };
1807 static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1808         .name           = "mcspi2",
1809         .class          = &dra7xx_mcspi_hwmod_class,
1810         .clkdm_name     = "l4per_clkdm",
1811         .main_clk       = "func_48m_fclk",
1812         .prcm = {
1813                 .omap4 = {
1814                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1815                         .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1816                         .modulemode   = MODULEMODE_SWCTRL,
1817                 },
1818         },
1819         .dev_attr       = &mcspi2_dev_attr,
1820 };
1822 /* mcspi3 */
1823 /* mcspi3 dev_attr */
1824 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1825         .num_chipselect = 2,
1826 };
1828 static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1829         .name           = "mcspi3",
1830         .class          = &dra7xx_mcspi_hwmod_class,
1831         .clkdm_name     = "l4per_clkdm",
1832         .main_clk       = "func_48m_fclk",
1833         .prcm = {
1834                 .omap4 = {
1835                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1836                         .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1837                         .modulemode   = MODULEMODE_SWCTRL,
1838                 },
1839         },
1840         .dev_attr       = &mcspi3_dev_attr,
1841 };
1843 /* mcspi4 */
1844 /* mcspi4 dev_attr */
1845 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1846         .num_chipselect = 1,
1847 };
1849 static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1850         .name           = "mcspi4",
1851         .class          = &dra7xx_mcspi_hwmod_class,
1852         .clkdm_name     = "l4per_clkdm",
1853         .main_clk       = "func_48m_fclk",
1854         .prcm = {
1855                 .omap4 = {
1856                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1857                         .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1858                         .modulemode   = MODULEMODE_SWCTRL,
1859                 },
1860         },
1861         .dev_attr       = &mcspi4_dev_attr,
1862 };
1864 /*
1865  * 'mcasp' class
1866  *
1867  */
1868 static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc = {
1869         .sysc_offs      = 0x0004,
1870         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1871         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1872         .sysc_fields    = &omap_hwmod_sysc_type3,
1873 };
1875 static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
1876         .name   = "mcasp",
1877         .sysc   = &dra7xx_mcasp_sysc,
1878 };
1880 /* mcasp2 */
1881 static struct omap_hwmod dra7xx_mcasp2_hwmod = {
1882         .name           = "mcasp2",
1883         .class          = &dra7xx_mcasp_hwmod_class,
1884         .clkdm_name     = "l4per2_clkdm",
1885         .main_clk       = "mcasp2_ahclkx_mux",
1886         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1887         .prcm = {
1888                 .omap4 = {
1889                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,
1890                         .context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
1891                         .modulemode   = MODULEMODE_SWCTRL,
1892                 },
1893         },
1894 };
1896 /* mcasp3 */
1897 static struct omap_hwmod dra7xx_mcasp3_hwmod = {
1898         .name           = "mcasp3",
1899         .class          = &dra7xx_mcasp_hwmod_class,
1900         .clkdm_name     = "l4per2_clkdm",
1901         .main_clk       = "mcasp3_ahclkx_mux",
1902         .flags          = HWMOD_SWSUP_SIDLE,
1903         .prcm = {
1904                 .omap4 = {
1905                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET,
1906                         .context_offs = DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET,
1907                         .modulemode   = MODULEMODE_SWCTRL,
1908                 },
1909         },
1910 };
1912 /* mcasp6 */
1913 static struct omap_hwmod dra7xx_mcasp6_hwmod = {
1914         .name           = "mcasp6",
1915         .class          = &dra7xx_mcasp_hwmod_class,
1916         .clkdm_name     = "l4per2_clkdm",
1917         .main_clk       = "mcasp6_ahclkx_mux",
1918         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1919         .prcm = {
1920                 .omap4 = {
1921                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,
1922                         .context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
1923                         .modulemode   = MODULEMODE_SWCTRL,
1924                 },
1925         },
1926 };
1928 /* mcasp7 */
1929 static struct omap_hwmod dra7xx_mcasp7_hwmod = {
1930         .name           = "mcasp7",
1931         .class          = &dra7xx_mcasp_hwmod_class,
1932         .clkdm_name     = "l4per2_clkdm",
1933         .main_clk       = "mcasp7_ahclkx_mux",
1934         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1935         .prcm = {
1936                 .omap4 = {
1937                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET,
1938                         .context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,
1939                         .modulemode = MODULEMODE_SWCTRL,
1940                 },
1941         },
1942 };
1944 /* mcasp8 */
1945 static struct omap_hwmod dra7xx_mcasp8_hwmod = {
1946         .name           = "mcasp8",
1947         .class          = &dra7xx_mcasp_hwmod_class,
1948         .clkdm_name     = "l4per2_clkdm",
1949         .main_clk       = "mcasp8_ahclkx_mux",
1950         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1951         .prcm = {
1952                 .omap4 = {
1953                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,
1954                         .context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
1955                         .modulemode   = MODULEMODE_SWCTRL,
1956                 },
1957         },
1958 };
1960 /*
1961  * 'mmc' class
1962  *
1963  */
1965 static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1966         .rev_offs       = 0x0000,
1967         .sysc_offs      = 0x0010,
1968         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1969                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1970                            SYSC_HAS_SOFTRESET),
1971         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1972                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1973                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1974         .sysc_fields    = &omap_hwmod_sysc_type2,
1975 };
1977 static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1978         .name   = "mmc",
1979         .sysc   = &dra7xx_mmc_sysc,
1980 };
1982 /* mmc1 */
1983 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1984         { .role = "clk32k", .clk = "mmc1_clk32k" },
1985 };
1987 /* mmc1 dev_attr */
1988 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1989         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1990 };
1992 static struct omap_hwmod dra7xx_mmc1_hwmod = {
1993         .name           = "mmc1",
1994         .class          = &dra7xx_mmc_hwmod_class,
1995         .clkdm_name     = "l3init_clkdm",
1996         .main_clk       = "mmc1_fclk_div",
1997         .prcm = {
1998                 .omap4 = {
1999                         .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2000                         .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2001                         .modulemode   = MODULEMODE_SWCTRL,
2002                 },
2003         },
2004         .opt_clks       = mmc1_opt_clks,
2005         .opt_clks_cnt   = ARRAY_SIZE(mmc1_opt_clks),
2006         .dev_attr       = &mmc1_dev_attr,
2007 };
2009 /* mmc2 */
2010 static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
2011         { .role = "clk32k", .clk = "mmc2_clk32k" },
2012 };
2014 static struct omap_hwmod dra7xx_mmc2_hwmod = {
2015         .name           = "mmc2",
2016         .class          = &dra7xx_mmc_hwmod_class,
2017         .clkdm_name     = "l3init_clkdm",
2018         .main_clk       = "mmc2_fclk_div",
2019         .prcm = {
2020                 .omap4 = {
2021                         .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2022                         .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2023                         .modulemode   = MODULEMODE_SWCTRL,
2024                 },
2025         },
2026         .opt_clks       = mmc2_opt_clks,
2027         .opt_clks_cnt   = ARRAY_SIZE(mmc2_opt_clks),
2028 };
2030 /* mmc3 */
2031 static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
2032         { .role = "clk32k", .clk = "mmc3_clk32k" },
2033 };
2035 static struct omap_hwmod dra7xx_mmc3_hwmod = {
2036         .name           = "mmc3",
2037         .class          = &dra7xx_mmc_hwmod_class,
2038         .clkdm_name     = "l4per_clkdm",
2039         .main_clk       = "mmc3_gfclk_div",
2040         .prcm = {
2041                 .omap4 = {
2042                         .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
2043                         .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
2044                         .modulemode   = MODULEMODE_SWCTRL,
2045                 },
2046         },
2047         .opt_clks       = mmc3_opt_clks,
2048         .opt_clks_cnt   = ARRAY_SIZE(mmc3_opt_clks),
2049 };
2051 /* mmc4 */
2052 static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
2053         { .role = "clk32k", .clk = "mmc4_clk32k" },
2054 };
2056 static struct omap_hwmod dra7xx_mmc4_hwmod = {
2057         .name           = "mmc4",
2058         .class          = &dra7xx_mmc_hwmod_class,
2059         .clkdm_name     = "l4per_clkdm",
2060         .main_clk       = "mmc4_gfclk_div",
2061         .prcm = {
2062                 .omap4 = {
2063                         .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
2064                         .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
2065                         .modulemode   = MODULEMODE_SWCTRL,
2066                 },
2067         },
2068         .opt_clks       = mmc4_opt_clks,
2069         .opt_clks_cnt   = ARRAY_SIZE(mmc4_opt_clks),
2070 };
2072 /*
2073  * 'mmu' class
2074  * The memory management unit performs virtual to physical address translation
2075  * for its requestors.
2076  */
2078 static struct omap_hwmod_class_sysconfig dra7xx_mmu_sysc = {
2079         .rev_offs       = 0x0000,
2080         .sysc_offs      = 0x0010,
2081         .syss_offs      = 0x0014,
2082         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2083                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2084                            SYSS_HAS_RESET_STATUS),
2085         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2086         .sysc_fields    = &omap_hwmod_sysc_type1,
2087 };
2089 static struct omap_hwmod_class dra7xx_mmu_hwmod_class = {
2090         .name = "mmu",
2091         .sysc = &dra7xx_mmu_sysc,
2092 };
2094 /* DSP MMUs */
2095 static struct omap_hwmod_rst_info dra7xx_mmu_dsp_resets[] = {
2096         { .name = "mmu_cache", .rst_shift = 1 },
2097 };
2099 /* mmu0 - dsp1 */
2100 static struct omap_hwmod dra7xx_mmu0_dsp1_hwmod = {
2101         .name           = "mmu0_dsp1",
2102         .class          = &dra7xx_mmu_hwmod_class,
2103         .clkdm_name     = "dsp1_clkdm",
2104         .rst_lines      = dra7xx_mmu_dsp_resets,
2105         .rst_lines_cnt  = ARRAY_SIZE(dra7xx_mmu_dsp_resets),
2106         .main_clk       = "dpll_dsp_m2_ck",
2107         .prcm = {
2108                 .omap4 = {
2109                         .clkctrl_offs = DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET,
2110                         .rstctrl_offs = DRA7XX_RM_DSP1_RSTCTRL_OFFSET,
2111                         .context_offs = DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET,
2112                         .modulemode   = MODULEMODE_HWCTRL,
2113                 },
2114         },
2115 };
2117 /* mmu1 - dsp1 */
2118 static struct omap_hwmod dra7xx_mmu1_dsp1_hwmod = {
2119         .name           = "mmu1_dsp1",
2120         .class          = &dra7xx_mmu_hwmod_class,
2121         .clkdm_name     = "dsp1_clkdm",
2122         .rst_lines      = dra7xx_mmu_dsp_resets,
2123         .rst_lines_cnt  = ARRAY_SIZE(dra7xx_mmu_dsp_resets),
2124         .main_clk       = "dpll_dsp_m2_ck",
2125         .prcm = {
2126                 .omap4 = {
2127                         .clkctrl_offs = DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET,
2128                         .rstctrl_offs = DRA7XX_RM_DSP1_RSTCTRL_OFFSET,
2129                         .context_offs = DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET,
2130                         .modulemode   = MODULEMODE_HWCTRL,
2131                 },
2132         },
2133 };
2135 /* mmu0 - dsp2 */
2136 static struct omap_hwmod dra7xx_mmu0_dsp2_hwmod = {
2137         .name           = "mmu0_dsp2",
2138         .class          = &dra7xx_mmu_hwmod_class,
2139         .clkdm_name     = "dsp2_clkdm",
2140         .rst_lines      = dra7xx_mmu_dsp_resets,
2141         .rst_lines_cnt  = ARRAY_SIZE(dra7xx_mmu_dsp_resets),
2142         .main_clk       = "dpll_dsp_m2_ck",
2143         .prcm = {
2144                 .omap4 = {
2145                         .clkctrl_offs = DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET,
2146                         .rstctrl_offs = DRA7XX_RM_DSP2_RSTCTRL_OFFSET,
2147                         .context_offs = DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET,
2148                         .modulemode   = MODULEMODE_HWCTRL,
2149                 },
2150         },
2151 };
2153 /* mmu1 - dsp2 */
2154 static struct omap_hwmod dra7xx_mmu1_dsp2_hwmod = {
2155         .name           = "mmu1_dsp2",
2156         .class          = &dra7xx_mmu_hwmod_class,
2157         .clkdm_name     = "dsp2_clkdm",
2158         .rst_lines      = dra7xx_mmu_dsp_resets,
2159         .rst_lines_cnt  = ARRAY_SIZE(dra7xx_mmu_dsp_resets),
2160         .main_clk       = "dpll_dsp_m2_ck",
2161         .prcm = {
2162                 .omap4 = {
2163                         .clkctrl_offs = DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET,
2164                         .rstctrl_offs = DRA7XX_RM_DSP2_RSTCTRL_OFFSET,
2165                         .context_offs = DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET,
2166                         .modulemode   = MODULEMODE_HWCTRL,
2167                 },
2168         },
2169 };
2171 /* IPU MMUs */
2172 static struct omap_hwmod_rst_info dra7xx_mmu_ipu_resets[] = {
2173         { .name = "mmu_cache", .rst_shift = 2 },
2174 };
2176 /* mmu ipu1 */
2177 static struct omap_hwmod dra7xx_mmu_ipu1_hwmod = {
2178         .name           = "mmu_ipu1",
2179         .class          = &dra7xx_mmu_hwmod_class,
2180         .clkdm_name     = "ipu1_clkdm",
2181         .rst_lines      = dra7xx_mmu_ipu_resets,
2182         .rst_lines_cnt  = ARRAY_SIZE(dra7xx_mmu_ipu_resets),
2183         .main_clk       = "ipu1_gfclk_mux",
2184         .prcm = {
2185                 .omap4 = {
2186                         .clkctrl_offs = DRA7XX_CM_IPU1_IPU1_CLKCTRL_OFFSET,
2187                         .rstctrl_offs = DRA7XX_RM_IPU1_RSTCTRL_OFFSET,
2188                         .context_offs = DRA7XX_RM_IPU1_IPU1_CONTEXT_OFFSET,
2189                         .modulemode   = MODULEMODE_HWCTRL,
2190                 },
2191         },
2192 };
2194 /* mmu ipu2 */
2195 static struct omap_hwmod dra7xx_mmu_ipu2_hwmod = {
2196         .name           = "mmu_ipu2",
2197         .class          = &dra7xx_mmu_hwmod_class,
2198         .clkdm_name     = "ipu2_clkdm",
2199         .rst_lines      = dra7xx_mmu_ipu_resets,
2200         .rst_lines_cnt  = ARRAY_SIZE(dra7xx_mmu_ipu_resets),
2201         .main_clk       = "dpll_core_h22x2_ck",
2202         .prcm = {
2203                 .omap4 = {
2204                         .clkctrl_offs = DRA7XX_CM_IPU2_IPU2_CLKCTRL_OFFSET,
2205                         .rstctrl_offs = DRA7XX_RM_IPU2_RSTCTRL_OFFSET,
2206                         .context_offs = DRA7XX_RM_IPU2_IPU2_CONTEXT_OFFSET,
2207                         .modulemode   = MODULEMODE_HWCTRL,
2208                 },
2209         },
2210 };
2212 /*
2213  * 'mpu' class
2214  *
2215  */
2217 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
2218         .name   = "mpu",
2219 };
2221 /* mpu */
2222 static struct omap_hwmod dra7xx_mpu_hwmod = {
2223         .name           = "mpu",
2224         .class          = &dra7xx_mpu_hwmod_class,
2225         .clkdm_name     = "mpu_clkdm",
2226         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2227         .main_clk       = "dpll_mpu_m2_ck",
2228         .prcm = {
2229                 .omap4 = {
2230                         .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
2231                         .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
2232                 },
2233         },
2234 };
2236 /*
2237  * 'ocp2scp' class
2238  *
2239  */
2241 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
2242         .rev_offs       = 0x0000,
2243         .sysc_offs      = 0x0010,
2244         .syss_offs      = 0x0014,
2245         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2246                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2247         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2248                            SIDLE_SMART_WKUP),
2249         .sysc_fields    = &omap_hwmod_sysc_type1,
2250 };
2252 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
2253         .name   = "ocp2scp",
2254         .sysc   = &dra7xx_ocp2scp_sysc,
2255 };
2257 /* ocp2scp1 */
2258 static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
2259         .name           = "ocp2scp1",
2260         .class          = &dra7xx_ocp2scp_hwmod_class,
2261         .clkdm_name     = "l3init_clkdm",
2262         .main_clk       = "l4_root_clk_div",
2263         .prcm = {
2264                 .omap4 = {
2265                         .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
2266                         .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
2267                         .modulemode   = MODULEMODE_HWCTRL,
2268                 },
2269         },
2270 };
2272 /* ocp2scp3 */
2273 static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
2274         .name           = "ocp2scp3",
2275         .class          = &dra7xx_ocp2scp_hwmod_class,
2276         .clkdm_name     = "l3init_clkdm",
2277         .main_clk       = "l4_root_clk_div",
2278         .prcm = {
2279                 .omap4 = {
2280                         .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
2281                         .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
2282                         .modulemode   = MODULEMODE_HWCTRL,
2283                 },
2284         },
2285 };
2287 /*
2288  * 'PCIE' class
2289  *
2290  */
2292 static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
2293         .name   = "pcie",
2294 };
2296 /* pcie1 */
2297 static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = {
2298         { .name = "pcie", .rst_shift = 0 },
2299 };
2301 static struct omap_hwmod dra7xx_pciess1_hwmod = {
2302         .name           = "pcie1",
2303         .class          = &dra7xx_pciess_hwmod_class,
2304         .clkdm_name     = "pcie_clkdm",
2305         .rst_lines      = dra7xx_pciess1_resets,
2306         .rst_lines_cnt  = ARRAY_SIZE(dra7xx_pciess1_resets),
2307         .main_clk       = "l4_root_clk_div",
2308         .prcm = {
2309                 .omap4 = {
2310                         .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
2311                         .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
2312                         .rstctrl_offs   = DRA7XX_RM_L3INIT_RSTCTRL_OFFSET,
2313                         .modulemode     = MODULEMODE_SWCTRL,
2314                 },
2315         },
2316 };
2318 /* pcie2 */
2319 static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = {
2320         { .name = "pcie", .rst_shift = 1 },
2321 };
2323 static struct omap_hwmod dra7xx_pciess2_hwmod = {
2324         .name           = "pcie2",
2325         .class          = &dra7xx_pciess_hwmod_class,
2326         .clkdm_name     = "pcie_clkdm",
2327         .rst_lines      = dra7xx_pciess2_resets,
2328         .rst_lines_cnt  = ARRAY_SIZE(dra7xx_pciess2_resets),
2329         .main_clk       = "l4_root_clk_div",
2330         .prcm = {
2331                 .omap4 = {
2332                         .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
2333                         .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
2334                         .rstctrl_offs = DRA7XX_RM_L3INIT_RSTCTRL_OFFSET,
2335                         .modulemode   = MODULEMODE_SWCTRL,
2336                 },
2337         },
2338 };
2340 /*
2341  * 'pru-icss' class
2342  * Programmable Real-Time Unit and Industrial Communication Subsystem
2343  */
2344 static struct omap_hwmod_class dra7xx_pruss_hwmod_class = {
2345         .name   = "pruss",
2346 };
2348 /* pru-icss1 */
2349 static struct omap_hwmod dra7xx_pruss1_hwmod = {
2350         .name           = "pruss1",
2351         .class          = &dra7xx_pruss_hwmod_class,
2352         .clkdm_name     = "l4per2_clkdm",
2353         .prcm           = {
2354                 .omap4  = {
2355                         .clkctrl_offs   = DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL_OFFSET,
2356                         .context_offs   = DRA7XX_RM_L4PER2_PRUSS1_CONTEXT_OFFSET,
2357                         .modulemode     = MODULEMODE_SWCTRL,
2358                 },
2359         },
2360 };
2362 /* pru-icss2 */
2363 static struct omap_hwmod dra7xx_pruss2_hwmod = {
2364         .name           = "pruss2",
2365         .class          = &dra7xx_pruss_hwmod_class,
2366         .clkdm_name     = "l4per2_clkdm",
2367         .prcm           = {
2368                 .omap4  = {
2369                         .clkctrl_offs   = DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL_OFFSET,
2370                         .context_offs   = DRA7XX_RM_L4PER2_PRUSS2_CONTEXT_OFFSET,
2371                         .modulemode     = MODULEMODE_SWCTRL,
2372                 },
2373         },
2374 };
2376 /*
2377  * 'qspi' class
2378  *
2379  */
2381 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
2382         .sysc_offs      = 0x0010,
2383         .sysc_flags     = SYSC_HAS_SIDLEMODE,
2384         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2385                            SIDLE_SMART_WKUP),
2386         .sysc_fields    = &omap_hwmod_sysc_type2,
2387 };
2389 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
2390         .name   = "qspi",
2391         .sysc   = &dra7xx_qspi_sysc,
2392 };
2394 /* qspi */
2395 static struct omap_hwmod dra7xx_qspi_hwmod = {
2396         .name           = "qspi",
2397         .class          = &dra7xx_qspi_hwmod_class,
2398         .clkdm_name     = "l4per2_clkdm",
2399         .main_clk       = "qspi_gfclk_div",
2400         .prcm = {
2401                 .omap4 = {
2402                         .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
2403                         .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
2404                         .modulemode   = MODULEMODE_SWCTRL,
2405                 },
2406         },
2407 };
2409 /*
2410  * 'rtcss' class
2411  *
2412  */
2413 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
2414         .sysc_offs      = 0x0078,
2415         .sysc_flags     = SYSC_HAS_SIDLEMODE,
2416         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2417                            SIDLE_SMART_WKUP),
2418         .sysc_fields    = &omap_hwmod_sysc_type3,
2419 };
2421 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
2422         .name   = "rtcss",
2423         .sysc   = &dra7xx_rtcss_sysc,
2424         .reset  = &omap_hwmod_rtc_unlock,
2425 };
2427 /* rtcss */
2428 static struct omap_hwmod dra7xx_rtcss_hwmod = {
2429         .name           = "rtcss",
2430         .class          = &dra7xx_rtcss_hwmod_class,
2431         .clkdm_name     = "rtc_clkdm",
2432         .main_clk       = "sys_32k_ck",
2433         .prcm = {
2434                 .omap4 = {
2435                         .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
2436                         .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
2437                         .modulemode   = MODULEMODE_SWCTRL,
2438                 },
2439         },
2440 };
2442 /*
2443  * 'sata' class
2444  *
2445  */
2447 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
2448         .sysc_offs      = 0x0000,
2449         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
2450         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2451                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2452                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2453         .sysc_fields    = &omap_hwmod_sysc_type2,
2454 };
2456 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
2457         .name   = "sata",
2458         .sysc   = &dra7xx_sata_sysc,
2459 };
2461 /* sata */
2463 static struct omap_hwmod dra7xx_sata_hwmod = {
2464         .name           = "sata",
2465         .class          = &dra7xx_sata_hwmod_class,
2466         .clkdm_name     = "l3init_clkdm",
2467         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2468         .main_clk       = "func_48m_fclk",
2469         .mpu_rt_idx     = 1,
2470         .prcm = {
2471                 .omap4 = {
2472                         .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
2473                         .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
2474                         .modulemode   = MODULEMODE_SWCTRL,
2475                 },
2476         },
2477 };
2479 /*
2480  * 'smartreflex' class
2481  *
2482  */
2484 /* The IP is not compliant to type1 / type2 scheme */
2485 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2486         .sidle_shift    = 24,
2487         .enwkup_shift   = 26,
2488 };
2490 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
2491         .sysc_offs      = 0x0038,
2492         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2493         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2494                            SIDLE_SMART_WKUP),
2495         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2496 };
2498 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
2499         .name   = "smartreflex",
2500         .sysc   = &dra7xx_smartreflex_sysc,
2501         .rev    = 2,
2502 };
2504 /* smartreflex_core */
2505 /* smartreflex_core dev_attr */
2506 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2507         .sensor_voltdm_name     = "core",
2508 };
2510 static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
2511         .name           = "smartreflex_core",
2512         .class          = &dra7xx_smartreflex_hwmod_class,
2513         .clkdm_name     = "coreaon_clkdm",
2514         .main_clk       = "wkupaon_iclk_mux",
2515         .prcm = {
2516                 .omap4 = {
2517                         .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
2518                         .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
2519                         .modulemode   = MODULEMODE_SWCTRL,
2520                 },
2521         },
2522         .dev_attr       = &smartreflex_core_dev_attr,
2523 };
2525 /* smartreflex_mpu */
2526 /* smartreflex_mpu dev_attr */
2527 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2528         .sensor_voltdm_name     = "mpu",
2529 };
2531 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
2532         .name           = "smartreflex_mpu",
2533         .class          = &dra7xx_smartreflex_hwmod_class,
2534         .clkdm_name     = "coreaon_clkdm",
2535         .main_clk       = "wkupaon_iclk_mux",
2536         .prcm = {
2537                 .omap4 = {
2538                         .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
2539                         .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
2540                         .modulemode   = MODULEMODE_SWCTRL,
2541                 },
2542         },
2543         .dev_attr       = &smartreflex_mpu_dev_attr,
2544 };
2546 /*
2547  * 'spinlock' class
2548  *
2549  */
2551 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
2552         .rev_offs       = 0x0000,
2553         .sysc_offs      = 0x0010,
2554         .syss_offs      = 0x0014,
2555         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2556                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2557                            SYSS_HAS_RESET_STATUS),
2558         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2559         .sysc_fields    = &omap_hwmod_sysc_type1,
2560 };
2562 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
2563         .name   = "spinlock",
2564         .sysc   = &dra7xx_spinlock_sysc,
2565 };
2567 /* spinlock */
2568 static struct omap_hwmod dra7xx_spinlock_hwmod = {
2569         .name           = "spinlock",
2570         .class          = &dra7xx_spinlock_hwmod_class,
2571         .clkdm_name     = "l4cfg_clkdm",
2572         .main_clk       = "l3_iclk_div",
2573         .prcm = {
2574                 .omap4 = {
2575                         .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
2576                         .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
2577                 },
2578         },
2579 };
2581 /*
2582  * 'timer' class
2583  *
2584  * This class contains several variants: ['timer_1ms', 'timer_secure',
2585  * 'timer']
2586  */
2588 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
2589         .rev_offs       = 0x0000,
2590         .sysc_offs      = 0x0010,
2591         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2592                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2593         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2594                            SIDLE_SMART_WKUP),
2595         .sysc_fields    = &omap_hwmod_sysc_type2,
2596 };
2598 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
2599         .name   = "timer",
2600         .sysc   = &dra7xx_timer_1ms_sysc,
2601 };
2603 static struct omap_hwmod_class_sysconfig dra7xx_timer_secure_sysc = {
2604         .rev_offs       = 0x0000,
2605         .sysc_offs      = 0x0010,
2606         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2607                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2608         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2609                            SIDLE_SMART_WKUP),
2610         .sysc_fields    = &omap_hwmod_sysc_type2,
2611 };
2613 static struct omap_hwmod_class dra7xx_timer_secure_hwmod_class = {
2614         .name   = "timer",
2615         .sysc   = &dra7xx_timer_secure_sysc,
2616 };
2618 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
2619         .rev_offs       = 0x0000,
2620         .sysc_offs      = 0x0010,
2621         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2622                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2623         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2624                            SIDLE_SMART_WKUP),
2625         .sysc_fields    = &omap_hwmod_sysc_type2,
2626 };
2628 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
2629         .name   = "timer",
2630         .sysc   = &dra7xx_timer_sysc,
2631 };
2633 /* timer1 */
2634 static struct omap_hwmod dra7xx_timer1_hwmod = {
2635         .name           = "timer1",
2636         .class          = &dra7xx_timer_1ms_hwmod_class,
2637         .clkdm_name     = "wkupaon_clkdm",
2638         .main_clk       = "timer1_gfclk_mux",
2639         .prcm = {
2640                 .omap4 = {
2641                         .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
2642                         .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
2643                         .modulemode   = MODULEMODE_SWCTRL,
2644                 },
2645         },
2646 };
2648 /* timer2 */
2649 static struct omap_hwmod dra7xx_timer2_hwmod = {
2650         .name           = "timer2",
2651         .class          = &dra7xx_timer_1ms_hwmod_class,
2652         .clkdm_name     = "l4per_clkdm",
2653         .main_clk       = "timer2_gfclk_mux",
2654         .prcm = {
2655                 .omap4 = {
2656                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
2657                         .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
2658                         .modulemode   = MODULEMODE_SWCTRL,
2659                 },
2660         },
2661 };
2663 /* timer3 */
2664 static struct omap_hwmod dra7xx_timer3_hwmod = {
2665         .name           = "timer3",
2666         .class          = &dra7xx_timer_hwmod_class,
2667         .clkdm_name     = "l4per_clkdm",
2668         .main_clk       = "timer3_gfclk_mux",
2669         .prcm = {
2670                 .omap4 = {
2671                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
2672                         .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
2673                         .modulemode   = MODULEMODE_SWCTRL,
2674                 },
2675         },
2676 };
2678 /* timer4 */
2679 static struct omap_hwmod dra7xx_timer4_hwmod = {
2680         .name           = "timer4",
2681         .class          = &dra7xx_timer_hwmod_class,
2682         .clkdm_name     = "l4per_clkdm",
2683         .main_clk       = "timer4_gfclk_mux",
2684         .prcm = {
2685                 .omap4 = {
2686                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
2687                         .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
2688                         .modulemode   = MODULEMODE_SWCTRL,
2689                 },
2690         },
2691 };
2693 /* timer5 */
2694 static struct omap_hwmod dra7xx_timer5_hwmod = {
2695         .name           = "timer5",
2696         .class          = &dra7xx_timer_hwmod_class,
2697         .clkdm_name     = "ipu_clkdm",
2698         .main_clk       = "timer5_gfclk_mux",
2699         .prcm = {
2700                 .omap4 = {
2701                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
2702                         .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
2703                         .modulemode   = MODULEMODE_SWCTRL,
2704                 },
2705         },
2706 };
2708 /* timer6 */
2709 static struct omap_hwmod dra7xx_timer6_hwmod = {
2710         .name           = "timer6",
2711         .class          = &dra7xx_timer_hwmod_class,
2712         .clkdm_name     = "ipu_clkdm",
2713         .main_clk       = "timer6_gfclk_mux",
2714         .prcm = {
2715                 .omap4 = {
2716                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
2717                         .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
2718                         .modulemode   = MODULEMODE_SWCTRL,
2719                 },
2720         },
2721 };
2723 /* timer7 */
2724 static struct omap_hwmod dra7xx_timer7_hwmod = {
2725         .name           = "timer7",
2726         .class          = &dra7xx_timer_hwmod_class,
2727         .clkdm_name     = "ipu_clkdm",
2728         .main_clk       = "timer7_gfclk_mux",
2729         .prcm = {
2730                 .omap4 = {
2731                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
2732                         .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
2733                         .modulemode   = MODULEMODE_SWCTRL,
2734                 },
2735         },
2736 };
2738 /* timer8 */
2739 static struct omap_hwmod dra7xx_timer8_hwmod = {
2740         .name           = "timer8",
2741         .class          = &dra7xx_timer_hwmod_class,
2742         .clkdm_name     = "ipu_clkdm",
2743         .main_clk       = "timer8_gfclk_mux",
2744         .prcm = {
2745                 .omap4 = {
2746                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
2747                         .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
2748                         .modulemode   = MODULEMODE_SWCTRL,
2749                 },
2750         },
2751 };
2753 /* timer9 */
2754 static struct omap_hwmod dra7xx_timer9_hwmod = {
2755         .name           = "timer9",
2756         .class          = &dra7xx_timer_hwmod_class,
2757         .clkdm_name     = "l4per_clkdm",
2758         .main_clk       = "timer9_gfclk_mux",
2759         .prcm = {
2760                 .omap4 = {
2761                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
2762                         .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
2763                         .modulemode   = MODULEMODE_SWCTRL,
2764                 },
2765         },
2766 };
2768 /* timer10 */
2769 static struct omap_hwmod dra7xx_timer10_hwmod = {
2770         .name           = "timer10",
2771         .class          = &dra7xx_timer_1ms_hwmod_class,
2772         .clkdm_name     = "l4per_clkdm",
2773         .main_clk       = "timer10_gfclk_mux",
2774         .prcm = {
2775                 .omap4 = {
2776                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
2777                         .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
2778                         .modulemode   = MODULEMODE_SWCTRL,
2779                 },
2780         },
2781 };
2783 /* timer11 */
2784 static struct omap_hwmod dra7xx_timer11_hwmod = {
2785         .name           = "timer11",
2786         .class          = &dra7xx_timer_hwmod_class,
2787         .clkdm_name     = "l4per_clkdm",
2788         .main_clk       = "timer11_gfclk_mux",
2789         .prcm = {
2790                 .omap4 = {
2791                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
2792                         .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
2793                         .modulemode   = MODULEMODE_SWCTRL,
2794                 },
2795         },
2796 };
2798 /* timer12 */
2799 static struct omap_hwmod dra7xx_timer12_hwmod = {
2800         .name           = "timer12",
2801         .class          = &dra7xx_timer_secure_hwmod_class,
2802         .clkdm_name     = "wkupaon_clkdm",
2803         .main_clk       = "secure_32k_clk_src_ck",
2804         .prcm = {
2805                 .omap4 = {
2806                         .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET,
2807                         .context_offs = DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET,
2808                 },
2809         },
2810 };
2812 /* timer13 */
2813 static struct omap_hwmod dra7xx_timer13_hwmod = {
2814         .name           = "timer13",
2815         .class          = &dra7xx_timer_hwmod_class,
2816         .clkdm_name     = "l4per3_clkdm",
2817         .main_clk       = "timer13_gfclk_mux",
2818         .prcm = {
2819                 .omap4 = {
2820                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
2821                         .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
2822                         .modulemode   = MODULEMODE_SWCTRL,
2823                 },
2824         },
2825 };
2827 /* timer14 */
2828 static struct omap_hwmod dra7xx_timer14_hwmod = {
2829         .name           = "timer14",
2830         .class          = &dra7xx_timer_hwmod_class,
2831         .clkdm_name     = "l4per3_clkdm",
2832         .main_clk       = "timer14_gfclk_mux",
2833         .prcm = {
2834                 .omap4 = {
2835                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
2836                         .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
2837                         .modulemode   = MODULEMODE_SWCTRL,
2838                 },
2839         },
2840 };
2842 /* timer15 */
2843 static struct omap_hwmod dra7xx_timer15_hwmod = {
2844         .name           = "timer15",
2845         .class          = &dra7xx_timer_hwmod_class,
2846         .clkdm_name     = "l4per3_clkdm",
2847         .main_clk       = "timer15_gfclk_mux",
2848         .prcm = {
2849                 .omap4 = {
2850                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
2851                         .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
2852                         .modulemode   = MODULEMODE_SWCTRL,
2853                 },
2854         },
2855 };
2857 /* timer16 */
2858 static struct omap_hwmod dra7xx_timer16_hwmod = {
2859         .name           = "timer16",
2860         .class          = &dra7xx_timer_hwmod_class,
2861         .clkdm_name     = "l4per3_clkdm",
2862         .main_clk       = "timer16_gfclk_mux",
2863         .prcm = {
2864                 .omap4 = {
2865                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
2866                         .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
2867                         .modulemode   = MODULEMODE_SWCTRL,
2868                 },
2869         },
2870 };
2872 /*
2873  * 'uart' class
2874  *
2875  */
2877 static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
2878         .rev_offs       = 0x0050,
2879         .sysc_offs      = 0x0054,
2880         .syss_offs      = 0x0058,
2881         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2882                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2883                            SYSS_HAS_RESET_STATUS),
2884         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2885                            SIDLE_SMART_WKUP),
2886         .sysc_fields    = &omap_hwmod_sysc_type1,
2887 };
2889 static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
2890         .name   = "uart",
2891         .sysc   = &dra7xx_uart_sysc,
2892 };
2894 /* uart1 */
2895 static struct omap_hwmod dra7xx_uart1_hwmod = {
2896         .name           = "uart1",
2897         .class          = &dra7xx_uart_hwmod_class,
2898         .clkdm_name     = "l4per_clkdm",
2899         .main_clk       = "uart1_gfclk_mux",
2900         .flags          = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
2901         .prcm = {
2902                 .omap4 = {
2903                         .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
2904                         .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
2905                         .modulemode   = MODULEMODE_SWCTRL,
2906                 },
2907         },
2908 };
2910 /* uart2 */
2911 static struct omap_hwmod dra7xx_uart2_hwmod = {
2912         .name           = "uart2",
2913         .class          = &dra7xx_uart_hwmod_class,
2914         .clkdm_name     = "l4per_clkdm",
2915         .main_clk       = "uart2_gfclk_mux",
2916         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2917         .prcm = {
2918                 .omap4 = {
2919                         .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
2920                         .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
2921                         .modulemode   = MODULEMODE_SWCTRL,
2922                 },
2923         },
2924 };
2926 /* uart3 */
2927 static struct omap_hwmod dra7xx_uart3_hwmod = {
2928         .name           = "uart3",
2929         .class          = &dra7xx_uart_hwmod_class,
2930         .clkdm_name     = "l4per_clkdm",
2931         .main_clk       = "uart3_gfclk_mux",
2932         .flags          = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART3_FLAGS,
2933         .prcm = {
2934                 .omap4 = {
2935                         .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
2936                         .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
2937                         .modulemode   = MODULEMODE_SWCTRL,
2938                 },
2939         },
2940 };
2942 /* uart4 */
2943 static struct omap_hwmod dra7xx_uart4_hwmod = {
2944         .name           = "uart4",
2945         .class          = &dra7xx_uart_hwmod_class,
2946         .clkdm_name     = "l4per_clkdm",
2947         .main_clk       = "uart4_gfclk_mux",
2948         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2949         .prcm = {
2950                 .omap4 = {
2951                         .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
2952                         .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
2953                         .modulemode   = MODULEMODE_SWCTRL,
2954                 },
2955         },
2956 };
2958 /* uart5 */
2959 static struct omap_hwmod dra7xx_uart5_hwmod = {
2960         .name           = "uart5",
2961         .class          = &dra7xx_uart_hwmod_class,
2962         .clkdm_name     = "l4per_clkdm",
2963         .main_clk       = "uart5_gfclk_mux",
2964         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2965         .prcm = {
2966                 .omap4 = {
2967                         .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
2968                         .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
2969                         .modulemode   = MODULEMODE_SWCTRL,
2970                 },
2971         },
2972 };
2974 /* uart6 */
2975 static struct omap_hwmod dra7xx_uart6_hwmod = {
2976         .name           = "uart6",
2977         .class          = &dra7xx_uart_hwmod_class,
2978         .clkdm_name     = "ipu_clkdm",
2979         .main_clk       = "uart6_gfclk_mux",
2980         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2981         .prcm = {
2982                 .omap4 = {
2983                         .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
2984                         .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
2985                         .modulemode   = MODULEMODE_SWCTRL,
2986                 },
2987         },
2988 };
2990 /* uart7 */
2991 static struct omap_hwmod dra7xx_uart7_hwmod = {
2992         .name           = "uart7",
2993         .class          = &dra7xx_uart_hwmod_class,
2994         .clkdm_name     = "l4per2_clkdm",
2995         .main_clk       = "uart7_gfclk_mux",
2996         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2997         .prcm = {
2998                 .omap4 = {
2999                         .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
3000                         .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
3001                         .modulemode   = MODULEMODE_SWCTRL,
3002                 },
3003         },
3004 };
3006 /* uart8 */
3007 static struct omap_hwmod dra7xx_uart8_hwmod = {
3008         .name           = "uart8",
3009         .class          = &dra7xx_uart_hwmod_class,
3010         .clkdm_name     = "l4per2_clkdm",
3011         .main_clk       = "uart8_gfclk_mux",
3012         .flags          = HWMOD_SWSUP_SIDLE_ACT,
3013         .prcm = {
3014                 .omap4 = {
3015                         .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
3016                         .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
3017                         .modulemode   = MODULEMODE_SWCTRL,
3018                 },
3019         },
3020 };
3022 /* uart9 */
3023 static struct omap_hwmod dra7xx_uart9_hwmod = {
3024         .name           = "uart9",
3025         .class          = &dra7xx_uart_hwmod_class,
3026         .clkdm_name     = "l4per2_clkdm",
3027         .main_clk       = "uart9_gfclk_mux",
3028         .flags          = HWMOD_SWSUP_SIDLE_ACT,
3029         .prcm = {
3030                 .omap4 = {
3031                         .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
3032                         .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
3033                         .modulemode   = MODULEMODE_SWCTRL,