1 /*
2 * Hardware modules present on the DRA7xx chips
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley
7 * Benoit Cousson
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
20 #include <linux/io.h>
21 #include <linux/platform_data/gpio-omap.h>
22 #include <linux/power/smartreflex.h>
23 #include <linux/i2c-omap.h>
25 #include <linux/omap-dma.h>
26 #include <linux/platform_data/spi-omap2-mcspi.h>
27 #include <linux/platform_data/asoc-ti-mcbsp.h>
28 #include <plat/dmtimer.h>
30 #include "omap_hwmod.h"
31 #include "omap_hwmod_common_data.h"
32 #include "cm1_7xx.h"
33 #include "cm2_7xx.h"
34 #include "prm7xx.h"
35 #include "i2c.h"
36 #include "mmc.h"
37 #include "wd_timer.h"
38 #include "soc.h"
40 /* Base offset for all DRA7XX interrupts external to MPUSS */
41 #define DRA7XX_IRQ_GIC_START 32
43 /* Base offset for all DRA7XX dma requests */
44 #define DRA7XX_DMA_REQ_START 1
47 /*
48 * IP blocks
49 */
51 /*
52 * 'l3' class
53 * instance(s): l3_instr, l3_main_1, l3_main_2
54 */
55 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
56 .name = "l3",
57 };
59 /* l3_instr */
60 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
61 .name = "l3_instr",
62 .class = &dra7xx_l3_hwmod_class,
63 .clkdm_name = "l3instr_clkdm",
64 .prcm = {
65 .omap4 = {
66 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
67 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
68 .modulemode = MODULEMODE_HWCTRL,
69 },
70 },
71 };
73 /* l3_main_1 */
74 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
75 .name = "l3_main_1",
76 .class = &dra7xx_l3_hwmod_class,
77 .clkdm_name = "l3main1_clkdm",
78 .prcm = {
79 .omap4 = {
80 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
81 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
82 },
83 },
84 };
86 /* l3_main_2 */
87 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
88 .name = "l3_main_2",
89 .class = &dra7xx_l3_hwmod_class,
90 .clkdm_name = "l3instr_clkdm",
91 .prcm = {
92 .omap4 = {
93 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
94 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
95 .modulemode = MODULEMODE_HWCTRL,
96 },
97 },
98 };
100 /*
101 * 'l4' class
102 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
103 */
104 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
105 .name = "l4",
106 };
108 /* l4_cfg */
109 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
110 .name = "l4_cfg",
111 .class = &dra7xx_l4_hwmod_class,
112 .clkdm_name = "l4cfg_clkdm",
113 .prcm = {
114 .omap4 = {
115 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
116 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
117 },
118 },
119 };
121 /* l4_per1 */
122 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
123 .name = "l4_per1",
124 .class = &dra7xx_l4_hwmod_class,
125 .clkdm_name = "l4per_clkdm",
126 .prcm = {
127 .omap4 = {
128 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
129 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
130 },
131 },
132 };
134 /* l4_per2 */
135 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
136 .name = "l4_per2",
137 .class = &dra7xx_l4_hwmod_class,
138 .clkdm_name = "l4per2_clkdm",
139 .prcm = {
140 .omap4 = {
141 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
142 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
143 },
144 },
145 };
147 /* l4_per3 */
148 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
149 .name = "l4_per3",
150 .class = &dra7xx_l4_hwmod_class,
151 .clkdm_name = "l4per3_clkdm",
152 .prcm = {
153 .omap4 = {
154 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
155 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
156 },
157 },
158 };
160 /* l4_wkup */
161 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
162 .name = "l4_wkup",
163 .class = &dra7xx_l4_hwmod_class,
164 .clkdm_name = "wkupaon_clkdm",
165 .prcm = {
166 .omap4 = {
167 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
168 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
169 },
170 },
171 };
173 /*
174 * 'atl' class
175 *
176 */
178 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
179 .name = "atl",
180 };
182 /* atl */
183 static struct omap_hwmod dra7xx_atl_hwmod = {
184 .name = "atl",
185 .class = &dra7xx_atl_hwmod_class,
186 .clkdm_name = "atl_clkdm",
187 .main_clk = "atl_gfclk_mux",
188 .lockdep_class = HWMOD_LOCKDEP_SUBCLASS_CLASS1,
189 .prcm = {
190 .omap4 = {
191 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
192 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
193 .modulemode = MODULEMODE_SWCTRL,
194 },
195 },
196 };
198 /*
199 * 'bb2d' class
200 *
201 */
203 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
204 .name = "bb2d",
205 };
207 /* bb2d */
208 static struct omap_hwmod dra7xx_bb2d_hwmod = {
209 .name = "bb2d",
210 .class = &dra7xx_bb2d_hwmod_class,
211 .clkdm_name = "dss_clkdm",
212 .main_clk = "dpll_core_h24x2_ck",
213 .prcm = {
214 .omap4 = {
215 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
216 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
217 .modulemode = MODULEMODE_SWCTRL,
218 },
219 },
220 };
222 /*
223 * 'counter' class
224 *
225 */
227 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
228 .rev_offs = 0x0000,
229 .sysc_offs = 0x0010,
230 .sysc_flags = SYSC_HAS_SIDLEMODE,
231 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
232 SIDLE_SMART_WKUP),
233 .sysc_fields = &omap_hwmod_sysc_type1,
234 };
236 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
237 .name = "counter",
238 .sysc = &dra7xx_counter_sysc,
239 };
241 /* counter_32k */
242 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
243 .name = "counter_32k",
244 .class = &dra7xx_counter_hwmod_class,
245 .clkdm_name = "wkupaon_clkdm",
246 .flags = HWMOD_SWSUP_SIDLE,
247 .main_clk = "wkupaon_iclk_mux",
248 .prcm = {
249 .omap4 = {
250 .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
251 .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
252 },
253 },
254 };
256 /*
257 * 'ctrl_module' class
258 *
259 */
261 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
262 .name = "ctrl_module",
263 };
265 /* ctrl_module_wkup */
266 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
267 .name = "ctrl_module_wkup",
268 .class = &dra7xx_ctrl_module_hwmod_class,
269 .clkdm_name = "wkupaon_clkdm",
270 .prcm = {
271 .omap4 = {
272 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
273 },
274 },
275 };
277 /*
278 * 'dcan' class
279 *
280 */
282 static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
283 .name = "dcan",
284 };
286 /* dcan1 */
287 static struct omap_hwmod dra7xx_dcan1_hwmod = {
288 .name = "dcan1",
289 .class = &dra7xx_dcan_hwmod_class,
290 .clkdm_name = "wkupaon_clkdm",
291 .main_clk = "dcan1_sys_clk_mux",
292 .prcm = {
293 .omap4 = {
294 .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
295 .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
296 .modulemode = MODULEMODE_SWCTRL,
297 },
298 },
299 };
301 /* dcan2 */
302 static struct omap_hwmod dra7xx_dcan2_hwmod = {
303 .name = "dcan2",
304 .class = &dra7xx_dcan_hwmod_class,
305 .clkdm_name = "l4per2_clkdm",
306 .main_clk = "sys_clkin1",
307 .prcm = {
308 .omap4 = {
309 .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
310 .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
311 .modulemode = MODULEMODE_SWCTRL,
312 },
313 },
314 };
316 /* pwmss */
317 static struct omap_hwmod_class_sysconfig dra7xx_epwmss_sysc = {
318 .rev_offs = 0x0,
319 .sysc_offs = 0x4,
320 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_RESET_STATUS,
321 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
322 .sysc_fields = &omap_hwmod_sysc_type2,
323 };
325 struct omap_hwmod_class dra7xx_epwmss_hwmod_class = {
326 .name = "epwmss",
327 .sysc = &dra7xx_epwmss_sysc,
328 };
330 static struct omap_hwmod_class dra7xx_ecap_hwmod_class = {
331 .name = "ecap",
332 };
334 static struct omap_hwmod_class dra7xx_eqep_hwmod_class = {
335 .name = "eqep",
336 };
338 struct omap_hwmod_class dra7xx_ehrpwm_hwmod_class = {
339 .name = "ehrpwm",
340 };
342 /* epwmss0 */
343 struct omap_hwmod dra7xx_epwmss0_hwmod = {
344 .name = "epwmss0",
345 .class = &dra7xx_epwmss_hwmod_class,
346 .clkdm_name = "l4per2_clkdm",
347 .main_clk = "l4_root_clk_div",
348 .prcm = {
349 .omap4 = {
350 .modulemode = MODULEMODE_SWCTRL,
351 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET,
352 .context_offs = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET,
353 },
354 },
355 };
357 /* ecap0 */
358 struct omap_hwmod dra7xx_ecap0_hwmod = {
359 .name = "ecap0",
360 .class = &dra7xx_ecap_hwmod_class,
361 .clkdm_name = "l4per2_clkdm",
362 .main_clk = "l4_root_clk_div",
363 };
365 /* eqep0 */
366 struct omap_hwmod dra7xx_eqep0_hwmod = {
367 .name = "eqep0",
368 .class = &dra7xx_eqep_hwmod_class,
369 .clkdm_name = "l4per2_clkdm",
370 .main_clk = "l4_root_clk_div",
371 };
373 /* ehrpwm0 */
374 struct omap_hwmod dra7xx_ehrpwm0_hwmod = {
375 .name = "ehrpwm0",
376 .class = &dra7xx_ehrpwm_hwmod_class,
377 .clkdm_name = "l4per2_clkdm",
378 .main_clk = "l4_root_clk_div",
379 };
381 /* epwmss1 */
382 struct omap_hwmod dra7xx_epwmss1_hwmod = {
383 .name = "epwmss1",
384 .class = &dra7xx_epwmss_hwmod_class,
385 .clkdm_name = "l4per2_clkdm",
386 .main_clk = "l4_root_clk_div",
387 .prcm = {
388 .omap4 = {
389 .modulemode = MODULEMODE_SWCTRL,
390 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET,
391 .context_offs = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET,
392 },
393 },
394 };
396 /* ecap1 */
397 struct omap_hwmod dra7xx_ecap1_hwmod = {
398 .name = "ecap1",
399 .class = &dra7xx_ecap_hwmod_class,
400 .clkdm_name = "l4per2_clkdm",
401 .main_clk = "l4_root_clk_div",
402 };
404 /* eqep1 */
405 struct omap_hwmod dra7xx_eqep1_hwmod = {
406 .name = "eqep1",
407 .class = &dra7xx_eqep_hwmod_class,
408 .clkdm_name = "l4per2_clkdm",
409 .main_clk = "l4_root_clk_div",
410 };
412 /* ehrpwm1 */
413 struct omap_hwmod dra7xx_ehrpwm1_hwmod = {
414 .name = "ehrpwm1",
415 .class = &dra7xx_ehrpwm_hwmod_class,
416 .clkdm_name = "l4per2_clkdm",
417 .main_clk = "l4_root_clk_div",
418 };
420 /* epwmss2 */
421 struct omap_hwmod dra7xx_epwmss2_hwmod = {
422 .name = "epwmss2",
423 .class = &dra7xx_epwmss_hwmod_class,
424 .clkdm_name = "l4per2_clkdm",
425 .main_clk = "l4_root_clk_div",
426 .prcm = {
427 .omap4 = {
428 .modulemode = MODULEMODE_SWCTRL,
429 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET,
430 .context_offs = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET,
431 },
432 },
433 };
435 /* ecap2 */
436 struct omap_hwmod dra7xx_ecap2_hwmod = {
437 .name = "ecap2",
438 .class = &dra7xx_ecap_hwmod_class,
439 .clkdm_name = "l4per2_clkdm",
440 .main_clk = "l4_root_clk_div",
441 };
443 /* eqep2 */
444 struct omap_hwmod dra7xx_eqep2_hwmod = {
445 .name = "eqep2",
446 .class = &dra7xx_eqep_hwmod_class,
447 .clkdm_name = "l4per2_clkdm",
448 .main_clk = "l4_root_clk_div",
449 };
451 /* ehrpwm2 */
452 struct omap_hwmod dra7xx_ehrpwm2_hwmod = {
453 .name = "ehrpwm2",
454 .class = &dra7xx_ehrpwm_hwmod_class,
455 .clkdm_name = "l4per2_clkdm",
456 .main_clk = "l4_root_clk_div",
457 };
459 /*
460 * 'dma' class
461 *
462 */
464 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
465 .rev_offs = 0x0000,
466 .sysc_offs = 0x002c,
467 .syss_offs = 0x0028,
468 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
469 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
470 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
471 SYSS_HAS_RESET_STATUS),
472 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
473 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
474 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
475 .sysc_fields = &omap_hwmod_sysc_type1,
476 };
478 static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
479 .name = "dma",
480 .sysc = &dra7xx_dma_sysc,
481 };
483 /* dma dev_attr */
484 static struct omap_dma_dev_attr dma_dev_attr = {
485 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
486 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
487 .lch_count = 32,
488 };
490 /* dma_system */
491 static struct omap_hwmod dra7xx_dma_system_hwmod = {
492 .name = "dma_system",
493 .class = &dra7xx_dma_hwmod_class,
494 .clkdm_name = "dma_clkdm",
495 .main_clk = "l3_iclk_div",
496 .prcm = {
497 .omap4 = {
498 .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
499 .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
500 },
501 },
502 .dev_attr = &dma_dev_attr,
503 };
505 /*
506 * 'dss' class
507 *
508 */
510 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
511 .rev_offs = 0x0000,
512 .syss_offs = 0x0014,
513 .sysc_flags = SYSS_HAS_RESET_STATUS,
514 };
516 static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
517 .name = "dss",
518 .sysc = &dra7xx_dss_sysc,
519 .reset = omap_dss_reset,
520 };
522 /* dss */
523 static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
524 { .dma_req = 75 + DRA7XX_DMA_REQ_START },
525 { .dma_req = -1 }
526 };
528 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
529 { .role = "dss_clk", .clk = "dss_dss_clk" },
530 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
531 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
532 { .role = "video2_clk", .clk = "dss_video2_clk" },
533 { .role = "video1_clk", .clk = "dss_video1_clk" },
534 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
535 };
537 static struct omap_hwmod dra7xx_dss_hwmod = {
538 .name = "dss_core",
539 .class = &dra7xx_dss_hwmod_class,
540 .clkdm_name = "dss_clkdm",
541 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
542 .sdma_reqs = dra7xx_dss_sdma_reqs,
543 .main_clk = "dss_dss_clk",
544 .prcm = {
545 .omap4 = {
546 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
547 .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
548 .modulemode = MODULEMODE_SWCTRL,
549 },
550 },
551 .opt_clks = dss_opt_clks,
552 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
553 };
555 /*
556 * 'dispc' class
557 * display controller
558 */
560 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
561 .rev_offs = 0x0000,
562 .sysc_offs = 0x0010,
563 .syss_offs = 0x0014,
564 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
565 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
566 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
567 SYSS_HAS_RESET_STATUS),
568 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
569 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
570 .sysc_fields = &omap_hwmod_sysc_type1,
571 };
573 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
574 .name = "dispc",
575 .sysc = &dra7xx_dispc_sysc,
576 };
578 /* dss_dispc */
579 /* dss_dispc dev_attr */
580 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
581 .has_framedonetv_irq = 1,
582 .manager_count = 4,
583 };
585 static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
586 .name = "dss_dispc",
587 .class = &dra7xx_dispc_hwmod_class,
588 .clkdm_name = "dss_clkdm",
589 .main_clk = "dss_dss_clk",
590 .prcm = {
591 .omap4 = {
592 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
593 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
594 },
595 },
596 .dev_attr = &dss_dispc_dev_attr,
597 .parent_hwmod = &dra7xx_dss_hwmod,
598 };
600 /*
601 * 'hdmi' class
602 * hdmi controller
603 */
605 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
606 .rev_offs = 0x0000,
607 .sysc_offs = 0x0010,
608 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
609 SYSC_HAS_SOFTRESET),
610 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
611 SIDLE_SMART_WKUP),
612 .sysc_fields = &omap_hwmod_sysc_type2,
613 };
615 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
616 .name = "hdmi",
617 .sysc = &dra7xx_hdmi_sysc,
618 };
620 /* dss_hdmi */
622 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
623 { .role = "sys_clk", .clk = "dss_hdmi_clk" },
624 };
626 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
627 .name = "dss_hdmi",
628 .class = &dra7xx_hdmi_hwmod_class,
629 .clkdm_name = "dss_clkdm",
630 .main_clk = "dss_48mhz_clk",
631 .prcm = {
632 .omap4 = {
633 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
634 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
635 },
636 },
637 .opt_clks = dss_hdmi_opt_clks,
638 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
639 .parent_hwmod = &dra7xx_dss_hwmod,
640 };
642 /* AES (the 'P' (public) device) */
643 static struct omap_hwmod_class_sysconfig dra7xx_aes_sysc = {
644 .rev_offs = 0x0080,
645 .sysc_offs = 0x0084,
646 .syss_offs = 0x0088,
647 .sysc_flags = SYSS_HAS_RESET_STATUS,
648 };
650 static struct omap_hwmod_class dra7xx_aes_hwmod_class = {
651 .name = "aes",
652 .sysc = &dra7xx_aes_sysc,
653 .rev = 2,
654 };
656 /* AES1 */
657 static struct omap_hwmod dra7xx_aes1_hwmod = {
658 .name = "aes1",
659 .class = &dra7xx_aes_hwmod_class,
660 .clkdm_name = "l4sec_clkdm",
661 .main_clk = "l3_iclk_div",
662 .prcm = {
663 .omap4 = {
664 .clkctrl_offs = DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET,
665 .context_offs = DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET,
666 .modulemode = MODULEMODE_HWCTRL,
667 },
668 },
669 };
671 /* AES2 */
672 static struct omap_hwmod dra7xx_aes2_hwmod = {
673 .name = "aes2",
674 .class = &dra7xx_aes_hwmod_class,
675 .clkdm_name = "l4sec_clkdm",
676 .main_clk = "l3_iclk_div",
677 .prcm = {
678 .omap4 = {
679 .clkctrl_offs = DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET,
680 .context_offs = DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET,
681 .modulemode = MODULEMODE_HWCTRL,
682 },
683 },
684 };
686 /* sha0 HIB2 (the 'P' (public) device) */
687 static struct omap_hwmod_class_sysconfig dra7xx_sha0_sysc = {
688 .rev_offs = 0x100,
689 .sysc_offs = 0x110,
690 .syss_offs = 0x114,
691 .sysc_flags = SYSS_HAS_RESET_STATUS,
692 };
694 static struct omap_hwmod_class dra7xx_sha0_hwmod_class = {
695 .name = "sham",
696 .sysc = &dra7xx_sha0_sysc,
697 .rev = 2,
698 };
700 struct omap_hwmod dra7xx_sha0_hwmod = {
701 .name = "sham",
702 .class = &dra7xx_sha0_hwmod_class,
703 .clkdm_name = "l4sec_clkdm",
704 .main_clk = "l3_iclk_div",
705 .prcm = {
706 .omap4 = {
707 .clkctrl_offs = DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
708 .context_offs = DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
709 .modulemode = MODULEMODE_HWCTRL,
710 },
711 },
712 };
714 /*
715 * 'elm' class
716 *
717 */
719 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
720 .rev_offs = 0x0000,
721 .sysc_offs = 0x0010,
722 .syss_offs = 0x0014,
723 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
724 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
725 SYSS_HAS_RESET_STATUS),
726 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
727 SIDLE_SMART_WKUP),
728 .sysc_fields = &omap_hwmod_sysc_type1,
729 };
731 static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
732 .name = "elm",
733 .sysc = &dra7xx_elm_sysc,
734 };
736 /* elm */
738 static struct omap_hwmod dra7xx_elm_hwmod = {
739 .name = "elm",
740 .class = &dra7xx_elm_hwmod_class,
741 .clkdm_name = "l4per_clkdm",
742 .main_clk = "l3_iclk_div",
743 .prcm = {
744 .omap4 = {
745 .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
746 .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
747 },
748 },
749 };
751 /*
752 * 'gpio' class
753 *
754 */
756 static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
757 .rev_offs = 0x0000,
758 .sysc_offs = 0x0010,
759 .syss_offs = 0x0114,
760 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
761 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
762 SYSS_HAS_RESET_STATUS),
763 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
764 SIDLE_SMART_WKUP),
765 .sysc_fields = &omap_hwmod_sysc_type1,
766 };
768 static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
769 .name = "gpio",
770 .sysc = &dra7xx_gpio_sysc,
771 .rev = 2,
772 };
774 /* gpio dev_attr */
775 static struct omap_gpio_dev_attr gpio_dev_attr = {
776 .bank_width = 32,
777 .dbck_flag = true,
778 };
780 /* gpio1 */
781 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
782 { .role = "dbclk", .clk = "gpio1_dbclk" },
783 };
785 static struct omap_hwmod dra7xx_gpio1_hwmod = {
786 .name = "gpio1",
787 .class = &dra7xx_gpio_hwmod_class,
788 .clkdm_name = "wkupaon_clkdm",
789 .main_clk = "wkupaon_iclk_mux",
790 .prcm = {
791 .omap4 = {
792 .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
793 .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
794 .modulemode = MODULEMODE_HWCTRL,
795 },
796 },
797 .opt_clks = gpio1_opt_clks,
798 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
799 .dev_attr = &gpio_dev_attr,
800 };
802 /* gpio2 */
803 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
804 { .role = "dbclk", .clk = "gpio2_dbclk" },
805 };
807 static struct omap_hwmod dra7xx_gpio2_hwmod = {
808 .name = "gpio2",
809 .class = &dra7xx_gpio_hwmod_class,
810 .clkdm_name = "l4per_clkdm",
811 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
812 .main_clk = "l3_iclk_div",
813 .prcm = {
814 .omap4 = {
815 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
816 .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
817 .modulemode = MODULEMODE_HWCTRL,
818 },
819 },
820 .opt_clks = gpio2_opt_clks,
821 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
822 .dev_attr = &gpio_dev_attr,
823 };
825 /* gpio3 */
826 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
827 { .role = "dbclk", .clk = "gpio3_dbclk" },
828 };
830 static struct omap_hwmod dra7xx_gpio3_hwmod = {
831 .name = "gpio3",
832 .class = &dra7xx_gpio_hwmod_class,
833 .clkdm_name = "l4per_clkdm",
834 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
835 .main_clk = "l3_iclk_div",
836 .prcm = {
837 .omap4 = {
838 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
839 .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
840 .modulemode = MODULEMODE_HWCTRL,
841 },
842 },
843 .opt_clks = gpio3_opt_clks,
844 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
845 .dev_attr = &gpio_dev_attr,
846 };
848 /* gpio4 */
849 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
850 { .role = "dbclk", .clk = "gpio4_dbclk" },
851 };
853 static struct omap_hwmod dra7xx_gpio4_hwmod = {
854 .name = "gpio4",
855 .class = &dra7xx_gpio_hwmod_class,
856 .clkdm_name = "l4per_clkdm",
857 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
858 .main_clk = "l3_iclk_div",
859 .prcm = {
860 .omap4 = {
861 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
862 .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
863 .modulemode = MODULEMODE_HWCTRL,
864 },
865 },
866 .opt_clks = gpio4_opt_clks,
867 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
868 .dev_attr = &gpio_dev_attr,
869 };
871 /* gpio5 */
872 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
873 { .role = "dbclk", .clk = "gpio5_dbclk" },
874 };
876 static struct omap_hwmod dra7xx_gpio5_hwmod = {
877 .name = "gpio5",
878 .class = &dra7xx_gpio_hwmod_class,
879 .clkdm_name = "l4per_clkdm",
880 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
881 .main_clk = "l3_iclk_div",
882 .prcm = {
883 .omap4 = {
884 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
885 .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
886 .modulemode = MODULEMODE_HWCTRL,
887 },
888 },
889 .opt_clks = gpio5_opt_clks,
890 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
891 .dev_attr = &gpio_dev_attr,
892 };
894 /* gpio6 */
895 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
896 { .role = "dbclk", .clk = "gpio6_dbclk" },
897 };
899 static struct omap_hwmod dra7xx_gpio6_hwmod = {
900 .name = "gpio6",
901 .class = &dra7xx_gpio_hwmod_class,
902 .clkdm_name = "l4per_clkdm",
903 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
904 .main_clk = "l3_iclk_div",
905 .prcm = {
906 .omap4 = {
907 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
908 .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
909 .modulemode = MODULEMODE_HWCTRL,
910 },
911 },
912 .opt_clks = gpio6_opt_clks,
913 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
914 .dev_attr = &gpio_dev_attr,
915 };
917 /* gpio7 */
918 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
919 { .role = "dbclk", .clk = "gpio7_dbclk" },
920 };
922 static struct omap_hwmod dra7xx_gpio7_hwmod = {
923 .name = "gpio7",
924 .class = &dra7xx_gpio_hwmod_class,
925 .clkdm_name = "l4per_clkdm",
926 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
927 .main_clk = "l3_iclk_div",
928 .prcm = {
929 .omap4 = {
930 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
931 .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
932 .modulemode = MODULEMODE_HWCTRL,
933 },
934 },
935 .opt_clks = gpio7_opt_clks,
936 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
937 .dev_attr = &gpio_dev_attr,
938 };
940 /* gpio8 */
941 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
942 { .role = "dbclk", .clk = "gpio8_dbclk" },
943 };
945 static struct omap_hwmod dra7xx_gpio8_hwmod = {
946 .name = "gpio8",
947 .class = &dra7xx_gpio_hwmod_class,
948 .clkdm_name = "l4per_clkdm",
949 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
950 .main_clk = "l3_iclk_div",
951 .prcm = {
952 .omap4 = {
953 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
954 .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
955 .modulemode = MODULEMODE_HWCTRL,
956 },
957 },
958 .opt_clks = gpio8_opt_clks,
959 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
960 .dev_attr = &gpio_dev_attr,
961 };
963 /*
964 * 'gpmc' class
965 *
966 */
968 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
969 .rev_offs = 0x0000,
970 .sysc_offs = 0x0010,
971 .syss_offs = 0x0014,
972 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
973 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
974 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
975 SIDLE_SMART_WKUP),
976 .sysc_fields = &omap_hwmod_sysc_type1,
977 };
979 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
980 .name = "gpmc",
981 .sysc = &dra7xx_gpmc_sysc,
982 };
984 /* gpmc */
986 static struct omap_hwmod dra7xx_gpmc_hwmod = {
987 .name = "gpmc",
988 .class = &dra7xx_gpmc_hwmod_class,
989 .clkdm_name = "l3main1_clkdm",
990 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
991 HWMOD_SWSUP_SIDLE),
992 .main_clk = "l3_iclk_div",
993 .prcm = {
994 .omap4 = {
995 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
996 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
997 .modulemode = MODULEMODE_HWCTRL,
998 },
999 },
1000 };
1002 /*
1003 * 'hdq1w' class
1004 *
1005 */
1007 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
1008 .rev_offs = 0x0000,
1009 .sysc_offs = 0x0014,
1010 .syss_offs = 0x0018,
1011 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1012 SYSS_HAS_RESET_STATUS),
1013 .sysc_fields = &omap_hwmod_sysc_type1,
1014 };
1016 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
1017 .name = "hdq1w",
1018 .sysc = &dra7xx_hdq1w_sysc,
1019 };
1021 /* hdq1w */
1023 static struct omap_hwmod dra7xx_hdq1w_hwmod = {
1024 .name = "hdq1w",
1025 .class = &dra7xx_hdq1w_hwmod_class,
1026 .clkdm_name = "l4per_clkdm",
1027 .flags = HWMOD_INIT_NO_RESET,
1028 .main_clk = "func_12m_fclk",
1029 .prcm = {
1030 .omap4 = {
1031 .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1032 .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1033 .modulemode = MODULEMODE_SWCTRL,
1034 },
1035 },
1036 };
1038 /*
1039 * 'i2c' class
1040 *
1041 */
1043 static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
1044 .sysc_offs = 0x0010,
1045 .syss_offs = 0x0090,
1046 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1047 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1048 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1049 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1050 SIDLE_SMART_WKUP),
1051 .clockact = CLOCKACT_TEST_ICLK,
1052 .sysc_fields = &omap_hwmod_sysc_type1,
1053 };
1055 static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
1056 .name = "i2c",
1057 .sysc = &dra7xx_i2c_sysc,
1058 .reset = &omap_i2c_reset,
1059 .rev = OMAP_I2C_IP_VERSION_2,
1060 };
1062 /* i2c dev_attr */
1063 static struct omap_i2c_dev_attr i2c_dev_attr = {
1064 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1065 };
1067 /* i2c1 */
1068 static struct omap_hwmod dra7xx_i2c1_hwmod = {
1069 .name = "i2c1",
1070 .class = &dra7xx_i2c_hwmod_class,
1071 .clkdm_name = "l4per_clkdm",
1072 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1073 .main_clk = "func_96m_fclk",
1074 .prcm = {
1075 .omap4 = {
1076 .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1077 .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
1078 .modulemode = MODULEMODE_SWCTRL,
1079 },
1080 },
1081 .dev_attr = &i2c_dev_attr,
1082 };
1084 /* i2c2 */
1085 static struct omap_hwmod dra7xx_i2c2_hwmod = {
1086 .name = "i2c2",
1087 .class = &dra7xx_i2c_hwmod_class,
1088 .clkdm_name = "l4per_clkdm",
1089 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1090 .main_clk = "func_96m_fclk",
1091 .prcm = {
1092 .omap4 = {
1093 .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1094 .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
1095 .modulemode = MODULEMODE_SWCTRL,
1096 },
1097 },
1098 .dev_attr = &i2c_dev_attr,
1099 };
1101 /* i2c3 */
1102 static struct omap_hwmod dra7xx_i2c3_hwmod = {
1103 .name = "i2c3",
1104 .class = &dra7xx_i2c_hwmod_class,
1105 .clkdm_name = "l4per_clkdm",
1106 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1107 .main_clk = "func_96m_fclk",
1108 .prcm = {
1109 .omap4 = {
1110 .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1111 .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
1112 .modulemode = MODULEMODE_SWCTRL,
1113 },
1114 },
1115 .dev_attr = &i2c_dev_attr,
1116 };
1118 /* i2c4 */
1119 static struct omap_hwmod dra7xx_i2c4_hwmod = {
1120 .name = "i2c4",
1121 .class = &dra7xx_i2c_hwmod_class,
1122 .clkdm_name = "l4per_clkdm",
1123 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1124 .main_clk = "func_96m_fclk",
1125 .prcm = {
1126 .omap4 = {
1127 .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1128 .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
1129 .modulemode = MODULEMODE_SWCTRL,
1130 },
1131 },
1132 .dev_attr = &i2c_dev_attr,
1133 };
1135 /* i2c5 */
1136 static struct omap_hwmod dra7xx_i2c5_hwmod = {
1137 .name = "i2c5",
1138 .class = &dra7xx_i2c_hwmod_class,
1139 .clkdm_name = "ipu_clkdm",
1140 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1141 .main_clk = "func_96m_fclk",
1142 .prcm = {
1143 .omap4 = {
1144 .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
1145 .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
1146 .modulemode = MODULEMODE_SWCTRL,
1147 },
1148 },
1149 .dev_attr = &i2c_dev_attr,
1150 };
1152 /*
1153 * 'mailbox' class
1154 *
1155 */
1157 static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
1158 .rev_offs = 0x0000,
1159 .sysc_offs = 0x0010,
1160 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1161 SYSC_HAS_SOFTRESET),
1162 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1163 .sysc_fields = &omap_hwmod_sysc_type2,
1164 };
1166 static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
1167 .name = "mailbox",
1168 .sysc = &dra7xx_mailbox_sysc,
1169 };
1171 /* mailbox1 */
1172 static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1173 .name = "mailbox1",
1174 .class = &dra7xx_mailbox_hwmod_class,
1175 .clkdm_name = "l4cfg_clkdm",
1176 .prcm = {
1177 .omap4 = {
1178 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1179 .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1180 },
1181 },
1182 };
1184 /* mailbox2 */
1185 static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1186 .name = "mailbox2",
1187 .class = &dra7xx_mailbox_hwmod_class,
1188 .clkdm_name = "l4cfg_clkdm",
1189 .prcm = {
1190 .omap4 = {
1191 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1192 .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1193 },
1194 },
1195 };
1197 /* mailbox3 */
1198 static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1199 .name = "mailbox3",
1200 .class = &dra7xx_mailbox_hwmod_class,
1201 .clkdm_name = "l4cfg_clkdm",
1202 .prcm = {
1203 .omap4 = {
1204 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1205 .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1206 },
1207 },
1208 };
1210 /* mailbox4 */
1211 static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1212 .name = "mailbox4",
1213 .class = &dra7xx_mailbox_hwmod_class,
1214 .clkdm_name = "l4cfg_clkdm",
1215 .prcm = {
1216 .omap4 = {
1217 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1218 .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1219 },
1220 },
1221 };
1223 /* mailbox5 */
1224 static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1225 .name = "mailbox5",
1226 .class = &dra7xx_mailbox_hwmod_class,
1227 .clkdm_name = "l4cfg_clkdm",
1228 .prcm = {
1229 .omap4 = {
1230 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1231 .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1232 },
1233 },
1234 };
1236 /* mailbox6 */
1237 static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1238 .name = "mailbox6",
1239 .class = &dra7xx_mailbox_hwmod_class,
1240 .clkdm_name = "l4cfg_clkdm",
1241 .prcm = {
1242 .omap4 = {
1243 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1244 .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1245 },
1246 },
1247 };
1249 /* mailbox7 */
1250 static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1251 .name = "mailbox7",
1252 .class = &dra7xx_mailbox_hwmod_class,
1253 .clkdm_name = "l4cfg_clkdm",
1254 .prcm = {
1255 .omap4 = {
1256 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1257 .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1258 },
1259 },
1260 };
1262 /* mailbox8 */
1263 static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1264 .name = "mailbox8",
1265 .class = &dra7xx_mailbox_hwmod_class,
1266 .clkdm_name = "l4cfg_clkdm",
1267 .prcm = {
1268 .omap4 = {
1269 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1270 .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1271 },
1272 },
1273 };
1275 /* mailbox9 */
1276 static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1277 .name = "mailbox9",
1278 .class = &dra7xx_mailbox_hwmod_class,
1279 .clkdm_name = "l4cfg_clkdm",
1280 .prcm = {
1281 .omap4 = {
1282 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1283 .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1284 },
1285 },
1286 };
1288 /* mailbox10 */
1289 static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1290 .name = "mailbox10",
1291 .class = &dra7xx_mailbox_hwmod_class,
1292 .clkdm_name = "l4cfg_clkdm",
1293 .prcm = {
1294 .omap4 = {
1295 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1296 .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1297 },
1298 },
1299 };
1301 /* mailbox11 */
1302 static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1303 .name = "mailbox11",
1304 .class = &dra7xx_mailbox_hwmod_class,
1305 .clkdm_name = "l4cfg_clkdm",
1306 .prcm = {
1307 .omap4 = {
1308 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1309 .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1310 },
1311 },
1312 };
1314 /* mailbox12 */
1315 static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1316 .name = "mailbox12",
1317 .class = &dra7xx_mailbox_hwmod_class,
1318 .clkdm_name = "l4cfg_clkdm",
1319 .prcm = {
1320 .omap4 = {
1321 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1322 .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1323 },
1324 },
1325 };
1327 /* mailbox13 */
1328 static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1329 .name = "mailbox13",
1330 .class = &dra7xx_mailbox_hwmod_class,
1331 .clkdm_name = "l4cfg_clkdm",
1332 .prcm = {
1333 .omap4 = {
1334 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1335 .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1336 },
1337 },
1338 };
1340 /*
1341 * 'mcspi' class
1342 *
1343 */
1345 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1346 .rev_offs = 0x0000,
1347 .sysc_offs = 0x0010,
1348 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1349 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1350 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1351 SIDLE_SMART_WKUP),
1352 .sysc_fields = &omap_hwmod_sysc_type2,
1353 };
1355 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1356 .name = "mcspi",
1357 .sysc = &dra7xx_mcspi_sysc,
1358 .rev = OMAP4_MCSPI_REV,
1359 };
1361 /* mcspi1 */
1362 /* mcspi1 dev_attr */
1363 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1364 .num_chipselect = 4,
1365 };
1367 static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1368 .name = "mcspi1",
1369 .class = &dra7xx_mcspi_hwmod_class,
1370 .clkdm_name = "l4per_clkdm",
1371 .main_clk = "func_48m_fclk",
1372 .prcm = {
1373 .omap4 = {
1374 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1375 .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1376 .modulemode = MODULEMODE_SWCTRL,
1377 },
1378 },
1379 .dev_attr = &mcspi1_dev_attr,
1380 };
1382 /* mcspi2 */
1383 /* mcspi2 dev_attr */
1384 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1385 .num_chipselect = 2,
1386 };
1388 static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1389 .name = "mcspi2",
1390 .class = &dra7xx_mcspi_hwmod_class,
1391 .clkdm_name = "l4per_clkdm",
1392 .main_clk = "func_48m_fclk",
1393 .prcm = {
1394 .omap4 = {
1395 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1396 .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1397 .modulemode = MODULEMODE_SWCTRL,
1398 },
1399 },
1400 .dev_attr = &mcspi2_dev_attr,
1401 };
1403 /* mcspi3 */
1404 /* mcspi3 dev_attr */
1405 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1406 .num_chipselect = 2,
1407 };
1409 static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1410 .name = "mcspi3",
1411 .class = &dra7xx_mcspi_hwmod_class,
1412 .clkdm_name = "l4per_clkdm",
1413 .main_clk = "func_48m_fclk",
1414 .prcm = {
1415 .omap4 = {
1416 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1417 .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1418 .modulemode = MODULEMODE_SWCTRL,
1419 },
1420 },
1421 .dev_attr = &mcspi3_dev_attr,
1422 };
1424 /* mcspi4 */
1425 /* mcspi4 dev_attr */
1426 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1427 .num_chipselect = 1,
1428 };
1430 static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1431 .name = "mcspi4",
1432 .class = &dra7xx_mcspi_hwmod_class,
1433 .clkdm_name = "l4per_clkdm",
1434 .main_clk = "func_48m_fclk",
1435 .prcm = {
1436 .omap4 = {
1437 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1438 .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1439 .modulemode = MODULEMODE_SWCTRL,
1440 },
1441 },
1442 .dev_attr = &mcspi4_dev_attr,
1443 };
1445 /*
1446 * 'mmc' class
1447 *
1448 */
1450 static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1451 .rev_offs = 0x0000,
1452 .sysc_offs = 0x0010,
1453 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1454 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1455 SYSC_HAS_SOFTRESET),
1456 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1457 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1458 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1459 .sysc_fields = &omap_hwmod_sysc_type2,
1460 };
1462 static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1463 .name = "mmc",
1464 .sysc = &dra7xx_mmc_sysc,
1465 };
1467 /* mmc1 */
1468 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1469 { .role = "clk32k", .clk = "mmc1_clk32k" },
1470 };
1472 /* mmc1 dev_attr */
1473 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1474 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1475 };
1477 static struct omap_hwmod dra7xx_mmc1_hwmod = {
1478 .name = "mmc1",
1479 .class = &dra7xx_mmc_hwmod_class,
1480 .clkdm_name = "l3init_clkdm",
1481 .main_clk = "mmc1_fclk_div",
1482 .prcm = {
1483 .omap4 = {
1484 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1485 .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1486 .modulemode = MODULEMODE_SWCTRL,
1487 },
1488 },
1489 .opt_clks = mmc1_opt_clks,
1490 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1491 .dev_attr = &mmc1_dev_attr,
1492 };
1494 /* mmc2 */
1495 static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1496 { .role = "clk32k", .clk = "mmc2_clk32k" },
1497 };
1499 static struct omap_hwmod dra7xx_mmc2_hwmod = {
1500 .name = "mmc2",
1501 .class = &dra7xx_mmc_hwmod_class,
1502 .clkdm_name = "l3init_clkdm",
1503 .main_clk = "mmc2_fclk_div",
1504 .prcm = {
1505 .omap4 = {
1506 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1507 .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1508 .modulemode = MODULEMODE_SWCTRL,
1509 },
1510 },
1511 .opt_clks = mmc2_opt_clks,
1512 .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks),
1513 };
1515 /* mmc3 */
1516 static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1517 { .role = "clk32k", .clk = "mmc3_clk32k" },
1518 };
1520 static struct omap_hwmod dra7xx_mmc3_hwmod = {
1521 .name = "mmc3",
1522 .class = &dra7xx_mmc_hwmod_class,
1523 .clkdm_name = "l4per_clkdm",
1524 .main_clk = "mmc3_gfclk_div",
1525 .prcm = {
1526 .omap4 = {
1527 .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1528 .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1529 .modulemode = MODULEMODE_SWCTRL,
1530 },
1531 },
1532 .opt_clks = mmc3_opt_clks,
1533 .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks),
1534 };
1536 /* mmc4 */
1537 static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1538 { .role = "clk32k", .clk = "mmc4_clk32k" },
1539 };
1541 static struct omap_hwmod dra7xx_mmc4_hwmod = {
1542 .name = "mmc4",
1543 .class = &dra7xx_mmc_hwmod_class,
1544 .clkdm_name = "l4per_clkdm",
1545 .main_clk = "mmc4_gfclk_div",
1546 .prcm = {
1547 .omap4 = {
1548 .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1549 .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1550 .modulemode = MODULEMODE_SWCTRL,
1551 },
1552 },
1553 .opt_clks = mmc4_opt_clks,
1554 .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks),
1555 };
1557 /*
1558 * 'mpu' class
1559 *
1560 */
1562 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1563 .name = "mpu",
1564 };
1566 /* mpu */
1567 static struct omap_hwmod dra7xx_mpu_hwmod = {
1568 .name = "mpu",
1569 .class = &dra7xx_mpu_hwmod_class,
1570 .clkdm_name = "mpu_clkdm",
1571 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1572 .main_clk = "dpll_mpu_m2_ck",
1573 .prcm = {
1574 .omap4 = {
1575 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1576 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1577 },
1578 },
1579 };
1581 /*
1582 * 'ocp2scp' class
1583 *
1584 */
1586 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1587 .rev_offs = 0x0000,
1588 .sysc_offs = 0x0010,
1589 .syss_offs = 0x0014,
1590 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1591 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1592 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1593 SIDLE_SMART_WKUP),
1594 .sysc_fields = &omap_hwmod_sysc_type1,
1595 };
1597 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1598 .name = "ocp2scp",
1599 .sysc = &dra7xx_ocp2scp_sysc,
1600 };
1602 /* ocp2scp1 */
1603 static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1604 .name = "ocp2scp1",
1605 .class = &dra7xx_ocp2scp_hwmod_class,
1606 .clkdm_name = "l3init_clkdm",
1607 .main_clk = "l4_root_clk_div",
1608 .prcm = {
1609 .omap4 = {
1610 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1611 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1612 .modulemode = MODULEMODE_HWCTRL,
1613 },
1614 },
1615 };
1617 /*
1618 * 'qspi' class
1619 *
1620 */
1622 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1623 .sysc_offs = 0x0010,
1624 .sysc_flags = SYSC_HAS_SIDLEMODE,
1625 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1626 SIDLE_SMART_WKUP),
1627 .sysc_fields = &omap_hwmod_sysc_type2,
1628 };
1630 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1631 .name = "qspi",
1632 .sysc = &dra7xx_qspi_sysc,
1633 };
1635 /* qspi */
1636 static struct omap_hwmod dra7xx_qspi_hwmod = {
1637 .name = "qspi",
1638 .class = &dra7xx_qspi_hwmod_class,
1639 .clkdm_name = "l4per2_clkdm",
1640 .main_clk = "qspi_gfclk_div",
1641 .prcm = {
1642 .omap4 = {
1643 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1644 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1645 .modulemode = MODULEMODE_SWCTRL,
1646 },
1647 },
1648 };
1650 /*
1651 * 'rtcss' class
1652 *
1653 */
1654 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
1655 .sysc_offs = 0x0078,
1656 .sysc_flags = SYSC_HAS_SIDLEMODE,
1657 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1658 SIDLE_SMART_WKUP),
1659 .sysc_fields = &omap_hwmod_sysc_type3,
1660 };
1662 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
1663 .name = "rtcss",
1664 .sysc = &dra7xx_rtcss_sysc,
1665 .reset = &omap_hwmod_rtc_unlock,
1666 };
1668 /* rtcss */
1669 static struct omap_hwmod dra7xx_rtcss_hwmod = {
1670 .name = "rtcss",
1671 .class = &dra7xx_rtcss_hwmod_class,
1672 .clkdm_name = "rtc_clkdm",
1673 .main_clk = "sys_32k_ck",
1674 .prcm = {
1675 .omap4 = {
1676 .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
1677 .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
1678 .modulemode = MODULEMODE_SWCTRL,
1679 },
1680 },
1681 };
1683 /*
1684 * 'sata' class
1685 *
1686 */
1688 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
1689 .sysc_offs = 0x0000,
1690 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1691 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1692 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1693 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1694 .sysc_fields = &omap_hwmod_sysc_type2,
1695 };
1697 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
1698 .name = "sata",
1699 .sysc = &dra7xx_sata_sysc,
1700 };
1702 /* sata */
1703 static struct omap_hwmod_opt_clk sata_opt_clks[] = {
1704 { .role = "ref_clk", .clk = "sata_ref_clk" },
1705 };
1707 static struct omap_hwmod dra7xx_sata_hwmod = {
1708 .name = "sata",
1709 .class = &dra7xx_sata_hwmod_class,
1710 .clkdm_name = "l3init_clkdm",
1711 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1712 .main_clk = "func_48m_fclk",
1713 .prcm = {
1714 .omap4 = {
1715 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
1716 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
1717 .modulemode = MODULEMODE_SWCTRL,
1718 },
1719 },
1720 .opt_clks = sata_opt_clks,
1721 .opt_clks_cnt = ARRAY_SIZE(sata_opt_clks),
1722 };
1724 /*
1725 * 'smartreflex' class
1726 *
1727 */
1729 /* The IP is not compliant to type1 / type2 scheme */
1730 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
1731 .sidle_shift = 24,
1732 .enwkup_shift = 26,
1733 };
1735 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
1736 .sysc_offs = 0x0038,
1737 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1738 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1739 SIDLE_SMART_WKUP),
1740 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
1741 };
1743 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
1744 .name = "smartreflex",
1745 .sysc = &dra7xx_smartreflex_sysc,
1746 .rev = 2,
1747 };
1749 /* smartreflex_core */
1750 /* smartreflex_core dev_attr */
1751 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
1752 .sensor_voltdm_name = "core",
1753 };
1755 static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
1756 .name = "smartreflex_core",
1757 .class = &dra7xx_smartreflex_hwmod_class,
1758 .clkdm_name = "coreaon_clkdm",
1759 .main_clk = "wkupaon_iclk_mux",
1760 .prcm = {
1761 .omap4 = {
1762 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
1763 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
1764 .modulemode = MODULEMODE_SWCTRL,
1765 },
1766 },
1767 .dev_attr = &smartreflex_core_dev_attr,
1768 };
1770 /* smartreflex_mpu */
1771 /* smartreflex_mpu dev_attr */
1772 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
1773 .sensor_voltdm_name = "mpu",
1774 };
1776 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
1777 .name = "smartreflex_mpu",
1778 .class = &dra7xx_smartreflex_hwmod_class,
1779 .clkdm_name = "coreaon_clkdm",
1780 .main_clk = "wkupaon_iclk_mux",
1781 .prcm = {
1782 .omap4 = {
1783 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
1784 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
1785 .modulemode = MODULEMODE_SWCTRL,
1786 },
1787 },
1788 .dev_attr = &smartreflex_mpu_dev_attr,
1789 };
1791 /*
1792 * 'spinlock' class
1793 *
1794 */
1796 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
1797 .rev_offs = 0x0000,
1798 .sysc_offs = 0x0010,
1799 .syss_offs = 0x0014,
1800 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1801 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1802 SYSS_HAS_RESET_STATUS),
1803 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1804 .sysc_fields = &omap_hwmod_sysc_type1,
1805 };
1807 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
1808 .name = "spinlock",
1809 .sysc = &dra7xx_spinlock_sysc,
1810 };
1812 /* spinlock */
1813 static struct omap_hwmod dra7xx_spinlock_hwmod = {
1814 .name = "spinlock",
1815 .class = &dra7xx_spinlock_hwmod_class,
1816 .clkdm_name = "l4cfg_clkdm",
1817 .main_clk = "l3_iclk_div",
1818 .prcm = {
1819 .omap4 = {
1820 .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
1821 .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1822 },
1823 },
1824 };
1826 /*
1827 * 'timer' class
1828 *
1829 * This class contains several variants: ['timer_1ms', 'timer_secure',
1830 * 'timer']
1831 */
1833 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
1834 .rev_offs = 0x0000,
1835 .sysc_offs = 0x0010,
1836 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1837 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1838 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1839 SIDLE_SMART_WKUP),
1840 .sysc_fields = &omap_hwmod_sysc_type2,
1841 };
1843 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
1844 .name = "timer",
1845 .sysc = &dra7xx_timer_1ms_sysc,
1846 };
1848 static struct omap_hwmod_class_sysconfig dra7xx_timer_secure_sysc = {
1849 .rev_offs = 0x0000,
1850 .sysc_offs = 0x0010,
1851 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1852 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1853 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1854 SIDLE_SMART_WKUP),
1855 .sysc_fields = &omap_hwmod_sysc_type2,
1856 };
1858 static struct omap_hwmod_class dra7xx_timer_secure_hwmod_class = {
1859 .name = "timer",
1860 .sysc = &dra7xx_timer_secure_sysc,
1861 };
1863 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
1864 .rev_offs = 0x0000,
1865 .sysc_offs = 0x0010,
1866 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1867 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1868 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1869 SIDLE_SMART_WKUP),
1870 .sysc_fields = &omap_hwmod_sysc_type2,
1871 };
1873 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
1874 .name = "timer",
1875 .sysc = &dra7xx_timer_sysc,
1876 };
1878 /* timer1 */
1879 static struct omap_hwmod dra7xx_timer1_hwmod = {
1880 .name = "timer1",
1881 .class = &dra7xx_timer_1ms_hwmod_class,
1882 .clkdm_name = "wkupaon_clkdm",
1883 .main_clk = "timer1_gfclk_mux",
1884 .prcm = {
1885 .omap4 = {
1886 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1887 .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1888 .modulemode = MODULEMODE_SWCTRL,
1889 },
1890 },
1891 };
1893 /* timer2 */
1894 static struct omap_hwmod dra7xx_timer2_hwmod = {
1895 .name = "timer2",
1896 .class = &dra7xx_timer_1ms_hwmod_class,
1897 .clkdm_name = "l4per_clkdm",
1898 .main_clk = "timer2_gfclk_mux",
1899 .prcm = {
1900 .omap4 = {
1901 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1902 .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1903 .modulemode = MODULEMODE_SWCTRL,
1904 },
1905 },
1906 };
1908 /* timer3 */
1909 static struct omap_hwmod dra7xx_timer3_hwmod = {
1910 .name = "timer3",
1911 .class = &dra7xx_timer_hwmod_class,
1912 .clkdm_name = "l4per_clkdm",
1913 .main_clk = "timer3_gfclk_mux",
1914 .prcm = {
1915 .omap4 = {
1916 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1917 .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1918 .modulemode = MODULEMODE_SWCTRL,
1919 },
1920 },
1921 };
1923 /* timer4 */
1924 static struct omap_hwmod dra7xx_timer4_hwmod = {
1925 .name = "timer4",
1926 .class = &dra7xx_timer_hwmod_class,
1927 .clkdm_name = "l4per_clkdm",
1928 .main_clk = "timer4_gfclk_mux",
1929 .prcm = {
1930 .omap4 = {
1931 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1932 .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1933 .modulemode = MODULEMODE_SWCTRL,
1934 },
1935 },
1936 };
1938 /* timer5 */
1939 static struct omap_hwmod dra7xx_timer5_hwmod = {
1940 .name = "timer5",
1941 .class = &dra7xx_timer_hwmod_class,
1942 .clkdm_name = "ipu_clkdm",
1943 .main_clk = "timer5_gfclk_mux",
1944 .prcm = {
1945 .omap4 = {
1946 .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
1947 .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
1948 .modulemode = MODULEMODE_SWCTRL,
1949 },
1950 },
1951 };
1953 /* timer6 */
1954 static struct omap_hwmod dra7xx_timer6_hwmod = {
1955 .name = "timer6",
1956 .class = &dra7xx_timer_hwmod_class,
1957 .clkdm_name = "ipu_clkdm",
1958 .main_clk = "timer6_gfclk_mux",
1959 .prcm = {
1960 .omap4 = {
1961 .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
1962 .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
1963 .modulemode = MODULEMODE_SWCTRL,
1964 },
1965 },
1966 };
1968 /* timer7 */
1969 static struct omap_hwmod dra7xx_timer7_hwmod = {
1970 .name = "timer7",
1971 .class = &dra7xx_timer_hwmod_class,
1972 .clkdm_name = "ipu_clkdm",
1973 .main_clk = "timer7_gfclk_mux",
1974 .prcm = {
1975 .omap4 = {
1976 .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
1977 .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
1978 .modulemode = MODULEMODE_SWCTRL,
1979 },
1980 },
1981 };
1983 /* timer8 */
1984 static struct omap_hwmod dra7xx_timer8_hwmod = {
1985 .name = "timer8",
1986 .class = &dra7xx_timer_hwmod_class,
1987 .clkdm_name = "ipu_clkdm",
1988 .main_clk = "timer8_gfclk_mux",
1989 .prcm = {
1990 .omap4 = {
1991 .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
1992 .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
1993 .modulemode = MODULEMODE_SWCTRL,
1994 },
1995 },
1996 };
1998 /* timer9 */
1999 static struct omap_hwmod dra7xx_timer9_hwmod = {
2000 .name = "timer9",
2001 .class = &dra7xx_timer_hwmod_class,
2002 .clkdm_name = "l4per_clkdm",
2003 .main_clk = "timer9_gfclk_mux",
2004 .prcm = {
2005 .omap4 = {
2006 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
2007 .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
2008 .modulemode = MODULEMODE_SWCTRL,
2009 },
2010 },
2011 };
2013 /* timer10 */
2014 static struct omap_hwmod dra7xx_timer10_hwmod = {
2015 .name = "timer10",
2016 .class = &dra7xx_timer_1ms_hwmod_class,
2017 .clkdm_name = "l4per_clkdm",
2018 .main_clk = "timer10_gfclk_mux",
2019 .prcm = {
2020 .omap4 = {
2021 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
2022 .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
2023 .modulemode = MODULEMODE_SWCTRL,
2024 },
2025 },
2026 };
2028 /* timer11 */
2029 static struct omap_hwmod dra7xx_timer11_hwmod = {
2030 .name = "timer11",
2031 .class = &dra7xx_timer_hwmod_class,
2032 .clkdm_name = "l4per_clkdm",
2033 .main_clk = "timer11_gfclk_mux",
2034 .prcm = {
2035 .omap4 = {
2036 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
2037 .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
2038 .modulemode = MODULEMODE_SWCTRL,
2039 },
2040 },
2041 };
2043 /* timer12 */
2044 static struct omap_hwmod dra7xx_timer12_hwmod = {
2045 .name = "timer12",
2046 .class = &dra7xx_timer_secure_hwmod_class,
2047 .clkdm_name = "wkupaon_clkdm",
2048 .main_clk = "secure_32k_clk_src_ck",
2049 .prcm = {
2050 .omap4 = {
2051 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET,
2052 .context_offs = DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET,
2053 },
2054 },
2055 };
2057 /* timer13 */
2058 static struct omap_hwmod dra7xx_timer13_hwmod = {
2059 .name = "timer13",
2060 .class = &dra7xx_timer_hwmod_class,
2061 .clkdm_name = "l4per3_clkdm",
2062 .main_clk = "timer13_gfclk_mux",
2063 .prcm = {
2064 .omap4 = {
2065 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
2066 .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
2067 .modulemode = MODULEMODE_SWCTRL,
2068 },
2069 },
2070 };
2072 /* timer14 */
2073 static struct omap_hwmod dra7xx_timer14_hwmod = {
2074 .name = "timer14",
2075 .class = &dra7xx_timer_hwmod_class,
2076 .clkdm_name = "l4per3_clkdm",
2077 .main_clk = "timer14_gfclk_mux",
2078 .prcm = {
2079 .omap4 = {
2080 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
2081 .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
2082 .modulemode = MODULEMODE_SWCTRL,
2083 },
2084 },
2085 };
2087 /* timer15 */
2088 static struct omap_hwmod dra7xx_timer15_hwmod = {
2089 .name = "timer15",
2090 .class = &dra7xx_timer_hwmod_class,
2091 .clkdm_name = "l4per3_clkdm",
2092 .main_clk = "timer15_gfclk_mux",
2093 .prcm = {
2094 .omap4 = {
2095 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
2096 .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
2097 .modulemode = MODULEMODE_SWCTRL,
2098 },
2099 },
2100 };
2102 /* timer16 */
2103 static struct omap_hwmod dra7xx_timer16_hwmod = {
2104 .name = "timer16",
2105 .class = &dra7xx_timer_hwmod_class,
2106 .clkdm_name = "l4per3_clkdm",
2107 .main_clk = "timer16_gfclk_mux",
2108 .prcm = {
2109 .omap4 = {
2110 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
2111 .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
2112 .modulemode = MODULEMODE_SWCTRL,
2113 },
2114 },
2115 };
2117 /*
2118 * 'uart' class
2119 *
2120 */
2122 static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
2123 .rev_offs = 0x0050,
2124 .sysc_offs = 0x0054,
2125 .syss_offs = 0x0058,
2126 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2127 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2128 SYSS_HAS_RESET_STATUS),
2129 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2130 SIDLE_SMART_WKUP),
2131 .sysc_fields = &omap_hwmod_sysc_type1,
2132 };
2134 static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
2135 .name = "uart",
2136 .sysc = &dra7xx_uart_sysc,
2137 };
2139 /* uart1 */
2140 static struct omap_hwmod dra7xx_uart1_hwmod = {
2141 .name = "uart1",
2142 .class = &dra7xx_uart_hwmod_class,
2143 .clkdm_name = "l4per_clkdm",
2144 .main_clk = "uart1_gfclk_mux",
2145 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
2146 .prcm = {
2147 .omap4 = {
2148 .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
2149 .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
2150 .modulemode = MODULEMODE_SWCTRL,
2151 },
2152 },
2153 };
2155 /* uart2 */
2156 static struct omap_hwmod dra7xx_uart2_hwmod = {
2157 .name = "uart2",
2158 .class = &dra7xx_uart_hwmod_class,
2159 .clkdm_name = "l4per_clkdm",
2160 .main_clk = "uart2_gfclk_mux",
2161 .flags = HWMOD_SWSUP_SIDLE_ACT,
2162 .prcm = {
2163 .omap4 = {
2164 .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
2165 .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
2166 .modulemode = MODULEMODE_SWCTRL,
2167 },
2168 },
2169 };
2171 /* uart3 */
2172 static struct omap_hwmod dra7xx_uart3_hwmod = {
2173 .name = "uart3",
2174 .class = &dra7xx_uart_hwmod_class,
2175 .clkdm_name = "l4per_clkdm",
2176 .main_clk = "uart3_gfclk_mux",
2177 .flags = HWMOD_SWSUP_SIDLE_ACT,
2178 .prcm = {
2179 .omap4 = {
2180 .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
2181 .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
2182 .modulemode = MODULEMODE_SWCTRL,
2183 },
2184 },
2185 };
2187 /* uart4 */
2188 static struct omap_hwmod dra7xx_uart4_hwmod = {
2189 .name = "uart4",
2190 .class = &dra7xx_uart_hwmod_class,
2191 .clkdm_name = "l4per_clkdm",
2192 .main_clk = "uart4_gfclk_mux",
2193 .flags = HWMOD_SWSUP_SIDLE_ACT,
2194 .prcm = {
2195 .omap4 = {
2196 .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
2197 .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
2198 .modulemode = MODULEMODE_SWCTRL,
2199 },
2200 },
2201 };
2203 /* uart5 */
2204 static struct omap_hwmod dra7xx_uart5_hwmod = {
2205 .name = "uart5",
2206 .class = &dra7xx_uart_hwmod_class,
2207 .clkdm_name = "l4per_clkdm",
2208 .main_clk = "uart5_gfclk_mux",
2209 .flags = HWMOD_SWSUP_SIDLE_ACT,
2210 .prcm = {
2211 .omap4 = {
2212 .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
2213 .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
2214 .modulemode = MODULEMODE_SWCTRL,
2215 },
2216 },
2217 };
2219 /* uart6 */
2220 static struct omap_hwmod dra7xx_uart6_hwmod = {
2221 .name = "uart6",
2222 .class = &dra7xx_uart_hwmod_class,
2223 .clkdm_name = "ipu_clkdm",
2224 .main_clk = "uart6_gfclk_mux",
2225 .flags = HWMOD_SWSUP_SIDLE_ACT,
2226 .prcm = {
2227 .omap4 = {
2228 .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
2229 .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
2230 .modulemode = MODULEMODE_SWCTRL,
2231 },
2232 },
2233 };
2235 /* uart7 */
2236 static struct omap_hwmod dra7xx_uart7_hwmod = {
2237 .name = "uart7",
2238 .class = &dra7xx_uart_hwmod_class,
2239 .clkdm_name = "l4per2_clkdm",
2240 .main_clk = "uart7_gfclk_mux",
2241 .flags = HWMOD_SWSUP_SIDLE_ACT,
2242 .prcm = {
2243 .omap4 = {
2244 .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
2245 .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
2246 .modulemode = MODULEMODE_SWCTRL,
2247 },
2248 },
2249 };
2251 /* uart8 */
2252 static struct omap_hwmod dra7xx_uart8_hwmod = {
2253 .name = "uart8",
2254 .class = &dra7xx_uart_hwmod_class,
2255 .clkdm_name = "l4per2_clkdm",
2256 .main_clk = "uart8_gfclk_mux",
2257 .flags = HWMOD_SWSUP_SIDLE_ACT,
2258 .prcm = {
2259 .omap4 = {
2260 .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
2261 .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
2262 .modulemode = MODULEMODE_SWCTRL,
2263 },
2264 },
2265 };
2267 /* uart9 */
2268 static struct omap_hwmod dra7xx_uart9_hwmod = {
2269 .name = "uart9",
2270 .class = &dra7xx_uart_hwmod_class,
2271 .clkdm_name = "l4per2_clkdm",
2272 .main_clk = "uart9_gfclk_mux",
2273 .flags = HWMOD_SWSUP_SIDLE_ACT,
2274 .prcm = {
2275 .omap4 = {
2276 .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
2277 .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
2278 .modulemode = MODULEMODE_SWCTRL,
2279 },
2280 },
2281 };
2283 /* uart10 */
2284 static struct omap_hwmod dra7xx_uart10_hwmod = {
2285 .name = "uart10",
2286 .class = &dra7xx_uart_hwmod_class,
2287 .clkdm_name = "wkupaon_clkdm",
2288 .main_clk = "uart10_gfclk_mux",
2289 .flags = HWMOD_SWSUP_SIDLE_ACT,
2290 .prcm = {
2291 .omap4 = {
2292 .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
2293 .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
2294 .modulemode = MODULEMODE_SWCTRL,
2295 },
2296 },
2297 };
2299 /* DES (the 'P' (public) device) */
2300 static struct omap_hwmod_class_sysconfig dra7xx_des_sysc = {
2301 .rev_offs = 0x0030,
2302 .sysc_offs = 0x0034,
2303 .syss_offs = 0x0038,
2304 .sysc_flags = SYSS_HAS_RESET_STATUS,
2305 };
2307 static struct omap_hwmod_class dra7xx_des_hwmod_class = {
2308 .name = "des",
2309 .sysc = &dra7xx_des_sysc,
2310 };
2312 /* DES */
2313 static struct omap_hwmod dra7xx_des_hwmod = {
2314 .name = "des",
2315 .class = &dra7xx_des_hwmod_class,
2316 .clkdm_name = "l4sec_clkdm",
2317 .main_clk = "l3_iclk_div",
2318 .prcm = {
2319 .omap4 = {
2320 .clkctrl_offs = DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
2321 .context_offs = DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
2322 .modulemode = MODULEMODE_HWCTRL,
2323 },
2324 },
2325 };
2327 /* rng */
2328 static struct omap_hwmod_class_sysconfig dra7xx_rng_sysc = {
2329 .rev_offs = 0x1fe0,
2330 .sysc_offs = 0x1fe4,
2331 .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
2332 .idlemodes = SIDLE_FORCE | SIDLE_NO,
2333 .sysc_fields = &omap_hwmod_sysc_type1,
2334 };
2336 static struct omap_hwmod_class dra7xx_rng_hwmod_class = {
2337 .name = "rng",
2338 .sysc = &dra7xx_rng_sysc,
2339 };
2341 static struct omap_hwmod dra7xx_rng_hwmod = {
2342 .name = "rng",
2343 .class = &dra7xx_rng_hwmod_class,
2344 .flags = HWMOD_SWSUP_SIDLE,
2345 .clkdm_name = "l4sec_clkdm",
2346 .prcm = {
2347 .omap4 = {
2348 .clkctrl_offs = DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET,
2349 .context_offs = DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET,
2350 .modulemode = MODULEMODE_HWCTRL,
2351 },
2352 },
2353 };
2355 /*
2356 * 'usb_otg_ss' class
2357 *
2358 */
2360 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
2361 .name = "usb_otg_ss",
2362 };
2364 /* usb_otg_ss1 */
2365 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
2366 { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
2367 };
2369 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
2370 .name = "usb_otg_ss1",
2371 .class = &dra7xx_usb_otg_ss_hwmod_class,
2372 .clkdm_name = "l3init_clkdm",
2373 .main_clk = "dpll_core_h13x2_ck",
2374 .prcm = {
2375 .omap4 = {
2376 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
2377 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
2378 .modulemode = MODULEMODE_HWCTRL,
2379 },
2380 },
2381 .opt_clks = usb_otg_ss1_opt_clks,
2382 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
2383 };
2385 /* usb_otg_ss2 */
2386 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
2387 { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
2388 };
2390 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
2391 .name = "usb_otg_ss2",
2392 .class = &dra7xx_usb_otg_ss_hwmod_class,
2393 .clkdm_name = "l3init_clkdm",
2394 .main_clk = "dpll_core_h13x2_ck",
2395 .prcm = {
2396 .omap4 = {
2397 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
2398 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
2399 .modulemode = MODULEMODE_HWCTRL,
2400 },
2401 },
2402 .opt_clks = usb_otg_ss2_opt_clks,
2403 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
2404 };
2406 /* usb_otg_ss3 */
2407 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
2408 .name = "usb_otg_ss3",
2409 .class = &dra7xx_usb_otg_ss_hwmod_class,
2410 .clkdm_name = "l3init_clkdm",
2411 .main_clk = "dpll_core_h13x2_ck",
2412 .prcm = {
2413 .omap4 = {
2414 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
2415 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
2416 .modulemode = MODULEMODE_HWCTRL,
2417 },
2418 },
2419 };
2421 /* usb_otg_ss4 */
2422 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
2423 .name = "usb_otg_ss4",
2424 .class = &dra7xx_usb_otg_ss_hwmod_class,
2425 .clkdm_name = "l3init_clkdm",
2426 .main_clk = "dpll_core_h13x2_ck",
2427 .prcm = {
2428 .omap4 = {
2429 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
2430 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
2431 .modulemode = MODULEMODE_HWCTRL,
2432 },
2433 },
2434 };
2436 /*
2437 * 'vcp' class
2438 *
2439 */
2441 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
2442 .name = "vcp",
2443 };
2445 /* vcp1 */
2446 static struct omap_hwmod dra7xx_vcp1_hwmod = {
2447 .name = "vcp1",
2448 .class = &dra7xx_vcp_hwmod_class,
2449 .clkdm_name = "l3main1_clkdm",
2450 .main_clk = "l3_iclk_div",
2451 .prcm = {
2452 .omap4 = {
2453 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
2454 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
2455 },
2456 },
2457 };
2459 /* vcp2 */
2460 static struct omap_hwmod dra7xx_vcp2_hwmod = {
2461 .name = "vcp2",
2462 .class = &dra7xx_vcp_hwmod_class,
2463 .clkdm_name = "l3main1_clkdm",
2464 .main_clk = "l3_iclk_div",
2465 .prcm = {
2466 .omap4 = {
2467 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
2468 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
2469 },
2470 },
2471 };
2473 /*
2474 * 'wd_timer' class
2475 *
2476 */
2478 static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
2479 .rev_offs = 0x0000,
2480 .sysc_offs = 0x0010,
2481 .syss_offs = 0x0014,
2482 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2483 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2484 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2485 SIDLE_SMART_WKUP),
2486 .sysc_fields = &omap_hwmod_sysc_type1,
2487 };
2489 static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
2490 .name = "wd_timer",
2491 .sysc = &dra7xx_wd_timer_sysc,
2492 .pre_shutdown = &omap2_wd_timer_disable,
2493 .reset = &omap2_wd_timer_reset,
2494 };
2496 /* wd_timer2 */
2497 static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
2498 .name = "wd_timer2",
2499 .class = &dra7xx_wd_timer_hwmod_class,
2500 .clkdm_name = "wkupaon_clkdm",
2501 .main_clk = "sys_32k_ck",
2502 .prcm = {
2503 .omap4 = {
2504 .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
2505 .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
2506 .modulemode = MODULEMODE_SWCTRL,
2507 },
2508 },
2509 };
2512 /*
2513 * Interfaces
2514 */
2516 /* l3_main_2 -> l3_instr */
2517 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
2518 .master = &dra7xx_l3_main_2_hwmod,
2519 .slave = &dra7xx_l3_instr_hwmod,
2520 .clk = "l3_iclk_div",
2521 .user = OCP_USER_MPU | OCP_USER_SDMA,
2522 };
2524 /* l4_cfg -> l3_main_1 */
2525 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
2526 .master = &dra7xx_l4_cfg_hwmod,
2527 .slave = &dra7xx_l3_main_1_hwmod,
2528 .clk = "l3_iclk_div",
2529 .user = OCP_USER_MPU | OCP_USER_SDMA,
2530 };
2532 /* mpu -> l3_main_1 */
2533 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
2534 .master = &dra7xx_mpu_hwmod,
2535 .slave = &dra7xx_l3_main_1_hwmod,
2536 .clk = "l3_iclk_div",
2537 .user = OCP_USER_MPU,
2538 };
2540 /* l3_main_1 -> l3_main_2 */
2541 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
2542 .master = &dra7xx_l3_main_1_hwmod,
2543 .slave = &dra7xx_l3_main_2_hwmod,
2544 .clk = "l3_iclk_div",
2545 .user = OCP_USER_MPU,
2546 };
2548 /* l4_cfg -> l3_main_2 */
2549 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
2550 .master = &dra7xx_l4_cfg_hwmod,
2551 .slave = &dra7xx_l3_main_2_hwmod,
2552 .clk = "l3_iclk_div",
2553 .user = OCP_USER_MPU | OCP_USER_SDMA,
2554 };
2556 /* l3_main_1 -> l4_cfg */
2557 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
2558 .master = &dra7xx_l3_main_1_hwmod,
2559 .slave = &dra7xx_l4_cfg_hwmod,
2560 .clk = "l3_iclk_div",
2561 .user = OCP_USER_MPU | OCP_USER_SDMA,
2562 };
2564 /* l3_main_1 -> l4_per1 */
2565 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
2566 .master = &dra7xx_l3_main_1_hwmod,
2567 .slave = &dra7xx_l4_per1_hwmod,
2568 .clk = "l3_iclk_div",
2569 .user = OCP_USER_MPU | OCP_USER_SDMA,
2570 };
2572 /* l3_main_1 -> l4_per2 */
2573 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
2574 .master = &dra7xx_l3_main_1_hwmod,
2575 .slave = &dra7xx_l4_per2_hwmod,
2576 .clk = "l3_iclk_div",
2577 .user = OCP_USER_MPU | OCP_USER_SDMA,
2578 };
2580 /* l3_main_1 -> l4_per3 */
2581 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
2582 .master = &dra7xx_l3_main_1_hwmod,
2583 .slave = &dra7xx_l4_per3_hwmod,
2584 .clk = "l3_iclk_div",
2585 .user = OCP_USER_MPU | OCP_USER_SDMA,
2586 };
2588 /* l3_main_1 -> l4_wkup */
2589 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
2590 .master = &dra7xx_l3_main_1_hwmod,
2591 .slave = &dra7xx_l4_wkup_hwmod,
2592 .clk = "wkupaon_iclk_mux",
2593 .user = OCP_USER_MPU | OCP_USER_SDMA,
2594 };
2596 /* l4_per2 -> atl */
2597 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
2598 .master = &dra7xx_l4_per2_hwmod,
2599 .slave = &dra7xx_atl_hwmod,
2600 .clk = "l3_iclk_div",
2601 .user = OCP_USER_MPU | OCP_USER_SDMA,
2602 };
2604 /* l3_main_1 -> bb2d */
2605 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
2606 .master = &dra7xx_l3_main_1_hwmod,
2607 .slave = &dra7xx_bb2d_hwmod,
2608 .clk = "l3_iclk_div",
2609 .user = OCP_USER_MPU | OCP_USER_SDMA,
2610 };
2612 /* l4_wkup -> counter_32k */
2613 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
2614 .master = &dra7xx_l4_wkup_hwmod,
2615 .slave = &dra7xx_counter_32k_hwmod,
2616 .clk = "wkupaon_iclk_mux",
2617 .user = OCP_USER_MPU | OCP_USER_SDMA,
2618 };
2620 /* l4_wkup -> ctrl_module_wkup */
2621 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
2622 .master = &dra7xx_l4_wkup_hwmod,
2623 .slave = &dra7xx_ctrl_module_wkup_hwmod,
2624 .clk = "wkupaon_iclk_mux",
2625 .user = OCP_USER_MPU | OCP_USER_SDMA,
2626 };
2628 /* l4_wkup -> dcan1 */
2629 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2630 .master = &dra7xx_l4_wkup_hwmod,
2631 .slave = &dra7xx_dcan1_hwmod,
2632 .clk = "wkupaon_iclk_mux",
2633 .user = OCP_USER_MPU | OCP_USER_SDMA,
2634 };
2636 /* l4_per2 -> dcan2 */
2637 static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2638 .master = &dra7xx_l4_per2_hwmod,
2639 .slave = &dra7xx_dcan2_hwmod,
2640 .clk = "l3_iclk_div",
2641 .user = OCP_USER_MPU | OCP_USER_SDMA,
2642 };
2644 static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
2645 {
2646 .pa_start = 0x4a056000,
2647 .pa_end = 0x4a056fff,
2648 .flags = ADDR_TYPE_RT
2649 },
2650 { }
2651 };
2653 /* l4_cfg -> dma_system */
2654 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
2655 .master = &dra7xx_l4_cfg_hwmod,
2656 .slave = &dra7xx_dma_system_hwmod,
2657 .clk = "l3_iclk_div",
2658 .addr = dra7xx_dma_system_addrs,
2659 .user = OCP_USER_MPU | OCP_USER_SDMA,
2660 };
2662 static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
2663 {
2664 .name = "family",
2665 .pa_start = 0x58000000,
2666 .pa_end = 0x5800007f,
2667 .flags = ADDR_TYPE_RT
2668 },
2669 };
2671 /* l3_main_1 -> dss */
2672 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
2673 .master = &dra7xx_l3_main_1_hwmod,
2674 .slave = &dra7xx_dss_hwmod,
2675 .clk = "l3_iclk_div",
2676 .addr = dra7xx_dss_addrs,
2677 .user = OCP_USER_MPU | OCP_USER_SDMA,
2678 };
2680 static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = {
2681 {
2682 .name = "dispc",
2683 .pa_start = 0x58001000,
2684 .pa_end = 0x58001fff,
2685 .flags = ADDR_TYPE_RT
2686 },
2687 };
2689 /* l3_main_1 -> dispc */
2690 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
2691 .master = &dra7xx_l3_main_1_hwmod,
2692 .slave = &dra7xx_dss_dispc_hwmod,
2693 .clk = "l3_iclk_div",
2694 .addr = dra7xx_dss_dispc_addrs,
2695 .user = OCP_USER_MPU | OCP_USER_SDMA,
2696 };
2698 static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = {
2699 {
2700 .name = "hdmi_wp",
2701 .pa_start = 0x58040000,
2702 .pa_end = 0x580400ff,
2703 .flags = ADDR_TYPE_RT
2704 },
2705 { }
2706 };
2708 /* l3_main_1 -> dispc */
2709 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
2710 .master = &dra7xx_l3_main_1_hwmod,
2711 .slave = &dra7xx_dss_hdmi_hwmod,
2712 .clk = "l3_iclk_div",
2713 .addr = dra7xx_dss_hdmi_addrs,
2714 .user = OCP_USER_MPU | OCP_USER_SDMA,
2715 };
2717 /* l3_main_1 -> aes1 */
2718 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes1 = {
2719 .master = &dra7xx_l3_main_1_hwmod,
2720 .slave = &dra7xx_aes1_hwmod,
2721 .clk = "l3_iclk_div",
2722 .user = OCP_USER_MPU | OCP_USER_SDMA,
2723 };
2725 /* l3_main_1 -> aes2 */
2726 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes2 = {
2727 .master = &dra7xx_l3_main_1_hwmod,
2728 .slave = &dra7xx_aes2_hwmod,
2729 .clk = "l3_iclk_div",
2730 .user = OCP_USER_MPU | OCP_USER_SDMA,
2731 };
2733 /* l3_main_1 -> sha0 */
2734 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__sha0 = {
2735 .master = &dra7xx_l3_main_1_hwmod,
2736 .slave = &dra7xx_sha0_hwmod,
2737 .clk = "l3_iclk_div",
2738 .user = OCP_USER_MPU | OCP_USER_SDMA,
2739 };
2741 static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = {
2742 {
2743 .pa_start = 0x48078000,
2744 .pa_end = 0x48078fff,
2745 .flags = ADDR_TYPE_RT
2746 },
2747 { }
2748 };
2750 /* l4_per1 -> elm */
2751 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
2752 .master = &dra7xx_l4_per1_hwmod,
2753 .slave = &dra7xx_elm_hwmod,
2754 .clk = "l3_iclk_div",
2755 .addr = dra7xx_elm_addrs,
2756 .user = OCP_USER_MPU | OCP_USER_SDMA,
2757 };
2759 /* l4_wkup -> gpio1 */
2760 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
2761 .master = &dra7xx_l4_wkup_hwmod,
2762 .slave = &dra7xx_gpio1_hwmod,
2763 .clk = "wkupaon_iclk_mux",
2764 .user = OCP_USER_MPU | OCP_USER_SDMA,
2765 };
2767 /* l4_per1 -> gpio2 */
2768 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
2769 .master = &dra7xx_l4_per1_hwmod,
2770 .slave = &dra7xx_gpio2_hwmod,
2771 .clk = "l3_iclk_div",
2772 .user = OCP_USER_MPU | OCP_USER_SDMA,
2773 };
2775 /* l4_per1 -> gpio3 */
2776 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
2777 .master = &dra7xx_l4_per1_hwmod,
2778 .slave = &dra7xx_gpio3_hwmod,
2779 .clk = "l3_iclk_div",
2780 .user = OCP_USER_MPU | OCP_USER_SDMA,
2781 };
2783 /* l4_per1 -> gpio4 */
2784 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
2785 .master = &dra7xx_l4_per1_hwmod,
2786 .slave = &dra7xx_gpio4_hwmod,
2787 .clk = "l3_iclk_div",
2788 .user = OCP_USER_MPU | OCP_USER_SDMA,
2789 };
2791 /* l4_per1 -> gpio5 */
2792 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
2793 .master = &dra7xx_l4_per1_hwmod,
2794 .slave = &dra7xx_gpio5_hwmod,
2795 .clk = "l3_iclk_div",
2796 .user = OCP_USER_MPU | OCP_USER_SDMA,
2797 };
2799 /* l4_per1 -> gpio6 */
2800 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
2801 .master = &dra7xx_l4_per1_hwmod,
2802 .slave = &dra7xx_gpio6_hwmod,
2803 .clk = "l3_iclk_div",
2804 .user = OCP_USER_MPU | OCP_USER_SDMA,
2805 };
2807 struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss0 = {
2808 .master = &dra7xx_l4_per2_hwmod,
2809 .slave = &dra7xx_epwmss0_hwmod,
2810 .clk = "l4_root_clk_div",
2811 .user = OCP_USER_MPU,
2812 };
2814 struct omap_hwmod_ocp_if dra7xx_epwmss0__ecap0 = {
2815 .master = &dra7xx_epwmss0_hwmod,
2816 .slave = &dra7xx_ecap0_hwmod,
2817 .clk = "l4_root_clk_div",
2818 .user = OCP_USER_MPU,
2819 };
2821 struct omap_hwmod_ocp_if dra7xx_epwmss0__eqep0 = {
2822 .master = &dra7xx_epwmss0_hwmod,
2823 .slave = &dra7xx_eqep0_hwmod,
2824 .clk = "l4_root_clk_div",
2825 .user = OCP_USER_MPU,
2826 };
2828 struct omap_hwmod_ocp_if dra7xx_epwmss0__ehrpwm0 = {
2829 .master = &dra7xx_epwmss0_hwmod,
2830 .slave = &dra7xx_ehrpwm0_hwmod,
2831 .clk = "l4_root_clk_div",
2832 .user = OCP_USER_MPU,
2833 };
2835 struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss1 = {
2836 .master = &dra7xx_l4_per2_hwmod,
2837 .slave = &dra7xx_epwmss1_hwmod,
2838 .clk = "l4_root_clk_div",
2839 .user = OCP_USER_MPU,
2840 };
2842 struct omap_hwmod_ocp_if dra7xx_epwmss1__ecap1 = {
2843 .master = &dra7xx_epwmss1_hwmod,
2844 .slave = &dra7xx_ecap1_hwmod,
2845 .clk = "l4_root_clk_div",
2846 .user = OCP_USER_MPU,
2847 };
2849 struct omap_hwmod_ocp_if dra7xx_epwmss1__eqep1 = {
2850 .master = &dra7xx_epwmss1_hwmod,
2851 .slave = &dra7xx_eqep1_hwmod,
2852 .clk = "l4_root_clk_div",
2853 .user = OCP_USER_MPU,
2854 };
2856 struct omap_hwmod_ocp_if dra7xx_epwmss1__ehrpwm1 = {
2857 .master = &dra7xx_epwmss1_hwmod,
2858 .slave = &dra7xx_ehrpwm1_hwmod,
2859 .clk = "l4_root_clk_div",
2860 .user = OCP_USER_MPU,
2861 };
2863 struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss2 = {
2864 .master = &dra7xx_l4_per2_hwmod,
2865 .slave = &dra7xx_epwmss2_hwmod,
2866 .clk = "l4_root_clk_div",
2867 .user = OCP_USER_MPU,
2868 };
2870 struct omap_hwmod_ocp_if dra7xx_epwmss2__ecap2 = {
2871 .master = &dra7xx_epwmss2_hwmod,
2872 .slave = &dra7xx_ecap2_hwmod,
2873 .clk = "l4_root_clk_div",
2874 .user = OCP_USER_MPU,
2875 };
2877 struct omap_hwmod_ocp_if dra7xx_epwmss2__eqep2 = {
2878 .master = &dra7xx_epwmss2_hwmod,
2879 .slave = &dra7xx_eqep2_hwmod,
2880 .clk = "l4_root_clk_div",
2881 .user = OCP_USER_MPU,
2882 };
2884 struct omap_hwmod_ocp_if dra7xx_epwmss2__ehrpwm2 = {
2885 .master = &dra7xx_epwmss2_hwmod,
2886 .slave = &dra7xx_ehrpwm2_hwmod,
2887 .clk = "l4_root_clk_div",
2888 .user = OCP_USER_MPU,
2889 };
2891 /* l4_per1 -> gpio7 */
2892 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
2893 .master = &dra7xx_l4_per1_hwmod,
2894 .slave = &dra7xx_gpio7_hwmod,
2895 .clk = "l3_iclk_div",
2896 .user = OCP_USER_MPU | OCP_USER_SDMA,
2897 };
2899 /* l4_per1 -> gpio8 */
2900 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
2901 .master = &dra7xx_l4_per1_hwmod,
2902 .slave = &dra7xx_gpio8_hwmod,
2903 .clk = "l3_iclk_div",
2904 .user = OCP_USER_MPU | OCP_USER_SDMA,
2905 };
2907 static struct omap_hwmod_addr_space dra7xx_gpmc_addrs[] = {
2908 {
2909 .pa_start = 0x50000000,
2910 .pa_end = 0x500003ff,
2911 .flags = ADDR_TYPE_RT
2912 },
2913 { }
2914 };
2916 /* l3_main_1 -> gpmc */
2917 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
2918 .master = &dra7xx_l3_main_1_hwmod,
2919 .slave = &dra7xx_gpmc_hwmod,
2920 .clk = "l3_iclk_div",
2921 .addr = dra7xx_gpmc_addrs,
2922 .user = OCP_USER_MPU | OCP_USER_SDMA,
2923 };
2925 static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
2926 {
2927 .pa_start = 0x480b2000,
2928 .pa_end = 0x480b201f,
2929 .flags = ADDR_TYPE_RT
2930 },
2931 { }
2932 };
2934 /* l4_per1 -> hdq1w */
2935 static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
2936 .master = &dra7xx_l4_per1_hwmod,
2937 .slave = &dra7xx_hdq1w_hwmod,
2938 .clk = "l3_iclk_div",
2939 .addr = dra7xx_hdq1w_addrs,
2940 .user = OCP_USER_MPU | OCP_USER_SDMA,
2941 };
2943 /* l4_per1 -> i2c1 */
2944 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
2945 .master = &dra7xx_l4_per1_hwmod,
2946 .slave = &dra7xx_i2c1_hwmod,
2947 .clk = "l3_iclk_div",
2948 .user = OCP_USER_MPU | OCP_USER_SDMA,
2949 };
2951 /* l4_per1 -> i2c2 */
2952 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
2953 .master = &dra7xx_l4_per1_hwmod,
2954 .slave = &dra7xx_i2c2_hwmod,
2955 .clk = "l3_iclk_div",
2956 .user = OCP_USER_MPU | OCP_USER_SDMA,
2957 };
2959 /* l4_per1 -> i2c3 */
2960 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
2961 .master = &dra7xx_l4_per1_hwmod,
2962 .slave = &dra7xx_i2c3_hwmod,
2963 .clk = "l3_iclk_div",
2964 .user = OCP_USER_MPU | OCP_USER_SDMA,
2965 };
2967 /* l4_per1 -> i2c4 */
2968 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
2969 .master = &dra7xx_l4_per1_hwmod,
2970 .slave = &dra7xx_i2c4_hwmod,
2971 .clk = "l3_iclk_div",
2972 .user = OCP_USER_MPU | OCP_USER_SDMA,
2973 };
2975 /* l4_per1 -> i2c5 */
2976 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
2977 .master = &dra7xx_l4_per1_hwmod,
2978 .slave = &dra7xx_i2c5_hwmod,
2979 .clk = "l3_iclk_div",
2980 .user = OCP_USER_MPU | OCP_USER_SDMA,
2981 };
2983 /* l4_cfg -> mailbox1 */
2984 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
2985 .master = &dra7xx_l4_cfg_hwmod,
2986 .slave = &dra7xx_mailbox1_hwmod,
2987 .clk = "l3_iclk_div",
2988 .user = OCP_USER_MPU | OCP_USER_SDMA,
2989 };
2991 /* l4_per3 -> mailbox2 */
2992 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
2993 .master = &dra7xx_l4_per3_hwmod,
2994 .slave = &dra7xx_mailbox2_hwmod,
2995 .clk = "l3_iclk_div",
2996 .user = OCP_USER_MPU | OCP_USER_SDMA,
2997 };
2999 /* l4_per3 -> mailbox3 */
3000 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
3001 .master = &dra7xx_l4_per3_hwmod,
3002 .slave = &dra7xx_mailbox3_hwmod,
3003 .clk = "l3_iclk_div",
3004 .user = OCP_USER_MPU | OCP_USER_SDMA,
3005 };
3007 /* l4_per3 -> mailbox4 */
3008 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
3009 .master = &dra7xx_l4_per3_hwmod,
3010 .slave = &dra7xx_mailbox4_hwmod,
3011 .clk = "l3_iclk_div",
3012 .user = OCP_USER_MPU | OCP_USER_SDMA,
3013 };
3015 /* l4_per3 -> mailbox5 */
3016 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
3017 .master = &dra7xx_l4_per3_hwmod,
3018 .slave = &dra7xx_mailbox5_hwmod,
3019 .clk = "l3_iclk_div",
3020 .user = OCP_USER_MPU | OCP_USER_SDMA,
3021 };
3023 /* l4_per3 -> mailbox6 */
3024 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
3025 .master = &dra7xx_l4_per3_hwmod,
3026 .slave = &dra7xx_mailbox6_hwmod,
3027 .clk = "l3_iclk_div",
3028 .user = OCP_USER_MPU | OCP_USER_SDMA,
3029 };
3031 /* l4_per3 -> mailbox7 */
3032 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
3033 .master = &dra7xx_l4_per3_hwmod,
3034 .slave = &dra7xx_mailbox7_hwmod,
3035 .clk = "l3_iclk_div",
3036 .user = OCP_USER_MPU | OCP_USER_SDMA,
3037 };
3039 /* l4_per3 -> mailbox8 */
3040 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
3041 .master = &dra7xx_l4_per3_hwmod,
3042 .slave = &dra7xx_mailbox8_hwmod,
3043 .clk = "l3_iclk_div",
3044 .user = OCP_USER_MPU | OCP_USER_SDMA,
3045 };
3047 /* l4_per3 -> mailbox9 */
3048 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
3049 .master = &dra7xx_l4_per3_hwmod,
3050 .slave = &dra7xx_mailbox9_hwmod,
3051 .clk = "l3_iclk_div",
3052 .user = OCP_USER_MPU | OCP_USER_SDMA,
3053 };
3055 /* l4_per3 -> mailbox10 */
3056 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
3057 .master = &dra7xx_l4_per3_hwmod,
3058 .slave = &dra7xx_mailbox10_hwmod,
3059 .clk = "l3_iclk_div",
3060 .user = OCP_USER_MPU | OCP_USER_SDMA,
3061 };
3063 /* l4_per3 -> mailbox11 */
3064 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
3065 .master = &dra7xx_l4_per3_hwmod,
3066 .slave = &dra7xx_mailbox11_hwmod,
3067 .clk = "l3_iclk_div",
3068 .user = OCP_USER_MPU | OCP_USER_SDMA,
3069 };
3071 /* l4_per3 -> mailbox12 */
3072 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
3073 .master = &dra7xx_l4_per3_hwmod,
3074 .slave = &dra7xx_mailbox12_hwmod,
3075 .clk = "l3_iclk_div",
3076 .user = OCP_USER_MPU | OCP_USER_SDMA,
3077 };
3079 /* l4_per3 -> mailbox13 */
3080 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
3081 .master = &dra7xx_l4_per3_hwmod,
3082 .slave = &dra7xx_mailbox13_hwmod,
3083 .clk = "l3_iclk_div",
3084 .user = OCP_USER_MPU | OCP_USER_SDMA,
3085 };
3087 /* l4_per1 -> mcspi1 */
3088 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
3089 .master = &dra7xx_l4_per1_hwmod,
3090 .slave = &dra7xx_mcspi1_hwmod,
3091 .clk = "l3_iclk_div",
3092 .user = OCP_USER_MPU | OCP_USER_SDMA,
3093 };
3095 /* l4_per1 -> mcspi2 */
3096 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
3097 .master = &dra7xx_l4_per1_hwmod,
3098 .slave = &dra7xx_mcspi2_hwmod,
3099 .clk = "l3_iclk_div",
3100 .user = OCP_USER_MPU | OCP_USER_SDMA,
3101 };
3103 /* l4_per1 -> mcspi3 */
3104 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
3105 .master = &dra7xx_l4_per1_hwmod,
3106 .slave = &dra7xx_mcspi3_hwmod,
3107 .clk = "l3_iclk_div",
3108 .user = OCP_USER_MPU | OCP_USER_SDMA,
3109 };
3111 /* l4_per1 -> mcspi4 */
3112 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
3113 .master = &dra7xx_l4_per1_hwmod,
3114 .slave = &dra7xx_mcspi4_hwmod,
3115 .clk = "l3_iclk_div",
3116 .user = OCP_USER_MPU | OCP_USER_SDMA,
3117 };
3119 /* l4_per1 -> mmc1 */
3120 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
3121 .master = &dra7xx_l4_per1_hwmod,
3122 .slave = &dra7xx_mmc1_hwmod,
3123 .clk = "l3_iclk_div",
3124 .user = OCP_USER_MPU | OCP_USER_SDMA,
3125 };
3127 /* l4_per1 -> mmc2 */
3128 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
3129 .master = &dra7xx_l4_per1_hwmod,
3130 .slave = &dra7xx_mmc2_hwmod,
3131 .clk = "l3_iclk_div",
3132 .user = OCP_USER_MPU | OCP_USER_SDMA,
3133 };
3135 /* l4_per1 -> mmc3 */
3136 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
3137 .master = &dra7xx_l4_per1_hwmod,
3138 .slave = &dra7xx_mmc3_hwmod,
3139 .clk = "l3_iclk_div",
3140 .user = OCP_USER_MPU | OCP_USER_SDMA,
3141 };
3143 /* l4_per1 -> mmc4 */
3144 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
3145 .master = &dra7xx_l4_per1_hwmod,
3146 .slave = &dra7xx_mmc4_hwmod,
3147 .clk = "l3_iclk_div",
3148 .user = OCP_USER_MPU | OCP_USER_SDMA,
3149 };
3151 /* l4_cfg -> mpu */
3152 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
3153 .master = &dra7xx_l4_cfg_hwmod,
3154 .slave = &dra7xx_mpu_hwmod,
3155 .clk = "l3_iclk_div",
3156 .user = OCP_USER_MPU | OCP_USER_SDMA,
3157 };
3159 /* l4_cfg -> ocp2scp1 */
3160 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
3161 .master = &dra7xx_l4_cfg_hwmod,
3162 .slave = &dra7xx_ocp2scp1_hwmod,
3163 .clk = "l4_root_clk_div",
3164 .user = OCP_USER_MPU | OCP_USER_SDMA,
3165 };
3167 static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
3168 {
3169 .pa_start = 0x4b300000,
3170 .pa_end = 0x4b30007f,
3171 .flags = ADDR_TYPE_RT
3172 },
3173 { }
3174 };
3176 /* l3_main_1 -> qspi */
3177 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
3178 .master = &dra7xx_l3_main_1_hwmod,
3179 .slave = &dra7xx_qspi_hwmod,
3180 .clk = "l3_iclk_div",
3181 .addr = dra7xx_qspi_addrs,
3182 .user = OCP_USER_MPU | OCP_USER_SDMA,
3183 };
3185 /* l4_per3 -> rtcss */
3186 static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
3187 .master = &dra7xx_l4_per3_hwmod,
3188 .slave = &dra7xx_rtcss_hwmod,
3189 .clk = "l4_root_clk_div",
3190 .user = OCP_USER_MPU | OCP_USER_SDMA,
3191 };
3193 static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
3194 {
3195 .name = "sysc",
3196 .pa_start = 0x4a141100,
3197 .pa_end = 0x4a141107,
3198 .flags = ADDR_TYPE_RT
3199 },
3200 { }
3201 };
3203 /* l4_cfg -> sata */
3204 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
3205 .master = &dra7xx_l4_cfg_hwmod,
3206 .slave = &dra7xx_sata_hwmod,
3207 .clk = "l3_iclk_div",
3208 .addr = dra7xx_sata_addrs,
3209 .user = OCP_USER_MPU | OCP_USER_SDMA,
3210 };
3212 static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
3213 {
3214 .pa_start = 0x4a0dd000,
3215 .pa_end = 0x4a0dd07f,
3216 .flags = ADDR_TYPE_RT
3217 },
3218 { }
3219 };
3221 /* l4_cfg -> smartreflex_core */
3222 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
3223 .master = &dra7xx_l4_cfg_hwmod,
3224 .slave = &dra7xx_smartreflex_core_hwmod,
3225 .clk = "l4_root_clk_div",
3226 .addr = dra7xx_smartreflex_core_addrs,
3227 .user = OCP_USER_MPU | OCP_USER_SDMA,
3228 };
3230 static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
3231 {
3232 .pa_start = 0x4a0d9000,
3233 .pa_end = 0x4a0d907f,
3234 .flags = ADDR_TYPE_RT
3235 },
3236 { }
3237 };
3239 /* l4_cfg -> smartreflex_mpu */
3240 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
3241 .master = &dra7xx_l4_cfg_hwmod,
3242 .slave = &dra7xx_smartreflex_mpu_hwmod,
3243 .clk = "l4_root_clk_div",
3244 .addr = dra7xx_smartreflex_mpu_addrs,
3245 .user = OCP_USER_MPU | OCP_USER_SDMA,
3246 };
3248 static struct omap_hwmod_addr_space dra7xx_spinlock_addrs[] = {
3249 {
3250 .pa_start = 0x4a0f6000,
3251 .pa_end = 0x4a0f6fff,
3252 .flags = ADDR_TYPE_RT
3253 },
3254 { }
3255 };
3257 /* l4_cfg -> spinlock */
3258 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
3259 .master = &dra7xx_l4_cfg_hwmod,
3260 .slave = &dra7xx_spinlock_hwmod,
3261 .clk = "l3_iclk_div",
3262 .addr = dra7xx_spinlock_addrs,
3263 .user = OCP_USER_MPU | OCP_USER_SDMA,
3264 };
3266 /* l4_wkup -> timer1 */
3267 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
3268 .master = &dra7xx_l4_wkup_hwmod,
3269 .slave = &dra7xx_timer1_hwmod,
3270 .clk = "wkupaon_iclk_mux",
3271 .user = OCP_USER_MPU | OCP_USER_SDMA,
3272 };
3274 /* l4_per1 -> timer2 */
3275 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
3276 .master = &dra7xx_l4_per1_hwmod,
3277 .slave = &dra7xx_timer2_hwmod,
3278 .clk = "l3_iclk_div",
3279 .user = OCP_USER_MPU | OCP_USER_SDMA,
3280 };
3282 /* l4_per1 -> timer3 */
3283 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
3284 .master = &dra7xx_l4_per1_hwmod,
3285 .slave = &dra7xx_timer3_hwmod,
3286 .clk = "l3_iclk_div",
3287 .user = OCP_USER_MPU | OCP_USER_SDMA,
3288 };
3290 /* l4_per1 -> timer4 */
3291 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
3292 .master = &dra7xx_l4_per1_hwmod,
3293 .slave = &dra7xx_timer4_hwmod,
3294 .clk = "l3_iclk_div",
3295 .user = OCP_USER_MPU | OCP_USER_SDMA,
3296 };
3298 /* l4_per3 -> timer5 */
3299 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
3300 .master = &dra7xx_l4_per3_hwmod,
3301 .slave = &dra7xx_timer5_hwmod,
3302 .clk = "l3_iclk_div",
3303 .user = OCP_USER_MPU | OCP_USER_SDMA,
3304 };
3306 /* l4_per3 -> timer6 */
3307 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
3308 .master = &dra7xx_l4_per3_hwmod,
3309 .slave = &dra7xx_timer6_hwmod,
3310 .clk = "l3_iclk_div",
3311 .user = OCP_USER_MPU | OCP_USER_SDMA,
3312 };
3314 /* l4_per3 -> timer7 */
3315 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
3316 .master = &dra7xx_l4_per3_hwmod,
3317 .slave = &dra7xx_timer7_hwmod,
3318 .clk = "l3_iclk_div",
3319 .user = OCP_USER_MPU | OCP_USER_SDMA,
3320 };
3322 /* l4_per3 -> timer8 */
3323 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
3324 .master = &dra7xx_l4_per3_hwmod,
3325 .slave = &dra7xx_timer8_hwmod,
3326 .clk = "l3_iclk_div",
3327 .user = OCP_USER_MPU | OCP_USER_SDMA,
3328 };
3330 /* l4_per1 -> timer9 */
3331 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
3332 .master = &dra7xx_l4_per1_hwmod,
3333 .slave = &dra7xx_timer9_hwmod,
3334 .clk = "l3_iclk_div",
3335 .user = OCP_USER_MPU | OCP_USER_SDMA,
3336 };
3338 /* l4_per1 -> timer10 */
3339 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
3340 .master = &dra7xx_l4_per1_hwmod,
3341 .slave = &dra7xx_timer10_hwmod,
3342 .clk = "l3_iclk_div",
3343 .user = OCP_USER_MPU | OCP_USER_SDMA,
3344 };
3346 /* l4_per1 -> timer11 */
3347 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
3348 .master = &dra7xx_l4_per1_hwmod,
3349 .slave = &dra7xx_timer11_hwmod,
3350 .clk = "l3_iclk_div",
3351 .user = OCP_USER_MPU | OCP_USER_SDMA,
3352 };
3354 /* l4_wkup -> timer12 */
3355 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer12 = {
3356 .master = &dra7xx_l4_wkup_hwmod,
3357 .slave = &dra7xx_timer12_hwmod,
3358 .clk = "wkupaon_iclk_mux",
3359 .user = OCP_USER_MPU | OCP_USER_SDMA,
3360 };
3362 /* l4_per3 -> timer13 */
3363 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
3364 .master = &dra7xx_l4_per3_hwmod,
3365 .slave = &dra7xx_timer13_hwmod,
3366 .clk = "l3_iclk_div",
3367 .user = OCP_USER_MPU | OCP_USER_SDMA,
3368 };
3370 /* l4_per3 -> timer14 */
3371 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
3372 .master = &dra7xx_l4_per3_hwmod,
3373 .slave = &dra7xx_timer14_hwmod,
3374 .clk = "l3_iclk_div",
3375 .user = OCP_USER_MPU | OCP_USER_SDMA,
3376 };
3378 /* l4_per3 -> timer15 */
3379 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
3380 .master = &dra7xx_l4_per3_hwmod,
3381 .slave = &dra7xx_timer15_hwmod,
3382 .clk = "l3_iclk_div",
3383 .user = OCP_USER_MPU | OCP_USER_SDMA,
3384 };
3386 /* l4_per3 -> timer16 */
3387 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
3388 .master = &dra7xx_l4_per3_hwmod,
3389 .slave = &dra7xx_timer16_hwmod,
3390 .clk = "l3_iclk_div",
3391 .user = OCP_USER_MPU | OCP_USER_SDMA,
3392 };
3394 /* l4_per1 -> uart1 */
3395 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
3396 .master = &dra7xx_l4_per1_hwmod,
3397 .slave = &dra7xx_uart1_hwmod,
3398 .clk = "l3_iclk_div",
3399 .user = OCP_USER_MPU | OCP_USER_SDMA,
3400 };
3402 /* l4_per1 -> uart2 */
3403 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
3404 .master = &dra7xx_l4_per1_hwmod,
3405 .slave = &dra7xx_uart2_hwmod,
3406 .clk = "l3_iclk_div",
3407 .user = OCP_USER_MPU | OCP_USER_SDMA,
3408 };
3410 /* l4_per1 -> uart3 */
3411 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
3412 .master = &dra7xx_l4_per1_hwmod,
3413 .slave = &dra7xx_uart3_hwmod,
3414 .clk = "l3_iclk_div",
3415 .user = OCP_USER_MPU | OCP_USER_SDMA,
3416 };
3418 /* l4_per1 -> uart4 */
3419 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
3420 .master = &dra7xx_l4_per1_hwmod,
3421 .slave = &dra7xx_uart4_hwmod,
3422 .clk = "l3_iclk_div",
3423 .user = OCP_USER_MPU | OCP_USER_SDMA,
3424 };
3426 /* l4_per1 -> uart5 */
3427 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
3428 .master = &dra7xx_l4_per1_hwmod,
3429 .slave = &dra7xx_uart5_hwmod,
3430 .clk = "l3_iclk_div",
3431 .user = OCP_USER_MPU | OCP_USER_SDMA,
3432 };
3434 /* l4_per1 -> uart6 */
3435 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
3436 .master = &dra7xx_l4_per1_hwmod,
3437 .slave = &dra7xx_uart6_hwmod,
3438 .clk = "l3_iclk_div",
3439 .user = OCP_USER_MPU | OCP_USER_SDMA,
3440 };
3442 /* l4_per2 -> uart7 */
3443 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
3444 .master = &dra7xx_l4_per2_hwmod,
3445 .slave = &dra7xx_uart7_hwmod,
3446 .clk = "l3_iclk_div",
3447 .user = OCP_USER_MPU | OCP_USER_SDMA,
3448 };
3450 /* l4_per2 -> uart8 */
3451 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
3452 .master = &dra7xx_l4_per2_hwmod,
3453 .slave = &dra7xx_uart8_hwmod,
3454 .clk = "l3_iclk_div",
3455 .user = OCP_USER_MPU | OCP_USER_SDMA,
3456 };
3458 /* l4_per2 -> uart9 */
3459 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
3460 .master = &dra7xx_l4_per2_hwmod,
3461 .slave = &dra7xx_uart9_hwmod,
3462 .clk = "l3_iclk_div",
3463 .user = OCP_USER_MPU | OCP_USER_SDMA,
3464 };
3466 /* l4_wkup -> uart10 */
3467 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
3468 .master = &dra7xx_l4_wkup_hwmod,
3469 .slave = &dra7xx_uart10_hwmod,
3470 .clk = "wkupaon_iclk_mux",
3471 .user = OCP_USER_MPU | OCP_USER_SDMA,
3472 };
3474 /* l4_per1 -> des */
3475 static struct omap_hwmod_ocp_if dra7xx_l4_per1__des = {
3476 .master = &dra7xx_l4_per1_hwmod,
3477 .slave = &dra7xx_des_hwmod,
3478 .clk = "l3_iclk_div",
3479 .user = OCP_USER_MPU | OCP_USER_SDMA,
3480 };
3482 /* l4_per1 -> rng */
3483 static struct omap_hwmod_ocp_if dra7xx_l4_per1__rng = {
3484 .master = &dra7xx_l4_per1_hwmod,
3485 .slave = &dra7xx_rng_hwmod,
3486 .user = OCP_USER_MPU,
3487 };
3489 /* l4_per3 -> usb_otg_ss1 */
3490 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
3491 .master = &dra7xx_l4_per3_hwmod,
3492 .slave = &dra7xx_usb_otg_ss1_hwmod,
3493 .clk = "dpll_core_h13x2_ck",
3494 .user = OCP_USER_MPU | OCP_USER_SDMA,
3495 };
3497 /* l4_per3 -> usb_otg_ss2 */
3498 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
3499 .master = &dra7xx_l4_per3_hwmod,
3500 .slave = &dra7xx_usb_otg_ss2_hwmod,
3501 .clk = "dpll_core_h13x2_ck",
3502 .user = OCP_USER_MPU | OCP_USER_SDMA,
3503 };
3505 /* l4_per3 -> usb_otg_ss3 */
3506 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
3507 .master = &dra7xx_l4_per3_hwmod,
3508 .slave = &dra7xx_usb_otg_ss3_hwmod,
3509 .clk = "dpll_core_h13x2_ck",
3510 .user = OCP_USER_MPU | OCP_USER_SDMA,
3511 };
3513 /* l4_per3 -> usb_otg_ss4 */
3514 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
3515 .master = &dra7xx_l4_per3_hwmod,
3516 .slave = &dra7xx_usb_otg_ss4_hwmod,
3517 .clk = "dpll_core_h13x2_ck",
3518 .user = OCP_USER_MPU | OCP_USER_SDMA,
3519 };
3521 /* l3_main_1 -> vcp1 */
3522 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
3523 .master = &dra7xx_l3_main_1_hwmod,
3524 .slave = &dra7xx_vcp1_hwmod,
3525 .clk = "l3_iclk_div",
3526 .user = OCP_USER_MPU | OCP_USER_SDMA,
3527 };
3529 /* l4_per2 -> vcp1 */
3530 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
3531 .master = &dra7xx_l4_per2_hwmod,
3532 .slave = &dra7xx_vcp1_hwmod,
3533 .clk = "l3_iclk_div",
3534 .user = OCP_USER_MPU | OCP_USER_SDMA,
3535 };
3537 /* l3_main_1 -> vcp2 */
3538 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
3539 .master = &dra7xx_l3_main_1_hwmod,
3540 .slave = &dra7xx_vcp2_hwmod,
3541 .clk = "l3_iclk_div",
3542 .user = OCP_USER_MPU | OCP_USER_SDMA,
3543 };
3545 /* l4_per2 -> vcp2 */
3546 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
3547 .master = &dra7xx_l4_per2_hwmod,
3548 .slave = &dra7xx_vcp2_hwmod,
3549 .clk = "l3_iclk_div",
3550 .user = OCP_USER_MPU | OCP_USER_SDMA,
3551 };
3553 /* l4_wkup -> wd_timer2 */
3554 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
3555 .master = &dra7xx_l4_wkup_hwmod,
3556 .slave = &dra7xx_wd_timer2_hwmod,
3557 .clk = "wkupaon_iclk_mux",
3558 .user = OCP_USER_MPU | OCP_USER_SDMA,
3559 };
3561 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
3562 &dra7xx_l3_main_2__l3_instr,
3563 &dra7xx_l4_cfg__l3_main_1,
3564 &dra7xx_mpu__l3_main_1,
3565 &dra7xx_l3_main_1__l3_main_2,
3566 &dra7xx_l4_cfg__l3_main_2,
3567 &dra7xx_l3_main_1__l4_cfg,
3568 &dra7xx_l3_main_1__l4_per1,
3569 &dra7xx_l3_main_1__l4_per2,
3570 &dra7xx_l3_main_1__l4_per3,
3571 &dra7xx_l3_main_1__l4_wkup,
3572 &dra7xx_l4_per2__atl,
3573 &dra7xx_l3_main_1__bb2d,
3574 &dra7xx_l4_wkup__counter_32k,
3575 &dra7xx_l4_wkup__ctrl_module_wkup,
3576 &dra7xx_l4_wkup__dcan1,
3577 &dra7xx_l4_per2__dcan2,
3578 &dra7xx_l4_cfg__dma_system,
3579 &dra7xx_l3_main_1__dss,
3580 &dra7xx_l3_main_1__dispc,
3581 &dra7xx_l3_main_1__hdmi,
3582 &dra7xx_l3_main_1__aes1,
3583 &dra7xx_l3_main_1__aes2,
3584 &dra7xx_l3_main_1__sha0,
3585 &dra7xx_l4_per1__elm,
3586 &dra7xx_l4_wkup__gpio1,
3587 &dra7xx_l4_per1__gpio2,
3588 &dra7xx_l4_per1__gpio3,
3589 &dra7xx_l4_per1__gpio4,
3590 &dra7xx_l4_per1__gpio5,
3591 &dra7xx_l4_per1__gpio6,
3592 &dra7xx_l4_per1__gpio7,
3593 &dra7xx_l4_per1__gpio8,
3594 &dra7xx_l3_main_1__gpmc,
3595 &dra7xx_l4_per1__hdq1w,
3596 &dra7xx_l4_per1__i2c1,
3597 &dra7xx_l4_per1__i2c2,
3598 &dra7xx_l4_per1__i2c3,
3599 &dra7xx_l4_per1__i2c4,
3600 &dra7xx_l4_per1__i2c5,
3601 &dra7xx_l4_cfg__mailbox1,
3602 &dra7xx_l4_per3__mailbox2,
3603 &dra7xx_l4_per3__mailbox3,
3604 &dra7xx_l4_per3__mailbox4,
3605 &dra7xx_l4_per3__mailbox5,
3606 &dra7xx_l4_per3__mailbox6,
3607 &dra7xx_l4_per3__mailbox7,
3608 &dra7xx_l4_per3__mailbox8,
3609 &dra7xx_l4_per3__mailbox9,
3610 &dra7xx_l4_per3__mailbox10,
3611 &dra7xx_l4_per3__mailbox11,
3612 &dra7xx_l4_per3__mailbox12,
3613 &dra7xx_l4_per3__mailbox13,
3614 &dra7xx_l4_per1__mcspi1,
3615 &dra7xx_l4_per1__mcspi2,
3616 &dra7xx_l4_per1__mcspi3,
3617 &dra7xx_l4_per1__mcspi4,
3618 &dra7xx_l4_per1__mmc1,
3619 &dra7xx_l4_per1__mmc2,
3620 &dra7xx_l4_per1__mmc3,
3621 &dra7xx_l4_per1__mmc4,
3622 &dra7xx_l4_cfg__mpu,
3623 &dra7xx_l4_cfg__ocp2scp1,
3624 &dra7xx_l3_main_1__qspi,
3625 &dra7xx_l4_per3__rtcss,
3626 &dra7xx_l4_cfg__sata,
3627 &dra7xx_l4_cfg__smartreflex_core,
3628 &dra7xx_l4_cfg__smartreflex_mpu,
3629 &dra7xx_l4_cfg__spinlock,
3630 &dra7xx_l4_wkup__timer1,
3631 &dra7xx_l4_per1__timer2,
3632 &dra7xx_l4_per1__timer3,
3633 &dra7xx_l4_per1__timer4,
3634 &dra7xx_l4_per3__timer5,
3635 &dra7xx_l4_per3__timer6,
3636 &dra7xx_l4_per3__timer7,
3637 &dra7xx_l4_per3__timer8,
3638 &dra7xx_l4_per1__timer9,
3639 &dra7xx_l4_per1__timer10,
3640 &dra7xx_l4_per1__timer11,
3641 &dra7xx_l4_wkup__timer12,
3642 &dra7xx_l4_per3__timer13,
3643 &dra7xx_l4_per3__timer14,
3644 &dra7xx_l4_per3__timer15,
3645 &dra7xx_l4_per3__timer16,
3646 &dra7xx_l4_per1__uart1,
3647 &dra7xx_l4_per1__uart2,
3648 &dra7xx_l4_per1__uart3,
3649 &dra7xx_l4_per1__uart4,
3650 &dra7xx_l4_per1__uart5,
3651 &dra7xx_l4_per1__uart6,
3652 &dra7xx_l4_per2__uart7,
3653 &dra7xx_l4_per2__uart8,
3654 &dra7xx_l4_per2__uart9,
3655 &dra7xx_l4_wkup__uart10,
3656 &dra7xx_l4_per1__des,
3657 &dra7xx_l4_per1__rng,
3658 &dra7xx_l4_per3__usb_otg_ss1,
3659 &dra7xx_l4_per3__usb_otg_ss2,
3660 &dra7xx_l4_per3__usb_otg_ss3,
3661 &dra7xx_l3_main_1__vcp1,
3662 &dra7xx_l4_per2__vcp1,
3663 &dra7xx_l3_main_1__vcp2,
3664 &dra7xx_l4_per2__vcp2,
3665 &dra7xx_l4_wkup__wd_timer2,
3666 &dra7xx_l4_per2__epwmss0,
3667 &dra7xx_epwmss0__ecap0,
3668 &dra7xx_epwmss0__eqep0,
3669 &dra7xx_epwmss0__ehrpwm0,
3670 &dra7xx_l4_per2__epwmss1,
3671 &dra7xx_epwmss1__ecap1,
3672 &dra7xx_epwmss1__eqep1,
3673 &dra7xx_epwmss1__ehrpwm1,
3674 &dra7xx_l4_per2__epwmss2,
3675 &dra7xx_epwmss2__ecap2,
3676 &dra7xx_epwmss2__eqep2,
3677 &dra7xx_epwmss2__ehrpwm2,
3678 NULL,
3679 };
3681 static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
3682 &dra7xx_l4_per3__usb_otg_ss4,
3683 NULL,
3684 };
3686 static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
3687 NULL,
3688 };
3690 int __init dra7xx_hwmod_init(void)
3691 {
3692 int ret;
3694 omap_hwmod_init();
3695 ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
3697 if (!ret && soc_is_dra74x())
3698 return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
3699 else if (!ret && soc_is_dra72x())
3700 return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
3702 return ret;
3703 }