1 /*
2 * Hardware modules present on the DRA7xx chips
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley
7 * Benoit Cousson
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
20 #include <linux/io.h>
21 #include <linux/platform_data/gpio-omap.h>
22 #include <linux/power/smartreflex.h>
23 #include <linux/platform_data/omap_ocp2scp.h>
24 #include <linux/i2c-omap.h>
26 #include <linux/omap-dma.h>
27 #include <linux/platform_data/spi-omap2-mcspi.h>
28 #include <linux/platform_data/asoc-ti-mcbsp.h>
29 #include <plat/dmtimer.h>
31 #include "omap_hwmod.h"
32 #include "omap_hwmod_common_data.h"
33 #include "cm1_7xx.h"
34 #include "cm2_7xx.h"
35 #include "prm7xx.h"
36 #include "prm-regbits-7xx.h"
37 #include "i2c.h"
38 #include "mmc.h"
39 #include "wd_timer.h"
41 /* Base offset for all DRA7XX interrupts external to MPUSS */
42 #define DRA7XX_IRQ_GIC_START 32
44 /* Base offset for all DRA7XX dma requests */
45 #define DRA7XX_DMA_REQ_START 1
48 /*
49 * IP blocks
50 */
52 /*
53 * 'dmm' class
54 * instance(s): dmm
55 */
56 static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
57 .name = "dmm",
58 };
60 /* dmm */
61 static struct omap_hwmod_irq_info dra7xx_dmm_irqs[] = {
62 { .irq = 113 + DRA7XX_IRQ_GIC_START },
63 { .irq = -1 }
64 };
66 static struct omap_hwmod dra7xx_dmm_hwmod = {
67 .name = "dmm",
68 .class = &dra7xx_dmm_hwmod_class,
69 .clkdm_name = "emif_clkdm",
70 .mpu_irqs = dra7xx_dmm_irqs,
71 .prcm = {
72 .omap4 = {
73 .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
74 .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
75 },
76 },
77 };
79 /*
80 * 'emif_ocp_fw' class
81 * instance(s): emif_ocp_fw
82 */
83 static struct omap_hwmod_class dra7xx_emif_ocp_fw_hwmod_class = {
84 .name = "emif_ocp_fw",
85 };
87 /* emif_ocp_fw */
88 static struct omap_hwmod dra7xx_emif_ocp_fw_hwmod = {
89 .name = "emif_ocp_fw",
90 .class = &dra7xx_emif_ocp_fw_hwmod_class,
91 .clkdm_name = "emif_clkdm",
92 .prcm = {
93 .omap4 = {
94 .clkctrl_offs = DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET,
95 .context_offs = DRA7XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET,
96 },
97 },
98 };
100 /*
101 * 'l3' class
102 * instance(s): l3_instr, l3_main_1, l3_main_2
103 */
104 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
105 .name = "l3",
106 };
108 /* l3_instr */
109 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
110 .name = "l3_instr",
111 .class = &dra7xx_l3_hwmod_class,
112 .clkdm_name = "l3instr_clkdm",
113 .prcm = {
114 .omap4 = {
115 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
116 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
117 .modulemode = MODULEMODE_HWCTRL,
118 },
119 },
120 };
122 /* l3_main_1 */
123 static struct omap_hwmod_irq_info dra7xx_l3_main_1_irqs[] = {
124 { .name = "dbg_err", .irq = 9 + DRA7XX_IRQ_GIC_START },
125 { .name = "app_err", .irq = 10 + DRA7XX_IRQ_GIC_START },
126 { .name = "stat_alarm", .irq = 16 + DRA7XX_IRQ_GIC_START },
127 { .irq = -1 }
128 };
130 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
131 .name = "l3_main_1",
132 .class = &dra7xx_l3_hwmod_class,
133 .clkdm_name = "l3main1_clkdm",
134 .mpu_irqs = dra7xx_l3_main_1_irqs,
135 .prcm = {
136 .omap4 = {
137 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
138 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
139 },
140 },
141 };
143 /* l3_main_2 */
144 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
145 .name = "l3_main_2",
146 .class = &dra7xx_l3_hwmod_class,
147 .clkdm_name = "l3instr_clkdm",
148 .prcm = {
149 .omap4 = {
150 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
151 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
152 .modulemode = MODULEMODE_HWCTRL,
153 },
154 },
155 };
157 /*
158 * 'l4' class
159 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
160 */
161 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
162 .name = "l4",
163 };
165 /* l4_cfg */
166 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
167 .name = "l4_cfg",
168 .class = &dra7xx_l4_hwmod_class,
169 .clkdm_name = "l4cfg_clkdm",
170 .prcm = {
171 .omap4 = {
172 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
173 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
174 },
175 },
176 };
178 /* l4_per1 */
179 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
180 .name = "l4_per1",
181 .class = &dra7xx_l4_hwmod_class,
182 .clkdm_name = "l4per_clkdm",
183 .prcm = {
184 .omap4 = {
185 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
186 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
187 },
188 },
189 };
191 /* l4_per2 */
192 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
193 .name = "l4_per2",
194 .class = &dra7xx_l4_hwmod_class,
195 .clkdm_name = "l4per2_clkdm",
196 .prcm = {
197 .omap4 = {
198 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
199 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
200 },
201 },
202 };
204 /* l4_per3 */
205 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
206 .name = "l4_per3",
207 .class = &dra7xx_l4_hwmod_class,
208 .clkdm_name = "l4per3_clkdm",
209 .prcm = {
210 .omap4 = {
211 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
212 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
213 },
214 },
215 };
217 /* l4_wkup */
218 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
219 .name = "l4_wkup",
220 .class = &dra7xx_l4_hwmod_class,
221 .clkdm_name = "wkupaon_clkdm",
222 .prcm = {
223 .omap4 = {
224 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
225 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
226 },
227 },
228 };
230 /*
231 * 'mpu_bus' class
232 * instance(s): mpu_private
233 */
234 static struct omap_hwmod_class dra7xx_mpu_bus_hwmod_class = {
235 .name = "mpu_bus",
236 };
238 /* mpu_private */
239 static struct omap_hwmod dra7xx_mpu_private_hwmod = {
240 .name = "mpu_private",
241 .class = &dra7xx_mpu_bus_hwmod_class,
242 .clkdm_name = "mpu_clkdm",
243 .prcm = {
244 .omap4 = {
245 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
246 },
247 },
248 };
250 /*
251 * 'ocp_wp_noc' class
252 * instance(s): ocp_wp_noc
253 */
254 static struct omap_hwmod_class dra7xx_ocp_wp_noc_hwmod_class = {
255 .name = "ocp_wp_noc",
256 };
258 /* ocp_wp_noc */
259 static struct omap_hwmod dra7xx_ocp_wp_noc_hwmod = {
260 .name = "ocp_wp_noc",
261 .class = &dra7xx_ocp_wp_noc_hwmod_class,
262 .clkdm_name = "l3instr_clkdm",
263 .prcm = {
264 .omap4 = {
265 .clkctrl_offs = DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET,
266 .context_offs = DRA7XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET,
267 .modulemode = MODULEMODE_HWCTRL,
268 },
269 },
270 };
272 /*
273 * 'atl' class
274 *
275 */
277 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
278 .name = "atl",
279 };
281 /* atl */
282 static struct omap_hwmod dra7xx_atl_hwmod = {
283 .name = "atl",
284 .class = &dra7xx_atl_hwmod_class,
285 .clkdm_name = "atl_clkdm",
286 .main_clk = "atl_gfclk_mux",
287 .prcm = {
288 .omap4 = {
289 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
290 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
291 .modulemode = MODULEMODE_SWCTRL,
292 },
293 },
294 };
296 /*
297 * 'bb2d' class
298 *
299 */
301 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
302 .name = "bb2d",
303 };
305 /* bb2d */
306 static struct omap_hwmod_irq_info dra7xx_bb2d_irqs[] = {
307 { .irq = 125 + DRA7XX_IRQ_GIC_START },
308 { .irq = -1 }
309 };
311 static struct omap_hwmod dra7xx_bb2d_hwmod = {
312 .name = "bb2d",
313 .class = &dra7xx_bb2d_hwmod_class,
314 .clkdm_name = "dss_clkdm",
315 .mpu_irqs = dra7xx_bb2d_irqs,
316 .main_clk = "dpll_core_h24x2_ck",
317 .prcm = {
318 .omap4 = {
319 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
320 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
321 .modulemode = MODULEMODE_SWCTRL,
322 },
323 },
324 };
326 /*
327 * 'counter' class
328 *
329 */
331 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
332 .rev_offs = 0x0000,
333 .sysc_offs = 0x0010,
334 .sysc_flags = SYSC_HAS_SIDLEMODE,
335 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
336 SIDLE_SMART_WKUP),
337 .sysc_fields = &omap_hwmod_sysc_type1,
338 };
340 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
341 .name = "counter",
342 .sysc = &dra7xx_counter_sysc,
343 };
345 /* counter_32k */
346 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
347 .name = "counter_32k",
348 .class = &dra7xx_counter_hwmod_class,
349 .clkdm_name = "wkupaon_clkdm",
350 .flags = HWMOD_SWSUP_SIDLE,
351 .main_clk = "wkupaon_iclk_mux",
352 .prcm = {
353 .omap4 = {
354 .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
355 .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
356 },
357 },
358 };
360 /*
361 * 'ctrl_module' class
362 *
363 */
365 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
366 .name = "ctrl_module",
367 };
369 /* ctrl_module_wkup */
370 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
371 .name = "ctrl_module_wkup",
372 .class = &dra7xx_ctrl_module_hwmod_class,
373 .clkdm_name = "wkupaon_clkdm",
374 .prcm = {
375 .omap4 = {
376 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
377 },
378 },
379 };
381 /*
382 * 'dcan' class
383 *
384 */
386 static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
387 .name = "dcan",
388 };
390 /* dcan1 */
391 static struct omap_hwmod dra7xx_dcan1_hwmod = {
392 .name = "dcan1",
393 .class = &dra7xx_dcan_hwmod_class,
394 .clkdm_name = "wkupaon_clkdm",
395 .main_clk = "dcan1_sys_clk_mux",
396 .prcm = {
397 .omap4 = {
398 .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
399 .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
400 .modulemode = MODULEMODE_SWCTRL,
401 },
402 },
403 };
405 /* dcan2 */
406 static struct omap_hwmod dra7xx_dcan2_hwmod = {
407 .name = "dcan2",
408 .class = &dra7xx_dcan_hwmod_class,
409 .clkdm_name = "l4per2_clkdm",
410 .main_clk = "sys_clkin1",
411 .prcm = {
412 .omap4 = {
413 .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
414 .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
415 .modulemode = MODULEMODE_SWCTRL,
416 },
417 },
418 };
420 /*
421 * 'dma' class
422 *
423 */
425 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
426 .rev_offs = 0x0000,
427 .sysc_offs = 0x002c,
428 .syss_offs = 0x0028,
429 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
430 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
431 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
432 SYSS_HAS_RESET_STATUS),
433 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
434 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
435 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
436 .sysc_fields = &omap_hwmod_sysc_type1,
437 };
439 static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
440 .name = "dma",
441 .sysc = &dra7xx_dma_sysc,
442 };
444 /* dma dev_attr */
445 static struct omap_dma_dev_attr dma_dev_attr = {
446 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
447 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
448 .lch_count = 32,
449 };
451 /* dma_system */
452 static struct omap_hwmod_irq_info dra7xx_dma_system_irqs[] = {
453 { .name = "0", .irq = 12 + DRA7XX_IRQ_GIC_START },
454 { .name = "1", .irq = 13 + DRA7XX_IRQ_GIC_START },
455 { .name = "2", .irq = 14 + DRA7XX_IRQ_GIC_START },
456 { .name = "3", .irq = 15 + DRA7XX_IRQ_GIC_START },
457 { .irq = -1 }
458 };
460 static struct omap_hwmod dra7xx_dma_system_hwmod = {
461 .name = "dma_system",
462 .class = &dra7xx_dma_hwmod_class,
463 .clkdm_name = "dma_clkdm",
464 .mpu_irqs = dra7xx_dma_system_irqs,
465 .main_clk = "l3_iclk_div",
466 .prcm = {
467 .omap4 = {
468 .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
469 .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
470 },
471 },
472 .dev_attr = &dma_dev_attr,
473 };
475 /*
476 * 'dss' class
477 *
478 */
480 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
481 .rev_offs = 0x0000,
482 .syss_offs = 0x0014,
483 .sysc_flags = SYSS_HAS_RESET_STATUS,
484 };
486 static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
487 .name = "dss",
488 .sysc = &dra7xx_dss_sysc,
489 .reset = omap_dss_reset,
490 };
492 /* dss */
493 static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
494 { .dma_req = 75 + DRA7XX_DMA_REQ_START },
495 { .dma_req = -1 }
496 };
498 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
499 { .role = "dss_clk", .clk = "dss_dss_clk" },
500 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
501 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
502 { .role = "video2_clk", .clk = "dss_video2_clk" },
503 { .role = "video1_clk", .clk = "dss_video1_clk" },
504 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
505 };
507 static struct omap_hwmod dra7xx_dss_hwmod = {
508 .name = "dss_core",
509 .class = &dra7xx_dss_hwmod_class,
510 .clkdm_name = "dss_clkdm",
511 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
512 .sdma_reqs = dra7xx_dss_sdma_reqs,
513 .main_clk = "dss_dss_clk",
514 .prcm = {
515 .omap4 = {
516 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
517 .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
518 .modulemode = MODULEMODE_SWCTRL,
519 },
520 },
521 .opt_clks = dss_opt_clks,
522 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
523 };
525 /*
526 * 'dispc' class
527 * display controller
528 */
530 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
531 .rev_offs = 0x0000,
532 .sysc_offs = 0x0010,
533 .syss_offs = 0x0014,
534 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
535 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
536 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
537 SYSS_HAS_RESET_STATUS),
538 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
539 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
540 .sysc_fields = &omap_hwmod_sysc_type1,
541 };
543 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
544 .name = "dispc",
545 .sysc = &dra7xx_dispc_sysc,
546 };
548 /* dss_dispc */
549 static struct omap_hwmod_irq_info dra7xx_dss_dispc_irqs[] = {
550 { .irq = 25 + DRA7XX_IRQ_GIC_START },
551 { .irq = -1 }
552 };
554 static struct omap_hwmod_dma_info dra7xx_dss_dispc_sdma_reqs[] = {
555 { .dma_req = 5 + DRA7XX_DMA_REQ_START },
556 { .dma_req = -1 }
557 };
559 /* dss_dispc dev_attr */
560 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
561 .has_framedonetv_irq = 1,
562 .manager_count = 4,
563 };
565 static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
566 .name = "dss_dispc",
567 .class = &dra7xx_dispc_hwmod_class,
568 .clkdm_name = "dss_clkdm",
569 .mpu_irqs = dra7xx_dss_dispc_irqs,
570 .sdma_reqs = dra7xx_dss_dispc_sdma_reqs,
571 .main_clk = "dss_dss_clk",
572 .prcm = {
573 .omap4 = {
574 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
575 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
576 },
577 },
578 .dev_attr = &dss_dispc_dev_attr,
579 };
581 /*
582 * 'hdmi' class
583 * hdmi controller
584 */
586 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
587 .rev_offs = 0x0000,
588 .sysc_offs = 0x0010,
589 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
590 SYSC_HAS_SOFTRESET),
591 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
592 SIDLE_SMART_WKUP),
593 .sysc_fields = &omap_hwmod_sysc_type2,
594 };
596 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
597 .name = "hdmi",
598 .sysc = &dra7xx_hdmi_sysc,
599 };
601 /* dss_hdmi */
602 static struct omap_hwmod_irq_info dra7xx_dss_hdmi_irqs[] = {
603 { .irq = 96 + DRA7XX_IRQ_GIC_START },
604 { .irq = -1 }
605 };
607 static struct omap_hwmod_dma_info dra7xx_dss_hdmi_sdma_reqs[] = {
608 { .dma_req = 75 + DRA7XX_DMA_REQ_START },
609 { .dma_req = -1 }
610 };
612 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
613 { .role = "sys_clk", .clk = "dss_hdmi_clk" },
614 };
616 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
617 .name = "dss_hdmi",
618 .class = &dra7xx_hdmi_hwmod_class,
619 .clkdm_name = "dss_clkdm",
620 .mpu_irqs = dra7xx_dss_hdmi_irqs,
621 .sdma_reqs = dra7xx_dss_hdmi_sdma_reqs,
622 .main_clk = "dss_48mhz_clk",
623 .prcm = {
624 .omap4 = {
625 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
626 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
627 },
628 },
629 .opt_clks = dss_hdmi_opt_clks,
630 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
631 };
633 /*
634 * 'elm' class
635 *
636 */
638 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
639 .rev_offs = 0x0000,
640 .sysc_offs = 0x0010,
641 .syss_offs = 0x0014,
642 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
643 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
644 SYSS_HAS_RESET_STATUS),
645 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
646 SIDLE_SMART_WKUP),
647 .sysc_fields = &omap_hwmod_sysc_type1,
648 };
650 static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
651 .name = "elm",
652 .sysc = &dra7xx_elm_sysc,
653 };
655 /* elm */
656 static struct omap_hwmod_irq_info dra7xx_elm_irqs[] = {
657 { .irq = 4 + DRA7XX_IRQ_GIC_START },
658 { .irq = -1 }
659 };
661 static struct omap_hwmod dra7xx_elm_hwmod = {
662 .name = "elm",
663 .class = &dra7xx_elm_hwmod_class,
664 .clkdm_name = "l4per_clkdm",
665 .mpu_irqs = dra7xx_elm_irqs,
666 .main_clk = "l3_iclk_div",
667 .prcm = {
668 .omap4 = {
669 .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
670 .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
671 },
672 },
673 };
675 /*
676 * 'emif' class
677 *
678 */
680 static struct omap_hwmod_class_sysconfig dra7xx_emif_sysc = {
681 .rev_offs = 0x0000,
682 };
684 static struct omap_hwmod_class dra7xx_emif_hwmod_class = {
685 .name = "emif",
686 .sysc = &dra7xx_emif_sysc,
687 };
689 /* emif1 */
690 static struct omap_hwmod_irq_info dra7xx_emif1_irqs[] = {
691 { .irq = 110 + DRA7XX_IRQ_GIC_START },
692 { .irq = -1 }
693 };
695 static struct omap_hwmod dra7xx_emif1_hwmod = {
696 .name = "emif1",
697 .class = &dra7xx_emif_hwmod_class,
698 .clkdm_name = "emif_clkdm",
699 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
700 .mpu_irqs = dra7xx_emif1_irqs,
701 .main_clk = "dpll_ddr_h11x2_ck",
702 .prcm = {
703 .omap4 = {
704 .clkctrl_offs = DRA7XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
705 .context_offs = DRA7XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
706 .modulemode = MODULEMODE_HWCTRL,
707 },
708 },
709 };
711 /* emif2 */
712 static struct omap_hwmod_irq_info dra7xx_emif2_irqs[] = {
713 { .irq = 111 + DRA7XX_IRQ_GIC_START },
714 { .irq = -1 }
715 };
717 static struct omap_hwmod dra7xx_emif2_hwmod = {
718 .name = "emif2",
719 .class = &dra7xx_emif_hwmod_class,
720 .clkdm_name = "emif_clkdm",
721 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
722 .mpu_irqs = dra7xx_emif2_irqs,
723 .main_clk = "dpll_ddr_h11x2_ck",
724 .prcm = {
725 .omap4 = {
726 .clkctrl_offs = DRA7XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
727 .context_offs = DRA7XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
728 .modulemode = MODULEMODE_HWCTRL,
729 },
730 },
731 };
733 /*
734 * 'gpio' class
735 *
736 */
738 static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
739 .rev_offs = 0x0000,
740 .sysc_offs = 0x0010,
741 .syss_offs = 0x0114,
742 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
743 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
744 SYSS_HAS_RESET_STATUS),
745 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
746 SIDLE_SMART_WKUP),
747 .sysc_fields = &omap_hwmod_sysc_type1,
748 };
750 static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
751 .name = "gpio",
752 .sysc = &dra7xx_gpio_sysc,
753 .rev = 2,
754 };
756 /* gpio dev_attr */
757 static struct omap_gpio_dev_attr gpio_dev_attr = {
758 .bank_width = 32,
759 .dbck_flag = true,
760 };
762 /* gpio1 */
763 static struct omap_hwmod_irq_info dra7xx_gpio1_irqs[] = {
764 { .irq = 29 + DRA7XX_IRQ_GIC_START },
765 { .irq = -1 }
766 };
768 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
769 { .role = "dbclk", .clk = "gpio1_dbclk" },
770 };
772 static struct omap_hwmod dra7xx_gpio1_hwmod = {
773 .name = "gpio1",
774 .class = &dra7xx_gpio_hwmod_class,
775 .clkdm_name = "wkupaon_clkdm",
776 .mpu_irqs = dra7xx_gpio1_irqs,
777 .main_clk = "wkupaon_iclk_mux",
778 .prcm = {
779 .omap4 = {
780 .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
781 .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
782 .modulemode = MODULEMODE_HWCTRL,
783 },
784 },
785 .opt_clks = gpio1_opt_clks,
786 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
787 .dev_attr = &gpio_dev_attr,
788 };
790 /* gpio2 */
791 static struct omap_hwmod_irq_info dra7xx_gpio2_irqs[] = {
792 { .irq = 30 + DRA7XX_IRQ_GIC_START },
793 { .irq = -1 }
794 };
796 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
797 { .role = "dbclk", .clk = "gpio2_dbclk" },
798 };
800 static struct omap_hwmod dra7xx_gpio2_hwmod = {
801 .name = "gpio2",
802 .class = &dra7xx_gpio_hwmod_class,
803 .clkdm_name = "l4per_clkdm",
804 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
805 .mpu_irqs = dra7xx_gpio2_irqs,
806 .main_clk = "l3_iclk_div",
807 .prcm = {
808 .omap4 = {
809 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
810 .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
811 .modulemode = MODULEMODE_HWCTRL,
812 },
813 },
814 .opt_clks = gpio2_opt_clks,
815 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
816 .dev_attr = &gpio_dev_attr,
817 };
819 /* gpio3 */
820 static struct omap_hwmod_irq_info dra7xx_gpio3_irqs[] = {
821 { .irq = 31 + DRA7XX_IRQ_GIC_START },
822 { .irq = -1 }
823 };
825 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
826 { .role = "dbclk", .clk = "gpio3_dbclk" },
827 };
829 static struct omap_hwmod dra7xx_gpio3_hwmod = {
830 .name = "gpio3",
831 .class = &dra7xx_gpio_hwmod_class,
832 .clkdm_name = "l4per_clkdm",
833 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
834 .mpu_irqs = dra7xx_gpio3_irqs,
835 .main_clk = "l3_iclk_div",
836 .prcm = {
837 .omap4 = {
838 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
839 .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
840 .modulemode = MODULEMODE_HWCTRL,
841 },
842 },
843 .opt_clks = gpio3_opt_clks,
844 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
845 .dev_attr = &gpio_dev_attr,
846 };
848 /* gpio4 */
849 static struct omap_hwmod_irq_info dra7xx_gpio4_irqs[] = {
850 { .irq = 32 + DRA7XX_IRQ_GIC_START },
851 { .irq = -1 }
852 };
854 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
855 { .role = "dbclk", .clk = "gpio4_dbclk" },
856 };
858 static struct omap_hwmod dra7xx_gpio4_hwmod = {
859 .name = "gpio4",
860 .class = &dra7xx_gpio_hwmod_class,
861 .clkdm_name = "l4per_clkdm",
862 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
863 .mpu_irqs = dra7xx_gpio4_irqs,
864 .main_clk = "l3_iclk_div",
865 .prcm = {
866 .omap4 = {
867 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
868 .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
869 .modulemode = MODULEMODE_HWCTRL,
870 },
871 },
872 .opt_clks = gpio4_opt_clks,
873 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
874 .dev_attr = &gpio_dev_attr,
875 };
877 /* gpio5 */
878 static struct omap_hwmod_irq_info dra7xx_gpio5_irqs[] = {
879 { .irq = 33 + DRA7XX_IRQ_GIC_START },
880 { .irq = -1 }
881 };
883 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
884 { .role = "dbclk", .clk = "gpio5_dbclk" },
885 };
887 static struct omap_hwmod dra7xx_gpio5_hwmod = {
888 .name = "gpio5",
889 .class = &dra7xx_gpio_hwmod_class,
890 .clkdm_name = "l4per_clkdm",
891 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
892 .mpu_irqs = dra7xx_gpio5_irqs,
893 .main_clk = "l3_iclk_div",
894 .prcm = {
895 .omap4 = {
896 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
897 .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
898 .modulemode = MODULEMODE_HWCTRL,
899 },
900 },
901 .opt_clks = gpio5_opt_clks,
902 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
903 .dev_attr = &gpio_dev_attr,
904 };
906 /* gpio6 */
907 static struct omap_hwmod_irq_info dra7xx_gpio6_irqs[] = {
908 { .irq = 34 + DRA7XX_IRQ_GIC_START },
909 { .irq = -1 }
910 };
912 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
913 { .role = "dbclk", .clk = "gpio6_dbclk" },
914 };
916 static struct omap_hwmod dra7xx_gpio6_hwmod = {
917 .name = "gpio6",
918 .class = &dra7xx_gpio_hwmod_class,
919 .clkdm_name = "l4per_clkdm",
920 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
921 .mpu_irqs = dra7xx_gpio6_irqs,
922 .main_clk = "l3_iclk_div",
923 .prcm = {
924 .omap4 = {
925 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
926 .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
927 .modulemode = MODULEMODE_HWCTRL,
928 },
929 },
930 .opt_clks = gpio6_opt_clks,
931 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
932 .dev_attr = &gpio_dev_attr,
933 };
935 /* gpio7 */
936 static struct omap_hwmod_irq_info dra7xx_gpio7_irqs[] = {
937 { .irq = 35 + DRA7XX_IRQ_GIC_START },
938 { .irq = -1 }
939 };
941 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
942 { .role = "dbclk", .clk = "gpio7_dbclk" },
943 };
945 static struct omap_hwmod dra7xx_gpio7_hwmod = {
946 .name = "gpio7",
947 .class = &dra7xx_gpio_hwmod_class,
948 .clkdm_name = "l4per_clkdm",
949 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
950 .mpu_irqs = dra7xx_gpio7_irqs,
951 .main_clk = "l3_iclk_div",
952 .prcm = {
953 .omap4 = {
954 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
955 .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
956 .modulemode = MODULEMODE_HWCTRL,
957 },
958 },
959 .opt_clks = gpio7_opt_clks,
960 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
961 .dev_attr = &gpio_dev_attr,
962 };
964 /* gpio8 */
965 static struct omap_hwmod_irq_info dra7xx_gpio8_irqs[] = {
966 { .irq = 121 + DRA7XX_IRQ_GIC_START },
967 { .irq = -1 }
968 };
970 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
971 { .role = "dbclk", .clk = "gpio8_dbclk" },
972 };
974 static struct omap_hwmod dra7xx_gpio8_hwmod = {
975 .name = "gpio8",
976 .class = &dra7xx_gpio_hwmod_class,
977 .clkdm_name = "l4per_clkdm",
978 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
979 .mpu_irqs = dra7xx_gpio8_irqs,
980 .main_clk = "l3_iclk_div",
981 .prcm = {
982 .omap4 = {
983 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
984 .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
985 .modulemode = MODULEMODE_HWCTRL,
986 },
987 },
988 .opt_clks = gpio8_opt_clks,
989 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
990 .dev_attr = &gpio_dev_attr,
991 };
993 /*
994 * 'gpmc' class
995 *
996 */
998 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
999 .rev_offs = 0x0000,
1000 .sysc_offs = 0x0010,
1001 .syss_offs = 0x0014,
1002 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1003 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1004 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1005 SIDLE_SMART_WKUP),
1006 .sysc_fields = &omap_hwmod_sysc_type1,
1007 };
1009 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
1010 .name = "gpmc",
1011 .sysc = &dra7xx_gpmc_sysc,
1012 };
1014 /* gpmc */
1015 static struct omap_hwmod_irq_info dra7xx_gpmc_irqs[] = {
1016 { .irq = 20 + DRA7XX_IRQ_GIC_START },
1017 { .irq = -1 }
1018 };
1020 static struct omap_hwmod_dma_info dra7xx_gpmc_sdma_reqs[] = {
1021 { .dma_req = 3 + DRA7XX_DMA_REQ_START },
1022 { .dma_req = -1 }
1023 };
1025 static struct omap_hwmod dra7xx_gpmc_hwmod = {
1026 .name = "gpmc",
1027 .class = &dra7xx_gpmc_hwmod_class,
1028 .clkdm_name = "l3main1_clkdm",
1029 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1030 .mpu_irqs = dra7xx_gpmc_irqs,
1031 .sdma_reqs = dra7xx_gpmc_sdma_reqs,
1032 .main_clk = "l3_iclk_div",
1033 .prcm = {
1034 .omap4 = {
1035 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
1036 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
1037 .modulemode = MODULEMODE_HWCTRL,
1038 },
1039 },
1040 };
1042 /*
1043 * 'gpu' class
1044 * 2d/3d graphics accelerator
1045 */
1047 static struct omap_hwmod_class_sysconfig dra7xx_gpu_sysc = {
1048 .rev_offs = 0x0000,
1049 .sysc_offs = 0x0010,
1050 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1051 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1052 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1053 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1054 .sysc_fields = &omap_hwmod_sysc_type2,
1055 };
1057 static struct omap_hwmod_class dra7xx_gpu_hwmod_class = {
1058 .name = "gpu",
1059 .sysc = &dra7xx_gpu_sysc,
1060 };
1062 /* gpu */
1063 static struct omap_hwmod_irq_info dra7xx_gpu_irqs[] = {
1064 { .irq = 21 + DRA7XX_IRQ_GIC_START },
1065 { .irq = -1 }
1066 };
1068 static struct omap_hwmod dra7xx_gpu_hwmod = {
1069 .name = "gpu",
1070 .class = &dra7xx_gpu_hwmod_class,
1071 .clkdm_name = "gpu_clkdm",
1072 .mpu_irqs = dra7xx_gpu_irqs,
1073 .main_clk = "gpu_core_gclk_mux",
1074 .prcm = {
1075 .omap4 = {
1076 .clkctrl_offs = DRA7XX_CM_GPU_GPU_CLKCTRL_OFFSET,
1077 .context_offs = DRA7XX_RM_GPU_GPU_CONTEXT_OFFSET,
1078 .modulemode = MODULEMODE_SWCTRL,
1079 },
1080 },
1081 };
1083 /*
1084 * 'hdq1w' class
1085 *
1086 */
1088 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
1089 .rev_offs = 0x0000,
1090 .sysc_offs = 0x0014,
1091 .syss_offs = 0x0018,
1092 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1093 SYSS_HAS_RESET_STATUS),
1094 .sysc_fields = &omap_hwmod_sysc_type1,
1095 };
1097 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
1098 .name = "hdq1w",
1099 .sysc = &dra7xx_hdq1w_sysc,
1100 };
1102 /* hdq1w */
1103 static struct omap_hwmod_irq_info dra7xx_hdq1w_irqs[] = {
1104 { .irq = 58 + DRA7XX_IRQ_GIC_START },
1105 { .irq = -1 }
1106 };
1108 static struct omap_hwmod dra7xx_hdq1w_hwmod = {
1109 .name = "hdq1w",
1110 .class = &dra7xx_hdq1w_hwmod_class,
1111 .clkdm_name = "l4per_clkdm",
1112 .flags = HWMOD_INIT_NO_RESET,
1113 .mpu_irqs = dra7xx_hdq1w_irqs,
1114 .main_clk = "func_12m_fclk",
1115 .prcm = {
1116 .omap4 = {
1117 .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1118 .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1119 .modulemode = MODULEMODE_SWCTRL,
1120 },
1121 },
1122 };
1124 /*
1125 * 'i2c' class
1126 *
1127 */
1129 static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
1130 .sysc_offs = 0x0010,
1131 .syss_offs = 0x0090,
1132 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1133 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1134 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1135 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1136 SIDLE_SMART_WKUP),
1137 .clockact = CLOCKACT_TEST_ICLK,
1138 .sysc_fields = &omap_hwmod_sysc_type1,
1139 };
1141 static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
1142 .name = "i2c",
1143 .sysc = &dra7xx_i2c_sysc,
1144 .reset = &omap_i2c_reset,
1145 .rev = OMAP_I2C_IP_VERSION_2,
1146 };
1148 /* i2c dev_attr */
1149 static struct omap_i2c_dev_attr i2c_dev_attr = {
1150 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1151 };
1153 /* i2c1 */
1154 static struct omap_hwmod_irq_info dra7xx_i2c1_irqs[] = {
1155 { .irq = 56 + DRA7XX_IRQ_GIC_START },
1156 { .irq = -1 }
1157 };
1159 static struct omap_hwmod_dma_info dra7xx_i2c1_sdma_reqs[] = {
1160 { .name = "27", .dma_req = 26 + DRA7XX_DMA_REQ_START },
1161 { .name = "28", .dma_req = 27 + DRA7XX_DMA_REQ_START },
1162 { .dma_req = -1 }
1163 };
1165 static struct omap_hwmod dra7xx_i2c1_hwmod = {
1166 .name = "i2c1",
1167 .class = &dra7xx_i2c_hwmod_class,
1168 .clkdm_name = "l4per_clkdm",
1169 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1170 .mpu_irqs = dra7xx_i2c1_irqs,
1171 .sdma_reqs = dra7xx_i2c1_sdma_reqs,
1172 .main_clk = "func_96m_fclk",
1173 .prcm = {
1174 .omap4 = {
1175 .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1176 .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
1177 .modulemode = MODULEMODE_SWCTRL,
1178 },
1179 },
1180 .dev_attr = &i2c_dev_attr,
1181 };
1183 /* i2c2 */
1184 static struct omap_hwmod_irq_info dra7xx_i2c2_irqs[] = {
1185 { .irq = 57 + DRA7XX_IRQ_GIC_START },
1186 { .irq = -1 }
1187 };
1189 static struct omap_hwmod_dma_info dra7xx_i2c2_sdma_reqs[] = {
1190 { .name = "29", .dma_req = 28 + DRA7XX_DMA_REQ_START },
1191 { .name = "30", .dma_req = 29 + DRA7XX_DMA_REQ_START },
1192 { .dma_req = -1 }
1193 };
1195 static struct omap_hwmod dra7xx_i2c2_hwmod = {
1196 .name = "i2c2",
1197 .class = &dra7xx_i2c_hwmod_class,
1198 .clkdm_name = "l4per_clkdm",
1199 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1200 .mpu_irqs = dra7xx_i2c2_irqs,
1201 .sdma_reqs = dra7xx_i2c2_sdma_reqs,
1202 .main_clk = "func_96m_fclk",
1203 .prcm = {
1204 .omap4 = {
1205 .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1206 .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
1207 .modulemode = MODULEMODE_SWCTRL,
1208 },
1209 },
1210 .dev_attr = &i2c_dev_attr,
1211 };
1213 /* i2c3 */
1214 static struct omap_hwmod_irq_info dra7xx_i2c3_irqs[] = {
1215 { .irq = 61 + DRA7XX_IRQ_GIC_START },
1216 { .irq = -1 }
1217 };
1219 static struct omap_hwmod_dma_info dra7xx_i2c3_sdma_reqs[] = {
1220 { .name = "25", .dma_req = 24 + DRA7XX_DMA_REQ_START },
1221 { .name = "26", .dma_req = 25 + DRA7XX_DMA_REQ_START },
1222 { .dma_req = -1 }
1223 };
1225 static struct omap_hwmod dra7xx_i2c3_hwmod = {
1226 .name = "i2c3",
1227 .class = &dra7xx_i2c_hwmod_class,
1228 .clkdm_name = "l4per_clkdm",
1229 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1230 .mpu_irqs = dra7xx_i2c3_irqs,
1231 .sdma_reqs = dra7xx_i2c3_sdma_reqs,
1232 .main_clk = "func_96m_fclk",
1233 .prcm = {
1234 .omap4 = {
1235 .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1236 .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
1237 .modulemode = MODULEMODE_SWCTRL,
1238 },
1239 },
1240 .dev_attr = &i2c_dev_attr,
1241 };
1243 /* i2c4 */
1244 static struct omap_hwmod_irq_info dra7xx_i2c4_irqs[] = {
1245 { .irq = 62 + DRA7XX_IRQ_GIC_START },
1246 { .irq = -1 }
1247 };
1249 static struct omap_hwmod_dma_info dra7xx_i2c4_sdma_reqs[] = {
1250 { .name = "124", .dma_req = 123 + DRA7XX_DMA_REQ_START },
1251 { .name = "125", .dma_req = 124 + DRA7XX_DMA_REQ_START },
1252 { .dma_req = -1 }
1253 };
1255 static struct omap_hwmod dra7xx_i2c4_hwmod = {
1256 .name = "i2c4",
1257 .class = &dra7xx_i2c_hwmod_class,
1258 .clkdm_name = "l4per_clkdm",
1259 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1260 .mpu_irqs = dra7xx_i2c4_irqs,
1261 .sdma_reqs = dra7xx_i2c4_sdma_reqs,
1262 .main_clk = "func_96m_fclk",
1263 .prcm = {
1264 .omap4 = {
1265 .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1266 .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
1267 .modulemode = MODULEMODE_SWCTRL,
1268 },
1269 },
1270 .dev_attr = &i2c_dev_attr,
1271 };
1273 /* i2c5 */
1274 static struct omap_hwmod_irq_info dra7xx_i2c5_irqs[] = {
1275 { .irq = 60 + DRA7XX_IRQ_GIC_START },
1276 { .irq = -1 }
1277 };
1279 static struct omap_hwmod dra7xx_i2c5_hwmod = {
1280 .name = "i2c5",
1281 .class = &dra7xx_i2c_hwmod_class,
1282 .clkdm_name = "ipu_clkdm",
1283 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1284 .mpu_irqs = dra7xx_i2c5_irqs,
1285 .main_clk = "func_96m_fclk",
1286 .prcm = {
1287 .omap4 = {
1288 .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
1289 .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
1290 .modulemode = MODULEMODE_SWCTRL,
1291 },
1292 },
1293 .dev_attr = &i2c_dev_attr,
1294 };
1296 /*
1297 * 'mailbox' class
1298 *
1299 */
1301 static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
1302 .rev_offs = 0x0000,
1303 .sysc_offs = 0x0010,
1304 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1305 SYSC_HAS_SOFTRESET),
1306 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1307 SIDLE_SMART_WKUP),
1308 .sysc_fields = &omap_hwmod_sysc_type2,
1309 };
1311 static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
1312 .name = "mailbox",
1313 .sysc = &dra7xx_mailbox_sysc,
1314 };
1316 /* mailbox1 */
1317 static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1318 .name = "mailbox1",
1319 .class = &dra7xx_mailbox_hwmod_class,
1320 .clkdm_name = "l4cfg_clkdm",
1321 .main_clk = "l3_iclk_div",
1322 .prcm = {
1323 .omap4 = {
1324 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1325 .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1326 },
1327 },
1328 };
1330 /* mailbox2 */
1331 static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1332 .name = "mailbox2",
1333 .class = &dra7xx_mailbox_hwmod_class,
1334 .clkdm_name = "l4cfg_clkdm",
1335 .main_clk = "l3_iclk_div",
1336 .prcm = {
1337 .omap4 = {
1338 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1339 .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1340 },
1341 },
1342 };
1344 /* mailbox3 */
1345 static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1346 .name = "mailbox3",
1347 .class = &dra7xx_mailbox_hwmod_class,
1348 .clkdm_name = "l4cfg_clkdm",
1349 .main_clk = "l3_iclk_div",
1350 .prcm = {
1351 .omap4 = {
1352 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1353 .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1354 },
1355 },
1356 };
1358 /* mailbox4 */
1359 static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1360 .name = "mailbox4",
1361 .class = &dra7xx_mailbox_hwmod_class,
1362 .clkdm_name = "l4cfg_clkdm",
1363 .main_clk = "l3_iclk_div",
1364 .prcm = {
1365 .omap4 = {
1366 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1367 .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1368 },
1369 },
1370 };
1372 /* mailbox5 */
1373 static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1374 .name = "mailbox5",
1375 .class = &dra7xx_mailbox_hwmod_class,
1376 .clkdm_name = "l4cfg_clkdm",
1377 .main_clk = "l3_iclk_div",
1378 .prcm = {
1379 .omap4 = {
1380 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1381 .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1382 },
1383 },
1384 };
1386 /* mailbox6 */
1387 static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1388 .name = "mailbox6",
1389 .class = &dra7xx_mailbox_hwmod_class,
1390 .clkdm_name = "l4cfg_clkdm",
1391 .main_clk = "l3_iclk_div",
1392 .prcm = {
1393 .omap4 = {
1394 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1395 .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1396 },
1397 },
1398 };
1400 /* mailbox7 */
1401 static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1402 .name = "mailbox7",
1403 .class = &dra7xx_mailbox_hwmod_class,
1404 .clkdm_name = "l4cfg_clkdm",
1405 .main_clk = "l3_iclk_div",
1406 .prcm = {
1407 .omap4 = {
1408 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1409 .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1410 },
1411 },
1412 };
1414 /* mailbox8 */
1415 static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1416 .name = "mailbox8",
1417 .class = &dra7xx_mailbox_hwmod_class,
1418 .clkdm_name = "l4cfg_clkdm",
1419 .main_clk = "l3_iclk_div",
1420 .prcm = {
1421 .omap4 = {
1422 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1423 .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1424 },
1425 },
1426 };
1428 /* mailbox9 */
1429 static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1430 .name = "mailbox9",
1431 .class = &dra7xx_mailbox_hwmod_class,
1432 .clkdm_name = "l4cfg_clkdm",
1433 .main_clk = "l3_iclk_div",
1434 .prcm = {
1435 .omap4 = {
1436 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1437 .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1438 },
1439 },
1440 };
1442 /* mailbox10 */
1443 static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1444 .name = "mailbox10",
1445 .class = &dra7xx_mailbox_hwmod_class,
1446 .clkdm_name = "l4cfg_clkdm",
1447 .main_clk = "l3_iclk_div",
1448 .prcm = {
1449 .omap4 = {
1450 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1451 .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1452 },
1453 },
1454 };
1456 /* mailbox11 */
1457 static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1458 .name = "mailbox11",
1459 .class = &dra7xx_mailbox_hwmod_class,
1460 .clkdm_name = "l4cfg_clkdm",
1461 .main_clk = "l3_iclk_div",
1462 .prcm = {
1463 .omap4 = {
1464 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1465 .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1466 },
1467 },
1468 };
1470 /* mailbox12 */
1471 static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1472 .name = "mailbox12",
1473 .class = &dra7xx_mailbox_hwmod_class,
1474 .clkdm_name = "l4cfg_clkdm",
1475 .main_clk = "l3_iclk_div",
1476 .prcm = {
1477 .omap4 = {
1478 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1479 .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1480 },
1481 },
1482 };
1484 /* mailbox13 */
1485 static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1486 .name = "mailbox13",
1487 .class = &dra7xx_mailbox_hwmod_class,
1488 .clkdm_name = "l4cfg_clkdm",
1489 .main_clk = "l3_iclk_div",
1490 .prcm = {
1491 .omap4 = {
1492 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1493 .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1494 },
1495 },
1496 };
1498 /*
1499 * 'mcasp' class
1500 *
1501 */
1503 static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc = {
1504 .sysc_offs = 0x0004,
1505 .sysc_flags = SYSC_HAS_SIDLEMODE,
1506 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1507 .sysc_fields = &omap_hwmod_sysc_type3,
1508 };
1510 static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
1511 .name = "mcasp",
1512 .sysc = &dra7xx_mcasp_sysc,
1513 };
1515 /* mcasp1 */
1516 static struct omap_hwmod dra7xx_mcasp1_hwmod = {
1517 .name = "mcasp1",
1518 .class = &dra7xx_mcasp_hwmod_class,
1519 .clkdm_name = "ipu_clkdm",
1520 .main_clk = "mcasp1_ahclkx_mux",
1521 .flags = HWMOD_SWSUP_SIDLE,
1522 .prcm = {
1523 .omap4 = {
1524 .clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET,
1525 .context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET,
1526 .modulemode = MODULEMODE_SWCTRL,
1527 },
1528 },
1529 };
1531 /* mcasp2 */
1532 static struct omap_hwmod dra7xx_mcasp2_hwmod = {
1533 .name = "mcasp2",
1534 .class = &dra7xx_mcasp_hwmod_class,
1535 .clkdm_name = "l4per2_clkdm",
1536 .main_clk = "mcasp2_ahclkr_mux",
1537 .flags = HWMOD_SWSUP_SIDLE,
1538 .prcm = {
1539 .omap4 = {
1540 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,
1541 .context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
1542 .modulemode = MODULEMODE_SWCTRL,
1543 },
1544 },
1545 };
1547 /* HACK: Taken from UART6 since they're not used in dra7-evm */
1548 static struct omap_hwmod_dma_info dra7xx_mcasp3_sdma_reqs[] = {
1549 { .name = "tx", .dma_req = 78 + DRA7XX_DMA_REQ_START },
1550 { .name = "rx", .dma_req = 79 + DRA7XX_DMA_REQ_START },
1551 { .dma_req = -1 }
1552 };
1554 /* mcasp3 */
1555 static struct omap_hwmod dra7xx_mcasp3_hwmod = {
1556 .name = "mcasp3",
1557 .class = &dra7xx_mcasp_hwmod_class,
1558 .clkdm_name = "l4per2_clkdm",
1559 .main_clk = "mcasp3_ahclkx_mux",
1560 .sdma_reqs = dra7xx_mcasp3_sdma_reqs,
1561 .flags = HWMOD_SWSUP_SIDLE,
1562 .prcm = {
1563 .omap4 = {
1564 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET,
1565 .context_offs = DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET,
1566 .modulemode = MODULEMODE_SWCTRL,
1567 },
1568 },
1569 };
1571 /* mcasp4 */
1572 static struct omap_hwmod dra7xx_mcasp4_hwmod = {
1573 .name = "mcasp4",
1574 .class = &dra7xx_mcasp_hwmod_class,
1575 .clkdm_name = "l4per2_clkdm",
1576 .main_clk = "mcasp4_ahclkx_mux",
1577 .flags = HWMOD_SWSUP_SIDLE,
1578 .prcm = {
1579 .omap4 = {
1580 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET,
1581 .context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET,
1582 .modulemode = MODULEMODE_SWCTRL,
1583 },
1584 },
1585 };
1587 /* mcasp5 */
1588 static struct omap_hwmod dra7xx_mcasp5_hwmod = {
1589 .name = "mcasp5",
1590 .class = &dra7xx_mcasp_hwmod_class,
1591 .clkdm_name = "l4per2_clkdm",
1592 .main_clk = "mcasp5_ahclkx_mux",
1593 .flags = HWMOD_SWSUP_SIDLE,
1594 .prcm = {
1595 .omap4 = {
1596 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET,
1597 .context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET,
1598 .modulemode = MODULEMODE_SWCTRL,
1599 },
1600 },
1601 };
1603 /* HACK: Taken from UART5 since they're not used in dra7-evm */
1604 static struct omap_hwmod_dma_info dra7xx_mcasp6_sdma_reqs[] = {
1605 { .name = "tx", .dma_req = 62 + DRA7XX_DMA_REQ_START },
1606 { .name = "rx", .dma_req = 63 + DRA7XX_DMA_REQ_START },
1607 { .dma_req = -1 }
1608 };
1610 /* mcasp6 */
1611 static struct omap_hwmod dra7xx_mcasp6_hwmod = {
1612 .name = "mcasp6",
1613 .class = &dra7xx_mcasp_hwmod_class,
1614 .clkdm_name = "l4per2_clkdm",
1615 .main_clk = "mcasp6_ahclkx_mux",
1616 .sdma_reqs = dra7xx_mcasp6_sdma_reqs,
1617 .flags = HWMOD_SWSUP_SIDLE,
1618 .prcm = {
1619 .omap4 = {
1620 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,
1621 .context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
1622 .modulemode = MODULEMODE_SWCTRL,
1623 },
1624 },
1625 };
1627 /* mcasp7 */
1628 static struct omap_hwmod dra7xx_mcasp7_hwmod = {
1629 .name = "mcasp7",
1630 .class = &dra7xx_mcasp_hwmod_class,
1631 .clkdm_name = "l4per2_clkdm",
1632 .main_clk = "mcasp7_ahclkx_mux",
1633 .flags = HWMOD_SWSUP_SIDLE,
1634 .prcm = {
1635 .omap4 = {
1636 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET,
1637 .context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,
1638 .modulemode = MODULEMODE_SWCTRL,
1639 },
1640 },
1641 };
1643 /* mcasp8 */
1644 static struct omap_hwmod dra7xx_mcasp8_hwmod = {
1645 .name = "mcasp8",
1646 .class = &dra7xx_mcasp_hwmod_class,
1647 .clkdm_name = "l4per2_clkdm",
1648 .main_clk = "mcasp8_ahclk_mux",
1649 .flags = HWMOD_SWSUP_SIDLE,
1650 .prcm = {
1651 .omap4 = {
1652 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,
1653 .context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
1654 .modulemode = MODULEMODE_SWCTRL,
1655 },
1656 },
1657 };
1659 /*
1660 * 'mcspi' class
1661 *
1662 */
1664 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1665 .rev_offs = 0x0000,
1666 .sysc_offs = 0x0010,
1667 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1668 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1669 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1670 SIDLE_SMART_WKUP),
1671 .sysc_fields = &omap_hwmod_sysc_type2,
1672 };
1674 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1675 .name = "mcspi",
1676 .sysc = &dra7xx_mcspi_sysc,
1677 .rev = OMAP4_MCSPI_REV,
1678 };
1680 /* mcspi1 */
1681 static struct omap_hwmod_irq_info dra7xx_mcspi1_irqs[] = {
1682 { .irq = 65 + DRA7XX_IRQ_GIC_START },
1683 { .irq = -1 }
1684 };
1686 static struct omap_hwmod_dma_info dra7xx_mcspi1_sdma_reqs[] = {
1687 { .name = "35", .dma_req = 34 + DRA7XX_DMA_REQ_START },
1688 { .name = "36", .dma_req = 35 + DRA7XX_DMA_REQ_START },
1689 { .name = "37", .dma_req = 36 + DRA7XX_DMA_REQ_START },
1690 { .name = "38", .dma_req = 37 + DRA7XX_DMA_REQ_START },
1691 { .name = "39", .dma_req = 38 + DRA7XX_DMA_REQ_START },
1692 { .name = "40", .dma_req = 39 + DRA7XX_DMA_REQ_START },
1693 { .name = "41", .dma_req = 40 + DRA7XX_DMA_REQ_START },
1694 { .name = "42", .dma_req = 41 + DRA7XX_DMA_REQ_START },
1695 { .dma_req = -1 }
1696 };
1698 /* mcspi1 dev_attr */
1699 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1700 .num_chipselect = 4,
1701 };
1703 static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1704 .name = "mcspi1",
1705 .class = &dra7xx_mcspi_hwmod_class,
1706 .clkdm_name = "l4per_clkdm",
1707 .mpu_irqs = dra7xx_mcspi1_irqs,
1708 .sdma_reqs = dra7xx_mcspi1_sdma_reqs,
1709 .main_clk = "func_48m_fclk",
1710 .prcm = {
1711 .omap4 = {
1712 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1713 .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1714 .modulemode = MODULEMODE_SWCTRL,
1715 },
1716 },
1717 .dev_attr = &mcspi1_dev_attr,
1718 };
1720 /* mcspi2 */
1721 static struct omap_hwmod_irq_info dra7xx_mcspi2_irqs[] = {
1722 { .irq = 66 + DRA7XX_IRQ_GIC_START },
1723 { .irq = -1 }
1724 };
1726 static struct omap_hwmod_dma_info dra7xx_mcspi2_sdma_reqs[] = {
1727 { .name = "43", .dma_req = 42 + DRA7XX_DMA_REQ_START },
1728 { .name = "44", .dma_req = 43 + DRA7XX_DMA_REQ_START },
1729 { .name = "45", .dma_req = 44 + DRA7XX_DMA_REQ_START },
1730 { .name = "46", .dma_req = 45 + DRA7XX_DMA_REQ_START },
1731 { .dma_req = -1 }
1732 };
1734 /* mcspi2 dev_attr */
1735 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1736 .num_chipselect = 2,
1737 };
1739 static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1740 .name = "mcspi2",
1741 .class = &dra7xx_mcspi_hwmod_class,
1742 .clkdm_name = "l4per_clkdm",
1743 .mpu_irqs = dra7xx_mcspi2_irqs,
1744 .sdma_reqs = dra7xx_mcspi2_sdma_reqs,
1745 .main_clk = "func_48m_fclk",
1746 .prcm = {
1747 .omap4 = {
1748 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1749 .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1750 .modulemode = MODULEMODE_SWCTRL,
1751 },
1752 },
1753 .dev_attr = &mcspi2_dev_attr,
1754 };
1756 /* mcspi3 */
1757 static struct omap_hwmod_irq_info dra7xx_mcspi3_irqs[] = {
1758 { .irq = 91 + DRA7XX_IRQ_GIC_START },
1759 { .irq = -1 }
1760 };
1762 static struct omap_hwmod_dma_info dra7xx_mcspi3_sdma_reqs[] = {
1763 { .name = "15", .dma_req = 14 + DRA7XX_DMA_REQ_START },
1764 { .name = "16", .dma_req = 15 + DRA7XX_DMA_REQ_START },
1765 { .name = "23", .dma_req = 22 + DRA7XX_DMA_REQ_START },
1766 { .name = "24", .dma_req = 23 + DRA7XX_DMA_REQ_START },
1767 { .dma_req = -1 }
1768 };
1770 /* mcspi3 dev_attr */
1771 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1772 .num_chipselect = 2,
1773 };
1775 static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1776 .name = "mcspi3",
1777 .class = &dra7xx_mcspi_hwmod_class,
1778 .clkdm_name = "l4per_clkdm",
1779 .mpu_irqs = dra7xx_mcspi3_irqs,
1780 .sdma_reqs = dra7xx_mcspi3_sdma_reqs,
1781 .main_clk = "func_48m_fclk",
1782 .prcm = {
1783 .omap4 = {
1784 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1785 .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1786 .modulemode = MODULEMODE_SWCTRL,
1787 },
1788 },
1789 .dev_attr = &mcspi3_dev_attr,
1790 };
1792 /* mcspi4 */
1793 static struct omap_hwmod_irq_info dra7xx_mcspi4_irqs[] = {
1794 { .irq = 48 + DRA7XX_IRQ_GIC_START },
1795 { .irq = -1 }
1796 };
1798 static struct omap_hwmod_dma_info dra7xx_mcspi4_sdma_reqs[] = {
1799 { .name = "70", .dma_req = 69 + DRA7XX_DMA_REQ_START },
1800 { .name = "71", .dma_req = 70 + DRA7XX_DMA_REQ_START },
1801 { .dma_req = -1 }
1802 };
1804 /* mcspi4 dev_attr */
1805 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1806 .num_chipselect = 1,
1807 };
1809 static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1810 .name = "mcspi4",
1811 .class = &dra7xx_mcspi_hwmod_class,
1812 .clkdm_name = "l4per_clkdm",
1813 .mpu_irqs = dra7xx_mcspi4_irqs,
1814 .sdma_reqs = dra7xx_mcspi4_sdma_reqs,
1815 .main_clk = "func_48m_fclk",
1816 .prcm = {
1817 .omap4 = {
1818 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1819 .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1820 .modulemode = MODULEMODE_SWCTRL,
1821 },
1822 },
1823 .dev_attr = &mcspi4_dev_attr,
1824 };
1826 /*
1827 * 'mmc' class
1828 *
1829 */
1831 static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1832 .rev_offs = 0x0000,
1833 .sysc_offs = 0x0010,
1834 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1835 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1836 SYSC_HAS_SOFTRESET),
1837 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1838 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1839 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1840 .sysc_fields = &omap_hwmod_sysc_type2,
1841 };
1843 static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1844 .name = "mmc",
1845 .sysc = &dra7xx_mmc_sysc,
1846 };
1848 /* mmc1 */
1849 static struct omap_hwmod_irq_info dra7xx_mmc1_irqs[] = {
1850 { .irq = 83 + DRA7XX_IRQ_GIC_START },
1851 { .irq = -1 }
1852 };
1854 static struct omap_hwmod_dma_info dra7xx_mmc1_sdma_reqs[] = {
1855 { .name = "tx", .dma_req = 60 + DRA7XX_DMA_REQ_START },
1856 { .name = "rx", .dma_req = 61 + DRA7XX_DMA_REQ_START },
1857 { .dma_req = -1 }
1858 };
1860 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1861 { .role = "clk32k", .clk = "mmc1_clk32k" },
1862 };
1864 /* mmc1 dev_attr */
1865 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1866 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1867 };
1869 static struct omap_hwmod dra7xx_mmc1_hwmod = {
1870 .name = "mmc1",
1871 .class = &dra7xx_mmc_hwmod_class,
1872 .clkdm_name = "l3init_clkdm",
1873 .mpu_irqs = dra7xx_mmc1_irqs,
1874 .sdma_reqs = dra7xx_mmc1_sdma_reqs,
1875 .main_clk = "mmc1_fclk_div",
1876 .prcm = {
1877 .omap4 = {
1878 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1879 .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1880 .modulemode = MODULEMODE_SWCTRL,
1881 },
1882 },
1883 .opt_clks = mmc1_opt_clks,
1884 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1885 .dev_attr = &mmc1_dev_attr,
1886 };
1888 /* mmc2 */
1889 static struct omap_hwmod_irq_info dra7xx_mmc2_irqs[] = {
1890 { .irq = 86 + DRA7XX_IRQ_GIC_START },
1891 { .irq = -1 }
1892 };
1894 static struct omap_hwmod_dma_info dra7xx_mmc2_sdma_reqs[] = {
1895 { .name = "tx", .dma_req = 46 + DRA7XX_DMA_REQ_START },
1896 { .name = "rx", .dma_req = 47 + DRA7XX_DMA_REQ_START },
1897 { .dma_req = -1 }
1898 };
1900 static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1901 { .role = "clk32k", .clk = "mmc2_clk32k" },
1902 };
1904 static struct omap_hwmod dra7xx_mmc2_hwmod = {
1905 .name = "mmc2",
1906 .class = &dra7xx_mmc_hwmod_class,
1907 .clkdm_name = "l3init_clkdm",
1908 .mpu_irqs = dra7xx_mmc2_irqs,
1909 .sdma_reqs = dra7xx_mmc2_sdma_reqs,
1910 .main_clk = "mmc2_fclk_div",
1911 .prcm = {
1912 .omap4 = {
1913 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1914 .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1915 .modulemode = MODULEMODE_SWCTRL,
1916 },
1917 },
1918 .opt_clks = mmc2_opt_clks,
1919 .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks),
1920 };
1922 /* mmc3 */
1923 static struct omap_hwmod_irq_info dra7xx_mmc3_irqs[] = {
1924 { .irq = 94 + DRA7XX_IRQ_GIC_START },
1925 { .irq = -1 }
1926 };
1928 static struct omap_hwmod_dma_info dra7xx_mmc3_sdma_reqs[] = {
1929 { .name = "77", .dma_req = 76 + DRA7XX_DMA_REQ_START },
1930 { .name = "78", .dma_req = 77 + DRA7XX_DMA_REQ_START },
1931 { .dma_req = -1 }
1932 };
1934 static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1935 { .role = "clk32k", .clk = "mmc3_clk32k" },
1936 };
1938 static struct omap_hwmod dra7xx_mmc3_hwmod = {
1939 .name = "mmc3",
1940 .class = &dra7xx_mmc_hwmod_class,
1941 .clkdm_name = "l4per_clkdm",
1942 .mpu_irqs = dra7xx_mmc3_irqs,
1943 .sdma_reqs = dra7xx_mmc3_sdma_reqs,
1944 .main_clk = "mmc3_gfclk_div",
1945 .prcm = {
1946 .omap4 = {
1947 .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1948 .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1949 .modulemode = MODULEMODE_SWCTRL,
1950 },
1951 },
1952 .opt_clks = mmc3_opt_clks,
1953 .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks),
1954 };
1956 /* mmc4 */
1957 static struct omap_hwmod_irq_info dra7xx_mmc4_irqs[] = {
1958 { .irq = 96 + DRA7XX_IRQ_GIC_START },
1959 { .irq = -1 }
1960 };
1962 static struct omap_hwmod_dma_info dra7xx_mmc4_sdma_reqs[] = {
1963 { .name = "57", .dma_req = 56 + DRA7XX_DMA_REQ_START },
1964 { .name = "58", .dma_req = 57 + DRA7XX_DMA_REQ_START },
1965 { .dma_req = -1 }
1966 };
1968 static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1969 { .role = "clk32k", .clk = "mmc4_clk32k" },
1970 };
1972 static struct omap_hwmod dra7xx_mmc4_hwmod = {
1973 .name = "mmc4",
1974 .class = &dra7xx_mmc_hwmod_class,
1975 .clkdm_name = "l4per_clkdm",
1976 .mpu_irqs = dra7xx_mmc4_irqs,
1977 .sdma_reqs = dra7xx_mmc4_sdma_reqs,
1978 .main_clk = "mmc4_gfclk_div",
1979 .prcm = {
1980 .omap4 = {
1981 .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1982 .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1983 .modulemode = MODULEMODE_SWCTRL,
1984 },
1985 },
1986 .opt_clks = mmc4_opt_clks,
1987 .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks),
1988 };
1990 /*
1991 * 'mpu' class
1992 *
1993 */
1995 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1996 .name = "mpu",
1997 };
1999 /* mpu */
2000 static struct omap_hwmod_irq_info dra7xx_mpu_irqs[] = {
2001 { .irq = 132 + DRA7XX_IRQ_GIC_START },
2002 { .irq = -1 }
2003 };
2005 static struct omap_hwmod dra7xx_mpu_hwmod = {
2006 .name = "mpu",
2007 .class = &dra7xx_mpu_hwmod_class,
2008 .clkdm_name = "mpu_clkdm",
2009 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2010 .mpu_irqs = dra7xx_mpu_irqs,
2011 .main_clk = "dpll_mpu_m2_ck",
2012 .prcm = {
2013 .omap4 = {
2014 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
2015 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
2016 },
2017 },
2018 };
2020 /*
2021 * 'ocmc_ram' class
2022 *
2023 */
2025 static struct omap_hwmod_class dra7xx_ocmc_ram_hwmod_class = {
2026 .name = "ocmc_ram",
2027 };
2029 /* ocmc_ram1 */
2030 static struct omap_hwmod dra7xx_ocmc_ram1_hwmod = {
2031 .name = "ocmc_ram1",
2032 .class = &dra7xx_ocmc_ram_hwmod_class,
2033 .clkdm_name = "l3main1_clkdm",
2034 .main_clk = "l3_iclk_div",
2035 .prcm = {
2036 .omap4 = {
2037 .clkctrl_offs = DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL_OFFSET,
2038 .context_offs = DRA7XX_RM_L3MAIN1_OCMC_RAM1_CONTEXT_OFFSET,
2039 },
2040 },
2041 };
2043 /* ocmc_ram2 */
2044 static struct omap_hwmod dra7xx_ocmc_ram2_hwmod = {
2045 .name = "ocmc_ram2",
2046 .class = &dra7xx_ocmc_ram_hwmod_class,
2047 .clkdm_name = "l3main1_clkdm",
2048 .main_clk = "l3_iclk_div",
2049 .prcm = {
2050 .omap4 = {
2051 .clkctrl_offs = DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL_OFFSET,
2052 .context_offs = DRA7XX_RM_L3MAIN1_OCMC_RAM2_CONTEXT_OFFSET,
2053 },
2054 },
2055 };
2057 /* ocmc_ram3 */
2058 static struct omap_hwmod dra7xx_ocmc_ram3_hwmod = {
2059 .name = "ocmc_ram3",
2060 .class = &dra7xx_ocmc_ram_hwmod_class,
2061 .clkdm_name = "l3main1_clkdm",
2062 .main_clk = "l3_iclk_div",
2063 .prcm = {
2064 .omap4 = {
2065 .clkctrl_offs = DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL_OFFSET,
2066 .context_offs = DRA7XX_RM_L3MAIN1_OCMC_RAM3_CONTEXT_OFFSET,
2067 },
2068 },
2069 };
2071 /*
2072 * 'ocmc_rom' class
2073 *
2074 */
2076 static struct omap_hwmod_class dra7xx_ocmc_rom_hwmod_class = {
2077 .name = "ocmc_rom",
2078 };
2080 /* ocmc_rom */
2081 static struct omap_hwmod dra7xx_ocmc_rom_hwmod = {
2082 .name = "ocmc_rom",
2083 .class = &dra7xx_ocmc_rom_hwmod_class,
2084 .clkdm_name = "l3main1_clkdm",
2085 .main_clk = "l3_iclk_div",
2086 .prcm = {
2087 .omap4 = {
2088 .clkctrl_offs = DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL_OFFSET,
2089 .context_offs = DRA7XX_RM_L3MAIN1_OCMC_ROM_CONTEXT_OFFSET,
2090 },
2091 },
2092 };
2094 /*
2095 * 'ocp2scp' class
2096 *
2097 */
2099 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
2100 .rev_offs = 0x0000,
2101 .sysc_offs = 0x0010,
2102 .syss_offs = 0x0014,
2103 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2104 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2105 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2106 SIDLE_SMART_WKUP),
2107 .sysc_fields = &omap_hwmod_sysc_type1,
2108 };
2110 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
2111 .name = "ocp2scp",
2112 .sysc = &dra7xx_ocp2scp_sysc,
2113 };
2115 /* ocp2scp1 */
2116 static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
2117 .name = "ocp2scp1",
2118 .class = &dra7xx_ocp2scp_hwmod_class,
2119 .clkdm_name = "l3init_clkdm",
2120 .main_clk = "l4_root_clk_div",
2121 .prcm = {
2122 .omap4 = {
2123 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
2124 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
2125 .modulemode = MODULEMODE_HWCTRL,
2126 },
2127 },
2128 };
2130 /*
2131 * 'pruss' class
2132 *
2133 */
2135 static struct omap_hwmod_class dra7xx_pruss_hwmod_class = {
2136 .name = "pruss",
2137 };
2139 /* pruss1 */
2140 static struct omap_hwmod dra7xx_pruss1_hwmod = {
2141 .name = "pruss1",
2142 .class = &dra7xx_pruss_hwmod_class,
2143 .clkdm_name = "l4per2_clkdm",
2144 .main_clk = "dpll_per_m2x2_ck",
2145 .prcm = {
2146 .omap4 = {
2147 .clkctrl_offs = DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL_OFFSET,
2148 .context_offs = DRA7XX_RM_L4PER2_PRUSS1_CONTEXT_OFFSET,
2149 .modulemode = MODULEMODE_SWCTRL,
2150 },
2151 },
2152 };
2154 /* pruss2 */
2155 static struct omap_hwmod dra7xx_pruss2_hwmod = {
2156 .name = "pruss2",
2157 .class = &dra7xx_pruss_hwmod_class,
2158 .clkdm_name = "l4per2_clkdm",
2159 .main_clk = "dpll_per_m2x2_ck",
2160 .prcm = {
2161 .omap4 = {
2162 .clkctrl_offs = DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL_OFFSET,
2163 .context_offs = DRA7XX_RM_L4PER2_PRUSS2_CONTEXT_OFFSET,
2164 .modulemode = MODULEMODE_SWCTRL,
2165 },
2166 },
2167 };
2169 /*
2170 * 'pwmss' class
2171 *
2172 */
2174 static struct omap_hwmod_class dra7xx_pwmss_hwmod_class = {
2175 .name = "pwmss",
2176 };
2178 /* pwmss1 */
2179 static struct omap_hwmod dra7xx_pwmss1_hwmod = {
2180 .name = "pwmss1",
2181 .class = &dra7xx_pwmss_hwmod_class,
2182 .clkdm_name = "l4per2_clkdm",
2183 .main_clk = "l3_iclk_div",
2184 .prcm = {
2185 .omap4 = {
2186 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET,
2187 .context_offs = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET,
2188 .modulemode = MODULEMODE_SWCTRL,
2189 },
2190 },
2191 };
2193 /* pwmss2 */
2194 static struct omap_hwmod dra7xx_pwmss2_hwmod = {
2195 .name = "pwmss2",
2196 .class = &dra7xx_pwmss_hwmod_class,
2197 .clkdm_name = "l4per2_clkdm",
2198 .main_clk = "l3_iclk_div",
2199 .prcm = {
2200 .omap4 = {
2201 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET,
2202 .context_offs = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET,
2203 .modulemode = MODULEMODE_SWCTRL,
2204 },
2205 },
2206 };
2208 /* pwmss3 */
2209 static struct omap_hwmod dra7xx_pwmss3_hwmod = {
2210 .name = "pwmss3",
2211 .class = &dra7xx_pwmss_hwmod_class,
2212 .clkdm_name = "l4per2_clkdm",
2213 .main_clk = "l3_iclk_div",
2214 .prcm = {
2215 .omap4 = {
2216 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET,
2217 .context_offs = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET,
2218 .modulemode = MODULEMODE_SWCTRL,
2219 },
2220 },
2221 };
2223 /*
2224 * 'qspi' class
2225 *
2226 */
2228 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
2229 .sysc_offs = 0x0010,
2230 .sysc_flags = SYSC_HAS_SIDLEMODE,
2231 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2232 SIDLE_SMART_WKUP),
2233 .sysc_fields = &omap_hwmod_sysc_type2,
2234 };
2236 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
2237 .name = "qspi",
2238 .sysc = &dra7xx_qspi_sysc,
2239 };
2241 /* qspi */
2242 static struct omap_hwmod dra7xx_qspi_hwmod = {
2243 .name = "qspi",
2244 .class = &dra7xx_qspi_hwmod_class,
2245 .clkdm_name = "l4per2_clkdm",
2246 .main_clk = "qspi_gfclk_div",
2247 .prcm = {
2248 .omap4 = {
2249 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
2250 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
2251 .modulemode = MODULEMODE_SWCTRL,
2252 },
2253 },
2254 };
2256 /*
2257 * 'rtcss' class
2258 *
2259 */
2261 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
2262 .sysc_offs = 0x0078,
2263 .sysc_flags = SYSC_HAS_SIDLEMODE,
2264 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2265 .sysc_fields = &omap_hwmod_sysc_type3,
2266 };
2268 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
2269 .name = "rtcss",
2270 .sysc = &dra7xx_rtcss_sysc,
2271 };
2273 /* rtcss */
2274 static struct omap_hwmod dra7xx_rtcss_hwmod = {
2275 .name = "rtcss",
2276 .class = &dra7xx_rtcss_hwmod_class,
2277 .clkdm_name = "rtc_clkdm",
2278 .main_clk = "sys_32k_ck",
2279 .prcm = {
2280 .omap4 = {
2281 .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
2282 .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
2283 .modulemode = MODULEMODE_SWCTRL,
2284 },
2285 },
2286 };
2288 /*
2289 * 'sata' class
2290 *
2291 */
2293 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
2294 .sysc_offs = 0x0000,
2295 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
2296 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2297 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2298 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2299 .sysc_fields = &omap_hwmod_sysc_type2,
2300 };
2302 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
2303 .name = "sata",
2304 .sysc = &dra7xx_sata_sysc,
2305 };
2307 /* sata */
2308 static struct omap_hwmod_irq_info dra7xx_sata_irqs[] = {
2309 { .irq = 54 + DRA7XX_IRQ_GIC_START },
2310 { .irq = -1 }
2311 };
2313 static struct omap_hwmod_opt_clk sata_opt_clks[] = {
2314 { .role = "ref_clk", .clk = "sata_ref_clk" },
2315 };
2317 static struct omap_hwmod dra7xx_sata_hwmod = {
2318 .name = "sata",
2319 .class = &dra7xx_sata_hwmod_class,
2320 .clkdm_name = "l3init_clkdm",
2321 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2322 .mpu_irqs = dra7xx_sata_irqs,
2323 .main_clk = "func_48m_fclk",
2324 .prcm = {
2325 .omap4 = {
2326 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
2327 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
2328 .modulemode = MODULEMODE_SWCTRL,
2329 },
2330 },
2331 .opt_clks = sata_opt_clks,
2332 .opt_clks_cnt = ARRAY_SIZE(sata_opt_clks),
2333 };
2335 /*
2336 * 'smartreflex' class
2337 *
2338 */
2340 /* The IP is not compliant to type1 / type2 scheme */
2341 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2342 .sidle_shift = 24,
2343 .enwkup_shift = 26,
2344 };
2346 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
2347 .sysc_offs = 0x0038,
2348 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2349 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2350 SIDLE_SMART_WKUP),
2351 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
2352 };
2354 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
2355 .name = "smartreflex",
2356 .sysc = &dra7xx_smartreflex_sysc,
2357 .rev = 2,
2358 };
2360 /* smartreflex_core */
2361 static struct omap_hwmod_irq_info dra7xx_smartreflex_core_irqs[] = {
2362 { .irq = 19 + DRA7XX_IRQ_GIC_START },
2363 { .irq = -1 }
2364 };
2366 /* smartreflex_core dev_attr */
2367 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2368 .sensor_voltdm_name = "core",
2369 };
2371 static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
2372 .name = "smartreflex_core",
2373 .class = &dra7xx_smartreflex_hwmod_class,
2374 .clkdm_name = "coreaon_clkdm",
2375 .mpu_irqs = dra7xx_smartreflex_core_irqs,
2376 .main_clk = "wkupaon_iclk_mux",
2377 .prcm = {
2378 .omap4 = {
2379 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
2380 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
2381 .modulemode = MODULEMODE_SWCTRL,
2382 },
2383 },
2384 .dev_attr = &smartreflex_core_dev_attr,
2385 };
2387 /* smartreflex_dspeve */
2388 static struct omap_hwmod dra7xx_smartreflex_dspeve_hwmod = {
2389 .name = "smartreflex_dspeve",
2390 .class = &dra7xx_smartreflex_hwmod_class,
2391 .clkdm_name = "coreaon_clkdm",
2392 .main_clk = "wkupaon_iclk_mux",
2393 .prcm = {
2394 .omap4 = {
2395 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL_OFFSET,
2396 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_DSPEVE_CONTEXT_OFFSET,
2397 .modulemode = MODULEMODE_SWCTRL,
2398 },
2399 },
2400 };
2402 /* smartreflex_gpu */
2403 static struct omap_hwmod dra7xx_smartreflex_gpu_hwmod = {
2404 .name = "smartreflex_gpu",
2405 .class = &dra7xx_smartreflex_hwmod_class,
2406 .clkdm_name = "coreaon_clkdm",
2407 .main_clk = "wkupaon_iclk_mux",
2408 .prcm = {
2409 .omap4 = {
2410 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL_OFFSET,
2411 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_GPU_CONTEXT_OFFSET,
2412 .modulemode = MODULEMODE_SWCTRL,
2413 },
2414 },
2415 };
2417 /* smartreflex_mpu */
2418 static struct omap_hwmod_irq_info dra7xx_smartreflex_mpu_irqs[] = {
2419 { .irq = 18 + DRA7XX_IRQ_GIC_START },
2420 { .irq = -1 }
2421 };
2423 /* smartreflex_mpu dev_attr */
2424 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2425 .sensor_voltdm_name = "mpu",
2426 };
2428 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
2429 .name = "smartreflex_mpu",
2430 .class = &dra7xx_smartreflex_hwmod_class,
2431 .clkdm_name = "coreaon_clkdm",
2432 .mpu_irqs = dra7xx_smartreflex_mpu_irqs,
2433 .main_clk = "wkupaon_iclk_mux",
2434 .prcm = {
2435 .omap4 = {
2436 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
2437 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
2438 .modulemode = MODULEMODE_SWCTRL,
2439 },
2440 },
2441 .dev_attr = &smartreflex_mpu_dev_attr,
2442 };
2444 /*
2445 * 'spare' class
2446 *
2447 */
2449 static struct omap_hwmod_class dra7xx_spare_hwmod_class = {
2450 .name = "spare",
2451 };
2453 /* spare_cme */
2454 static struct omap_hwmod dra7xx_spare_cme_hwmod = {
2455 .name = "spare_cme",
2456 .class = &dra7xx_spare_hwmod_class,
2457 .clkdm_name = "l3main1_clkdm",
2458 .main_clk = "l4_root_clk_div",
2459 .prcm = {
2460 .omap4 = {
2461 .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL_OFFSET,
2462 .context_offs = DRA7XX_RM_L3MAIN1_SPARE_CME_CONTEXT_OFFSET,
2463 },
2464 },
2465 };
2467 /* spare_icm */
2468 static struct omap_hwmod dra7xx_spare_icm_hwmod = {
2469 .name = "spare_icm",
2470 .class = &dra7xx_spare_hwmod_class,
2471 .clkdm_name = "l3main1_clkdm",
2472 .main_clk = "l4_root_clk_div",
2473 .prcm = {
2474 .omap4 = {
2475 .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL_OFFSET,
2476 .context_offs = DRA7XX_RM_L3MAIN1_SPARE_ICM_CONTEXT_OFFSET,
2477 },
2478 },
2479 };
2481 /* spare_iva2 */
2482 static struct omap_hwmod dra7xx_spare_iva2_hwmod = {
2483 .name = "spare_iva2",
2484 .class = &dra7xx_spare_hwmod_class,
2485 .clkdm_name = "l3main1_clkdm",
2486 .main_clk = "l3_iclk_div",
2487 .prcm = {
2488 .omap4 = {
2489 .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL_OFFSET,
2490 .context_offs = DRA7XX_RM_L3MAIN1_SPARE_IVA2_CONTEXT_OFFSET,
2491 },
2492 },
2493 };
2495 /* spare_safety1 */
2496 static struct omap_hwmod dra7xx_spare_safety1_hwmod = {
2497 .name = "spare_safety1",
2498 .class = &dra7xx_spare_hwmod_class,
2499 .clkdm_name = "wkupaon_clkdm",
2500 .main_clk = "wkupaon_iclk_mux",
2501 .prcm = {
2502 .omap4 = {
2503 .clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL_OFFSET,
2504 .context_offs = DRA7XX_RM_WKUPAON_SPARE_SAFETY1_CONTEXT_OFFSET,
2505 },
2506 },
2507 };
2509 /* spare_safety2 */
2510 static struct omap_hwmod dra7xx_spare_safety2_hwmod = {
2511 .name = "spare_safety2",
2512 .class = &dra7xx_spare_hwmod_class,
2513 .clkdm_name = "wkupaon_clkdm",
2514 .main_clk = "wkupaon_iclk_mux",
2515 .prcm = {
2516 .omap4 = {
2517 .clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL_OFFSET,
2518 .context_offs = DRA7XX_RM_WKUPAON_SPARE_SAFETY2_CONTEXT_OFFSET,
2519 },
2520 },
2521 };
2523 /* spare_safety3 */
2524 static struct omap_hwmod dra7xx_spare_safety3_hwmod = {
2525 .name = "spare_safety3",
2526 .class = &dra7xx_spare_hwmod_class,
2527 .clkdm_name = "wkupaon_clkdm",
2528 .main_clk = "wkupaon_iclk_mux",
2529 .prcm = {
2530 .omap4 = {
2531 .clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL_OFFSET,
2532 .context_offs = DRA7XX_RM_WKUPAON_SPARE_SAFETY3_CONTEXT_OFFSET,
2533 },
2534 },
2535 };
2537 /* spare_safety4 */
2538 static struct omap_hwmod dra7xx_spare_safety4_hwmod = {
2539 .name = "spare_safety4",
2540 .class = &dra7xx_spare_hwmod_class,
2541 .clkdm_name = "wkupaon_clkdm",
2542 .main_clk = "wkupaon_iclk_mux",
2543 .prcm = {
2544 .omap4 = {
2545 .clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL_OFFSET,
2546 .context_offs = DRA7XX_RM_WKUPAON_SPARE_SAFETY4_CONTEXT_OFFSET,
2547 },
2548 },
2549 };
2551 /* spare_unknown2 */
2552 static struct omap_hwmod dra7xx_spare_unknown2_hwmod = {
2553 .name = "spare_unknown2",
2554 .class = &dra7xx_spare_hwmod_class,
2555 .clkdm_name = "wkupaon_clkdm",
2556 .main_clk = "wkupaon_iclk_mux",
2557 .prcm = {
2558 .omap4 = {
2559 .clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL_OFFSET,
2560 .context_offs = DRA7XX_RM_WKUPAON_SPARE_UNKNOWN2_CONTEXT_OFFSET,
2561 },
2562 },
2563 };
2565 /* spare_unknown3 */
2566 static struct omap_hwmod dra7xx_spare_unknown3_hwmod = {
2567 .name = "spare_unknown3",
2568 .class = &dra7xx_spare_hwmod_class,
2569 .clkdm_name = "wkupaon_clkdm",
2570 .main_clk = "wkupaon_iclk_mux",
2571 .prcm = {
2572 .omap4 = {
2573 .clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL_OFFSET,
2574 .context_offs = DRA7XX_RM_WKUPAON_SPARE_UNKNOWN3_CONTEXT_OFFSET,
2575 },
2576 },
2577 };
2579 /* spare_unknown4 */
2580 static struct omap_hwmod dra7xx_spare_unknown4_hwmod = {
2581 .name = "spare_unknown4",
2582 .class = &dra7xx_spare_hwmod_class,
2583 .clkdm_name = "l3main1_clkdm",
2584 .main_clk = "l4_root_clk_div",
2585 .prcm = {
2586 .omap4 = {
2587 .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL_OFFSET,
2588 .context_offs = DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN4_CONTEXT_OFFSET,
2589 },
2590 },
2591 };
2593 /* spare_unknown5 */
2594 static struct omap_hwmod dra7xx_spare_unknown5_hwmod = {
2595 .name = "spare_unknown5",
2596 .class = &dra7xx_spare_hwmod_class,
2597 .clkdm_name = "l3main1_clkdm",
2598 .main_clk = "l4_root_clk_div",
2599 .prcm = {
2600 .omap4 = {
2601 .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL_OFFSET,
2602 .context_offs = DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN5_CONTEXT_OFFSET,
2603 },
2604 },
2605 };
2607 /* spare_unknown6 */
2608 static struct omap_hwmod dra7xx_spare_unknown6_hwmod = {
2609 .name = "spare_unknown6",
2610 .class = &dra7xx_spare_hwmod_class,
2611 .clkdm_name = "l3main1_clkdm",
2612 .main_clk = "l4_root_clk_div",
2613 .prcm = {
2614 .omap4 = {
2615 .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL_OFFSET,
2616 .context_offs = DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN6_CONTEXT_OFFSET,
2617 },
2618 },
2619 };
2621 /* spare_videopll1 */
2622 static struct omap_hwmod dra7xx_spare_videopll1_hwmod = {
2623 .name = "spare_videopll1",
2624 .class = &dra7xx_spare_hwmod_class,
2625 .clkdm_name = "l3main1_clkdm",
2626 .main_clk = "l4_root_clk_div",
2627 .prcm = {
2628 .omap4 = {
2629 .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL_OFFSET,
2630 .context_offs = DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL1_CONTEXT_OFFSET,
2631 },
2632 },
2633 };
2635 /* spare_videopll2 */
2636 static struct omap_hwmod dra7xx_spare_videopll2_hwmod = {
2637 .name = "spare_videopll2",
2638 .class = &dra7xx_spare_hwmod_class,
2639 .clkdm_name = "l3main1_clkdm",
2640 .main_clk = "l4_root_clk_div",
2641 .prcm = {
2642 .omap4 = {
2643 .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL_OFFSET,
2644 .context_offs = DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL2_CONTEXT_OFFSET,
2645 },
2646 },
2647 };
2649 /* spare_videopll3 */
2650 static struct omap_hwmod dra7xx_spare_videopll3_hwmod = {
2651 .name = "spare_videopll3",
2652 .class = &dra7xx_spare_hwmod_class,
2653 .clkdm_name = "l3main1_clkdm",
2654 .main_clk = "l4_root_clk_div",
2655 .prcm = {
2656 .omap4 = {
2657 .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL_OFFSET,
2658 .context_offs = DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL3_CONTEXT_OFFSET,
2659 },
2660 },
2661 };
2663 /*
2664 * 'spare_sata2' class
2665 *
2666 */
2668 static struct omap_hwmod_class dra7xx_spare_sata2_hwmod_class = {
2669 .name = "spare_sata2",
2670 };
2672 /* spare_sata2 */
2673 static struct omap_hwmod dra7xx_spare_sata2_hwmod = {
2674 .name = "spare_sata2",
2675 .class = &dra7xx_spare_sata2_hwmod_class,
2676 .clkdm_name = "l3main1_clkdm",
2677 .main_clk = "l4_root_clk_div",
2678 .prcm = {
2679 .omap4 = {
2680 .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL_OFFSET,
2681 .context_offs = DRA7XX_RM_L3MAIN1_SPARE_SATA2_CONTEXT_OFFSET,
2682 },
2683 },
2684 };
2686 /*
2687 * 'spare_smartreflex' class
2688 *
2689 */
2691 static struct omap_hwmod_class dra7xx_spare_smartreflex_hwmod_class = {
2692 .name = "spare_smartreflex",
2693 };
2695 /* spare_smartreflex_rtc */
2696 static struct omap_hwmod dra7xx_spare_smartreflex_rtc_hwmod = {
2697 .name = "spare_smartreflex_rtc",
2698 .class = &dra7xx_spare_smartreflex_hwmod_class,
2699 .clkdm_name = "l4cfg_clkdm",
2700 .main_clk = "l4_root_clk_div",
2701 .prcm = {
2702 .omap4 = {
2703 .clkctrl_offs = DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL_OFFSET,
2704 .context_offs = DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_RTC_CONTEXT_OFFSET,
2705 },
2706 },
2707 };
2709 /* spare_smartreflex_sdram */
2710 static struct omap_hwmod dra7xx_spare_smartreflex_sdram_hwmod = {
2711 .name = "spare_smartreflex_sdram",
2712 .class = &dra7xx_spare_smartreflex_hwmod_class,
2713 .clkdm_name = "l4cfg_clkdm",
2714 .main_clk = "l4_root_clk_div",
2715 .prcm = {
2716 .omap4 = {
2717 .clkctrl_offs = DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL_OFFSET,
2718 .context_offs = DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CONTEXT_OFFSET,
2719 },
2720 },
2721 };
2723 /* spare_smartreflex_wkup */
2724 static struct omap_hwmod dra7xx_spare_smartreflex_wkup_hwmod = {
2725 .name = "spare_smartreflex_wkup",
2726 .class = &dra7xx_spare_smartreflex_hwmod_class,
2727 .clkdm_name = "l4cfg_clkdm",
2728 .main_clk = "l4_root_clk_div",
2729 .prcm = {
2730 .omap4 = {
2731 .clkctrl_offs = DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL_OFFSET,
2732 .context_offs = DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_WKUP_CONTEXT_OFFSET,
2733 },
2734 },
2735 };
2737 /*
2738 * 'spinlock' class
2739 *
2740 */
2742 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
2743 .rev_offs = 0x0000,
2744 .sysc_offs = 0x0010,
2745 .syss_offs = 0x0014,
2746 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2747 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2748 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2749 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2750 SIDLE_SMART_WKUP),
2751 .sysc_fields = &omap_hwmod_sysc_type1,
2752 };
2754 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
2755 .name = "spinlock",
2756 .sysc = &dra7xx_spinlock_sysc,
2757 };
2759 /* spinlock */
2760 static struct omap_hwmod dra7xx_spinlock_hwmod = {
2761 .name = "spinlock",
2762 .class = &dra7xx_spinlock_hwmod_class,
2763 .clkdm_name = "l4cfg_clkdm",
2764 .main_clk = "l3_iclk_div",
2765 .prcm = {
2766 .omap4 = {
2767 .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
2768 .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
2769 },
2770 },
2771 };
2773 /*
2774 * 'timer' class
2775 *
2776 * This class contains several variants: ['timer_1ms', 'timer_secure',
2777 * 'timer']
2778 */
2780 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
2781 .rev_offs = 0x0000,
2782 .sysc_offs = 0x0010,
2783 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2784 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2785 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2786 SIDLE_SMART_WKUP),
2787 .sysc_fields = &omap_hwmod_sysc_type2,
2788 };
2790 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
2791 .name = "timer",
2792 .sysc = &dra7xx_timer_1ms_sysc,
2793 };
2795 static struct omap_hwmod_class_sysconfig dra7xx_timer_secure_sysc = {
2796 .rev_offs = 0x0000,
2797 .sysc_offs = 0x0010,
2798 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2799 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2800 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2801 SIDLE_SMART_WKUP),
2802 .sysc_fields = &omap_hwmod_sysc_type2,
2803 };
2805 static struct omap_hwmod_class dra7xx_timer_secure_hwmod_class = {
2806 .name = "timer",
2807 .sysc = &dra7xx_timer_secure_sysc,
2808 };
2810 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
2811 .rev_offs = 0x0000,
2812 .sysc_offs = 0x0010,
2813 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2814 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2815 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2816 SIDLE_SMART_WKUP),
2817 .sysc_fields = &omap_hwmod_sysc_type2,
2818 };
2820 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
2821 .name = "timer",
2822 .sysc = &dra7xx_timer_sysc,
2823 };
2825 /* timer1 */
2826 static struct omap_hwmod_irq_info dra7xx_timer1_irqs[] = {
2827 { .irq = 37 + DRA7XX_IRQ_GIC_START },
2828 { .irq = -1 }
2829 };
2831 static struct omap_hwmod dra7xx_timer1_hwmod = {
2832 .name = "timer1",
2833 .class = &dra7xx_timer_1ms_hwmod_class,
2834 .clkdm_name = "wkupaon_clkdm",
2835 .mpu_irqs = dra7xx_timer1_irqs,
2836 .main_clk = "timer1_gfclk_mux",
2837 .prcm = {
2838 .omap4 = {
2839 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
2840 .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
2841 .modulemode = MODULEMODE_SWCTRL,
2842 },
2843 },
2844 };
2846 /* timer2 */
2847 static struct omap_hwmod_irq_info dra7xx_timer2_irqs[] = {
2848 { .irq = 38 + DRA7XX_IRQ_GIC_START },
2849 { .irq = -1 }
2850 };
2852 static struct omap_hwmod dra7xx_timer2_hwmod = {
2853 .name = "timer2",
2854 .class = &dra7xx_timer_1ms_hwmod_class,
2855 .clkdm_name = "l4per_clkdm",
2856 .mpu_irqs = dra7xx_timer2_irqs,
2857 .main_clk = "timer2_gfclk_mux",
2858 .prcm = {
2859 .omap4 = {
2860 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
2861 .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
2862 .modulemode = MODULEMODE_SWCTRL,
2863 },
2864 },
2865 };
2867 /* timer3 */
2868 static struct omap_hwmod_irq_info dra7xx_timer3_irqs[] = {
2869 { .irq = 39 + DRA7XX_IRQ_GIC_START },
2870 { .irq = -1 }
2871 };
2873 static struct omap_hwmod dra7xx_timer3_hwmod = {
2874 .name = "timer3",
2875 .class = &dra7xx_timer_hwmod_class,
2876 .clkdm_name = "l4per_clkdm",
2877 .mpu_irqs = dra7xx_timer3_irqs,
2878 .main_clk = "timer3_gfclk_mux",
2879 .prcm = {
2880 .omap4 = {
2881 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
2882 .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
2883 .modulemode = MODULEMODE_SWCTRL,
2884 },
2885 },
2886 };
2888 /* timer4 */
2889 static struct omap_hwmod_irq_info dra7xx_timer4_irqs[] = {
2890 { .irq = 40 + DRA7XX_IRQ_GIC_START },
2891 { .irq = -1 }
2892 };
2894 static struct omap_hwmod dra7xx_timer4_hwmod = {
2895 .name = "timer4",
2896 .class = &dra7xx_timer_secure_hwmod_class,
2897 .clkdm_name = "l4per_clkdm",
2898 .mpu_irqs = dra7xx_timer4_irqs,
2899 .main_clk = "timer4_gfclk_mux",
2900 .prcm = {
2901 .omap4 = {
2902 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
2903 .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
2904 .modulemode = MODULEMODE_SWCTRL,
2905 },
2906 },
2907 };
2909 /* timer5 */
2910 static struct omap_hwmod_irq_info dra7xx_timer5_irqs[] = {
2911 { .irq = 41 + DRA7XX_IRQ_GIC_START },
2912 { .irq = -1 }
2913 };
2915 static struct omap_hwmod dra7xx_timer5_hwmod = {
2916 .name = "timer5",
2917 .class = &dra7xx_timer_hwmod_class,
2918 .clkdm_name = "ipu_clkdm",
2919 .mpu_irqs = dra7xx_timer5_irqs,
2920 .main_clk = "timer5_gfclk_mux",
2921 .prcm = {
2922 .omap4 = {
2923 .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
2924 .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
2925 .modulemode = MODULEMODE_SWCTRL,
2926 },
2927 },
2928 };
2930 /* timer6 */
2931 static struct omap_hwmod_irq_info dra7xx_timer6_irqs[] = {
2932 { .irq = 42 + DRA7XX_IRQ_GIC_START },
2933 { .irq = -1 }
2934 };
2936 static struct omap_hwmod dra7xx_timer6_hwmod = {
2937 .name = "timer6",
2938 .class = &dra7xx_timer_hwmod_class,
2939 .clkdm_name = "ipu_clkdm",
2940 .mpu_irqs = dra7xx_timer6_irqs,
2941 .main_clk = "timer6_gfclk_mux",
2942 .prcm = {
2943 .omap4 = {
2944 .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
2945 .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
2946 .modulemode = MODULEMODE_SWCTRL,
2947 },
2948 },
2949 };
2951 /* timer7 */
2952 static struct omap_hwmod_irq_info dra7xx_timer7_irqs[] = {
2953 { .irq = 43 + DRA7XX_IRQ_GIC_START },
2954 { .irq = -1 }
2955 };
2957 static struct omap_hwmod dra7xx_timer7_hwmod = {
2958 .name = "timer7",
2959 .class = &dra7xx_timer_hwmod_class,
2960 .clkdm_name = "ipu_clkdm",
2961 .mpu_irqs = dra7xx_timer7_irqs,
2962 .main_clk = "timer7_gfclk_mux",
2963 .prcm = {
2964 .omap4 = {
2965 .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
2966 .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
2967 .modulemode = MODULEMODE_SWCTRL,
2968 },
2969 },
2970 };
2972 /* timer8 */
2973 static struct omap_hwmod_irq_info dra7xx_timer8_irqs[] = {
2974 { .irq = 44 + DRA7XX_IRQ_GIC_START },
2975 { .irq = -1 }
2976 };
2978 static struct omap_hwmod dra7xx_timer8_hwmod = {
2979 .name = "timer8",
2980 .class = &dra7xx_timer_hwmod_class,
2981 .clkdm_name = "ipu_clkdm",
2982 .mpu_irqs = dra7xx_timer8_irqs,
2983 .main_clk = "timer8_gfclk_mux",
2984 .prcm = {
2985 .omap4 = {
2986 .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
2987 .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
2988 .modulemode = MODULEMODE_SWCTRL,
2989 },
2990 },
2991 };
2993 /* timer9 */
2994 static struct omap_hwmod_irq_info dra7xx_timer9_irqs[] = {
2995 { .irq = 45 + DRA7XX_IRQ_GIC_START },
2996 { .irq = -1 }
2997 };
2999 static struct omap_hwmod dra7xx_timer9_hwmod = {
3000 .name = "timer9",
3001 .class = &dra7xx_timer_hwmod_class,
3002 .clkdm_name = "l4per_clkdm",
3003 .mpu_irqs = dra7xx_timer9_irqs,
3004 .main_clk = "timer9_gfclk_mux",
3005 .prcm = {
3006 .omap4 = {
3007 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
3008 .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
3009 .modulemode = MODULEMODE_SWCTRL,
3010 },
3011 },
3012 };
3014 /* timer10 */
3015 static struct omap_hwmod_irq_info dra7xx_timer10_irqs[] = {
3016 { .irq = 46 + DRA7XX_IRQ_GIC_START },
3017 { .irq = -1 }
3018 };
3020 static struct omap_hwmod dra7xx_timer10_hwmod = {
3021 .name = "timer10",
3022 .class = &dra7xx_timer_1ms_hwmod_class,
3023 .clkdm_name = "l4per_clkdm",
3024 .mpu_irqs = dra7xx_timer10_irqs,
3025 .main_clk = "timer10_gfclk_mux",
3026 .prcm = {
3027 .omap4 = {
3028 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
3029 .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
3030 .modulemode = MODULEMODE_SWCTRL,
3031 },
3032 },
3033 };
3035 /* timer11 */
3036 static struct omap_hwmod_irq_info dra7xx_timer11_irqs[] = {
3037 { .irq = 47 + DRA7XX_IRQ_GIC_START },
3038 { .irq = -1 }
3039 };
3041 static struct omap_hwmod dra7xx_timer11_hwmod = {
3042 .name = "timer11",
3043 .class = &dra7xx_timer_hwmod_class,
3044 .clkdm_name = "l4per_clkdm",
3045 .mpu_irqs = dra7xx_timer11_irqs,
3046 .main_clk = "timer11_gfclk_mux",
3047 .prcm = {
3048 .omap4 = {
3049 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
3050 .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
3051 .modulemode = MODULEMODE_SWCTRL,
3052 },
3053 },
3054 };
3056 /* timer13 */
3057 static struct omap_hwmod dra7xx_timer13_hwmod = {
3058 .name = "timer13",
3059 .class = &dra7xx_timer_hwmod_class,
3060 .clkdm_name = "l4per3_clkdm",
3061 .main_clk = "timer13_gfclk_mux",
3062 .prcm = {
3063 .omap4 = {
3064 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
3065 .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
3066 .modulemode = MODULEMODE_SWCTRL,
3067 },
3068 },
3069 };
3071 /* timer14 */
3072 static struct omap_hwmod dra7xx_timer14_hwmod = {
3073 .name = "timer14",
3074 .class = &dra7xx_timer_hwmod_class,
3075 .clkdm_name = "l4per3_clkdm",
3076 .main_clk = "timer14_gfclk_mux",
3077 .prcm = {
3078 .omap4 = {
3079 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
3080 .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
3081 .modulemode = MODULEMODE_SWCTRL,
3082 },
3083 },
3084 };
3086 /* timer15 */
3087 static struct omap_hwmod dra7xx_timer15_hwmod = {
3088 .name = "timer15",
3089 .class = &dra7xx_timer_hwmod_class,
3090 .clkdm_name = "l4per3_clkdm",
3091 .main_clk = "timer15_gfclk_mux",
3092 .prcm = {
3093 .omap4 = {
3094 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
3095 .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
3096 .modulemode = MODULEMODE_SWCTRL,
3097 },
3098 },
3099 };
3101 /* timer16 */
3102 static struct omap_hwmod dra7xx_timer16_hwmod = {
3103 .name = "timer16",
3104 .class = &dra7xx_timer_hwmod_class,
3105 .clkdm_name = "l4per3_clkdm",
3106 .main_clk = "timer16_gfclk_mux",
3107 .prcm = {
3108 .omap4 = {
3109 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
3110 .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
3111 .modulemode = MODULEMODE_SWCTRL,
3112 },
3113 },
3114 };
3116 /*
3117 * 'uart' class
3118 *
3119 */
3121 static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
3122 .rev_offs = 0x0050,
3123 .sysc_offs = 0x0054,
3124 .syss_offs = 0x0058,
3125 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3126 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3127 SYSS_HAS_RESET_STATUS),
3128 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3129 SIDLE_SMART_WKUP),
3130 .sysc_fields = &omap_hwmod_sysc_type1,
3131 };
3133 static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
3134 .name = "uart",
3135 .sysc = &dra7xx_uart_sysc,
3136 };
3138 /* uart1 */
3139 static struct omap_hwmod_irq_info dra7xx_uart1_irqs[] = {
3140 { .irq = 72 + DRA7XX_IRQ_GIC_START },
3141 { .irq = -1 }
3142 };
3144 static struct omap_hwmod_dma_info dra7xx_uart1_sdma_reqs[] = {
3145 { .name = "49", .dma_req = 48 + DRA7XX_DMA_REQ_START },
3146 { .name = "50", .dma_req = 49 + DRA7XX_DMA_REQ_START },
3147 { .dma_req = -1 }
3148 };
3150 static struct omap_hwmod dra7xx_uart1_hwmod = {
3151 .name = "uart1",
3152 .class = &dra7xx_uart_hwmod_class,
3153 .clkdm_name = "l4per_clkdm",
3154 .mpu_irqs = dra7xx_uart1_irqs,
3155 .sdma_reqs = dra7xx_uart1_sdma_reqs,
3156 .main_clk = "uart1_gfclk_mux",
3157 .flags = HWMOD_SWSUP_SIDLE_ACT,
3158 .prcm = {
3159 .omap4 = {
3160 .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
3161 .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
3162 .modulemode = MODULEMODE_SWCTRL,
3163 },
3164 },
3165 };
3167 /* uart2 */
3168 static struct omap_hwmod_irq_info dra7xx_uart2_irqs[] = {
3169 { .irq = 73 + DRA7XX_IRQ_GIC_START },
3170 { .irq = -1 }
3171 };
3173 static struct omap_hwmod_dma_info dra7xx_uart2_sdma_reqs[] = {
3174 { .name = "51", .dma_req = 50 + DRA7XX_DMA_REQ_START },
3175 { .name = "52", .dma_req = 51 + DRA7XX_DMA_REQ_START },
3176 { .dma_req = -1 }
3177 };
3179 static struct omap_hwmod dra7xx_uart2_hwmod = {
3180 .name = "uart2",
3181 .class = &dra7xx_uart_hwmod_class,
3182 .clkdm_name = "l4per_clkdm",
3183 .mpu_irqs = dra7xx_uart2_irqs,
3184 .sdma_reqs = dra7xx_uart2_sdma_reqs,
3185 .main_clk = "uart2_gfclk_mux",
3186 .flags = HWMOD_SWSUP_SIDLE_ACT,
3187 .prcm = {
3188 .omap4 = {
3189 .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
3190 .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
3191 .modulemode = MODULEMODE_SWCTRL,
3192 },
3193 },
3194 };
3196 /* uart3 */
3197 static struct omap_hwmod_irq_info dra7xx_uart3_irqs[] = {
3198 { .irq = 74 + DRA7XX_IRQ_GIC_START },
3199 { .irq = -1 }
3200 };
3202 static struct omap_hwmod_dma_info dra7xx_uart3_sdma_reqs[] = {
3203 { .name = "53", .dma_req = 52 + DRA7XX_DMA_REQ_START },
3204 { .name = "54", .dma_req = 53 + DRA7XX_DMA_REQ_START },
3205 { .dma_req = -1 }
3206 };
3208 static struct omap_hwmod dra7xx_uart3_hwmod = {
3209 .name = "uart3",
3210 .class = &dra7xx_uart_hwmod_class,
3211 .clkdm_name = "l4per_clkdm",
3212 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
3213 HWMOD_SWSUP_SIDLE_ACT,
3214 .mpu_irqs = dra7xx_uart3_irqs,
3215 .sdma_reqs = dra7xx_uart3_sdma_reqs,
3216 .main_clk = "uart3_gfclk_mux",
3217 .prcm = {
3218 .omap4 = {
3219 .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
3220 .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
3221 .modulemode = MODULEMODE_SWCTRL,
3222 },
3223 },
3224 };
3226 /* uart4 */
3227 static struct omap_hwmod_irq_info dra7xx_uart4_irqs[] = {
3228 { .irq = 70 + DRA7XX_IRQ_GIC_START },
3229 { .irq = -1 }
3230 };
3232 static struct omap_hwmod_dma_info dra7xx_uart4_sdma_reqs[] = {
3233 { .name = "55", .dma_req = 54 + DRA7XX_DMA_REQ_START },
3234 { .name = "56", .dma_req = 55 + DRA7XX_DMA_REQ_START },
3235 { .dma_req = -1 }
3236 };
3238 static struct omap_hwmod dra7xx_uart4_hwmod = {
3239 .name = "uart4",
3240 .class = &dra7xx_uart_hwmod_class,
3241 .clkdm_name = "l4per_clkdm",
3242 .mpu_irqs = dra7xx_uart4_irqs,
3243 .sdma_reqs = dra7xx_uart4_sdma_reqs,
3244 .main_clk = "uart4_gfclk_mux",
3245 .flags = HWMOD_SWSUP_SIDLE_ACT,
3246 .prcm = {
3247 .omap4 = {
3248 .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
3249 .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
3250 .modulemode = MODULEMODE_SWCTRL,
3251 },
3252 },
3253 };
3255 /* uart5 */
3256 static struct omap_hwmod_irq_info dra7xx_uart5_irqs[] = {
3257 { .irq = 105 + DRA7XX_IRQ_GIC_START },
3258 { .irq = -1 }
3259 };
3261 static struct omap_hwmod_dma_info dra7xx_uart5_sdma_reqs[] = {
3262 { .name = "63", .dma_req = 62 + DRA7XX_DMA_REQ_START },
3263 { .name = "64", .dma_req = 63 + DRA7XX_DMA_REQ_START },
3264 { .dma_req = -1 }
3265 };
3267 static struct omap_hwmod dra7xx_uart5_hwmod = {
3268 .name = "uart5",
3269 .class = &dra7xx_uart_hwmod_class,
3270 .clkdm_name = "l4per_clkdm",
3271 .mpu_irqs = dra7xx_uart5_irqs,
3272 .sdma_reqs = dra7xx_uart5_sdma_reqs,
3273 .main_clk = "uart5_gfclk_mux",
3274 .flags = HWMOD_SWSUP_SIDLE_ACT,
3275 .prcm = {
3276 .omap4 = {
3277 .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
3278 .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
3279 .modulemode = MODULEMODE_SWCTRL,
3280 },
3281 },
3282 };
3284 /* uart6 */
3285 static struct omap_hwmod_irq_info dra7xx_uart6_irqs[] = {
3286 { .irq = 106 + DRA7XX_IRQ_GIC_START },
3287 { .irq = -1 }
3288 };
3290 static struct omap_hwmod_dma_info dra7xx_uart6_sdma_reqs[] = {
3291 { .name = "79", .dma_req = 78 + DRA7XX_DMA_REQ_START },
3292 { .name = "80", .dma_req = 79 + DRA7XX_DMA_REQ_START },
3293 { .dma_req = -1 }
3294 };
3296 static struct omap_hwmod dra7xx_uart6_hwmod = {
3297 .name = "uart6",
3298 .class = &dra7xx_uart_hwmod_class,
3299 .clkdm_name = "ipu_clkdm",
3300 .mpu_irqs = dra7xx_uart6_irqs,
3301 .sdma_reqs = dra7xx_uart6_sdma_reqs,
3302 .main_clk = "uart6_gfclk_mux",
3303 .flags = HWMOD_SWSUP_SIDLE_ACT,
3304 .prcm = {
3305 .omap4 = {
3306 .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
3307 .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
3308 .modulemode = MODULEMODE_SWCTRL,
3309 },
3310 },
3311 };
3313 /* uart7 */
3314 static struct omap_hwmod dra7xx_uart7_hwmod = {
3315 .name = "uart7",
3316 .class = &dra7xx_uart_hwmod_class,
3317 .clkdm_name = "l4per2_clkdm",
3318 .main_clk = "uart7_gfclk_mux",
3319 .flags = HWMOD_SWSUP_SIDLE_ACT,
3320 .prcm = {
3321 .omap4 = {
3322 .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
3323 .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
3324 .modulemode = MODULEMODE_SWCTRL,
3325 },
3326 },
3327 };
3329 /* uart8 */
3330 static struct omap_hwmod dra7xx_uart8_hwmod = {
3331 .name = "uart8",
3332 .class = &dra7xx_uart_hwmod_class,
3333 .clkdm_name = "l4per2_clkdm",
3334 .main_clk = "uart8_gfclk_mux",
3335 .flags = HWMOD_SWSUP_SIDLE_ACT,
3336 .prcm = {
3337 .omap4 = {
3338 .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
3339 .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
3340 .modulemode = MODULEMODE_SWCTRL,
3341 },
3342 },
3343 };
3345 /* uart9 */
3346 static struct omap_hwmod dra7xx_uart9_hwmod = {
3347 .name = "uart9",
3348 .class = &dra7xx_uart_hwmod_class,
3349 .clkdm_name = "l4per2_clkdm",
3350 .main_clk = "uart9_gfclk_mux",
3351 .flags = HWMOD_SWSUP_SIDLE_ACT,
3352 .prcm = {
3353 .omap4 = {
3354 .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
3355 .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
3356 .modulemode = MODULEMODE_SWCTRL,
3357 },
3358 },
3359 };
3361 /* uart10 */
3362 static struct omap_hwmod dra7xx_uart10_hwmod = {
3363 .name = "uart10",
3364 .class = &dra7xx_uart_hwmod_class,
3365 .clkdm_name = "wkupaon_clkdm",
3366 .main_clk = "uart10_gfclk_mux",
3367 .flags = HWMOD_SWSUP_SIDLE_ACT,
3368 .prcm = {
3369 .omap4 = {
3370 .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
3371 .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
3372 .modulemode = MODULEMODE_SWCTRL,
3373 },
3374 },
3375 };
3377 /*
3378 * 'usb_otg_ss' class
3379 *
3380 */
3382 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
3383 .name = "usb_otg_ss",
3384 };
3386 /* usb_otg_ss1 */
3387 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
3388 { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
3389 };
3391 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
3392 .name = "usb_otg_ss1",
3393 .class = &dra7xx_usb_otg_ss_hwmod_class,
3394 .clkdm_name = "l3init_clkdm",
3395 .main_clk = "dpll_core_h13x2_ck",
3396 .prcm = {
3397 .omap4 = {
3398 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
3399 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
3400 .modulemode = MODULEMODE_HWCTRL,
3401 },
3402 },
3403 .opt_clks = usb_otg_ss1_opt_clks,
3404 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
3405 };
3407 /* usb_otg_ss2 */
3408 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
3409 { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
3410 };
3412 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
3413 .name = "usb_otg_ss2",
3414 .class = &dra7xx_usb_otg_ss_hwmod_class,
3415 .clkdm_name = "l3init_clkdm",
3416 .main_clk = "dpll_core_h13x2_ck",
3417 .prcm = {
3418 .omap4 = {
3419 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
3420 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
3421 .modulemode = MODULEMODE_HWCTRL,
3422 },
3423 },
3424 .opt_clks = usb_otg_ss2_opt_clks,
3425 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
3426 };
3428 /* usb_otg_ss3 */
3429 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
3430 .name = "usb_otg_ss3",
3431 .class = &dra7xx_usb_otg_ss_hwmod_class,
3432 .clkdm_name = "l3init_clkdm",
3433 .main_clk = "dpll_core_h13x2_ck",
3434 .prcm = {
3435 .omap4 = {
3436 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
3437 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
3438 .modulemode = MODULEMODE_HWCTRL,
3439 },
3440 },
3441 };
3443 /* usb_otg_ss4 */
3444 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
3445 .name = "usb_otg_ss4",
3446 .class = &dra7xx_usb_otg_ss_hwmod_class,
3447 .clkdm_name = "l3init_clkdm",
3448 .main_clk = "dpll_core_h13x2_ck",
3449 .prcm = {
3450 .omap4 = {
3451 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
3452 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
3453 .modulemode = MODULEMODE_HWCTRL,
3454 },
3455 },
3456 };
3458 /*
3459 * 'vcp' class
3460 *
3461 */
3463 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
3464 .name = "vcp",
3465 };
3467 /* vcp1 */
3468 static struct omap_hwmod dra7xx_vcp1_hwmod = {
3469 .name = "vcp1",
3470 .class = &dra7xx_vcp_hwmod_class,
3471 .clkdm_name = "l3main1_clkdm",
3472 .main_clk = "l3_iclk_div",
3473 .prcm = {
3474 .omap4 = {
3475 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
3476 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
3477 },
3478 },
3479 };
3481 /* vcp2 */
3482 static struct omap_hwmod dra7xx_vcp2_hwmod = {
3483 .name = "vcp2",
3484 .class = &dra7xx_vcp_hwmod_class,
3485 .clkdm_name = "l3main1_clkdm",
3486 .main_clk = "l3_iclk_div",
3487 .prcm = {
3488 .omap4 = {
3489 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
3490 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
3491 },
3492 },
3493 };
3495 /*
3496 * 'vip' class
3497 *
3498 */
3500 static struct omap_hwmod_class_sysconfig dra7xx_vip_sysc = {
3501 .sysc_offs = 0x0010,
3502 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
3503 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3504 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3505 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3506 .sysc_fields = &omap_hwmod_sysc_type2,
3507 };
3509 static struct omap_hwmod_class dra7xx_vip_hwmod_class = {
3510 .name = "vip",
3511 .sysc = &dra7xx_vip_sysc,
3512 };
3514 /* vip1 */
3515 static struct omap_hwmod dra7xx_vip1_hwmod = {
3516 .name = "vip1",
3517 .class = &dra7xx_vip_hwmod_class,
3518 .clkdm_name = "cam_clkdm",
3519 .main_clk = "vip1_gclk_mux",
3520 .prcm = {
3521 .omap4 = {
3522 .clkctrl_offs = DRA7XX_CM_CAM_VIP1_CLKCTRL_OFFSET,
3523 .context_offs = DRA7XX_RM_CAM_VIP1_CONTEXT_OFFSET,
3524 .modulemode = MODULEMODE_HWCTRL,
3525 },
3526 },
3527 };
3529 /* vip2 */
3530 static struct omap_hwmod dra7xx_vip2_hwmod = {
3531 .name = "vip2",
3532 .class = &dra7xx_vip_hwmod_class,
3533 .clkdm_name = "cam_clkdm",
3534 .main_clk = "vip2_gclk_mux",
3535 .prcm = {
3536 .omap4 = {
3537 .clkctrl_offs = DRA7XX_CM_CAM_VIP2_CLKCTRL_OFFSET,
3538 .context_offs = DRA7XX_RM_CAM_VIP2_CONTEXT_OFFSET,
3539 .modulemode = MODULEMODE_HWCTRL,
3540 },
3541 },
3542 };
3544 /* vip3 */
3545 static struct omap_hwmod dra7xx_vip3_hwmod = {
3546 .name = "vip3",
3547 .class = &dra7xx_vip_hwmod_class,
3548 .clkdm_name = "cam_clkdm",
3549 .main_clk = "vip3_gclk_mux",
3550 .prcm = {
3551 .omap4 = {
3552 .clkctrl_offs = DRA7XX_CM_CAM_VIP3_CLKCTRL_OFFSET,
3553 .context_offs = DRA7XX_RM_CAM_VIP3_CONTEXT_OFFSET,
3554 .modulemode = MODULEMODE_HWCTRL,
3555 },
3556 },
3557 };
3559 /*
3560 * 'vpe' class
3561 *
3562 */
3564 static struct omap_hwmod_class_sysconfig dra7xx_vpe_sysc = {
3565 .sysc_offs = 0x0010,
3566 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
3567 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3568 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3569 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3570 .sysc_fields = &omap_hwmod_sysc_type2,
3571 };
3573 static struct omap_hwmod_class dra7xx_vpe_hwmod_class = {
3574 .name = "vpe",
3575 .sysc = &dra7xx_vpe_sysc,
3576 };
3578 /* vpe */
3579 static struct omap_hwmod dra7xx_vpe_hwmod = {
3580 .name = "vpe",
3581 .class = &dra7xx_vpe_hwmod_class,
3582 .clkdm_name = "vpe_clkdm",
3583 .main_clk = "dpll_core_h23x2_ck",
3584 .prcm = {
3585 .omap4 = {
3586 .clkctrl_offs = DRA7XX_CM_VPE_VPE_CLKCTRL_OFFSET,
3587 .context_offs = DRA7XX_RM_VPE_VPE_CONTEXT_OFFSET,
3588 .modulemode = MODULEMODE_HWCTRL,
3589 },
3590 },
3591 };
3593 /*
3594 * 'wd_timer' class
3595 *
3596 */
3598 static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
3599 .rev_offs = 0x0000,
3600 .sysc_offs = 0x0010,
3601 .syss_offs = 0x0014,
3602 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3603 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3604 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3605 SIDLE_SMART_WKUP),
3606 .sysc_fields = &omap_hwmod_sysc_type1,
3607 };
3609 static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
3610 .name = "wd_timer",
3611 .sysc = &dra7xx_wd_timer_sysc,
3612 .pre_shutdown = &omap2_wd_timer_disable,
3613 .reset = &omap2_wd_timer_reset,
3614 };
3616 /* wd_timer2 */
3617 static struct omap_hwmod_irq_info dra7xx_wd_timer2_irqs[] = {
3618 { .irq = 80 + DRA7XX_IRQ_GIC_START },
3619 { .irq = -1 }
3620 };
3622 static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
3623 .name = "wd_timer2",
3624 .class = &dra7xx_wd_timer_hwmod_class,
3625 .clkdm_name = "wkupaon_clkdm",
3626 .mpu_irqs = dra7xx_wd_timer2_irqs,
3627 .main_clk = "sys_32k_ck",
3628 .prcm = {
3629 .omap4 = {
3630 .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
3631 .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
3632 .modulemode = MODULEMODE_SWCTRL,
3633 },
3634 },
3635 };
3638 /*
3639 * Interfaces
3640 */
3642 static struct omap_hwmod_addr_space dra7xx_dmm_addrs[] = {
3643 {
3644 .pa_start = 0x4e000000,
3645 .pa_end = 0x4e0007ff,
3646 .flags = ADDR_TYPE_RT
3647 },
3648 { }
3649 };
3651 /* l3_main_1 -> dmm */
3652 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
3653 .master = &dra7xx_l3_main_1_hwmod,
3654 .slave = &dra7xx_dmm_hwmod,
3655 .clk = "l3_iclk_div",
3656 .addr = dra7xx_dmm_addrs,
3657 .user = OCP_USER_SDMA,
3658 };
3660 /* dmm -> emif_ocp_fw */
3661 static struct omap_hwmod_ocp_if dra7xx_dmm__emif_ocp_fw = {
3662 .master = &dra7xx_dmm_hwmod,
3663 .slave = &dra7xx_emif_ocp_fw_hwmod,
3664 .clk = "l3_iclk_div",
3665 .user = OCP_USER_MPU | OCP_USER_SDMA,
3666 };
3668 /* l4_cfg -> emif_ocp_fw */
3669 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__emif_ocp_fw = {
3670 .master = &dra7xx_l4_cfg_hwmod,
3671 .slave = &dra7xx_emif_ocp_fw_hwmod,
3672 .clk = "l3_iclk_div",
3673 .user = OCP_USER_MPU | OCP_USER_SDMA,
3674 };
3676 /* l3_main_2 -> l3_instr */
3677 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
3678 .master = &dra7xx_l3_main_2_hwmod,
3679 .slave = &dra7xx_l3_instr_hwmod,
3680 .clk = "l3_iclk_div",
3681 .user = OCP_USER_MPU | OCP_USER_SDMA,
3682 };
3684 /* ocp_wp_noc -> l3_instr */
3685 static struct omap_hwmod_ocp_if dra7xx_ocp_wp_noc__l3_instr = {
3686 .master = &dra7xx_ocp_wp_noc_hwmod,
3687 .slave = &dra7xx_l3_instr_hwmod,
3688 .clk = "l3_iclk_div",
3689 .user = OCP_USER_MPU | OCP_USER_SDMA,
3690 };
3692 /* l4_cfg -> l3_main_1 */
3693 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
3694 .master = &dra7xx_l4_cfg_hwmod,
3695 .slave = &dra7xx_l3_main_1_hwmod,
3696 .clk = "l3_iclk_div",
3697 .user = OCP_USER_MPU | OCP_USER_SDMA,
3698 };
3700 static struct omap_hwmod_addr_space dra7xx_l3_main_1_addrs[] = {
3701 {
3702 .pa_start = 0x44000000,
3703 .pa_end = 0x44805fff,
3704 },
3705 { }
3706 };
3708 /* mpu -> l3_main_1 */
3709 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
3710 .master = &dra7xx_mpu_hwmod,
3711 .slave = &dra7xx_l3_main_1_hwmod,
3712 .clk = "l3_iclk_div",
3713 .addr = dra7xx_l3_main_1_addrs,
3714 .user = OCP_USER_MPU,
3715 };
3717 static struct omap_hwmod_addr_space dra7xx_l3_main_2_addrs[] = {
3718 {
3719 .pa_start = 0x45000000,
3720 .pa_end = 0x4500afff,
3721 },
3722 { }
3723 };
3725 /* l3_main_1 -> l3_main_2 */
3726 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
3727 .master = &dra7xx_l3_main_1_hwmod,
3728 .slave = &dra7xx_l3_main_2_hwmod,
3729 .clk = "l3_iclk_div",
3730 .addr = dra7xx_l3_main_2_addrs,
3731 .user = OCP_USER_MPU,
3732 };
3734 /* l4_cfg -> l3_main_2 */
3735 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
3736 .master = &dra7xx_l4_cfg_hwmod,
3737 .slave = &dra7xx_l3_main_2_hwmod,
3738 .clk = "l3_iclk_div",
3739 .user = OCP_USER_MPU | OCP_USER_SDMA,
3740 };
3742 /* l3_main_1 -> l4_cfg */
3743 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
3744 .master = &dra7xx_l3_main_1_hwmod,
3745 .slave = &dra7xx_l4_cfg_hwmod,
3746 .clk = "l3_iclk_div",
3747 .user = OCP_USER_MPU | OCP_USER_SDMA,
3748 };
3750 /* l3_main_1 -> l4_per1 */
3751 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
3752 .master = &dra7xx_l3_main_1_hwmod,
3753 .slave = &dra7xx_l4_per1_hwmod,
3754 .clk = "l3_iclk_div",
3755 .user = OCP_USER_MPU | OCP_USER_SDMA,
3756 };
3758 /* l3_main_1 -> l4_per2 */
3759 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
3760 .master = &dra7xx_l3_main_1_hwmod,
3761 .slave = &dra7xx_l4_per2_hwmod,
3762 .clk = "l3_iclk_div",
3763 .user = OCP_USER_MPU | OCP_USER_SDMA,
3764 };
3766 /* l3_main_1 -> l4_per3 */
3767 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
3768 .master = &dra7xx_l3_main_1_hwmod,
3769 .slave = &dra7xx_l4_per3_hwmod,
3770 .clk = "l3_iclk_div",
3771 .user = OCP_USER_MPU | OCP_USER_SDMA,
3772 };
3774 /* l3_main_1 -> l4_wkup */
3775 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
3776 .master = &dra7xx_l3_main_1_hwmod,
3777 .slave = &dra7xx_l4_wkup_hwmod,
3778 .clk = "wkupaon_iclk_mux",
3779 .user = OCP_USER_MPU | OCP_USER_SDMA,
3780 };
3782 /* mpu -> mpu_private */
3783 static struct omap_hwmod_ocp_if dra7xx_mpu__mpu_private = {
3784 .master = &dra7xx_mpu_hwmod,
3785 .slave = &dra7xx_mpu_private_hwmod,
3786 .clk = "l3_iclk_div",
3787 .user = OCP_USER_MPU | OCP_USER_SDMA,
3788 };
3790 /* l3_main_2 -> ocp_wp_noc */
3791 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__ocp_wp_noc = {
3792 .master = &dra7xx_l3_main_2_hwmod,
3793 .slave = &dra7xx_ocp_wp_noc_hwmod,
3794 .clk = "l3_iclk_div",
3795 .user = OCP_USER_MPU | OCP_USER_SDMA,
3796 };
3798 static struct omap_hwmod_addr_space dra7xx_ocp_wp_noc_addrs[] = {
3799 {
3800 .pa_start = 0x4a102000,
3801 .pa_end = 0x4a10207f,
3802 .flags = ADDR_TYPE_RT
3803 },
3804 { }
3805 };
3807 /* l4_cfg -> ocp_wp_noc */
3808 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp_wp_noc = {
3809 .master = &dra7xx_l4_cfg_hwmod,
3810 .slave = &dra7xx_ocp_wp_noc_hwmod,
3811 .clk = "l3_iclk_div",
3812 .addr = dra7xx_ocp_wp_noc_addrs,
3813 .user = OCP_USER_MPU,
3814 };
3816 /* l4_per2 -> atl */
3817 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
3818 .master = &dra7xx_l4_per2_hwmod,
3819 .slave = &dra7xx_atl_hwmod,
3820 .clk = "l3_iclk_div",
3821 .user = OCP_USER_MPU | OCP_USER_SDMA,
3822 };
3824 static struct omap_hwmod_addr_space dra7xx_bb2d_addrs[] = {
3825 {
3826 .pa_start = 0x59000000,
3827 .pa_end = 0x590007ff,
3828 .flags = ADDR_TYPE_RT
3829 },
3830 { }
3831 };
3833 /* l3_main_1 -> bb2d */
3834 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
3835 .master = &dra7xx_l3_main_1_hwmod,
3836 .slave = &dra7xx_bb2d_hwmod,
3837 .clk = "l3_iclk_div",
3838 .addr = dra7xx_bb2d_addrs,
3839 .user = OCP_USER_MPU | OCP_USER_SDMA,
3840 };
3842 static struct omap_hwmod_addr_space dra7xx_counter_32k_addrs[] = {
3843 {
3844 .pa_start = 0x4ae04000,
3845 .pa_end = 0x4ae0403f,
3846 .flags = ADDR_TYPE_RT
3847 },
3848 { }
3849 };
3851 /* l4_wkup -> counter_32k */
3852 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
3853 .master = &dra7xx_l4_wkup_hwmod,
3854 .slave = &dra7xx_counter_32k_hwmod,
3855 .clk = "wkupaon_iclk_mux",
3856 .addr = dra7xx_counter_32k_addrs,
3857 .user = OCP_USER_MPU | OCP_USER_SDMA,
3858 };
3860 static struct omap_hwmod_addr_space dra7xx_ctrl_module_wkup_addrs[] = {
3861 {
3862 .name = "avatar_control_wkup_ocpintf",
3863 .pa_start = 0x4ae0c100,
3864 .pa_end = 0x4ae0c8ff,
3865 },
3866 {
3867 .name = "avatar_control_wkup_pad_ocpintf",
3868 .pa_start = 0x4ae0c5a0,
3869 .pa_end = 0x4ae0c61f,
3870 },
3871 { }
3872 };
3874 /* l4_wkup -> ctrl_module_wkup */
3875 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
3876 .master = &dra7xx_l4_wkup_hwmod,
3877 .slave = &dra7xx_ctrl_module_wkup_hwmod,
3878 .clk = "wkupaon_iclk_mux",
3879 .addr = dra7xx_ctrl_module_wkup_addrs,
3880 .user = OCP_USER_MPU | OCP_USER_SDMA,
3881 };
3883 /* l4_wkup -> dcan1 */
3884 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
3885 .master = &dra7xx_l4_wkup_hwmod,
3886 .slave = &dra7xx_dcan1_hwmod,
3887 .clk = "wkupaon_iclk_mux",
3888 .user = OCP_USER_MPU | OCP_USER_SDMA,
3889 };
3891 /* l4_per2 -> dcan2 */
3892 static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
3893 .master = &dra7xx_l4_per2_hwmod,
3894 .slave = &dra7xx_dcan2_hwmod,
3895 .clk = "l3_iclk_div",
3896 .user = OCP_USER_MPU | OCP_USER_SDMA,
3897 };
3899 static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
3900 {
3901 .pa_start = 0x4a056000,
3902 .pa_end = 0x4a056fff,
3903 .flags = ADDR_TYPE_RT
3904 },
3905 { }
3906 };
3908 /* l4_cfg -> dma_system */
3909 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
3910 .master = &dra7xx_l4_cfg_hwmod,
3911 .slave = &dra7xx_dma_system_hwmod,
3912 .clk = "l3_iclk_div",
3913 .addr = dra7xx_dma_system_addrs,
3914 .user = OCP_USER_MPU | OCP_USER_SDMA,
3915 };
3917 static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
3918 {
3919 .name = "family",
3920 .pa_start = 0x58000000,
3921 .pa_end = 0x5800007f,
3922 .flags = ADDR_TYPE_RT
3923 },
3924 {
3925 .name = "pllctrl1",
3926 .pa_start = 0x58004000,
3927 .pa_end = 0x5800433f,
3928 },
3929 {
3930 .name = "pllctrl2",
3931 .pa_start = 0x58005000,
3932 .pa_end = 0x5800533f,
3933 },
3934 };
3936 /* l3_main_1 -> dss */
3937 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
3938 .master = &dra7xx_l3_main_1_hwmod,
3939 .slave = &dra7xx_dss_hwmod,
3940 .clk = "l3_iclk_div",
3941 .addr = dra7xx_dss_addrs,
3942 .user = OCP_USER_MPU | OCP_USER_SDMA,
3943 };
3945 static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = {
3946 {
3947 .name = "dispc",
3948 .pa_start = 0x58001000,
3949 .pa_end = 0x58001fff,
3950 .flags = ADDR_TYPE_RT
3951 },
3952 };
3954 /* l3_main_1 -> dispc */
3955 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
3956 .master = &dra7xx_l3_main_1_hwmod,
3957 .slave = &dra7xx_dss_dispc_hwmod,
3958 .clk = "l3_iclk_div",
3959 .addr = dra7xx_dss_dispc_addrs,
3960 .user = OCP_USER_MPU | OCP_USER_SDMA,
3961 };
3963 static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = {
3964 {
3965 .name = "hdmi_wp",
3966 .pa_start = 0x58040000,
3967 .pa_end = 0x580400ff,
3968 .flags = ADDR_TYPE_RT
3969 },
3970 {
3971 .name = "pllctrl",
3972 .pa_start = 0x58040200,
3973 .pa_end = 0x5804023f,
3974 },
3975 {
3976 .name = "hdmitxphy",
3977 .pa_start = 0x58040300,
3978 .pa_end = 0x5804033f,
3979 },
3980 {
3981 .name = "hdmi_core",
3982 .pa_start = 0x58060000,
3983 .pa_end = 0x58078fff,
3984 },
3985 {
3986 .name = "deshdcp",
3987 .pa_start = 0x58007000,
3988 .pa_end = 0x5800707f,
3989 },
3990 { }
3991 };
3993 /* l3_main_1 -> dispc */
3994 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
3995 .master = &dra7xx_l3_main_1_hwmod,
3996 .slave = &dra7xx_dss_hdmi_hwmod,
3997 .clk = "l3_iclk_div",
3998 .addr = dra7xx_dss_hdmi_addrs,
3999 .user = OCP_USER_MPU | OCP_USER_SDMA,
4000 };
4002 static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = {
4003 {
4004 .pa_start = 0x48078000,
4005 .pa_end = 0x48078fff,
4006 .flags = ADDR_TYPE_RT
4007 },
4008 { }
4009 };
4011 /* l4_per1 -> elm */
4012 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
4013 .master = &dra7xx_l4_per1_hwmod,
4014 .slave = &dra7xx_elm_hwmod,
4015 .clk = "l3_iclk_div",
4016 .addr = dra7xx_elm_addrs,
4017 .user = OCP_USER_MPU | OCP_USER_SDMA,
4018 };
4020 /* emif_ocp_fw -> emif1 */
4021 static struct omap_hwmod_ocp_if dra7xx_emif_ocp_fw__emif1 = {
4022 .master = &dra7xx_emif_ocp_fw_hwmod,
4023 .slave = &dra7xx_emif1_hwmod,
4024 .clk = "dpll_ddr_h11x2_ck",
4025 .user = OCP_USER_MPU | OCP_USER_SDMA,
4026 };
4028 static struct omap_hwmod_addr_space dra7xx_emif1_addrs[] = {
4029 {
4030 .pa_start = 0x4c000000,
4031 .pa_end = 0x4c0003ff,
4032 .flags = ADDR_TYPE_RT
4033 },
4034 { }
4035 };
4037 /* mpu -> emif1 */
4038 static struct omap_hwmod_ocp_if dra7xx_mpu__emif1 = {
4039 .master = &dra7xx_mpu_hwmod,
4040 .slave = &dra7xx_emif1_hwmod,
4041 .clk = "dpll_ddr_h11x2_ck",
4042 .addr = dra7xx_emif1_addrs,
4043 .user = OCP_USER_MPU,
4044 };
4046 /* emif_ocp_fw -> emif2 */
4047 static struct omap_hwmod_ocp_if dra7xx_emif_ocp_fw__emif2 = {
4048 .master = &dra7xx_emif_ocp_fw_hwmod,
4049 .slave = &dra7xx_emif2_hwmod,
4050 .clk = "dpll_ddr_h11x2_ck",
4051 .user = OCP_USER_MPU | OCP_USER_SDMA,
4052 };
4054 static struct omap_hwmod_addr_space dra7xx_emif2_addrs[] = {
4055 {
4056 .pa_start = 0x4d000000,
4057 .pa_end = 0x4d0003ff,
4058 .flags = ADDR_TYPE_RT
4059 },
4060 { }
4061 };
4063 /* mpu -> emif2 */
4064 static struct omap_hwmod_ocp_if dra7xx_mpu__emif2 = {
4065 .master = &dra7xx_mpu_hwmod,
4066 .slave = &dra7xx_emif2_hwmod,
4067 .clk = "dpll_ddr_h11x2_ck",
4068 .addr = dra7xx_emif2_addrs,
4069 .user = OCP_USER_MPU,
4070 };
4072 static struct omap_hwmod_addr_space dra7xx_gpio1_addrs[] = {
4073 {
4074 .pa_start = 0x4ae10000,
4075 .pa_end = 0x4ae101ff,
4076 .flags = ADDR_TYPE_RT
4077 },
4078 { }
4079 };
4081 /* l4_wkup -> gpio1 */
4082 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
4083 .master = &dra7xx_l4_wkup_hwmod,
4084 .slave = &dra7xx_gpio1_hwmod,
4085 .clk = "wkupaon_iclk_mux",
4086 .addr = dra7xx_gpio1_addrs,
4087 .user = OCP_USER_MPU | OCP_USER_SDMA,
4088 };
4090 static struct omap_hwmod_addr_space dra7xx_gpio2_addrs[] = {
4091 {
4092 .pa_start = 0x48055000,
4093 .pa_end = 0x480551ff,
4094 .flags = ADDR_TYPE_RT
4095 },
4096 { }
4097 };
4099 /* l4_per1 -> gpio2 */
4100 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
4101 .master = &dra7xx_l4_per1_hwmod,
4102 .slave = &dra7xx_gpio2_hwmod,
4103 .clk = "l3_iclk_div",
4104 .addr = dra7xx_gpio2_addrs,
4105 .user = OCP_USER_MPU | OCP_USER_SDMA,
4106 };
4108 static struct omap_hwmod_addr_space dra7xx_gpio3_addrs[] = {
4109 {
4110 .pa_start = 0x48057000,
4111 .pa_end = 0x480571ff,
4112 .flags = ADDR_TYPE_RT
4113 },
4114 { }
4115 };
4117 /* l4_per1 -> gpio3 */
4118 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
4119 .master = &dra7xx_l4_per1_hwmod,
4120 .slave = &dra7xx_gpio3_hwmod,
4121 .clk = "l3_iclk_div",
4122 .addr = dra7xx_gpio3_addrs,
4123 .user = OCP_USER_MPU | OCP_USER_SDMA,
4124 };
4126 static struct omap_hwmod_addr_space dra7xx_gpio4_addrs[] = {
4127 {
4128 .pa_start = 0x48059000,
4129 .pa_end = 0x480591ff,
4130 .flags = ADDR_TYPE_RT
4131 },
4132 { }
4133 };
4135 /* l4_per1 -> gpio4 */
4136 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
4137 .master = &dra7xx_l4_per1_hwmod,
4138 .slave = &dra7xx_gpio4_hwmod,
4139 .clk = "l3_iclk_div",
4140 .addr = dra7xx_gpio4_addrs,
4141 .user = OCP_USER_MPU | OCP_USER_SDMA,
4142 };
4144 static struct omap_hwmod_addr_space dra7xx_gpio5_addrs[] = {
4145 {
4146 .pa_start = 0x4805b000,
4147 .pa_end = 0x4805b1ff,
4148 .flags = ADDR_TYPE_RT
4149 },
4150 { }
4151 };
4153 /* l4_per1 -> gpio5 */
4154 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
4155 .master = &dra7xx_l4_per1_hwmod,
4156 .slave = &dra7xx_gpio5_hwmod,
4157 .clk = "l3_iclk_div",
4158 .addr = dra7xx_gpio5_addrs,
4159 .user = OCP_USER_MPU | OCP_USER_SDMA,
4160 };
4162 static struct omap_hwmod_addr_space dra7xx_gpio6_addrs[] = {
4163 {
4164 .pa_start = 0x4805d000,
4165 .pa_end = 0x4805d1ff,
4166 .flags = ADDR_TYPE_RT
4167 },
4168 { }
4169 };
4171 /* l4_per1 -> gpio6 */
4172 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
4173 .master = &dra7xx_l4_per1_hwmod,
4174 .slave = &dra7xx_gpio6_hwmod,
4175 .clk = "l3_iclk_div",
4176 .addr = dra7xx_gpio6_addrs,
4177 .user = OCP_USER_MPU | OCP_USER_SDMA,
4178 };
4180 static struct omap_hwmod_addr_space dra7xx_gpio7_addrs[] = {
4181 {
4182 .pa_start = 0x48051000,
4183 .pa_end = 0x480511ff,
4184 .flags = ADDR_TYPE_RT
4185 },
4186 { }
4187 };
4189 /* l4_per1 -> gpio7 */
4190 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
4191 .master = &dra7xx_l4_per1_hwmod,
4192 .slave = &dra7xx_gpio7_hwmod,
4193 .clk = "l3_iclk_div",
4194 .addr = dra7xx_gpio7_addrs,
4195 .user = OCP_USER_MPU | OCP_USER_SDMA,
4196 };
4198 static struct omap_hwmod_addr_space dra7xx_gpio8_addrs[] = {
4199 {
4200 .pa_start = 0x48053000,
4201 .pa_end = 0x480531ff,
4202 .flags = ADDR_TYPE_RT
4203 },
4204 { }
4205 };
4207 /* l4_per1 -> gpio8 */
4208 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
4209 .master = &dra7xx_l4_per1_hwmod,
4210 .slave = &dra7xx_gpio8_hwmod,
4211 .clk = "l3_iclk_div",
4212 .addr = dra7xx_gpio8_addrs,
4213 .user = OCP_USER_MPU | OCP_USER_SDMA,
4214 };
4216 static struct omap_hwmod_addr_space dra7xx_gpmc_addrs[] = {
4217 {
4218 .pa_start = 0x50000000,
4219 .pa_end = 0x500003ff,
4220 .flags = ADDR_TYPE_RT
4221 },
4222 { }
4223 };
4225 /* l3_main_1 -> gpmc */
4226 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
4227 .master = &dra7xx_l3_main_1_hwmod,
4228 .slave = &dra7xx_gpmc_hwmod,
4229 .clk = "l3_iclk_div",
4230 .addr = dra7xx_gpmc_addrs,
4231 .user = OCP_USER_MPU | OCP_USER_SDMA,
4232 };
4234 static struct omap_hwmod_addr_space dra7xx_gpu_addrs[] = {
4235 {
4236 .name = "klio",
4237 .pa_start = 0x56000000,
4238 .pa_end = 0x56001fff,
4239 },
4240 {
4241 .name = "hydra2",
4242 .pa_start = 0x56004000,
4243 .pa_end = 0x56004fff,
4244 },
4245 {
4246 .name = "klio_0",
4247 .pa_start = 0x56008000,
4248 .pa_end = 0x56009fff,
4249 },
4250 {
4251 .name = "klio_1",
4252 .pa_start = 0x5600c000,
4253 .pa_end = 0x5600dfff,
4254 },
4255 {
4256 .name = "klio_hl",
4257 .pa_start = 0x5600fe00,
4258 .pa_end = 0x5600ffff,
4259 .flags = ADDR_TYPE_RT
4260 },
4261 { }
4262 };
4264 /* l3_main_1 -> gpu */
4265 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpu = {
4266 .master = &dra7xx_l3_main_1_hwmod,
4267 .slave = &dra7xx_gpu_hwmod,
4268 .clk = "gpu_l3_iclk",
4269 .addr = dra7xx_gpu_addrs,
4270 .user = OCP_USER_MPU | OCP_USER_SDMA,
4271 };
4273 static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
4274 {
4275 .pa_start = 0x480b2000,
4276 .pa_end = 0x480b201f,
4277 .flags = ADDR_TYPE_RT
4278 },
4279 { }
4280 };
4282 /* l4_per1 -> hdq1w */
4283 static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
4284 .master = &dra7xx_l4_per1_hwmod,
4285 .slave = &dra7xx_hdq1w_hwmod,
4286 .clk = "l3_iclk_div",
4287 .addr = dra7xx_hdq1w_addrs,
4288 .user = OCP_USER_MPU | OCP_USER_SDMA,
4289 };
4291 static struct omap_hwmod_addr_space dra7xx_i2c1_addrs[] = {
4292 {
4293 .pa_start = 0x48070000,
4294 .pa_end = 0x480700ff,
4295 .flags = ADDR_TYPE_RT
4296 },
4297 { }
4298 };
4300 /* l4_per1 -> i2c1 */
4301 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
4302 .master = &dra7xx_l4_per1_hwmod,
4303 .slave = &dra7xx_i2c1_hwmod,
4304 .clk = "l3_iclk_div",
4305 .addr = dra7xx_i2c1_addrs,
4306 .user = OCP_USER_MPU | OCP_USER_SDMA,
4307 };
4309 static struct omap_hwmod_addr_space dra7xx_i2c2_addrs[] = {
4310 {
4311 .pa_start = 0x48072000,
4312 .pa_end = 0x480720ff,
4313 .flags = ADDR_TYPE_RT
4314 },
4315 { }
4316 };
4318 /* l4_per1 -> i2c2 */
4319 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
4320 .master = &dra7xx_l4_per1_hwmod,
4321 .slave = &dra7xx_i2c2_hwmod,
4322 .clk = "l3_iclk_div",
4323 .addr = dra7xx_i2c2_addrs,
4324 .user = OCP_USER_MPU | OCP_USER_SDMA,
4325 };
4327 static struct omap_hwmod_addr_space dra7xx_i2c3_addrs[] = {
4328 {
4329 .pa_start = 0x48060000,
4330 .pa_end = 0x480600ff,
4331 .flags = ADDR_TYPE_RT
4332 },
4333 { }
4334 };
4336 /* l4_per1 -> i2c3 */
4337 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
4338 .master = &dra7xx_l4_per1_hwmod,
4339 .slave = &dra7xx_i2c3_hwmod,
4340 .clk = "l3_iclk_div",
4341 .addr = dra7xx_i2c3_addrs,
4342 .user = OCP_USER_MPU | OCP_USER_SDMA,
4343 };
4345 static struct omap_hwmod_addr_space dra7xx_i2c4_addrs[] = {
4346 {
4347 .pa_start = 0x4807a000,
4348 .pa_end = 0x4807a0ff,
4349 .flags = ADDR_TYPE_RT
4350 },
4351 { }
4352 };
4354 /* l4_per1 -> i2c4 */
4355 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
4356 .master = &dra7xx_l4_per1_hwmod,
4357 .slave = &dra7xx_i2c4_hwmod,
4358 .clk = "l3_iclk_div",
4359 .addr = dra7xx_i2c4_addrs,
4360 .user = OCP_USER_MPU | OCP_USER_SDMA,
4361 };
4363 static struct omap_hwmod_addr_space dra7xx_i2c5_addrs[] = {
4364 {
4365 .pa_start = 0x4807c000,
4366 .pa_end = 0x4807c0ff,
4367 .flags = ADDR_TYPE_RT
4368 },
4369 { }
4370 };
4372 /* l4_per1 -> i2c5 */
4373 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
4374 .master = &dra7xx_l4_per1_hwmod,
4375 .slave = &dra7xx_i2c5_hwmod,
4376 .clk = "l3_iclk_div",
4377 .addr = dra7xx_i2c5_addrs,
4378 .user = OCP_USER_MPU | OCP_USER_SDMA,
4379 };
4381 static struct omap_hwmod_addr_space dra7xx_mailbox1_addrs[] = {
4382 {
4383 .pa_start = 0x4a0f4000,
4384 .pa_end = 0x4a0f41ff,
4385 .flags = ADDR_TYPE_RT
4386 },
4387 { }
4388 };
4390 /* l4_cfg -> mailbox1 */
4391 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
4392 .master = &dra7xx_l4_cfg_hwmod,
4393 .slave = &dra7xx_mailbox1_hwmod,
4394 .clk = "l3_iclk_div",
4395 .addr = dra7xx_mailbox1_addrs,
4396 .user = OCP_USER_MPU | OCP_USER_SDMA,
4397 };
4399 static struct omap_hwmod_addr_space dra7xx_mailbox2_addrs[] = {
4400 {
4401 .pa_start = 0x4883a000,
4402 .pa_end = 0x4883a1ff,
4403 .flags = ADDR_TYPE_RT
4404 },
4405 { }
4406 };
4408 /* l4_per3 -> mailbox2 */
4409 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
4410 .master = &dra7xx_l4_per3_hwmod,
4411 .slave = &dra7xx_mailbox2_hwmod,
4412 .clk = "l3_iclk_div",
4413 .addr = dra7xx_mailbox2_addrs,
4414 .user = OCP_USER_MPU | OCP_USER_SDMA,
4415 };
4417 static struct omap_hwmod_addr_space dra7xx_mailbox3_addrs[] = {
4418 {
4419 .pa_start = 0x4883c000,
4420 .pa_end = 0x4883c1ff,
4421 .flags = ADDR_TYPE_RT
4422 },
4423 { }
4424 };
4426 /* l4_per3 -> mailbox3 */
4427 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
4428 .master = &dra7xx_l4_per3_hwmod,
4429 .slave = &dra7xx_mailbox3_hwmod,
4430 .clk = "l3_iclk_div",
4431 .addr = dra7xx_mailbox3_addrs,
4432 .user = OCP_USER_MPU | OCP_USER_SDMA,
4433 };
4435 static struct omap_hwmod_addr_space dra7xx_mailbox4_addrs[] = {
4436 {
4437 .pa_start = 0x4883e000,
4438 .pa_end = 0x4883e1ff,
4439 .flags = ADDR_TYPE_RT
4440 },
4441 { }
4442 };
4444 /* l4_per3 -> mailbox4 */
4445 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
4446 .master = &dra7xx_l4_per3_hwmod,
4447 .slave = &dra7xx_mailbox4_hwmod,
4448 .clk = "l3_iclk_div",
4449 .addr = dra7xx_mailbox4_addrs,
4450 .user = OCP_USER_MPU | OCP_USER_SDMA,
4451 };
4453 static struct omap_hwmod_addr_space dra7xx_mailbox5_addrs[] = {
4454 {
4455 .pa_start = 0x48840000,
4456 .pa_end = 0x488401ff,
4457 .flags = ADDR_TYPE_RT
4458 },
4459 { }
4460 };
4462 /* l4_per3 -> mailbox5 */
4463 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
4464 .master = &dra7xx_l4_per3_hwmod,
4465 .slave = &dra7xx_mailbox5_hwmod,
4466 .clk = "l3_iclk_div",
4467 .addr = dra7xx_mailbox5_addrs,
4468 .user = OCP_USER_MPU | OCP_USER_SDMA,
4469 };
4471 static struct omap_hwmod_addr_space dra7xx_mailbox6_addrs[] = {
4472 {
4473 .pa_start = 0x48842000,
4474 .pa_end = 0x488421ff,
4475 .flags = ADDR_TYPE_RT
4476 },
4477 { }
4478 };
4480 /* l4_per3 -> mailbox6 */
4481 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
4482 .master = &dra7xx_l4_per3_hwmod,
4483 .slave = &dra7xx_mailbox6_hwmod,
4484 .clk = "l3_iclk_div",
4485 .addr = dra7xx_mailbox6_addrs,
4486 .user = OCP_USER_MPU | OCP_USER_SDMA,
4487 };
4489 static struct omap_hwmod_addr_space dra7xx_mailbox7_addrs[] = {
4490 {
4491 .pa_start = 0x48844000,
4492 .pa_end = 0x488441ff,
4493 .flags = ADDR_TYPE_RT
4494 },
4495 { }
4496 };
4498 /* l4_per3 -> mailbox7 */
4499 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
4500 .master = &dra7xx_l4_per3_hwmod,
4501 .slave = &dra7xx_mailbox7_hwmod,
4502 .clk = "l3_iclk_div",
4503 .addr = dra7xx_mailbox7_addrs,
4504 .user = OCP_USER_MPU | OCP_USER_SDMA,
4505 };
4507 static struct omap_hwmod_addr_space dra7xx_mailbox8_addrs[] = {
4508 {
4509 .pa_start = 0x48846000,
4510 .pa_end = 0x488461ff,
4511 .flags = ADDR_TYPE_RT
4512 },
4513 { }
4514 };
4516 /* l4_per3 -> mailbox8 */
4517 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
4518 .master = &dra7xx_l4_per3_hwmod,
4519 .slave = &dra7xx_mailbox8_hwmod,
4520 .clk = "l3_iclk_div",
4521 .addr = dra7xx_mailbox8_addrs,
4522 .user = OCP_USER_MPU | OCP_USER_SDMA,
4523 };
4525 static struct omap_hwmod_addr_space dra7xx_mailbox9_addrs[] = {
4526 {
4527 .pa_start = 0x4885e000,
4528 .pa_end = 0x4885e1ff,
4529 .flags = ADDR_TYPE_RT
4530 },
4531 { }
4532 };
4534 /* l4_per3 -> mailbox9 */
4535 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
4536 .master = &dra7xx_l4_per3_hwmod,
4537 .slave = &dra7xx_mailbox9_hwmod,
4538 .clk = "l3_iclk_div",
4539 .addr = dra7xx_mailbox9_addrs,
4540 .user = OCP_USER_MPU | OCP_USER_SDMA,
4541 };
4543 static struct omap_hwmod_addr_space dra7xx_mailbox10_addrs[] = {
4544 {
4545 .pa_start = 0x48860000,
4546 .pa_end = 0x488601ff,
4547 .flags = ADDR_TYPE_RT
4548 },
4549 { }
4550 };
4552 /* l4_per3 -> mailbox10 */
4553 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
4554 .master = &dra7xx_l4_per3_hwmod,
4555 .slave = &dra7xx_mailbox10_hwmod,
4556 .clk = "l3_iclk_div",
4557 .addr = dra7xx_mailbox10_addrs,
4558 .user = OCP_USER_MPU | OCP_USER_SDMA,
4559 };
4561 static struct omap_hwmod_addr_space dra7xx_mailbox11_addrs[] = {
4562 {
4563 .pa_start = 0x48862000,
4564 .pa_end = 0x488621ff,
4565 .flags = ADDR_TYPE_RT
4566 },
4567 { }
4568 };
4570 /* l4_per3 -> mailbox11 */
4571 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
4572 .master = &dra7xx_l4_per3_hwmod,
4573 .slave = &dra7xx_mailbox11_hwmod,
4574 .clk = "l3_iclk_div",
4575 .addr = dra7xx_mailbox11_addrs,
4576 .user = OCP_USER_MPU | OCP_USER_SDMA,
4577 };
4579 static struct omap_hwmod_addr_space dra7xx_mailbox12_addrs[] = {
4580 {
4581 .pa_start = 0x48864000,
4582 .pa_end = 0x488641ff,
4583 .flags = ADDR_TYPE_RT
4584 },
4585 { }
4586 };
4588 /* l4_per3 -> mailbox12 */
4589 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
4590 .master = &dra7xx_l4_per3_hwmod,
4591 .slave = &dra7xx_mailbox12_hwmod,
4592 .clk = "l3_iclk_div",
4593 .addr = dra7xx_mailbox12_addrs,
4594 .user = OCP_USER_MPU | OCP_USER_SDMA,
4595 };
4597 static struct omap_hwmod_addr_space dra7xx_mailbox13_addrs[] = {
4598 {
4599 .pa_start = 0x48802000,
4600 .pa_end = 0x488021ff,
4601 .flags = ADDR_TYPE_RT
4602 },
4603 { }
4604 };
4606 /* l4_per3 -> mailbox13 */
4607 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
4608 .master = &dra7xx_l4_per3_hwmod,
4609 .slave = &dra7xx_mailbox13_hwmod,
4610 .clk = "l3_iclk_div",
4611 .addr = dra7xx_mailbox13_addrs,
4612 .user = OCP_USER_MPU | OCP_USER_SDMA,
4613 };
4615 /* l3_main_1 -> mcasp1 */
4616 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp1 = {
4617 .master = &dra7xx_l3_main_1_hwmod,
4618 .slave = &dra7xx_mcasp1_hwmod,
4619 .clk = "l3_iclk_div",
4620 .user = OCP_USER_MPU | OCP_USER_SDMA,
4621 };
4623 static struct omap_hwmod_addr_space dra7xx_mcasp1_addrs[] = {
4624 {
4625 .pa_start = 0x48460000,
4626 .pa_end = 0x484603ff,
4627 .flags = ADDR_TYPE_RT
4628 },
4629 { }
4630 };
4632 /* l4_per2 -> mcasp1 */
4633 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = {
4634 .master = &dra7xx_l4_per2_hwmod,
4635 .slave = &dra7xx_mcasp1_hwmod,
4636 .clk = "l3_iclk_div",
4637 .addr = dra7xx_mcasp1_addrs,
4638 .user = OCP_USER_MPU,
4639 };
4641 static struct omap_hwmod_addr_space dra7xx_mcasp2_addrs[] = {
4642 {
4643 .pa_start = 0x48464000,
4644 .pa_end = 0x484643ff,
4645 .flags = ADDR_TYPE_RT
4646 },
4647 { }
4648 };
4650 /* l3_main_1 -> mcasp2 */
4651 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp2 = {
4652 .master = &dra7xx_l3_main_1_hwmod,
4653 .slave = &dra7xx_mcasp2_hwmod,
4654 .clk = "l3_iclk_div",
4655 .addr = dra7xx_mcasp2_addrs,
4656 .user = OCP_USER_MPU | OCP_USER_SDMA,
4657 };
4659 static struct omap_hwmod_addr_space dra7xx_mcasp3_addrs[] = {
4660 {
4661 .pa_start = 0x48468000,
4662 .pa_end = 0x484683ff,
4663 .flags = ADDR_TYPE_RT
4664 },
4665 { }
4666 };
4668 /* l3_main_1 -> mcasp3 */
4669 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = {
4670 .master = &dra7xx_l3_main_1_hwmod,
4671 .slave = &dra7xx_mcasp3_hwmod,
4672 .clk = "l3_iclk_div",
4673 .addr = dra7xx_mcasp3_addrs,
4674 .user = OCP_USER_MPU | OCP_USER_SDMA,
4675 };
4677 static struct omap_hwmod_addr_space dra7xx_mcasp4_addrs[] = {
4678 {
4679 .pa_start = 0x4846c000,
4680 .pa_end = 0x4846c3ff,
4681 .flags = ADDR_TYPE_RT
4682 },
4683 { }
4684 };
4686 /* l4_per2 -> mcasp4 */
4687 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp4 = {
4688 .master = &dra7xx_l4_per2_hwmod,
4689 .slave = &dra7xx_mcasp4_hwmod,
4690 .clk = "l3_iclk_div",
4691 .addr = dra7xx_mcasp4_addrs,
4692 .user = OCP_USER_MPU | OCP_USER_SDMA,
4693 };
4695 static struct omap_hwmod_addr_space dra7xx_mcasp5_addrs[] = {
4696 {
4697 .pa_start = 0x48470000,
4698 .pa_end = 0x484703ff,
4699 .flags = ADDR_TYPE_RT
4700 },
4701 { }
4702 };
4704 /* l4_per2 -> mcasp5 */
4705 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp5 = {
4706 .master = &dra7xx_l4_per2_hwmod,
4707 .slave = &dra7xx_mcasp5_hwmod,
4708 .clk = "l3_iclk_div",
4709 .addr = dra7xx_mcasp5_addrs,
4710 .user = OCP_USER_MPU | OCP_USER_SDMA,
4711 };
4713 static struct omap_hwmod_addr_space dra7xx_mcasp6_addrs[] = {
4714 {
4715 .pa_start = 0x48474000,
4716 .pa_end = 0x484743ff,
4717 .flags = ADDR_TYPE_RT
4718 },
4719 { }
4720 };
4722 /* l4_per2 -> mcasp6 */
4723 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = {
4724 .master = &dra7xx_l4_per2_hwmod,
4725 .slave = &dra7xx_mcasp6_hwmod,
4726 .clk = "l3_iclk_div",
4727 .addr = dra7xx_mcasp6_addrs,
4728 .user = OCP_USER_MPU | OCP_USER_SDMA,
4729 };
4731 static struct omap_hwmod_addr_space dra7xx_mcasp7_addrs[] = {
4732 {
4733 .pa_start = 0x48478000,
4734 .pa_end = 0x484783ff,
4735 .flags = ADDR_TYPE_RT
4736 },
4737 { }
4738 };
4740 /* l4_per2 -> mcasp7 */
4741 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = {
4742 .master = &dra7xx_l4_per2_hwmod,
4743 .slave = &dra7xx_mcasp7_hwmod,
4744 .clk = "l3_iclk_div",
4745 .addr = dra7xx_mcasp7_addrs,
4746 .user = OCP_USER_MPU | OCP_USER_SDMA,
4747 };
4749 static struct omap_hwmod_addr_space dra7xx_mcasp8_addrs[] = {
4750 {
4751 .pa_start = 0x4847c000,
4752 .pa_end = 0x4847c3ff,
4753 .flags = ADDR_TYPE_RT
4754 },
4755 { }
4756 };
4758 /* l4_per2 -> mcasp8 */
4759 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = {
4760 .master = &dra7xx_l4_per2_hwmod,
4761 .slave = &dra7xx_mcasp8_hwmod,
4762 .clk = "l3_iclk_div",
4763 .addr = dra7xx_mcasp8_addrs,
4764 .user = OCP_USER_MPU | OCP_USER_SDMA,
4765 };
4767 static struct omap_hwmod_addr_space dra7xx_mcspi1_addrs[] = {
4768 {
4769 .pa_start = 0x48098000,
4770 .pa_end = 0x480981ff,
4771 .flags = ADDR_TYPE_RT
4772 },
4773 { }
4774 };
4776 /* l4_per1 -> mcspi1 */
4777 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
4778 .master = &dra7xx_l4_per1_hwmod,
4779 .slave = &dra7xx_mcspi1_hwmod,
4780 .clk = "l3_iclk_div",
4781 .addr = dra7xx_mcspi1_addrs,
4782 .user = OCP_USER_MPU | OCP_USER_SDMA,
4783 };
4785 static struct omap_hwmod_addr_space dra7xx_mcspi2_addrs[] = {
4786 {
4787 .pa_start = 0x4809a000,
4788 .pa_end = 0x4809a1ff,
4789 .flags = ADDR_TYPE_RT
4790 },
4791 { }
4792 };
4794 /* l4_per1 -> mcspi2 */
4795 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
4796 .master = &dra7xx_l4_per1_hwmod,
4797 .slave = &dra7xx_mcspi2_hwmod,
4798 .clk = "l3_iclk_div",
4799 .addr = dra7xx_mcspi2_addrs,
4800 .user = OCP_USER_MPU | OCP_USER_SDMA,
4801 };
4803 static struct omap_hwmod_addr_space dra7xx_mcspi3_addrs[] = {
4804 {
4805 .pa_start = 0x480b8000,
4806 .pa_end = 0x480b81ff,
4807 .flags = ADDR_TYPE_RT
4808 },
4809 { }
4810 };
4812 /* l4_per1 -> mcspi3 */
4813 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
4814 .master = &dra7xx_l4_per1_hwmod,
4815 .slave = &dra7xx_mcspi3_hwmod,
4816 .clk = "l3_iclk_div",
4817 .addr = dra7xx_mcspi3_addrs,
4818 .user = OCP_USER_MPU | OCP_USER_SDMA,
4819 };
4821 static struct omap_hwmod_addr_space dra7xx_mcspi4_addrs[] = {
4822 {
4823 .pa_start = 0x480ba000,
4824 .pa_end = 0x480ba1ff,
4825 .flags = ADDR_TYPE_RT
4826 },
4827 { }
4828 };
4830 /* l4_per1 -> mcspi4 */
4831 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
4832 .master = &dra7xx_l4_per1_hwmod,
4833 .slave = &dra7xx_mcspi4_hwmod,
4834 .clk = "l3_iclk_div",
4835 .addr = dra7xx_mcspi4_addrs,
4836 .user = OCP_USER_MPU | OCP_USER_SDMA,
4837 };
4839 static struct omap_hwmod_addr_space dra7xx_mmc1_addrs[] = {
4840 {
4841 .pa_start = 0x4809c000,
4842 .pa_end = 0x4809c3ff,
4843 .flags = ADDR_TYPE_RT
4844 },
4845 { }
4846 };
4848 /* l4_per1 -> mmc1 */
4849 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
4850 .master = &dra7xx_l4_per1_hwmod,
4851 .slave = &dra7xx_mmc1_hwmod,
4852 .clk = "l3_iclk_div",
4853 .addr = dra7xx_mmc1_addrs,
4854 .user = OCP_USER_MPU | OCP_USER_SDMA,
4855 };
4857 static struct omap_hwmod_addr_space dra7xx_mmc2_addrs[] = {
4858 {
4859 .pa_start = 0x480b4000,
4860 .pa_end = 0x480b43ff,
4861 .flags = ADDR_TYPE_RT
4862 },
4863 { }
4864 };
4866 /* l4_per1 -> mmc2 */
4867 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
4868 .master = &dra7xx_l4_per1_hwmod,
4869 .slave = &dra7xx_mmc2_hwmod,
4870 .clk = "l3_iclk_div",
4871 .addr = dra7xx_mmc2_addrs,
4872 .user = OCP_USER_MPU | OCP_USER_SDMA,
4873 };
4875 static struct omap_hwmod_addr_space dra7xx_mmc3_addrs[] = {
4876 {
4877 .pa_start = 0x480ad000,
4878 .pa_end = 0x480ad3ff,
4879 .flags = ADDR_TYPE_RT
4880 },
4881 { }
4882 };
4884 /* l4_per1 -> mmc3 */
4885 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
4886 .master = &dra7xx_l4_per1_hwmod,
4887 .slave = &dra7xx_mmc3_hwmod,
4888 .clk = "l3_iclk_div",
4889 .addr = dra7xx_mmc3_addrs,
4890 .user = OCP_USER_MPU | OCP_USER_SDMA,
4891 };
4893 static struct omap_hwmod_addr_space dra7xx_mmc4_addrs[] = {
4894 {
4895 .pa_start = 0x480d1000,
4896 .pa_end = 0x480d13ff,
4897 .flags = ADDR_TYPE_RT
4898 },
4899 { }
4900 };
4902 /* l4_per1 -> mmc4 */
4903 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
4904 .master = &dra7xx_l4_per1_hwmod,
4905 .slave = &dra7xx_mmc4_hwmod,
4906 .clk = "l3_iclk_div",
4907 .addr = dra7xx_mmc4_addrs,
4908 .user = OCP_USER_MPU | OCP_USER_SDMA,
4909 };
4911 static struct omap_hwmod_addr_space dra7xx_mpu_addrs[] = {
4912 {
4913 .pa_start = 0x47000000,
4914 .pa_end = 0x482af27f,
4915 },
4916 { }
4917 };
4919 /* l4_cfg -> mpu */
4920 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
4921 .master = &dra7xx_l4_cfg_hwmod,
4922 .slave = &dra7xx_mpu_hwmod,
4923 .clk = "l3_iclk_div",
4924 .addr = dra7xx_mpu_addrs,
4925 .user = OCP_USER_MPU | OCP_USER_SDMA,
4926 };
4928 /* l4_per3 -> ocmc_ram1 */
4929 static struct omap_hwmod_ocp_if dra7xx_l4_per3__ocmc_ram1 = {
4930 .master = &dra7xx_l4_per3_hwmod,
4931 .slave = &dra7xx_ocmc_ram1_hwmod,
4932 .clk = "l3_iclk_div",
4933 .user = OCP_USER_MPU | OCP_USER_SDMA,
4934 };
4936 /* l4_per3 -> ocmc_ram2 */
4937 static struct omap_hwmod_ocp_if dra7xx_l4_per3__ocmc_ram2 = {
4938 .master = &dra7xx_l4_per3_hwmod,
4939 .slave = &dra7xx_ocmc_ram2_hwmod,
4940 .clk = "l3_iclk_div",
4941 .user = OCP_USER_MPU | OCP_USER_SDMA,
4942 };
4944 /* l4_per3 -> ocmc_ram3 */
4945 static struct omap_hwmod_ocp_if dra7xx_l4_per3__ocmc_ram3 = {
4946 .master = &dra7xx_l4_per3_hwmod,
4947 .slave = &dra7xx_ocmc_ram3_hwmod,
4948 .clk = "l3_iclk_div",
4949 .user = OCP_USER_MPU | OCP_USER_SDMA,
4950 };
4952 /* l3_main_1 -> ocmc_rom */
4953 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__ocmc_rom = {
4954 .master = &dra7xx_l3_main_1_hwmod,
4955 .slave = &dra7xx_ocmc_rom_hwmod,
4956 .clk = "l3_iclk_div",
4957 .user = OCP_USER_MPU | OCP_USER_SDMA,
4958 };
4960 static struct omap_hwmod_addr_space dra7xx_ocp2scp1_addrs[] = {
4961 {
4962 .pa_start = 0x4a080000,
4963 .pa_end = 0x4a08001f,
4964 .flags = ADDR_TYPE_RT
4965 },
4966 { }
4967 };
4969 /* l4_cfg -> ocp2scp1 */
4970 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
4971 .master = &dra7xx_l4_cfg_hwmod,
4972 .slave = &dra7xx_ocp2scp1_hwmod,
4973 .clk = "l4_root_clk_div",
4974 .addr = dra7xx_ocp2scp1_addrs,
4975 .user = OCP_USER_MPU | OCP_USER_SDMA,
4976 };
4978 static struct omap_hwmod_addr_space dra7xx_pruss1_addrs[] = {
4979 {
4980 .name = "u_intc",
4981 .pa_start = 0x4b220000,
4982 .pa_end = 0x4b221fff,
4983 },
4984 {
4985 .name = "u_pru0_ctrl",
4986 .pa_start = 0x4b222000,
4987 .pa_end = 0x4b22203f,
4988 },
4989 {
4990 .name = "u_pru0_debug",
4991 .pa_start = 0x4b222400,
4992 .pa_end = 0x4b2224ff,
4993 },
4994 {
4995 .name = "u_pru1_ctrl",
4996 .pa_start = 0x4b224000,
4997 .pa_end = 0x4b22403f,
4998 },
4999 {
5000 .name = "u_pru1_debug",
5001 .pa_start = 0x4b224400,
5002 .pa_end = 0x4b2244ff,
5003 },
5004 {
5005 .name = "u_cfg",
5006 .pa_start = 0x4b226000,
5007 .pa_end = 0x4b22607f,
5008 },
5009 {
5010 .name = "u_uart",
5011 .pa_start = 0x4b228000,
5012 .pa_end = 0x4b22803f,
5013 },
5014 {
5015 .name = "u_iep",
5016 .pa_start = 0x4b22e000,
5017 .pa_end = 0x4b22e3ff,
5018 },
5019 {
5020 .name = "u_ecap",
5021 .pa_start = 0x4b230000,
5022 .pa_end = 0x4b23007f,
5023 },
5024 {
5025 .name = "u_mii_rt_cfg",
5026 .pa_start = 0x4b232000,
5027 .pa_end = 0x4b23207f,
5028 },
5029 {
5030 .name = "u_mii_mdio",
5031 .pa_start = 0x4b232400,
5032 .pa_end = 0x4b2324ff,
5033 },
5034 { }
5035 };
5037 /* l3_main_1 -> pruss1 */
5038 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pruss1 = {
5039 .master = &dra7xx_l3_main_1_hwmod,
5040 .slave = &dra7xx_pruss1_hwmod,
5041 .clk = "dpll_gmac_h13x2_ck",
5042 .addr = dra7xx_pruss1_addrs,
5043 .user = OCP_USER_MPU | OCP_USER_SDMA,
5044 };
5046 static struct omap_hwmod_addr_space dra7xx_pruss2_addrs[] = {
5047 {
5048 .name = "u_intc",
5049 .pa_start = 0x4b2a0000,
5050 .pa_end = 0x4b2a1fff,
5051 },
5052 {
5053 .name = "u_pru0_ctrl",
5054 .pa_start = 0x4b2a2000,
5055 .pa_end = 0x4b2a203f,
5056 },
5057 {
5058 .name = "u_pru0_debug",
5059 .pa_start = 0x4b2a2400,
5060 .pa_end = 0x4b2a24ff,
5061 },
5062 {
5063 .name = "u_pru1_ctrl",
5064 .pa_start = 0x4b2a4000,
5065 .pa_end = 0x4b2a403f,
5066 },
5067 {
5068 .name = "u_pru1_debug",
5069 .pa_start = 0x4b2a4400,
5070 .pa_end = 0x4b2a44ff,
5071 },
5072 {
5073 .name = "u_cfg",
5074 .pa_start = 0x4b2a6000,
5075 .pa_end = 0x4b2a607f,
5076 },
5077 {
5078 .name = "u_uart",
5079 .pa_start = 0x4b2a8000,
5080 .pa_end = 0x4b2a803f,
5081 },
5082 {
5083 .name = "u_iep",
5084 .pa_start = 0x4b2ae000,
5085 .pa_end = 0x4b2ae3ff,
5086 },
5087 {
5088 .name = "u_ecap",
5089 .pa_start = 0x4b2b0000,
5090 .pa_end = 0x4b2b007f,
5091 },
5092 {
5093 .name = "u_mii_rt_cfg",
5094 .pa_start = 0x4b2b2000,
5095 .pa_end = 0x4b2b207f,
5096 },
5097 {
5098 .name = "u_mii_mdio",
5099 .pa_start = 0x4b2b2400,
5100 .pa_end = 0x4b2b24ff,
5101 },
5102 { }
5103 };
5105 /* l3_main_1 -> pruss2 */
5106 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pruss2 = {
5107 .master = &dra7xx_l3_main_1_hwmod,
5108 .slave = &dra7xx_pruss2_hwmod,
5109 .clk = "dpll_gmac_h13x2_ck",
5110 .addr = dra7xx_pruss2_addrs,
5111 .user = OCP_USER_MPU | OCP_USER_SDMA,
5112 };
5114 /* l4_per2 -> pwmss1 */
5115 static struct omap_hwmod_ocp_if dra7xx_l4_per2__pwmss1 = {
5116 .master = &dra7xx_l4_per2_hwmod,
5117 .slave = &dra7xx_pwmss1_hwmod,
5118 .clk = "l3_iclk_div",
5119 .user = OCP_USER_MPU | OCP_USER_SDMA,
5120 };
5122 /* l4_per2 -> pwmss2 */
5123 static struct omap_hwmod_ocp_if dra7xx_l4_per2__pwmss2 = {
5124 .master = &dra7xx_l4_per2_hwmod,
5125 .slave = &dra7xx_pwmss2_hwmod,
5126 .clk = "l3_iclk_div",
5127 .user = OCP_USER_MPU | OCP_USER_SDMA,
5128 };
5130 /* l4_per2 -> pwmss3 */
5131 static struct omap_hwmod_ocp_if dra7xx_l4_per2__pwmss3 = {
5132 .master = &dra7xx_l4_per2_hwmod,
5133 .slave = &dra7xx_pwmss3_hwmod,
5134 .clk = "l3_iclk_div",
5135 .user = OCP_USER_MPU | OCP_USER_SDMA,
5136 };
5138 static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
5139 {
5140 .pa_start = 0x4b300000,
5141 .pa_end = 0x4b30007f,
5142 .flags = ADDR_TYPE_RT
5143 },
5144 { }
5145 };
5147 /* l3_main_1 -> qspi */
5148 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
5149 .master = &dra7xx_l3_main_1_hwmod,
5150 .slave = &dra7xx_qspi_hwmod,
5151 .clk = "l3_iclk_div",
5152 .addr = dra7xx_qspi_addrs,
5153 .user = OCP_USER_MPU | OCP_USER_SDMA,
5154 };
5156 static struct omap_hwmod_addr_space dra7xx_rtcss_addrs[] = {
5157 {
5158 .pa_start = 0x48838000,
5159 .pa_end = 0x488380ff,
5160 .flags = ADDR_TYPE_RT
5161 },
5162 { }
5163 };
5165 /* l4_per3 -> rtcss */
5166 static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
5167 .master = &dra7xx_l4_per3_hwmod,
5168 .slave = &dra7xx_rtcss_hwmod,
5169 .clk = "l4_root_clk_div",
5170 .addr = dra7xx_rtcss_addrs,
5171 .user = OCP_USER_MPU | OCP_USER_SDMA,
5172 };
5174 static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
5175 {
5176 .name = "ahci",
5177 .pa_start = 0x4a140000,
5178 .pa_end = 0x4a1401ff,
5179 },
5180 {
5181 .name = "sysc",
5182 .pa_start = 0x4a141100,
5183 .pa_end = 0x4a141107,
5184 .flags = ADDR_TYPE_RT
5185 },
5186 { }
5187 };
5189 /* l4_cfg -> sata */
5190 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
5191 .master = &dra7xx_l4_cfg_hwmod,
5192 .slave = &dra7xx_sata_hwmod,
5193 .clk = "l3_iclk_div",
5194 .addr = dra7xx_sata_addrs,
5195 .user = OCP_USER_MPU | OCP_USER_SDMA,
5196 };
5198 static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
5199 {
5200 .pa_start = 0x4a0dd000,
5201 .pa_end = 0x4a0dd07f,
5202 .flags = ADDR_TYPE_RT
5203 },
5204 { }
5205 };
5207 /* l4_cfg -> smartreflex_core */
5208 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
5209 .master = &dra7xx_l4_cfg_hwmod,
5210 .slave = &dra7xx_smartreflex_core_hwmod,
5211 .clk = "l4_root_clk_div",
5212 .addr = dra7xx_smartreflex_core_addrs,
5213 .user = OCP_USER_MPU | OCP_USER_SDMA,
5214 };
5216 static struct omap_hwmod_addr_space dra7xx_smartreflex_dspeve_addrs[] = {
5217 {
5218 .pa_start = 0x4a183000,
5219 .pa_end = 0x4a18307f,
5220 .flags = ADDR_TYPE_RT
5221 },
5222 { }
5223 };
5225 /* l4_cfg -> smartreflex_dspeve */
5226 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_dspeve = {
5227 .master = &dra7xx_l4_cfg_hwmod,
5228 .slave = &dra7xx_smartreflex_dspeve_hwmod,
5229 .clk = "l4_root_clk_div",
5230 .addr = dra7xx_smartreflex_dspeve_addrs,
5231 .user = OCP_USER_MPU | OCP_USER_SDMA,
5232 };
5234 static struct omap_hwmod_addr_space dra7xx_smartreflex_gpu_addrs[] = {
5235 {
5236 .pa_start = 0x4a185000,
5237 .pa_end = 0x4a18507f,
5238 .flags = ADDR_TYPE_RT
5239 },
5240 { }
5241 };
5243 /* l4_cfg -> smartreflex_gpu */
5244 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_gpu = {
5245 .master = &dra7xx_l4_cfg_hwmod,
5246 .slave = &dra7xx_smartreflex_gpu_hwmod,
5247 .clk = "l4_root_clk_div",
5248 .addr = dra7xx_smartreflex_gpu_addrs,
5249 .user = OCP_USER_MPU | OCP_USER_SDMA,
5250 };
5252 static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
5253 {
5254 .pa_start = 0x4a0d9000,
5255 .pa_end = 0x4a0d907f,
5256 .flags = ADDR_TYPE_RT
5257 },
5258 { }
5259 };
5261 /* l4_cfg -> smartreflex_mpu */
5262 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
5263 .master = &dra7xx_l4_cfg_hwmod,
5264 .slave = &dra7xx_smartreflex_mpu_hwmod,
5265 .clk = "l4_root_clk_div",
5266 .addr = dra7xx_smartreflex_mpu_addrs,
5267 .user = OCP_USER_MPU | OCP_USER_SDMA,
5268 };
5270 /* l4_per3 -> spare_cme */
5271 static struct omap_hwmod_ocp_if dra7xx_l4_per3__spare_cme = {
5272 .master = &dra7xx_l4_per3_hwmod,
5273 .slave = &dra7xx_spare_cme_hwmod,
5274 .clk = "l4_root_clk_div",
5275 .user = OCP_USER_MPU | OCP_USER_SDMA,
5276 };
5278 /* l4_per3 -> spare_icm */
5279 static struct omap_hwmod_ocp_if dra7xx_l4_per3__spare_icm = {
5280 .master = &dra7xx_l4_per3_hwmod,
5281 .slave = &dra7xx_spare_icm_hwmod,
5282 .clk = "l4_root_clk_div",
5283 .user = OCP_USER_MPU | OCP_USER_SDMA,
5284 };
5286 /* l3_main_1 -> spare_iva2 */
5287 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__spare_iva2 = {
5288 .master = &dra7xx_l3_main_1_hwmod,
5289 .slave = &dra7xx_spare_iva2_hwmod,
5290 .clk = "l3_iclk_div",
5291 .user = OCP_USER_MPU | OCP_USER_SDMA,
5292 };
5294 /* l4_wkup -> spare_safety1 */
5295 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__spare_safety1 = {
5296 .master = &dra7xx_l4_wkup_hwmod,
5297 .slave = &dra7xx_spare_safety1_hwmod,
5298 .clk = "wkupaon_iclk_mux",
5299 .user = OCP_USER_MPU | OCP_USER_SDMA,
5300 };
5302 /* l4_wkup -> spare_safety2 */
5303 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__spare_safety2 = {
5304 .master = &dra7xx_l4_wkup_hwmod,
5305 .slave = &dra7xx_spare_safety2_hwmod,
5306 .clk = "wkupaon_iclk_mux",
5307 .user = OCP_USER_MPU | OCP_USER_SDMA,
5308 };
5310 /* l4_wkup -> spare_safety3 */
5311 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__spare_safety3 = {
5312 .master = &dra7xx_l4_wkup_hwmod,
5313 .slave = &dra7xx_spare_safety3_hwmod,
5314 .clk = "wkupaon_iclk_mux",
5315 .user = OCP_USER_MPU | OCP_USER_SDMA,
5316 };
5318 /* l4_wkup -> spare_safety4 */
5319 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__spare_safety4 = {
5320 .master = &dra7xx_l4_wkup_hwmod,
5321 .slave = &dra7xx_spare_safety4_hwmod,
5322 .clk = "wkupaon_iclk_mux",
5323 .user = OCP_USER_MPU | OCP_USER_SDMA,
5324 };
5326 /* l4_wkup -> spare_unknown2 */
5327 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__spare_unknown2 = {
5328 .master = &dra7xx_l4_wkup_hwmod,
5329 .slave = &dra7xx_spare_unknown2_hwmod,
5330 .clk = "wkupaon_iclk_mux",
5331 .user = OCP_USER_MPU | OCP_USER_SDMA,
5332 };
5334 /* l4_wkup -> spare_unknown3 */
5335 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__spare_unknown3 = {
5336 .master = &dra7xx_l4_wkup_hwmod,
5337 .slave = &dra7xx_spare_unknown3_hwmod,
5338 .clk = "wkupaon_iclk_mux",
5339 .user = OCP_USER_MPU | OCP_USER_SDMA,
5340 };
5342 /* l4_per2 -> spare_unknown4 */
5343 static struct omap_hwmod_ocp_if dra7xx_l4_per2__spare_unknown4 = {
5344 .master = &dra7xx_l4_per2_hwmod,
5345 .slave = &dra7xx_spare_unknown4_hwmod,
5346 .clk = "l4_root_clk_div",
5347 .user = OCP_USER_MPU | OCP_USER_SDMA,
5348 };
5350 /* l4_per2 -> spare_unknown5 */
5351 static struct omap_hwmod_ocp_if dra7xx_l4_per2__spare_unknown5 = {
5352 .master = &dra7xx_l4_per2_hwmod,
5353 .slave = &dra7xx_spare_unknown5_hwmod,
5354 .clk = "l4_root_clk_div",
5355 .user = OCP_USER_MPU | OCP_USER_SDMA,
5356 };
5358 /* l4_per2 -> spare_unknown6 */
5359 static struct omap_hwmod_ocp_if dra7xx_l4_per2__spare_unknown6 = {
5360 .master = &dra7xx_l4_per2_hwmod,
5361 .slave = &dra7xx_spare_unknown6_hwmod,
5362 .clk = "l4_root_clk_div",
5363 .user = OCP_USER_MPU | OCP_USER_SDMA,
5364 };
5366 /* l4_per3 -> spare_videopll1 */
5367 static struct omap_hwmod_ocp_if dra7xx_l4_per3__spare_videopll1 = {
5368 .master = &dra7xx_l4_per3_hwmod,
5369 .slave = &dra7xx_spare_videopll1_hwmod,
5370 .clk = "l4_root_clk_div",
5371 .user = OCP_USER_MPU | OCP_USER_SDMA,
5372 };
5374 /* l4_per3 -> spare_videopll2 */
5375 static struct omap_hwmod_ocp_if dra7xx_l4_per3__spare_videopll2 = {
5376 .master = &dra7xx_l4_per3_hwmod,
5377 .slave = &dra7xx_spare_videopll2_hwmod,
5378 .clk = "l4_root_clk_div",
5379 .user = OCP_USER_MPU | OCP_USER_SDMA,
5380 };
5382 /* l4_per3 -> spare_videopll3 */
5383 static struct omap_hwmod_ocp_if dra7xx_l4_per3__spare_videopll3 = {
5384 .master = &dra7xx_l4_per3_hwmod,
5385 .slave = &dra7xx_spare_videopll3_hwmod,
5386 .clk = "l4_root_clk_div",
5387 .user = OCP_USER_MPU | OCP_USER_SDMA,
5388 };
5390 /* l4_per3 -> spare_sata2 */
5391 static struct omap_hwmod_ocp_if dra7xx_l4_per3__spare_sata2 = {
5392 .master = &dra7xx_l4_per3_hwmod,
5393 .slave = &dra7xx_spare_sata2_hwmod,
5394 .clk = "l4_root_clk_div",
5395 .user = OCP_USER_MPU | OCP_USER_SDMA,
5396 };
5398 /* l4_cfg -> spare_smartreflex_rtc */
5399 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spare_smartreflex_rtc = {
5400 .master = &dra7xx_l4_cfg_hwmod,
5401 .slave = &dra7xx_spare_smartreflex_rtc_hwmod,
5402 .clk = "l4_root_clk_div",
5403 .user = OCP_USER_MPU | OCP_USER_SDMA,
5404 };
5406 /* l4_cfg -> spare_smartreflex_sdram */
5407 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spare_smartreflex_sdram = {
5408 .master = &dra7xx_l4_cfg_hwmod,
5409 .slave = &dra7xx_spare_smartreflex_sdram_hwmod,
5410 .clk = "l4_root_clk_div",
5411 .user = OCP_USER_MPU | OCP_USER_SDMA,
5412 };
5414 /* l4_cfg -> spare_smartreflex_wkup */
5415 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spare_smartreflex_wkup = {
5416 .master = &dra7xx_l4_cfg_hwmod,
5417 .slave = &dra7xx_spare_smartreflex_wkup_hwmod,
5418 .clk = "l4_root_clk_div",
5419 .user = OCP_USER_MPU | OCP_USER_SDMA,
5420 };
5422 static struct omap_hwmod_addr_space dra7xx_spinlock_addrs[] = {
5423 {
5424 .pa_start = 0x4a0f6000,
5425 .pa_end = 0x4a0f6fff,
5426 .flags = ADDR_TYPE_RT
5427 },
5428 { }
5429 };
5431 /* l4_cfg -> spinlock */
5432 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
5433 .master = &dra7xx_l4_cfg_hwmod,
5434 .slave = &dra7xx_spinlock_hwmod,
5435 .clk = "l3_iclk_div",
5436 .addr = dra7xx_spinlock_addrs,
5437 .user = OCP_USER_MPU | OCP_USER_SDMA,
5438 };
5440 static struct omap_hwmod_addr_space dra7xx_timer1_addrs[] = {
5441 {
5442 .pa_start = 0x4ae18000,
5443 .pa_end = 0x4ae1807f,
5444 .flags = ADDR_TYPE_RT
5445 },
5446 { }
5447 };
5449 /* l4_wkup -> timer1 */
5450 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
5451 .master = &dra7xx_l4_wkup_hwmod,
5452 .slave = &dra7xx_timer1_hwmod,
5453 .clk = "wkupaon_iclk_mux",
5454 .addr = dra7xx_timer1_addrs,
5455 .user = OCP_USER_MPU | OCP_USER_SDMA,
5456 };
5458 static struct omap_hwmod_addr_space dra7xx_timer2_addrs[] = {
5459 {
5460 .pa_start = 0x48032000,
5461 .pa_end = 0x4803207f,
5462 .flags = ADDR_TYPE_RT
5463 },
5464 { }
5465 };
5467 /* l4_per1 -> timer2 */
5468 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
5469 .master = &dra7xx_l4_per1_hwmod,
5470 .slave = &dra7xx_timer2_hwmod,
5471 .clk = "l3_iclk_div",
5472 .addr = dra7xx_timer2_addrs,
5473 .user = OCP_USER_MPU | OCP_USER_SDMA,
5474 };
5476 static struct omap_hwmod_addr_space dra7xx_timer3_addrs[] = {
5477 {
5478 .pa_start = 0x48034000,
5479 .pa_end = 0x4803407f,
5480 .flags = ADDR_TYPE_RT
5481 },
5482 { }
5483 };
5485 /* l4_per1 -> timer3 */
5486 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
5487 .master = &dra7xx_l4_per1_hwmod,
5488 .slave = &dra7xx_timer3_hwmod,
5489 .clk = "l3_iclk_div",
5490 .addr = dra7xx_timer3_addrs,
5491 .user = OCP_USER_MPU | OCP_USER_SDMA,
5492 };
5494 static struct omap_hwmod_addr_space dra7xx_timer4_addrs[] = {
5495 {
5496 .pa_start = 0x48036000,
5497 .pa_end = 0x4803607f,
5498 .flags = ADDR_TYPE_RT
5499 },
5500 { }
5501 };
5503 /* l4_per1 -> timer4 */
5504 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
5505 .master = &dra7xx_l4_per1_hwmod,
5506 .slave = &dra7xx_timer4_hwmod,
5507 .clk = "l3_iclk_div",
5508 .addr = dra7xx_timer4_addrs,
5509 .user = OCP_USER_MPU | OCP_USER_SDMA,
5510 };
5512 static struct omap_hwmod_addr_space dra7xx_timer5_addrs[] = {
5513 {
5514 .pa_start = 0x48820000,
5515 .pa_end = 0x4882007f,
5516 .flags = ADDR_TYPE_RT
5517 },
5518 { }
5519 };
5521 /* l4_per3 -> timer5 */
5522 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
5523 .master = &dra7xx_l4_per3_hwmod,
5524 .slave = &dra7xx_timer5_hwmod,
5525 .clk = "l3_iclk_div",
5526 .addr = dra7xx_timer5_addrs,
5527 .user = OCP_USER_MPU | OCP_USER_SDMA,
5528 };
5530 static struct omap_hwmod_addr_space dra7xx_timer6_addrs[] = {
5531 {
5532 .pa_start = 0x48822000,
5533 .pa_end = 0x4882207f,
5534 .flags = ADDR_TYPE_RT
5535 },
5536 { }
5537 };
5539 /* l4_per3 -> timer6 */
5540 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
5541 .master = &dra7xx_l4_per3_hwmod,
5542 .slave = &dra7xx_timer6_hwmod,
5543 .clk = "l3_iclk_div",
5544 .addr = dra7xx_timer6_addrs,
5545 .user = OCP_USER_MPU | OCP_USER_SDMA,
5546 };
5548 static struct omap_hwmod_addr_space dra7xx_timer7_addrs[] = {
5549 {
5550 .pa_start = 0x48824000,
5551 .pa_end = 0x4882407f,
5552 .flags = ADDR_TYPE_RT
5553 },
5554 { }
5555 };
5557 /* l4_per3 -> timer7 */
5558 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
5559 .master = &dra7xx_l4_per3_hwmod,
5560 .slave = &dra7xx_timer7_hwmod,
5561 .clk = "l3_iclk_div",
5562 .addr = dra7xx_timer7_addrs,
5563 .user = OCP_USER_MPU | OCP_USER_SDMA,
5564 };
5566 static struct omap_hwmod_addr_space dra7xx_timer8_addrs[] = {
5567 {
5568 .pa_start = 0x48826000,
5569 .pa_end = 0x4882607f,
5570 .flags = ADDR_TYPE_RT
5571 },
5572 { }
5573 };
5575 /* l4_per3 -> timer8 */
5576 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
5577 .master = &dra7xx_l4_per3_hwmod,
5578 .slave = &dra7xx_timer8_hwmod,
5579 .clk = "l3_iclk_div",
5580 .addr = dra7xx_timer8_addrs,
5581 .user = OCP_USER_MPU | OCP_USER_SDMA,
5582 };
5584 static struct omap_hwmod_addr_space dra7xx_timer9_addrs[] = {
5585 {
5586 .pa_start = 0x4803e000,
5587 .pa_end = 0x4803e07f,
5588 .flags = ADDR_TYPE_RT
5589 },
5590 { }
5591 };
5593 /* l4_per1 -> timer9 */
5594 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
5595 .master = &dra7xx_l4_per1_hwmod,
5596 .slave = &dra7xx_timer9_hwmod,
5597 .clk = "l3_iclk_div",
5598 .addr = dra7xx_timer9_addrs,
5599 .user = OCP_USER_MPU | OCP_USER_SDMA,
5600 };
5602 static struct omap_hwmod_addr_space dra7xx_timer10_addrs[] = {
5603 {
5604 .pa_start = 0x48086000,
5605 .pa_end = 0x4808607f,
5606 .flags = ADDR_TYPE_RT
5607 },
5608 { }
5609 };
5611 /* l4_per1 -> timer10 */
5612 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
5613 .master = &dra7xx_l4_per1_hwmod,
5614 .slave = &dra7xx_timer10_hwmod,
5615 .clk = "l3_iclk_div",
5616 .addr = dra7xx_timer10_addrs,
5617 .user = OCP_USER_MPU | OCP_USER_SDMA,
5618 };
5620 static struct omap_hwmod_addr_space dra7xx_timer11_addrs[] = {
5621 {
5622 .pa_start = 0x48088000,
5623 .pa_end = 0x4808807f,
5624 .flags = ADDR_TYPE_RT
5625 },
5626 { }
5627 };
5629 /* l4_per1 -> timer11 */
5630 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
5631 .master = &dra7xx_l4_per1_hwmod,
5632 .slave = &dra7xx_timer11_hwmod,
5633 .clk = "l3_iclk_div",
5634 .addr = dra7xx_timer11_addrs,
5635 .user = OCP_USER_MPU | OCP_USER_SDMA,
5636 };
5638 static struct omap_hwmod_addr_space dra7xx_timer13_addrs[] = {
5639 {
5640 .pa_start = 0x48828000,
5641 .pa_end = 0x4882807f,
5642 .flags = ADDR_TYPE_RT
5643 },
5644 { }
5645 };
5647 /* l4_per3 -> timer13 */
5648 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
5649 .master = &dra7xx_l4_per3_hwmod,
5650 .slave = &dra7xx_timer13_hwmod,
5651 .clk = "l3_iclk_div",
5652 .addr = dra7xx_timer13_addrs,
5653 .user = OCP_USER_MPU | OCP_USER_SDMA,
5654 };
5656 static struct omap_hwmod_addr_space dra7xx_timer14_addrs[] = {
5657 {
5658 .pa_start = 0x4882a000,
5659 .pa_end = 0x4882a07f,
5660 .flags = ADDR_TYPE_RT
5661 },
5662 { }
5663 };
5665 /* l4_per3 -> timer14 */
5666 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
5667 .master = &dra7xx_l4_per3_hwmod,
5668 .slave = &dra7xx_timer14_hwmod,
5669 .clk = "l3_iclk_div",
5670 .addr = dra7xx_timer14_addrs,
5671 .user = OCP_USER_MPU | OCP_USER_SDMA,
5672 };
5674 static struct omap_hwmod_addr_space dra7xx_timer15_addrs[] = {
5675 {
5676 .pa_start = 0x4882c000,
5677 .pa_end = 0x4882c07f,
5678 .flags = ADDR_TYPE_RT
5679 },
5680 { }
5681 };
5683 /* l4_per3 -> timer15 */
5684 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
5685 .master = &dra7xx_l4_per3_hwmod,
5686 .slave = &dra7xx_timer15_hwmod,
5687 .clk = "l3_iclk_div",
5688 .addr = dra7xx_timer15_addrs,
5689 .user = OCP_USER_MPU | OCP_USER_SDMA,
5690 };
5692 static struct omap_hwmod_addr_space dra7xx_timer16_addrs[] = {
5693 {
5694 .pa_start = 0x4882e000,
5695 .pa_end = 0x4882e07f,
5696 .flags = ADDR_TYPE_RT
5697 },
5698 { }
5699 };
5701 /* l4_per3 -> timer16 */
5702 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
5703 .master = &dra7xx_l4_per3_hwmod,
5704 .slave = &dra7xx_timer16_hwmod,
5705 .clk = "l3_iclk_div",
5706 .addr = dra7xx_timer16_addrs,
5707 .user = OCP_USER_MPU | OCP_USER_SDMA,
5708 };
5710 static struct omap_hwmod_addr_space dra7xx_uart1_addrs[] = {
5711 {
5712 .pa_start = 0x4806a000,
5713 .pa_end = 0x4806a0ff,
5714 .flags = ADDR_TYPE_RT
5715 },
5716 { }
5717 };
5719 /* l4_per1 -> uart1 */
5720 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
5721 .master = &dra7xx_l4_per1_hwmod,
5722 .slave = &dra7xx_uart1_hwmod,
5723 .clk = "l3_iclk_div",
5724 .addr = dra7xx_uart1_addrs,
5725 .user = OCP_USER_MPU | OCP_USER_SDMA,
5726 };
5728 static struct omap_hwmod_addr_space dra7xx_uart2_addrs[] = {
5729 {
5730 .pa_start = 0x4806c000,
5731 .pa_end = 0x4806c0ff,
5732 .flags = ADDR_TYPE_RT
5733 },
5734 { }
5735 };
5737 /* l4_per1 -> uart2 */
5738 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
5739 .master = &dra7xx_l4_per1_hwmod,
5740 .slave = &dra7xx_uart2_hwmod,
5741 .clk = "l3_iclk_div",
5742 .addr = dra7xx_uart2_addrs,
5743 .user = OCP_USER_MPU | OCP_USER_SDMA,
5744 };
5746 static struct omap_hwmod_addr_space dra7xx_uart3_addrs[] = {
5747 {
5748 .pa_start = 0x48020000,
5749 .pa_end = 0x480200ff,
5750 .flags = ADDR_TYPE_RT
5751 },
5752 { }
5753 };
5755 /* l4_per1 -> uart3 */
5756 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
5757 .master = &dra7xx_l4_per1_hwmod,
5758 .slave = &dra7xx_uart3_hwmod,
5759 .clk = "l3_iclk_div",
5760 .addr = dra7xx_uart3_addrs,
5761 .user = OCP_USER_MPU | OCP_USER_SDMA,
5762 };
5764 static struct omap_hwmod_addr_space dra7xx_uart4_addrs[] = {
5765 {
5766 .pa_start = 0x4806e000,
5767 .pa_end = 0x4806e0ff,
5768 .flags = ADDR_TYPE_RT
5769 },
5770 { }
5771 };
5773 /* l4_per1 -> uart4 */
5774 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
5775 .master = &dra7xx_l4_per1_hwmod,
5776 .slave = &dra7xx_uart4_hwmod,
5777 .clk = "l3_iclk_div",
5778 .addr = dra7xx_uart4_addrs,
5779 .user = OCP_USER_MPU | OCP_USER_SDMA,
5780 };
5782 static struct omap_hwmod_addr_space dra7xx_uart5_addrs[] = {
5783 {
5784 .pa_start = 0x48066000,
5785 .pa_end = 0x480660ff,
5786 .flags = ADDR_TYPE_RT
5787 },
5788 { }
5789 };
5791 /* l4_per1 -> uart5 */
5792 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
5793 .master = &dra7xx_l4_per1_hwmod,
5794 .slave = &dra7xx_uart5_hwmod,
5795 .clk = "l3_iclk_div",
5796 .addr = dra7xx_uart5_addrs,
5797 .user = OCP_USER_MPU | OCP_USER_SDMA,
5798 };
5800 static struct omap_hwmod_addr_space dra7xx_uart6_addrs[] = {
5801 {
5802 .pa_start = 0x48068000,
5803 .pa_end = 0x480680ff,
5804 .flags = ADDR_TYPE_RT
5805 },
5806 { }
5807 };
5809 /* l4_per1 -> uart6 */
5810 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
5811 .master = &dra7xx_l4_per1_hwmod,
5812 .slave = &dra7xx_uart6_hwmod,
5813 .clk = "l3_iclk_div",
5814 .addr = dra7xx_uart6_addrs,
5815 .user = OCP_USER_MPU | OCP_USER_SDMA,
5816 };
5818 static struct omap_hwmod_addr_space dra7xx_uart7_addrs[] = {
5819 {
5820 .pa_start = 0x48420000,
5821 .pa_end = 0x484200ff,
5822 .flags = ADDR_TYPE_RT
5823 },
5824 { }
5825 };
5827 /* l4_per2 -> uart7 */
5828 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
5829 .master = &dra7xx_l4_per2_hwmod,
5830 .slave = &dra7xx_uart7_hwmod,
5831 .clk = "l3_iclk_div",
5832 .addr = dra7xx_uart7_addrs,
5833 .user = OCP_USER_MPU | OCP_USER_SDMA,
5834 };
5836 static struct omap_hwmod_addr_space dra7xx_uart8_addrs[] = {
5837 {
5838 .pa_start = 0x48422000,
5839 .pa_end = 0x484220ff,
5840 .flags = ADDR_TYPE_RT
5841 },
5842 { }
5843 };
5845 /* l4_per2 -> uart8 */
5846 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
5847 .master = &dra7xx_l4_per2_hwmod,
5848 .slave = &dra7xx_uart8_hwmod,
5849 .clk = "l3_iclk_div",
5850 .addr = dra7xx_uart8_addrs,
5851 .user = OCP_USER_MPU | OCP_USER_SDMA,
5852 };
5854 static struct omap_hwmod_addr_space dra7xx_uart9_addrs[] = {
5855 {
5856 .pa_start = 0x48424000,
5857 .pa_end = 0x484240ff,
5858 .flags = ADDR_TYPE_RT
5859 },
5860 { }
5861 };
5863 /* l4_per2 -> uart9 */
5864 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
5865 .master = &dra7xx_l4_per2_hwmod,
5866 .slave = &dra7xx_uart9_hwmod,
5867 .clk = "l3_iclk_div",
5868 .addr = dra7xx_uart9_addrs,
5869 .user = OCP_USER_MPU | OCP_USER_SDMA,
5870 };
5872 static struct omap_hwmod_addr_space dra7xx_uart10_addrs[] = {
5873 {
5874 .pa_start = 0x4ae2b000,
5875 .pa_end = 0x4ae2b0ff,
5876 .flags = ADDR_TYPE_RT
5877 },
5878 { }
5879 };
5881 /* l4_wkup -> uart10 */
5882 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
5883 .master = &dra7xx_l4_wkup_hwmod,
5884 .slave = &dra7xx_uart10_hwmod,
5885 .clk = "wkupaon_iclk_mux",
5886 .addr = dra7xx_uart10_addrs,
5887 .user = OCP_USER_MPU | OCP_USER_SDMA,
5888 };
5890 /* l4_per3 -> usb_otg_ss1 */
5891 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
5892 .master = &dra7xx_l4_per3_hwmod,
5893 .slave = &dra7xx_usb_otg_ss1_hwmod,
5894 .clk = "dpll_core_h13x2_ck",
5895 .user = OCP_USER_MPU | OCP_USER_SDMA,
5896 };
5898 /* l4_per3 -> usb_otg_ss2 */
5899 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
5900 .master = &dra7xx_l4_per3_hwmod,
5901 .slave = &dra7xx_usb_otg_ss2_hwmod,
5902 .clk = "dpll_core_h13x2_ck",
5903 .user = OCP_USER_MPU | OCP_USER_SDMA,
5904 };
5906 /* l4_per3 -> usb_otg_ss3 */
5907 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
5908 .master = &dra7xx_l4_per3_hwmod,
5909 .slave = &dra7xx_usb_otg_ss3_hwmod,
5910 .clk = "dpll_core_h13x2_ck",
5911 .user = OCP_USER_MPU | OCP_USER_SDMA,
5912 };
5914 /* l4_per3 -> usb_otg_ss4 */
5915 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
5916 .master = &dra7xx_l4_per3_hwmod,
5917 .slave = &dra7xx_usb_otg_ss4_hwmod,
5918 .clk = "dpll_core_h13x2_ck",
5919 .user = OCP_USER_MPU | OCP_USER_SDMA,
5920 };
5922 /* l3_main_1 -> vcp1 */
5923 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
5924 .master = &dra7xx_l3_main_1_hwmod,
5925 .slave = &dra7xx_vcp1_hwmod,
5926 .clk = "l3_iclk_div",
5927 .user = OCP_USER_MPU | OCP_USER_SDMA,
5928 };
5930 /* l4_per2 -> vcp1 */
5931 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
5932 .master = &dra7xx_l4_per2_hwmod,
5933 .slave = &dra7xx_vcp1_hwmod,
5934 .clk = "l3_iclk_div",
5935 .user = OCP_USER_MPU | OCP_USER_SDMA,
5936 };
5938 /* l3_main_1 -> vcp2 */
5939 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
5940 .master = &dra7xx_l3_main_1_hwmod,
5941 .slave = &dra7xx_vcp2_hwmod,
5942 .clk = "l3_iclk_div",
5943 .user = OCP_USER_MPU | OCP_USER_SDMA,
5944 };
5946 /* l4_per2 -> vcp2 */
5947 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
5948 .master = &dra7xx_l4_per2_hwmod,
5949 .slave = &dra7xx_vcp2_hwmod,
5950 .clk = "l3_iclk_div",
5951 .user = OCP_USER_MPU | OCP_USER_SDMA,
5952 };
5954 static struct omap_hwmod_addr_space dra7xx_vip1_addrs[] = {
5955 {
5956 .name = "vip_top_level",
5957 .pa_start = 0x48970000,
5958 .pa_end = 0x489701ff,
5959 .flags = ADDR_TYPE_RT
5960 },
5961 {
5962 .name = "vip_slice0_parser",
5963 .pa_start = 0x48975500,
5964 .pa_end = 0x489755ff,
5965 },
5966 {
5967 .name = "vip_slice0_csc",
5968 .pa_start = 0x48975700,
5969 .pa_end = 0x4897571f,
5970 },
5971 {
5972 .name = "vip_slice0_sc",
5973 .pa_start = 0x48975800,
5974 .pa_end = 0x4897587f,
5975 },
5976 {
5977 .name = "vip_slice1_parser",
5978 .pa_start = 0x48975a00,
5979 .pa_end = 0x48975aff,
5980 },
5981 {
5982 .name = "vip_slice1_csc",
5983 .pa_start = 0x48975c00,
5984 .pa_end = 0x48975c1f,
5985 },
5986 {
5987 .name = "vip_slice1_sc",
5988 .pa_start = 0x48975d00,
5989 .pa_end = 0x48975d7f,
5990 },
5991 {
5992 .name = "vip_vpdma",
5993 .pa_start = 0x4897d000,
5994 .pa_end = 0x4897d3ff,
5995 },
5996 { }
5997 };
5999 /* l4_per3 -> vip1 */
6000 static struct omap_hwmod_ocp_if dra7xx_l4_per3__vip1 = {
6001 .master = &dra7xx_l4_per3_hwmod,
6002 .slave = &dra7xx_vip1_hwmod,
6003 .clk = "l3_iclk_div",
6004 .addr = dra7xx_vip1_addrs,
6005 .user = OCP_USER_MPU | OCP_USER_SDMA,
6006 };
6008 static struct omap_hwmod_addr_space dra7xx_vip2_addrs[] = {
6009 {
6010 .name = "vip_top_level",
6011 .pa_start = 0x48990000,
6012 .pa_end = 0x489901ff,
6013 .flags = ADDR_TYPE_RT
6014 },
6015 {
6016 .name = "vip_slice0_parser",
6017 .pa_start = 0x48995500,
6018 .pa_end = 0x489955ff,
6019 },
6020 {
6021 .name = "vip_slice0_csc",
6022 .pa_start = 0x48995700,
6023 .pa_end = 0x4899571f,
6024 },
6025 {
6026 .name = "vip_slice0_sc",
6027 .pa_start = 0x48995800,
6028 .pa_end = 0x4899587f,
6029 },
6030 {
6031 .name = "vip_slice1_parser",
6032 .pa_start = 0x48995a00,
6033 .pa_end = 0x48995aff,
6034 },
6035 {
6036 .name = "vip_slice1_csc",
6037 .pa_start = 0x48995c00,
6038 .pa_end = 0x48995c1f,
6039 },
6040 {
6041 .name = "vip_slice1_sc",
6042 .pa_start = 0x48995d00,
6043 .pa_end = 0x48995d7f,
6044 },
6045 {
6046 .name = "vip_vpdma",
6047 .pa_start = 0x4899d000,
6048 .pa_end = 0x4899d3ff,
6049 },
6050 { }
6051 };
6053 /* l4_per3 -> vip2 */
6054 static struct omap_hwmod_ocp_if dra7xx_l4_per3__vip2 = {
6055 .master = &dra7xx_l4_per3_hwmod,
6056 .slave = &dra7xx_vip2_hwmod,
6057 .clk = "l3_iclk_div",
6058 .addr = dra7xx_vip2_addrs,
6059 .user = OCP_USER_MPU | OCP_USER_SDMA,
6060 };
6062 static struct omap_hwmod_addr_space dra7xx_vip3_addrs[] = {
6063 {
6064 .name = "vip_top_level",
6065 .pa_start = 0x489b0000,
6066 .pa_end = 0x489b01ff,
6067 .flags = ADDR_TYPE_RT
6068 },
6069 {
6070 .name = "vip_slice0_parser",
6071 .pa_start = 0x489b5500,
6072 .pa_end = 0x489b55ff,
6073 },
6074 {
6075 .name = "vip_slice0_csc",
6076 .pa_start = 0x489b5700,
6077 .pa_end = 0x489b571f,
6078 },
6079 {
6080 .name = "vip_slice0_sc",
6081 .pa_start = 0x489b5800,
6082 .pa_end = 0x489b587f,
6083 },
6084 {
6085 .name = "vip_slice1_parser",
6086 .pa_start = 0x489b5a00,
6087 .pa_end = 0x489b5aff,
6088 },
6089 {
6090 .name = "vip_slice1_csc",
6091 .pa_start = 0x489b5c00,
6092 .pa_end = 0x489b5c1f,
6093 },
6094 {
6095 .name = "vip_slice1_sc",
6096 .pa_start = 0x489b5d00,
6097 .pa_end = 0x489b5d7f,
6098 },
6099 {
6100 .name = "vip_vpdma",
6101 .pa_start = 0x489bd000,
6102 .pa_end = 0x489bd3ff,
6103 },
6104 { }
6105 };
6107 /* l4_per3 -> vip3 */
6108 static struct omap_hwmod_ocp_if dra7xx_l4_per3__vip3 = {
6109 .master = &dra7xx_l4_per3_hwmod,
6110 .slave = &dra7xx_vip3_hwmod,
6111 .clk = "l3_iclk_div",
6112 .addr = dra7xx_vip3_addrs,
6113 .user = OCP_USER_MPU | OCP_USER_SDMA,
6114 };
6116 static struct omap_hwmod_addr_space dra7xx_vpe_addrs[] = {
6117 {
6118 .name = "vpe0_vayu_register_inst_0",
6119 .pa_start = 0x489d0000,
6120 .pa_end = 0x489d01ff,
6121 .flags = ADDR_TYPE_RT
6122 },
6123 {
6124 .name = "dss_chr_us_register_inst_0",
6125 .pa_start = 0x489d0300,
6126 .pa_end = 0x489d033f,
6127 },
6128 {
6129 .name = "dss_chr_us_register_inst_1",
6130 .pa_start = 0x489d0400,
6131 .pa_end = 0x489d043f,
6132 },
6133 {
6134 .name = "dss_chr_us_register_inst_2",
6135 .pa_start = 0x489d0500,
6136 .pa_end = 0x489d053f,
6137 },
6138 {
6139 .name = "dss_dei_register_inst_0",
6140 .pa_start = 0x489d0600,
6141 .pa_end = 0x489d063f,
6142 },
6143 {
6144 .name = "dss_sc_m_register_inst_0",
6145 .pa_start = 0x489d0700,
6146 .pa_end = 0x489d077f,
6147 },
6148 {
6149 .name = "dss_csc_register_inst_0",
6150 .pa_start = 0x489d5700,
6151 .pa_end = 0x489d571f,
6152 },
6153 {
6154 .name = "hd_dss_centaurus_vpdma_register_inst_0",
6155 .pa_start = 0x489dd000,
6156 .pa_end = 0x489dd3ff,
6157 },
6158 { }
6159 };
6161 /* l4_per3 -> vpe */
6162 static struct omap_hwmod_ocp_if dra7xx_l4_per3__vpe = {
6163 .master = &dra7xx_l4_per3_hwmod,
6164 .slave = &dra7xx_vpe_hwmod,
6165 .clk = "l3_iclk_div",
6166 .addr = dra7xx_vpe_addrs,
6167 .user = OCP_USER_MPU | OCP_USER_SDMA,
6168 };
6170 static struct omap_hwmod_addr_space dra7xx_wd_timer2_addrs[] = {
6171 {
6172 .pa_start = 0x4ae14000,
6173 .pa_end = 0x4ae1407f,
6174 .flags = ADDR_TYPE_RT
6175 },
6176 { }
6177 };
6179 /* l4_wkup -> wd_timer2 */
6180 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
6181 .master = &dra7xx_l4_wkup_hwmod,
6182 .slave = &dra7xx_wd_timer2_hwmod,
6183 .clk = "wkupaon_iclk_mux",
6184 .addr = dra7xx_wd_timer2_addrs,
6185 .user = OCP_USER_MPU | OCP_USER_SDMA,
6186 };
6188 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
6189 &dra7xx_l3_main_1__dmm,
6190 &dra7xx_dmm__emif_ocp_fw,
6191 &dra7xx_l4_cfg__emif_ocp_fw,
6192 &dra7xx_l3_main_2__l3_instr,
6193 &dra7xx_ocp_wp_noc__l3_instr,
6194 &dra7xx_l4_cfg__l3_main_1,
6195 &dra7xx_mpu__l3_main_1,
6196 &dra7xx_l3_main_1__l3_main_2,
6197 &dra7xx_l4_cfg__l3_main_2,
6198 &dra7xx_l3_main_1__l4_cfg,
6199 &dra7xx_l3_main_1__l4_per1,
6200 &dra7xx_l3_main_1__l4_per2,
6201 &dra7xx_l3_main_1__l4_per3,
6202 &dra7xx_l3_main_1__l4_wkup,
6203 &dra7xx_mpu__mpu_private,
6204 &dra7xx_l3_main_2__ocp_wp_noc,
6205 &dra7xx_l4_cfg__ocp_wp_noc,
6206 &dra7xx_l4_per2__atl,
6207 &dra7xx_l3_main_1__bb2d,
6208 &dra7xx_l4_wkup__counter_32k,
6209 &dra7xx_l4_wkup__ctrl_module_wkup,
6210 &dra7xx_l4_wkup__dcan1,
6211 &dra7xx_l4_per2__dcan2,
6212 &dra7xx_l4_cfg__dma_system,
6213 &dra7xx_l3_main_1__dss,
6214 &dra7xx_l3_main_1__dispc,
6215 &dra7xx_l3_main_1__hdmi,
6216 &dra7xx_l4_per1__elm,
6217 &dra7xx_emif_ocp_fw__emif1,
6218 &dra7xx_mpu__emif1,
6219 &dra7xx_emif_ocp_fw__emif2,
6220 &dra7xx_mpu__emif2,
6221 &dra7xx_l4_wkup__gpio1,
6222 &dra7xx_l4_per1__gpio2,
6223 &dra7xx_l4_per1__gpio3,
6224 &dra7xx_l4_per1__gpio4,
6225 &dra7xx_l4_per1__gpio5,
6226 &dra7xx_l4_per1__gpio6,
6227 &dra7xx_l4_per1__gpio7,
6228 &dra7xx_l4_per1__gpio8,
6229 &dra7xx_l3_main_1__gpmc,
6230 &dra7xx_l3_main_1__gpu,
6231 &dra7xx_l4_per1__hdq1w,
6232 &dra7xx_l4_per1__i2c1,
6233 &dra7xx_l4_per1__i2c2,
6234 &dra7xx_l4_per1__i2c3,
6235 &dra7xx_l4_per1__i2c4,
6236 &dra7xx_l4_per1__i2c5,
6237 &dra7xx_l4_cfg__mailbox1,
6238 &dra7xx_l4_per3__mailbox2,
6239 &dra7xx_l4_per3__mailbox3,
6240 &dra7xx_l4_per3__mailbox4,
6241 &dra7xx_l4_per3__mailbox5,
6242 &dra7xx_l4_per3__mailbox6,
6243 &dra7xx_l4_per3__mailbox7,
6244 &dra7xx_l4_per3__mailbox8,
6245 &dra7xx_l4_per3__mailbox9,
6246 &dra7xx_l4_per3__mailbox10,
6247 &dra7xx_l4_per3__mailbox11,
6248 &dra7xx_l4_per3__mailbox12,
6249 &dra7xx_l4_per3__mailbox13,
6250 &dra7xx_l3_main_1__mcasp1,
6251 &dra7xx_l4_per2__mcasp1,
6252 &dra7xx_l3_main_1__mcasp2,
6253 &dra7xx_l3_main_1__mcasp3,
6254 &dra7xx_l4_per2__mcasp4,
6255 &dra7xx_l4_per2__mcasp5,
6256 &dra7xx_l4_per2__mcasp6,
6257 &dra7xx_l4_per2__mcasp7,
6258 &dra7xx_l4_per2__mcasp8,
6259 &dra7xx_l4_per1__mcspi1,
6260 &dra7xx_l4_per1__mcspi2,
6261 &dra7xx_l4_per1__mcspi3,
6262 &dra7xx_l4_per1__mcspi4,
6263 &dra7xx_l4_per1__mmc1,
6264 &dra7xx_l4_per1__mmc2,
6265 &dra7xx_l4_per1__mmc3,
6266 &dra7xx_l4_per1__mmc4,
6267 &dra7xx_l4_cfg__mpu,
6268 &dra7xx_l4_per3__ocmc_ram1,
6269 &dra7xx_l4_per3__ocmc_ram2,
6270 &dra7xx_l4_per3__ocmc_ram3,
6271 &dra7xx_l3_main_1__ocmc_rom,
6272 &dra7xx_l4_cfg__ocp2scp1,
6273 &dra7xx_l3_main_1__pruss1,
6274 &dra7xx_l3_main_1__pruss2,
6275 &dra7xx_l4_per2__pwmss1,
6276 &dra7xx_l4_per2__pwmss2,
6277 &dra7xx_l4_per2__pwmss3,
6278 &dra7xx_l3_main_1__qspi,
6279 &dra7xx_l4_per3__rtcss,
6280 &dra7xx_l4_cfg__sata,
6281 &dra7xx_l4_cfg__smartreflex_core,
6282 &dra7xx_l4_cfg__smartreflex_dspeve,
6283 &dra7xx_l4_cfg__smartreflex_gpu,
6284 &dra7xx_l4_cfg__smartreflex_mpu,
6285 &dra7xx_l4_per3__spare_cme,
6286 &dra7xx_l4_per3__spare_icm,
6287 &dra7xx_l3_main_1__spare_iva2,
6288 &dra7xx_l4_wkup__spare_safety1,
6289 &dra7xx_l4_wkup__spare_safety2,
6290 &dra7xx_l4_wkup__spare_safety3,
6291 &dra7xx_l4_wkup__spare_safety4,
6292 &dra7xx_l4_wkup__spare_unknown2,
6293 &dra7xx_l4_wkup__spare_unknown3,
6294 &dra7xx_l4_per2__spare_unknown4,
6295 &dra7xx_l4_per2__spare_unknown5,
6296 &dra7xx_l4_per2__spare_unknown6,
6297 &dra7xx_l4_per3__spare_videopll1,
6298 &dra7xx_l4_per3__spare_videopll2,
6299 &dra7xx_l4_per3__spare_videopll3,
6300 &dra7xx_l4_per3__spare_sata2,
6301 &dra7xx_l4_cfg__spare_smartreflex_rtc,
6302 &dra7xx_l4_cfg__spare_smartreflex_sdram,
6303 &dra7xx_l4_cfg__spare_smartreflex_wkup,
6304 &dra7xx_l4_cfg__spinlock,
6305 &dra7xx_l4_wkup__timer1,
6306 &dra7xx_l4_per1__timer2,
6307 &dra7xx_l4_per1__timer3,
6308 &dra7xx_l4_per1__timer4,
6309 &dra7xx_l4_per3__timer5,
6310 &dra7xx_l4_per3__timer6,
6311 &dra7xx_l4_per3__timer7,
6312 &dra7xx_l4_per3__timer8,
6313 &dra7xx_l4_per1__timer9,
6314 &dra7xx_l4_per1__timer10,
6315 &dra7xx_l4_per1__timer11,
6316 &dra7xx_l4_per3__timer13,
6317 &dra7xx_l4_per3__timer14,
6318 &dra7xx_l4_per3__timer15,
6319 &dra7xx_l4_per3__timer16,
6320 &dra7xx_l4_per1__uart1,
6321 &dra7xx_l4_per1__uart2,
6322 &dra7xx_l4_per1__uart3,
6323 &dra7xx_l4_per1__uart4,
6324 &dra7xx_l4_per1__uart5,
6325 &dra7xx_l4_per1__uart6,
6326 &dra7xx_l4_per2__uart7,
6327 &dra7xx_l4_per2__uart8,
6328 &dra7xx_l4_per2__uart9,
6329 &dra7xx_l4_wkup__uart10,
6330 &dra7xx_l4_per3__usb_otg_ss1,
6331 &dra7xx_l4_per3__usb_otg_ss2,
6332 &dra7xx_l4_per3__usb_otg_ss3,
6333 &dra7xx_l4_per3__usb_otg_ss4,
6334 &dra7xx_l3_main_1__vcp1,
6335 &dra7xx_l4_per2__vcp1,
6336 &dra7xx_l3_main_1__vcp2,
6337 &dra7xx_l4_per2__vcp2,
6338 &dra7xx_l4_per3__vip1,
6339 &dra7xx_l4_per3__vip2,
6340 &dra7xx_l4_per3__vip3,
6341 &dra7xx_l4_per3__vpe,
6342 &dra7xx_l4_wkup__wd_timer2,
6343 NULL,
6344 };
6346 int __init dra7xx_hwmod_init(void)
6347 {
6348 omap_hwmod_init();
6349 return omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
6350 }