1 /*
2 * Hardware modules present on the DRA7xx chips
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley
7 * Benoit Cousson
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
20 #include <linux/io.h>
21 #include <linux/platform_data/gpio-omap.h>
22 #include <linux/power/smartreflex.h>
23 #include <linux/i2c-omap.h>
25 #include <linux/omap-dma.h>
26 #include <linux/platform_data/spi-omap2-mcspi.h>
27 #include <linux/platform_data/asoc-ti-mcbsp.h>
28 #include <linux/platform_data/iommu-omap.h>
29 #include <plat/dmtimer.h>
31 #include "omap_hwmod.h"
32 #include "omap_hwmod_common_data.h"
33 #include "cm1_7xx.h"
34 #include "cm2_7xx.h"
35 #include "prm7xx.h"
36 #include "i2c.h"
37 #include "mmc.h"
38 #include "wd_timer.h"
39 #include "soc.h"
41 /* Base offset for all DRA7XX interrupts external to MPUSS */
42 #define DRA7XX_IRQ_GIC_START 32
44 /* Base offset for all DRA7XX dma requests */
45 #define DRA7XX_DMA_REQ_START 1
48 /*
49 * IP blocks
50 */
52 /*
53 * 'dmm' class
54 * instance(s): dmm
55 */
56 static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
57 .name = "dmm",
58 };
60 /* dmm */
61 static struct omap_hwmod dra7xx_dmm_hwmod = {
62 .name = "dmm",
63 .class = &dra7xx_dmm_hwmod_class,
64 .clkdm_name = "emif_clkdm",
65 .prcm = {
66 .omap4 = {
67 .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
68 .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
69 },
70 },
71 };
73 /*
74 * 'emif_ocp_fw' class
75 * instance(s): emif_ocp_fw
76 */
77 static struct omap_hwmod_class dra7xx_emif_ocp_fw_hwmod_class = {
78 .name = "emif_ocp_fw",
79 };
81 /* emif_ocp_fw */
82 static struct omap_hwmod dra7xx_emif_ocp_fw_hwmod = {
83 .name = "emif_ocp_fw",
84 .class = &dra7xx_emif_ocp_fw_hwmod_class,
85 .clkdm_name = "emif_clkdm",
86 .prcm = {
87 .omap4 = {
88 .clkctrl_offs = DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET,
89 .context_offs = DRA7XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET,
90 },
91 },
92 };
94 /*
95 * 'l3' class
96 * instance(s): l3_instr, l3_main_1, l3_main_2
97 */
98 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
99 .name = "l3",
100 };
102 /* l3_instr */
103 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
104 .name = "l3_instr",
105 .class = &dra7xx_l3_hwmod_class,
106 .clkdm_name = "l3instr_clkdm",
107 .prcm = {
108 .omap4 = {
109 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
110 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
111 .modulemode = MODULEMODE_HWCTRL,
112 },
113 },
114 };
116 /* l3_main_1 */
117 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
118 .name = "l3_main_1",
119 .class = &dra7xx_l3_hwmod_class,
120 .clkdm_name = "l3main1_clkdm",
121 .prcm = {
122 .omap4 = {
123 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
124 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
125 },
126 },
127 };
129 /* l3_main_2 */
130 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
131 .name = "l3_main_2",
132 .class = &dra7xx_l3_hwmod_class,
133 .clkdm_name = "l3instr_clkdm",
134 .prcm = {
135 .omap4 = {
136 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
137 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
138 .modulemode = MODULEMODE_HWCTRL,
139 },
140 },
141 };
143 /*
144 * 'l4' class
145 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
146 */
147 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
148 .name = "l4",
149 };
151 /* l4_cfg */
152 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
153 .name = "l4_cfg",
154 .class = &dra7xx_l4_hwmod_class,
155 .clkdm_name = "l4cfg_clkdm",
156 .prcm = {
157 .omap4 = {
158 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
159 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
160 },
161 },
162 };
164 /* l4_per1 */
165 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
166 .name = "l4_per1",
167 .class = &dra7xx_l4_hwmod_class,
168 .clkdm_name = "l4per_clkdm",
169 .prcm = {
170 .omap4 = {
171 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
172 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
173 },
174 },
175 };
177 /* l4_per2 */
178 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
179 .name = "l4_per2",
180 .class = &dra7xx_l4_hwmod_class,
181 .clkdm_name = "l4per2_clkdm",
182 .prcm = {
183 .omap4 = {
184 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
185 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
186 },
187 },
188 };
190 /* l4_per3 */
191 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
192 .name = "l4_per3",
193 .class = &dra7xx_l4_hwmod_class,
194 .clkdm_name = "l4per3_clkdm",
195 .prcm = {
196 .omap4 = {
197 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
198 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
199 },
200 },
201 };
203 /* l4_wkup */
204 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
205 .name = "l4_wkup",
206 .class = &dra7xx_l4_hwmod_class,
207 .clkdm_name = "wkupaon_clkdm",
208 .prcm = {
209 .omap4 = {
210 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
211 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
212 },
213 },
214 };
216 /*
217 * 'atl' class
218 *
219 */
221 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
222 .name = "atl",
223 };
225 /* atl */
226 static struct omap_hwmod dra7xx_atl_hwmod = {
227 .name = "atl",
228 .class = &dra7xx_atl_hwmod_class,
229 .clkdm_name = "atl_clkdm",
230 .main_clk = "atl_gfclk_mux",
231 .lockdep_class = HWMOD_LOCKDEP_SUBCLASS_CLASS1,
232 .prcm = {
233 .omap4 = {
234 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
235 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
236 .modulemode = MODULEMODE_SWCTRL,
237 },
238 },
239 };
241 /*
242 * 'bb2d' class
243 *
244 */
246 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
247 .name = "bb2d",
248 };
250 /* bb2d */
251 static struct omap_hwmod dra7xx_bb2d_hwmod = {
252 .name = "bb2d",
253 .class = &dra7xx_bb2d_hwmod_class,
254 .clkdm_name = "dss_clkdm",
255 .main_clk = "dpll_core_h24x2_ck",
256 .prcm = {
257 .omap4 = {
258 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
259 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
260 .modulemode = MODULEMODE_SWCTRL,
261 },
262 },
263 };
265 /*
266 * 'vpe' class
267 *
268 */
270 static struct omap_hwmod_class_sysconfig dra7xx_vpe_sysc = {
271 .sysc_offs = 0x0010,
272 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
273 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
274 MSTANDBY_FORCE | MSTANDBY_NO |
275 MSTANDBY_SMART),
276 .sysc_fields = &omap_hwmod_sysc_type2,
277 };
279 static struct omap_hwmod_class dra7xx_vpe_hwmod_class = {
280 .name = "vpe",
281 .sysc = &dra7xx_vpe_sysc,
282 };
284 /* vpe */
285 static struct omap_hwmod dra7xx_vpe_hwmod = {
286 .name = "vpe",
287 .class = &dra7xx_vpe_hwmod_class,
288 .clkdm_name = "vpe_clkdm",
289 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
290 .prcm = {
291 .omap4 = {
292 .clkctrl_offs = DRA7XX_CM_VPE_VPE_CLKCTRL_OFFSET,
293 .context_offs = DRA7XX_RM_VPE_VPE_CONTEXT_OFFSET,
294 .modulemode = MODULEMODE_HWCTRL,
295 },
296 },
297 };
299 /*
300 * 'vip' class
301 *
302 */
304 static struct omap_hwmod_class_sysconfig dra7xx_vip_sysc = {
305 .sysc_offs = 0x0010,
306 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
307 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
308 MSTANDBY_FORCE | MSTANDBY_NO |
309 MSTANDBY_SMART),
310 .sysc_fields = &omap_hwmod_sysc_type2,
311 };
313 static struct omap_hwmod_class dra7xx_vip_hwmod_class = {
314 .name = "vip",
315 .sysc = &dra7xx_vip_sysc,
316 };
318 /* vip1 */
319 static struct omap_hwmod dra7xx_vip1_hwmod = {
320 .name = "vip1",
321 .class = &dra7xx_vip_hwmod_class,
322 .clkdm_name = "cam_clkdm",
323 .main_clk = "vip1_gclk_mux",
324 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
325 .prcm = {
326 .omap4 = {
327 .clkctrl_offs = DRA7XX_CM_CAM_VIP1_CLKCTRL_OFFSET,
328 .context_offs = DRA7XX_RM_CAM_VIP1_CONTEXT_OFFSET,
329 .modulemode = MODULEMODE_HWCTRL,
330 },
331 },
332 };
334 /* vip2 */
335 static struct omap_hwmod dra7xx_vip2_hwmod = {
336 .name = "vip2",
337 .class = &dra7xx_vip_hwmod_class,
338 .clkdm_name = "cam_clkdm",
339 .main_clk = "vip2_gclk_mux",
340 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
341 .prcm = {
342 .omap4 = {
343 .clkctrl_offs = DRA7XX_CM_CAM_VIP2_CLKCTRL_OFFSET,
344 .context_offs = DRA7XX_RM_CAM_VIP2_CONTEXT_OFFSET,
345 .modulemode = MODULEMODE_HWCTRL,
346 },
347 },
348 };
350 /* vip3 */
351 static struct omap_hwmod dra7xx_vip3_hwmod = {
352 .name = "vip3",
353 .class = &dra7xx_vip_hwmod_class,
354 .clkdm_name = "cam_clkdm",
355 .main_clk = "vip3_gclk_mux",
356 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
357 .prcm = {
358 .omap4 = {
359 .clkctrl_offs = DRA7XX_CM_CAM_VIP3_CLKCTRL_OFFSET,
360 .context_offs = DRA7XX_RM_CAM_VIP3_CONTEXT_OFFSET,
361 .modulemode = MODULEMODE_HWCTRL,
362 },
363 },
364 };
366 /*
367 * 'cal' class
368 *
369 */
371 static struct omap_hwmod_class_sysconfig dra7xx_cal_sysc = {
372 .sysc_offs = 0x0010,
373 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_RESET_STATUS |
374 SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE),
375 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
376 MSTANDBY_FORCE | MSTANDBY_NO),
377 .sysc_fields = &omap_hwmod_sysc_type2,
378 };
380 static struct omap_hwmod_class dra7xx_cal_hwmod_class = {
381 .name = "cal",
382 .sysc = &dra7xx_cal_sysc,
383 };
385 /* cal */
386 static struct omap_hwmod dra7xx_cal_hwmod = {
387 .name = "cal",
388 .class = &dra7xx_cal_hwmod_class,
389 .clkdm_name = "cam_clkdm",
390 .main_clk = "vip2_gclk_mux",
391 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
392 .prcm = {
393 .omap4 = {
394 .clkctrl_offs = DRA7XX_CM_CAM_VIP2_CLKCTRL_OFFSET,
395 .context_offs = DRA7XX_RM_CAM_VIP2_CONTEXT_OFFSET,
396 .modulemode = MODULEMODE_HWCTRL,
397 },
398 },
399 };
401 /*
402 * 'counter' class
403 *
404 */
406 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
407 .rev_offs = 0x0000,
408 .sysc_offs = 0x0010,
409 .sysc_flags = SYSC_HAS_SIDLEMODE,
410 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
411 SIDLE_SMART_WKUP),
412 .sysc_fields = &omap_hwmod_sysc_type1,
413 };
415 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
416 .name = "counter",
417 .sysc = &dra7xx_counter_sysc,
418 };
420 /* counter_32k */
421 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
422 .name = "counter_32k",
423 .class = &dra7xx_counter_hwmod_class,
424 .clkdm_name = "wkupaon_clkdm",
425 .flags = HWMOD_SWSUP_SIDLE,
426 .main_clk = "wkupaon_iclk_mux",
427 .prcm = {
428 .omap4 = {
429 .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
430 .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
431 },
432 },
433 };
435 /*
436 * 'ctrl_module' class
437 *
438 */
440 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
441 .name = "ctrl_module",
442 };
444 /* ctrl_module_wkup */
445 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
446 .name = "ctrl_module_wkup",
447 .class = &dra7xx_ctrl_module_hwmod_class,
448 .clkdm_name = "wkupaon_clkdm",
449 .prcm = {
450 .omap4 = {
451 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
452 },
453 },
454 };
456 /*
457 * 'gmac' class
458 * cpsw/gmac sub system
459 */
460 static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
461 .rev_offs = 0x0,
462 .sysc_offs = 0x8,
463 .syss_offs = 0x4,
464 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
465 SYSS_HAS_RESET_STATUS),
466 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
467 MSTANDBY_NO),
468 .sysc_fields = &omap_hwmod_sysc_type3,
469 };
471 static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
472 .name = "gmac",
473 .sysc = &dra7xx_gmac_sysc,
474 };
476 static struct omap_hwmod dra7xx_gmac_hwmod = {
477 .name = "gmac",
478 .class = &dra7xx_gmac_hwmod_class,
479 .clkdm_name = "gmac_clkdm",
480 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
481 .main_clk = "dpll_gmac_ck",
482 .mpu_rt_idx = 1,
483 .prcm = {
484 .omap4 = {
485 .clkctrl_offs = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
486 .context_offs = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
487 .modulemode = MODULEMODE_SWCTRL,
488 },
489 },
490 };
492 /*
493 * 'mdio' class
494 */
495 static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
496 .name = "davinci_mdio",
497 };
499 static struct omap_hwmod dra7xx_mdio_hwmod = {
500 .name = "davinci_mdio",
501 .class = &dra7xx_mdio_hwmod_class,
502 .clkdm_name = "gmac_clkdm",
503 .main_clk = "dpll_gmac_ck",
504 };
506 /*
507 * 'dcan' class
508 *
509 */
511 static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
512 .name = "dcan",
513 };
515 /* dcan1 */
516 static struct omap_hwmod dra7xx_dcan1_hwmod = {
517 .name = "dcan1",
518 .class = &dra7xx_dcan_hwmod_class,
519 .clkdm_name = "wkupaon_clkdm",
520 .prcm = {
521 .omap4 = {
522 .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
523 .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
524 .modulemode = MODULEMODE_SWCTRL,
525 },
526 },
527 };
529 /* dcan2 */
530 static struct omap_hwmod dra7xx_dcan2_hwmod = {
531 .name = "dcan2",
532 .class = &dra7xx_dcan_hwmod_class,
533 .clkdm_name = "l4per2_clkdm",
534 .prcm = {
535 .omap4 = {
536 .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
537 .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
538 .modulemode = MODULEMODE_SWCTRL,
539 },
540 },
541 };
543 /* pwmss */
544 static struct omap_hwmod_class_sysconfig dra7xx_epwmss_sysc = {
545 .rev_offs = 0x0,
546 .sysc_offs = 0x4,
547 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_RESET_STATUS,
548 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
549 .sysc_fields = &omap_hwmod_sysc_type2,
550 };
552 struct omap_hwmod_class dra7xx_epwmss_hwmod_class = {
553 .name = "epwmss",
554 .sysc = &dra7xx_epwmss_sysc,
555 };
557 static struct omap_hwmod_class dra7xx_ecap_hwmod_class = {
558 .name = "ecap",
559 };
561 static struct omap_hwmod_class dra7xx_eqep_hwmod_class = {
562 .name = "eqep",
563 };
565 struct omap_hwmod_class dra7xx_ehrpwm_hwmod_class = {
566 .name = "ehrpwm",
567 };
569 /* epwmss0 */
570 struct omap_hwmod dra7xx_epwmss0_hwmod = {
571 .name = "epwmss0",
572 .class = &dra7xx_epwmss_hwmod_class,
573 .clkdm_name = "l4per2_clkdm",
574 .main_clk = "l4_root_clk_div",
575 .prcm = {
576 .omap4 = {
577 .modulemode = MODULEMODE_SWCTRL,
578 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET,
579 .context_offs = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET,
580 },
581 },
582 };
584 /* ecap0 */
585 struct omap_hwmod dra7xx_ecap0_hwmod = {
586 .name = "ecap0",
587 .class = &dra7xx_ecap_hwmod_class,
588 .clkdm_name = "l4per2_clkdm",
589 .main_clk = "l4_root_clk_div",
590 };
592 /* eqep0 */
593 struct omap_hwmod dra7xx_eqep0_hwmod = {
594 .name = "eqep0",
595 .class = &dra7xx_eqep_hwmod_class,
596 .clkdm_name = "l4per2_clkdm",
597 .main_clk = "l4_root_clk_div",
598 };
600 /* ehrpwm0 */
601 struct omap_hwmod dra7xx_ehrpwm0_hwmod = {
602 .name = "ehrpwm0",
603 .class = &dra7xx_ehrpwm_hwmod_class,
604 .clkdm_name = "l4per2_clkdm",
605 .main_clk = "l4_root_clk_div",
606 };
608 /* epwmss1 */
609 struct omap_hwmod dra7xx_epwmss1_hwmod = {
610 .name = "epwmss1",
611 .class = &dra7xx_epwmss_hwmod_class,
612 .clkdm_name = "l4per2_clkdm",
613 .main_clk = "l4_root_clk_div",
614 .prcm = {
615 .omap4 = {
616 .modulemode = MODULEMODE_SWCTRL,
617 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET,
618 .context_offs = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET,
619 },
620 },
621 };
623 /* ecap1 */
624 struct omap_hwmod dra7xx_ecap1_hwmod = {
625 .name = "ecap1",
626 .class = &dra7xx_ecap_hwmod_class,
627 .clkdm_name = "l4per2_clkdm",
628 .main_clk = "l4_root_clk_div",
629 };
631 /* eqep1 */
632 struct omap_hwmod dra7xx_eqep1_hwmod = {
633 .name = "eqep1",
634 .class = &dra7xx_eqep_hwmod_class,
635 .clkdm_name = "l4per2_clkdm",
636 .main_clk = "l4_root_clk_div",
637 };
639 /* ehrpwm1 */
640 struct omap_hwmod dra7xx_ehrpwm1_hwmod = {
641 .name = "ehrpwm1",
642 .class = &dra7xx_ehrpwm_hwmod_class,
643 .clkdm_name = "l4per2_clkdm",
644 .main_clk = "l4_root_clk_div",
645 };
647 /* epwmss2 */
648 struct omap_hwmod dra7xx_epwmss2_hwmod = {
649 .name = "epwmss2",
650 .class = &dra7xx_epwmss_hwmod_class,
651 .clkdm_name = "l4per2_clkdm",
652 .main_clk = "l4_root_clk_div",
653 .prcm = {
654 .omap4 = {
655 .modulemode = MODULEMODE_SWCTRL,
656 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET,
657 .context_offs = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET,
658 },
659 },
660 };
662 /* ecap2 */
663 struct omap_hwmod dra7xx_ecap2_hwmod = {
664 .name = "ecap2",
665 .class = &dra7xx_ecap_hwmod_class,
666 .clkdm_name = "l4per2_clkdm",
667 .main_clk = "l4_root_clk_div",
668 };
670 /* eqep2 */
671 struct omap_hwmod dra7xx_eqep2_hwmod = {
672 .name = "eqep2",
673 .class = &dra7xx_eqep_hwmod_class,
674 .clkdm_name = "l4per2_clkdm",
675 .main_clk = "l4_root_clk_div",
676 };
678 /* ehrpwm2 */
679 struct omap_hwmod dra7xx_ehrpwm2_hwmod = {
680 .name = "ehrpwm2",
681 .class = &dra7xx_ehrpwm_hwmod_class,
682 .clkdm_name = "l4per2_clkdm",
683 .main_clk = "l4_root_clk_div",
684 };
686 /*
687 * 'dma' class
688 *
689 */
691 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
692 .rev_offs = 0x0000,
693 .sysc_offs = 0x002c,
694 .syss_offs = 0x0028,
695 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
696 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
697 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
698 SYSS_HAS_RESET_STATUS),
699 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
700 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
701 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
702 .sysc_fields = &omap_hwmod_sysc_type1,
703 };
705 static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
706 .name = "dma",
707 .sysc = &dra7xx_dma_sysc,
708 };
710 /* dma dev_attr */
711 static struct omap_dma_dev_attr dma_dev_attr = {
712 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
713 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
714 .lch_count = 32,
715 };
717 /* dma_system */
718 static struct omap_hwmod dra7xx_dma_system_hwmod = {
719 .name = "dma_system",
720 .class = &dra7xx_dma_hwmod_class,
721 .clkdm_name = "dma_clkdm",
722 .main_clk = "l3_iclk_div",
723 .prcm = {
724 .omap4 = {
725 .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
726 .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
727 },
728 },
729 .dev_attr = &dma_dev_attr,
730 };
732 /*
733 * 'dsp' class
734 * dsp sub-system
735 */
737 static struct omap_hwmod_class dra7xx_dsp_hwmod_class = {
738 .name = "dsp",
739 };
741 static struct omap_hwmod_rst_info dra7xx_dsp_resets[] = {
742 { .name = "dsp", .rst_shift = 0 },
743 };
745 /* dsp1 processor */
746 static struct omap_hwmod dra7xx_dsp1_hwmod = {
747 .name = "dsp1",
748 .class = &dra7xx_dsp_hwmod_class,
749 .clkdm_name = "dsp1_clkdm",
750 .rst_lines = dra7xx_dsp_resets,
751 .rst_lines_cnt = ARRAY_SIZE(dra7xx_dsp_resets),
752 .main_clk = "dpll_dsp_m2_ck",
753 .prcm = {
754 .omap4 = {
755 .clkctrl_offs = DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET,
756 .rstctrl_offs = DRA7XX_RM_DSP1_RSTCTRL_OFFSET,
757 .context_offs = DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET,
758 },
759 },
760 };
762 /* dsp2 processor */
763 static struct omap_hwmod dra7xx_dsp2_hwmod = {
764 .name = "dsp2",
765 .class = &dra7xx_dsp_hwmod_class,
766 .clkdm_name = "dsp2_clkdm",
767 .rst_lines = dra7xx_dsp_resets,
768 .rst_lines_cnt = ARRAY_SIZE(dra7xx_dsp_resets),
769 .main_clk = "dpll_dsp_m2_ck",
770 .prcm = {
771 .omap4 = {
772 .clkctrl_offs = DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET,
773 .rstctrl_offs = DRA7XX_RM_DSP2_RSTCTRL_OFFSET,
774 .context_offs = DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET,
775 },
776 },
777 };
779 /*
780 * 'dss' class
781 *
782 */
784 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
785 .rev_offs = 0x0000,
786 .syss_offs = 0x0014,
787 .sysc_flags = SYSS_HAS_RESET_STATUS,
788 };
790 static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
791 .name = "dss",
792 .sysc = &dra7xx_dss_sysc,
793 .reset = omap_dss_reset,
794 };
796 /* dss */
797 static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
798 { .dma_req = 75 + DRA7XX_DMA_REQ_START },
799 { .dma_req = -1 }
800 };
802 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
803 { .role = "dss_clk", .clk = "dss_dss_clk" },
804 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
805 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
806 { .role = "video2_clk", .clk = "dss_video2_clk" },
807 { .role = "video1_clk", .clk = "dss_video1_clk" },
808 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
809 };
811 static struct omap_hwmod dra7xx_dss_hwmod = {
812 .name = "dss_core",
813 .class = &dra7xx_dss_hwmod_class,
814 .clkdm_name = "dss_clkdm",
815 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
816 .sdma_reqs = dra7xx_dss_sdma_reqs,
817 .main_clk = "dss_dss_clk",
818 .prcm = {
819 .omap4 = {
820 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
821 .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
822 .modulemode = MODULEMODE_SWCTRL,
823 },
824 },
825 .opt_clks = dss_opt_clks,
826 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
827 };
829 /*
830 * 'dispc' class
831 * display controller
832 */
834 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
835 .rev_offs = 0x0000,
836 .sysc_offs = 0x0010,
837 .syss_offs = 0x0014,
838 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
839 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
840 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
841 SYSS_HAS_RESET_STATUS),
842 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
843 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
844 .sysc_fields = &omap_hwmod_sysc_type1,
845 };
847 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
848 .name = "dispc",
849 .sysc = &dra7xx_dispc_sysc,
850 };
852 /* dss_dispc */
853 /* dss_dispc dev_attr */
854 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
855 .has_framedonetv_irq = 1,
856 .manager_count = 4,
857 };
859 static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
860 .name = "dss_dispc",
861 .class = &dra7xx_dispc_hwmod_class,
862 .clkdm_name = "dss_clkdm",
863 .main_clk = "dss_dss_clk",
864 .prcm = {
865 .omap4 = {
866 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
867 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
868 },
869 },
870 .dev_attr = &dss_dispc_dev_attr,
871 .parent_hwmod = &dra7xx_dss_hwmod,
872 };
874 /*
875 * 'hdmi' class
876 * hdmi controller
877 */
879 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
880 .rev_offs = 0x0000,
881 .sysc_offs = 0x0010,
882 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
883 SYSC_HAS_SOFTRESET),
884 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
885 SIDLE_SMART_WKUP),
886 .sysc_fields = &omap_hwmod_sysc_type2,
887 };
889 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
890 .name = "hdmi",
891 .sysc = &dra7xx_hdmi_sysc,
892 };
894 /* dss_hdmi */
896 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
897 { .role = "sys_clk", .clk = "dss_hdmi_clk" },
898 };
900 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
901 .name = "dss_hdmi",
902 .class = &dra7xx_hdmi_hwmod_class,
903 .clkdm_name = "dss_clkdm",
904 .main_clk = "dss_48mhz_clk",
905 .prcm = {
906 .omap4 = {
907 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
908 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
909 },
910 },
911 .opt_clks = dss_hdmi_opt_clks,
912 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
913 .parent_hwmod = &dra7xx_dss_hwmod,
914 };
916 /* AES (the 'P' (public) device) */
917 static struct omap_hwmod_class_sysconfig dra7xx_aes_sysc = {
918 .rev_offs = 0x0080,
919 .sysc_offs = 0x0084,
920 .syss_offs = 0x0088,
921 .sysc_flags = SYSS_HAS_RESET_STATUS,
922 };
924 static struct omap_hwmod_class dra7xx_aes_hwmod_class = {
925 .name = "aes",
926 .sysc = &dra7xx_aes_sysc,
927 .rev = 2,
928 };
930 /* AES */
931 static struct omap_hwmod dra7xx_aes_hwmod = {
932 .name = "aes",
933 .class = &dra7xx_aes_hwmod_class,
934 .clkdm_name = "l4sec_clkdm",
935 .main_clk = "l3_iclk_div",
936 .prcm = {
937 .omap4 = {
938 .clkctrl_offs = DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET,
939 .context_offs = DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET,
940 .modulemode = MODULEMODE_HWCTRL,
941 },
942 },
943 };
945 /* sha0 HIB2 (the 'P' (public) device) */
946 static struct omap_hwmod_class_sysconfig dra7xx_sha0_sysc = {
947 .rev_offs = 0x100,
948 .sysc_offs = 0x110,
949 .syss_offs = 0x114,
950 .sysc_flags = SYSS_HAS_RESET_STATUS,
951 };
953 static struct omap_hwmod_class dra7xx_sha0_hwmod_class = {
954 .name = "sham",
955 .sysc = &dra7xx_sha0_sysc,
956 .rev = 2,
957 };
959 struct omap_hwmod dra7xx_sha0_hwmod = {
960 .name = "sham",
961 .class = &dra7xx_sha0_hwmod_class,
962 .clkdm_name = "l4sec_clkdm",
963 .main_clk = "l3_iclk_div",
964 .prcm = {
965 .omap4 = {
966 .clkctrl_offs = DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
967 .context_offs = DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
968 .modulemode = MODULEMODE_HWCTRL,
969 },
970 },
971 };
973 /*
974 * 'elm' class
975 *
976 */
978 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
979 .rev_offs = 0x0000,
980 .sysc_offs = 0x0010,
981 .syss_offs = 0x0014,
982 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
983 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
984 SYSS_HAS_RESET_STATUS),
985 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
986 SIDLE_SMART_WKUP),
987 .sysc_fields = &omap_hwmod_sysc_type1,
988 };
990 static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
991 .name = "elm",
992 .sysc = &dra7xx_elm_sysc,
993 };
995 /* elm */
997 static struct omap_hwmod dra7xx_elm_hwmod = {
998 .name = "elm",
999 .class = &dra7xx_elm_hwmod_class,
1000 .clkdm_name = "l4per_clkdm",
1001 .main_clk = "l3_iclk_div",
1002 .prcm = {
1003 .omap4 = {
1004 .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
1005 .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
1006 },
1007 },
1008 };
1010 /*
1011 * 'gpio' class
1012 *
1013 */
1015 static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
1016 .rev_offs = 0x0000,
1017 .sysc_offs = 0x0010,
1018 .syss_offs = 0x0114,
1019 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1020 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1021 SYSS_HAS_RESET_STATUS),
1022 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1023 SIDLE_SMART_WKUP),
1024 .sysc_fields = &omap_hwmod_sysc_type1,
1025 };
1027 static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
1028 .name = "gpio",
1029 .sysc = &dra7xx_gpio_sysc,
1030 .rev = 2,
1031 };
1033 /* gpio dev_attr */
1034 static struct omap_gpio_dev_attr gpio_dev_attr = {
1035 .bank_width = 32,
1036 .dbck_flag = true,
1037 };
1039 /* gpio1 */
1040 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1041 { .role = "dbclk", .clk = "gpio1_dbclk" },
1042 };
1044 static struct omap_hwmod dra7xx_gpio1_hwmod = {
1045 .name = "gpio1",
1046 .class = &dra7xx_gpio_hwmod_class,
1047 .clkdm_name = "wkupaon_clkdm",
1048 .main_clk = "wkupaon_iclk_mux",
1049 .prcm = {
1050 .omap4 = {
1051 .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
1052 .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
1053 .modulemode = MODULEMODE_HWCTRL,
1054 },
1055 },
1056 .opt_clks = gpio1_opt_clks,
1057 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1058 .dev_attr = &gpio_dev_attr,
1059 };
1061 /* gpio2 */
1062 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1063 { .role = "dbclk", .clk = "gpio2_dbclk" },
1064 };
1066 static struct omap_hwmod dra7xx_gpio2_hwmod = {
1067 .name = "gpio2",
1068 .class = &dra7xx_gpio_hwmod_class,
1069 .clkdm_name = "l4per_clkdm",
1070 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1071 .main_clk = "l3_iclk_div",
1072 .prcm = {
1073 .omap4 = {
1074 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1075 .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1076 .modulemode = MODULEMODE_HWCTRL,
1077 },
1078 },
1079 .opt_clks = gpio2_opt_clks,
1080 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1081 .dev_attr = &gpio_dev_attr,
1082 };
1084 /* gpio3 */
1085 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1086 { .role = "dbclk", .clk = "gpio3_dbclk" },
1087 };
1089 static struct omap_hwmod dra7xx_gpio3_hwmod = {
1090 .name = "gpio3",
1091 .class = &dra7xx_gpio_hwmod_class,
1092 .clkdm_name = "l4per_clkdm",
1093 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1094 .main_clk = "l3_iclk_div",
1095 .prcm = {
1096 .omap4 = {
1097 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1098 .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1099 .modulemode = MODULEMODE_HWCTRL,
1100 },
1101 },
1102 .opt_clks = gpio3_opt_clks,
1103 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1104 .dev_attr = &gpio_dev_attr,
1105 };
1107 /* gpio4 */
1108 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1109 { .role = "dbclk", .clk = "gpio4_dbclk" },
1110 };
1112 static struct omap_hwmod dra7xx_gpio4_hwmod = {
1113 .name = "gpio4",
1114 .class = &dra7xx_gpio_hwmod_class,
1115 .clkdm_name = "l4per_clkdm",
1116 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1117 .main_clk = "l3_iclk_div",
1118 .prcm = {
1119 .omap4 = {
1120 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1121 .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1122 .modulemode = MODULEMODE_HWCTRL,
1123 },
1124 },
1125 .opt_clks = gpio4_opt_clks,
1126 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1127 .dev_attr = &gpio_dev_attr,
1128 };
1130 /* gpio5 */
1131 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1132 { .role = "dbclk", .clk = "gpio5_dbclk" },
1133 };
1135 static struct omap_hwmod dra7xx_gpio5_hwmod = {
1136 .name = "gpio5",
1137 .class = &dra7xx_gpio_hwmod_class,
1138 .clkdm_name = "l4per_clkdm",
1139 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1140 .main_clk = "l3_iclk_div",
1141 .prcm = {
1142 .omap4 = {
1143 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1144 .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1145 .modulemode = MODULEMODE_HWCTRL,
1146 },
1147 },
1148 .opt_clks = gpio5_opt_clks,
1149 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1150 .dev_attr = &gpio_dev_attr,
1151 };
1153 /* gpio6 */
1154 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1155 { .role = "dbclk", .clk = "gpio6_dbclk" },
1156 };
1158 static struct omap_hwmod dra7xx_gpio6_hwmod = {
1159 .name = "gpio6",
1160 .class = &dra7xx_gpio_hwmod_class,
1161 .clkdm_name = "l4per_clkdm",
1162 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1163 .main_clk = "l3_iclk_div",
1164 .prcm = {
1165 .omap4 = {
1166 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1167 .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1168 .modulemode = MODULEMODE_HWCTRL,
1169 },
1170 },
1171 .opt_clks = gpio6_opt_clks,
1172 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1173 .dev_attr = &gpio_dev_attr,
1174 };
1176 /* gpio7 */
1177 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
1178 { .role = "dbclk", .clk = "gpio7_dbclk" },
1179 };
1181 static struct omap_hwmod dra7xx_gpio7_hwmod = {
1182 .name = "gpio7",
1183 .class = &dra7xx_gpio_hwmod_class,
1184 .clkdm_name = "l4per_clkdm",
1185 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1186 .main_clk = "l3_iclk_div",
1187 .prcm = {
1188 .omap4 = {
1189 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
1190 .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
1191 .modulemode = MODULEMODE_HWCTRL,
1192 },
1193 },
1194 .opt_clks = gpio7_opt_clks,
1195 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
1196 .dev_attr = &gpio_dev_attr,
1197 };
1199 /* gpio8 */
1200 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
1201 { .role = "dbclk", .clk = "gpio8_dbclk" },
1202 };
1204 static struct omap_hwmod dra7xx_gpio8_hwmod = {
1205 .name = "gpio8",
1206 .class = &dra7xx_gpio_hwmod_class,
1207 .clkdm_name = "l4per_clkdm",
1208 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1209 .main_clk = "l3_iclk_div",
1210 .prcm = {
1211 .omap4 = {
1212 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
1213 .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
1214 .modulemode = MODULEMODE_HWCTRL,
1215 },
1216 },
1217 .opt_clks = gpio8_opt_clks,
1218 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
1219 .dev_attr = &gpio_dev_attr,
1220 };
1222 /*
1223 * 'gpmc' class
1224 *
1225 */
1227 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
1228 .rev_offs = 0x0000,
1229 .sysc_offs = 0x0010,
1230 .syss_offs = 0x0014,
1231 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1232 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1233 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1234 SIDLE_SMART_WKUP),
1235 .sysc_fields = &omap_hwmod_sysc_type1,
1236 };
1238 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
1239 .name = "gpmc",
1240 .sysc = &dra7xx_gpmc_sysc,
1241 };
1243 /* gpmc */
1245 static struct omap_hwmod dra7xx_gpmc_hwmod = {
1246 .name = "gpmc",
1247 .class = &dra7xx_gpmc_hwmod_class,
1248 .clkdm_name = "l3main1_clkdm",
1249 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
1250 HWMOD_SWSUP_SIDLE),
1251 .main_clk = "l3_iclk_div",
1252 .prcm = {
1253 .omap4 = {
1254 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
1255 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
1256 .modulemode = MODULEMODE_HWCTRL,
1257 },
1258 },
1259 };
1261 /*
1262 * 'gpu' class
1263 * 2d/3d graphics accelerator
1264 */
1266 static struct omap_hwmod_class_sysconfig dra7xx_gpu_sysc = {
1267 .rev_offs = 0x0000,
1268 .sysc_offs = 0x0010,
1269 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1270 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1271 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1272 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1273 .sysc_fields = &omap_hwmod_sysc_type2,
1274 };
1276 static struct omap_hwmod_class dra7xx_gpu_hwmod_class = {
1277 .name = "gpu",
1278 .sysc = &dra7xx_gpu_sysc,
1279 };
1281 static struct omap_hwmod dra7xx_gpu_hwmod = {
1282 .name = "gpu",
1283 .class = &dra7xx_gpu_hwmod_class,
1284 .clkdm_name = "gpu_clkdm",
1285 .main_clk = "gpu_core_gclk_mux",
1286 .prcm = {
1287 .omap4 = {
1288 .clkctrl_offs = DRA7XX_CM_GPU_GPU_CLKCTRL_OFFSET,
1289 .context_offs = DRA7XX_RM_GPU_GPU_CONTEXT_OFFSET,
1290 .modulemode = MODULEMODE_SWCTRL,
1291 },
1292 },
1293 };
1295 /*
1296 * 'hdq1w' class
1297 *
1298 */
1300 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
1301 .rev_offs = 0x0000,
1302 .sysc_offs = 0x0014,
1303 .syss_offs = 0x0018,
1304 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1305 SYSS_HAS_RESET_STATUS),
1306 .sysc_fields = &omap_hwmod_sysc_type1,
1307 };
1309 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
1310 .name = "hdq1w",
1311 .sysc = &dra7xx_hdq1w_sysc,
1312 };
1314 /* hdq1w */
1316 static struct omap_hwmod dra7xx_hdq1w_hwmod = {
1317 .name = "hdq1w",
1318 .class = &dra7xx_hdq1w_hwmod_class,
1319 .clkdm_name = "l4per_clkdm",
1320 .flags = HWMOD_INIT_NO_RESET,
1321 .main_clk = "func_12m_fclk",
1322 .prcm = {
1323 .omap4 = {
1324 .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1325 .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1326 .modulemode = MODULEMODE_SWCTRL,
1327 },
1328 },
1329 };
1331 /*
1332 * 'i2c' class
1333 *
1334 */
1336 static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
1337 .sysc_offs = 0x0010,
1338 .syss_offs = 0x0090,
1339 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1340 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1341 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1342 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1343 SIDLE_SMART_WKUP),
1344 .clockact = CLOCKACT_TEST_ICLK,
1345 .sysc_fields = &omap_hwmod_sysc_type1,
1346 };
1348 static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
1349 .name = "i2c",
1350 .sysc = &dra7xx_i2c_sysc,
1351 .reset = &omap_i2c_reset,
1352 .rev = OMAP_I2C_IP_VERSION_2,
1353 };
1355 /* i2c dev_attr */
1356 static struct omap_i2c_dev_attr i2c_dev_attr = {
1357 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1358 };
1360 /* i2c1 */
1361 static struct omap_hwmod dra7xx_i2c1_hwmod = {
1362 .name = "i2c1",
1363 .class = &dra7xx_i2c_hwmod_class,
1364 .clkdm_name = "l4per_clkdm",
1365 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1366 .main_clk = "func_96m_fclk",
1367 .prcm = {
1368 .omap4 = {
1369 .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1370 .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
1371 .modulemode = MODULEMODE_SWCTRL,
1372 },
1373 },
1374 .dev_attr = &i2c_dev_attr,
1375 };
1377 /* i2c2 */
1378 static struct omap_hwmod dra7xx_i2c2_hwmod = {
1379 .name = "i2c2",
1380 .class = &dra7xx_i2c_hwmod_class,
1381 .clkdm_name = "l4per_clkdm",
1382 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1383 .main_clk = "func_96m_fclk",
1384 .prcm = {
1385 .omap4 = {
1386 .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1387 .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
1388 .modulemode = MODULEMODE_SWCTRL,
1389 },
1390 },
1391 .dev_attr = &i2c_dev_attr,
1392 };
1394 /* i2c3 */
1395 static struct omap_hwmod dra7xx_i2c3_hwmod = {
1396 .name = "i2c3",
1397 .class = &dra7xx_i2c_hwmod_class,
1398 .clkdm_name = "l4per_clkdm",
1399 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1400 .main_clk = "func_96m_fclk",
1401 .prcm = {
1402 .omap4 = {
1403 .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1404 .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
1405 .modulemode = MODULEMODE_SWCTRL,
1406 },
1407 },
1408 .dev_attr = &i2c_dev_attr,
1409 };
1411 /* i2c4 */
1412 static struct omap_hwmod dra7xx_i2c4_hwmod = {
1413 .name = "i2c4",
1414 .class = &dra7xx_i2c_hwmod_class,
1415 .clkdm_name = "l4per_clkdm",
1416 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1417 .main_clk = "func_96m_fclk",
1418 .prcm = {
1419 .omap4 = {
1420 .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1421 .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
1422 .modulemode = MODULEMODE_SWCTRL,
1423 },
1424 },
1425 .dev_attr = &i2c_dev_attr,
1426 };
1428 /* i2c5 */
1429 static struct omap_hwmod dra7xx_i2c5_hwmod = {
1430 .name = "i2c5",
1431 .class = &dra7xx_i2c_hwmod_class,
1432 .clkdm_name = "ipu_clkdm",
1433 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1434 .main_clk = "func_96m_fclk",
1435 .prcm = {
1436 .omap4 = {
1437 .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
1438 .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
1439 .modulemode = MODULEMODE_SWCTRL,
1440 },
1441 },
1442 .dev_attr = &i2c_dev_attr,
1443 };
1445 /*
1446 * 'ipu' class
1447 * imaging processor unit
1448 */
1450 static struct omap_hwmod_class dra7xx_ipu_hwmod_class = {
1451 .name = "ipu",
1452 };
1454 static struct omap_hwmod_rst_info dra7xx_ipu_resets[] = {
1455 { .name = "cpu0", .rst_shift = 0 },
1456 { .name = "cpu1", .rst_shift = 1 },
1457 };
1459 /* ipu1 processor */
1460 static struct omap_hwmod dra7xx_ipu1_hwmod = {
1461 .name = "ipu1",
1462 .class = &dra7xx_ipu_hwmod_class,
1463 .clkdm_name = "ipu1_clkdm",
1464 .rst_lines = dra7xx_ipu_resets,
1465 .rst_lines_cnt = ARRAY_SIZE(dra7xx_ipu_resets),
1466 .main_clk = "ipu1_gfclk_mux",
1467 .prcm = {
1468 .omap4 = {
1469 .clkctrl_offs = DRA7XX_CM_IPU1_IPU1_CLKCTRL_OFFSET,
1470 .rstctrl_offs = DRA7XX_RM_IPU1_RSTCTRL_OFFSET,
1471 .context_offs = DRA7XX_RM_IPU1_IPU1_CONTEXT_OFFSET,
1472 },
1473 },
1474 };
1476 /* ipu2 processor */
1477 static struct omap_hwmod dra7xx_ipu2_hwmod = {
1478 .name = "ipu2",
1479 .class = &dra7xx_ipu_hwmod_class,
1480 .clkdm_name = "ipu2_clkdm",
1481 .rst_lines = dra7xx_ipu_resets,
1482 .rst_lines_cnt = ARRAY_SIZE(dra7xx_ipu_resets),
1483 .main_clk = "dpll_core_h22x2_ck",
1484 .prcm = {
1485 .omap4 = {
1486 .clkctrl_offs = DRA7XX_CM_IPU2_IPU2_CLKCTRL_OFFSET,
1487 .rstctrl_offs = DRA7XX_RM_IPU2_RSTCTRL_OFFSET,
1488 .context_offs = DRA7XX_RM_IPU2_IPU2_CONTEXT_OFFSET,
1489 },
1490 },
1491 };
1493 /*
1494 * 'mailbox' class
1495 *
1496 */
1498 static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
1499 .rev_offs = 0x0000,
1500 .sysc_offs = 0x0010,
1501 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1502 SYSC_HAS_SOFTRESET),
1503 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1504 .sysc_fields = &omap_hwmod_sysc_type2,
1505 };
1507 static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
1508 .name = "mailbox",
1509 .sysc = &dra7xx_mailbox_sysc,
1510 };
1512 /* mailbox1 */
1513 static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1514 .name = "mailbox1",
1515 .class = &dra7xx_mailbox_hwmod_class,
1516 .clkdm_name = "l4cfg_clkdm",
1517 .prcm = {
1518 .omap4 = {
1519 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1520 .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1521 },
1522 },
1523 };
1525 /* mailbox2 */
1526 static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1527 .name = "mailbox2",
1528 .class = &dra7xx_mailbox_hwmod_class,
1529 .clkdm_name = "l4cfg_clkdm",
1530 .prcm = {
1531 .omap4 = {
1532 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1533 .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1534 },
1535 },
1536 };
1538 /* mailbox3 */
1539 static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1540 .name = "mailbox3",
1541 .class = &dra7xx_mailbox_hwmod_class,
1542 .clkdm_name = "l4cfg_clkdm",
1543 .prcm = {
1544 .omap4 = {
1545 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1546 .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1547 },
1548 },
1549 };
1551 /* mailbox4 */
1552 static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1553 .name = "mailbox4",
1554 .class = &dra7xx_mailbox_hwmod_class,
1555 .clkdm_name = "l4cfg_clkdm",
1556 .prcm = {
1557 .omap4 = {
1558 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1559 .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1560 },
1561 },
1562 };
1564 /* mailbox5 */
1565 static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1566 .name = "mailbox5",
1567 .class = &dra7xx_mailbox_hwmod_class,
1568 .clkdm_name = "l4cfg_clkdm",
1569 .prcm = {
1570 .omap4 = {
1571 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1572 .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1573 },
1574 },
1575 };
1577 /* mailbox6 */
1578 static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1579 .name = "mailbox6",
1580 .class = &dra7xx_mailbox_hwmod_class,
1581 .clkdm_name = "l4cfg_clkdm",
1582 .prcm = {
1583 .omap4 = {
1584 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1585 .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1586 },
1587 },
1588 };
1590 /* mailbox7 */
1591 static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1592 .name = "mailbox7",
1593 .class = &dra7xx_mailbox_hwmod_class,
1594 .clkdm_name = "l4cfg_clkdm",
1595 .prcm = {
1596 .omap4 = {
1597 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1598 .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1599 },
1600 },
1601 };
1603 /* mailbox8 */
1604 static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1605 .name = "mailbox8",
1606 .class = &dra7xx_mailbox_hwmod_class,
1607 .clkdm_name = "l4cfg_clkdm",
1608 .prcm = {
1609 .omap4 = {
1610 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1611 .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1612 },
1613 },
1614 };
1616 /* mailbox9 */
1617 static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1618 .name = "mailbox9",
1619 .class = &dra7xx_mailbox_hwmod_class,
1620 .clkdm_name = "l4cfg_clkdm",
1621 .prcm = {
1622 .omap4 = {
1623 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1624 .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1625 },
1626 },
1627 };
1629 /* mailbox10 */
1630 static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1631 .name = "mailbox10",
1632 .class = &dra7xx_mailbox_hwmod_class,
1633 .clkdm_name = "l4cfg_clkdm",
1634 .prcm = {
1635 .omap4 = {
1636 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1637 .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1638 },
1639 },
1640 };
1642 /* mailbox11 */
1643 static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1644 .name = "mailbox11",
1645 .class = &dra7xx_mailbox_hwmod_class,
1646 .clkdm_name = "l4cfg_clkdm",
1647 .prcm = {
1648 .omap4 = {
1649 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1650 .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1651 },
1652 },
1653 };
1655 /* mailbox12 */
1656 static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1657 .name = "mailbox12",
1658 .class = &dra7xx_mailbox_hwmod_class,
1659 .clkdm_name = "l4cfg_clkdm",
1660 .prcm = {
1661 .omap4 = {
1662 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1663 .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1664 },
1665 },
1666 };
1668 /* mailbox13 */
1669 static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1670 .name = "mailbox13",
1671 .class = &dra7xx_mailbox_hwmod_class,
1672 .clkdm_name = "l4cfg_clkdm",
1673 .prcm = {
1674 .omap4 = {
1675 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1676 .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1677 },
1678 },
1679 };
1681 /*
1682 * 'mcspi' class
1683 *
1684 */
1686 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1687 .rev_offs = 0x0000,
1688 .sysc_offs = 0x0010,
1689 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1690 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1691 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1692 SIDLE_SMART_WKUP),
1693 .sysc_fields = &omap_hwmod_sysc_type2,
1694 };
1696 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1697 .name = "mcspi",
1698 .sysc = &dra7xx_mcspi_sysc,
1699 .rev = OMAP4_MCSPI_REV,
1700 };
1702 /* mcspi1 */
1703 /* mcspi1 dev_attr */
1704 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1705 .num_chipselect = 4,
1706 };
1708 static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1709 .name = "mcspi1",
1710 .class = &dra7xx_mcspi_hwmod_class,
1711 .clkdm_name = "l4per_clkdm",
1712 .main_clk = "func_48m_fclk",
1713 .prcm = {
1714 .omap4 = {
1715 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1716 .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1717 .modulemode = MODULEMODE_SWCTRL,
1718 },
1719 },
1720 .dev_attr = &mcspi1_dev_attr,
1721 };
1723 /* mcspi2 */
1724 /* mcspi2 dev_attr */
1725 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1726 .num_chipselect = 2,
1727 };
1729 static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1730 .name = "mcspi2",
1731 .class = &dra7xx_mcspi_hwmod_class,
1732 .clkdm_name = "l4per_clkdm",
1733 .main_clk = "func_48m_fclk",
1734 .prcm = {
1735 .omap4 = {
1736 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1737 .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1738 .modulemode = MODULEMODE_SWCTRL,
1739 },
1740 },
1741 .dev_attr = &mcspi2_dev_attr,
1742 };
1744 /* mcspi3 */
1745 /* mcspi3 dev_attr */
1746 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1747 .num_chipselect = 2,
1748 };
1750 static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1751 .name = "mcspi3",
1752 .class = &dra7xx_mcspi_hwmod_class,
1753 .clkdm_name = "l4per_clkdm",
1754 .main_clk = "func_48m_fclk",
1755 .prcm = {
1756 .omap4 = {
1757 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1758 .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1759 .modulemode = MODULEMODE_SWCTRL,
1760 },
1761 },
1762 .dev_attr = &mcspi3_dev_attr,
1763 };
1765 /* mcspi4 */
1766 /* mcspi4 dev_attr */
1767 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1768 .num_chipselect = 1,
1769 };
1771 static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1772 .name = "mcspi4",
1773 .class = &dra7xx_mcspi_hwmod_class,
1774 .clkdm_name = "l4per_clkdm",
1775 .main_clk = "func_48m_fclk",
1776 .prcm = {
1777 .omap4 = {
1778 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1779 .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1780 .modulemode = MODULEMODE_SWCTRL,
1781 },
1782 },
1783 .dev_attr = &mcspi4_dev_attr,
1784 };
1786 /*
1787 * 'mcasp' class
1788 *
1789 */
1790 static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc = {
1791 .sysc_offs = 0x0004,
1792 .sysc_flags = SYSC_HAS_SIDLEMODE,
1793 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1794 .sysc_fields = &omap_hwmod_sysc_type3,
1795 };
1797 static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
1798 .name = "mcasp",
1799 .sysc = &dra7xx_mcasp_sysc,
1800 };
1802 /* mcasp2 */
1803 static struct omap_hwmod dra7xx_mcasp2_hwmod = {
1804 .name = "mcasp2",
1805 .class = &dra7xx_mcasp_hwmod_class,
1806 .clkdm_name = "l4per2_clkdm",
1807 .main_clk = "mcasp2_ahclkx_mux",
1808 .flags = HWMOD_SWSUP_SIDLE_ACT,
1809 .prcm = {
1810 .omap4 = {
1811 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,
1812 .context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
1813 .modulemode = MODULEMODE_SWCTRL,
1814 },
1815 },
1816 };
1818 /* mcasp3 */
1819 static struct omap_hwmod dra7xx_mcasp3_hwmod = {
1820 .name = "mcasp3",
1821 .class = &dra7xx_mcasp_hwmod_class,
1822 .clkdm_name = "l4per2_clkdm",
1823 .main_clk = "mcasp3_ahclkx_mux",
1824 .flags = HWMOD_SWSUP_SIDLE,
1825 .prcm = {
1826 .omap4 = {
1827 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET,
1828 .context_offs = DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET,
1829 .modulemode = MODULEMODE_SWCTRL,
1830 },
1831 },
1832 };
1834 /* mcasp6 */
1835 static struct omap_hwmod dra7xx_mcasp6_hwmod = {
1836 .name = "mcasp6",
1837 .class = &dra7xx_mcasp_hwmod_class,
1838 .clkdm_name = "l4per2_clkdm",
1839 .main_clk = "mcasp6_ahclkx_mux",
1840 .flags = HWMOD_SWSUP_SIDLE_ACT,
1841 .prcm = {
1842 .omap4 = {
1843 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,
1844 .context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
1845 .modulemode = MODULEMODE_SWCTRL,
1846 },
1847 },
1848 };
1850 /*
1851 * 'mmc' class
1852 *
1853 */
1855 static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1856 .rev_offs = 0x0000,
1857 .sysc_offs = 0x0010,
1858 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1859 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1860 SYSC_HAS_SOFTRESET),
1861 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1862 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1863 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1864 .sysc_fields = &omap_hwmod_sysc_type2,
1865 };
1867 static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1868 .name = "mmc",
1869 .sysc = &dra7xx_mmc_sysc,
1870 };
1872 /* mmc1 */
1873 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1874 { .role = "clk32k", .clk = "mmc1_clk32k" },
1875 };
1877 /* mmc1 dev_attr */
1878 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1879 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1880 };
1882 static struct omap_hwmod dra7xx_mmc1_hwmod = {
1883 .name = "mmc1",
1884 .class = &dra7xx_mmc_hwmod_class,
1885 .clkdm_name = "l3init_clkdm",
1886 .main_clk = "mmc1_fclk_div",
1887 .prcm = {
1888 .omap4 = {
1889 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1890 .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1891 .modulemode = MODULEMODE_SWCTRL,
1892 },
1893 },
1894 .opt_clks = mmc1_opt_clks,
1895 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1896 .dev_attr = &mmc1_dev_attr,
1897 };
1899 /* mmc2 */
1900 static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1901 { .role = "clk32k", .clk = "mmc2_clk32k" },
1902 };
1904 static struct omap_hwmod dra7xx_mmc2_hwmod = {
1905 .name = "mmc2",
1906 .class = &dra7xx_mmc_hwmod_class,
1907 .clkdm_name = "l3init_clkdm",
1908 .main_clk = "mmc2_fclk_div",
1909 .prcm = {
1910 .omap4 = {
1911 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1912 .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1913 .modulemode = MODULEMODE_SWCTRL,
1914 },
1915 },
1916 .opt_clks = mmc2_opt_clks,
1917 .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks),
1918 };
1920 /* mmc3 */
1921 static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1922 { .role = "clk32k", .clk = "mmc3_clk32k" },
1923 };
1925 static struct omap_hwmod dra7xx_mmc3_hwmod = {
1926 .name = "mmc3",
1927 .class = &dra7xx_mmc_hwmod_class,
1928 .clkdm_name = "l4per_clkdm",
1929 .main_clk = "mmc3_gfclk_div",
1930 .prcm = {
1931 .omap4 = {
1932 .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1933 .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1934 .modulemode = MODULEMODE_SWCTRL,
1935 },
1936 },
1937 .opt_clks = mmc3_opt_clks,
1938 .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks),
1939 };
1941 /* mmc4 */
1942 static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1943 { .role = "clk32k", .clk = "mmc4_clk32k" },
1944 };
1946 static struct omap_hwmod dra7xx_mmc4_hwmod = {
1947 .name = "mmc4",
1948 .class = &dra7xx_mmc_hwmod_class,
1949 .clkdm_name = "l4per_clkdm",
1950 .main_clk = "mmc4_gfclk_div",
1951 .prcm = {
1952 .omap4 = {
1953 .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1954 .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1955 .modulemode = MODULEMODE_SWCTRL,
1956 },
1957 },
1958 .opt_clks = mmc4_opt_clks,
1959 .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks),
1960 };
1962 /*
1963 * 'mmu' class
1964 * The memory management unit performs virtual to physical address translation
1965 * for its requestors.
1966 */
1968 static struct omap_hwmod_class_sysconfig dra7xx_mmu_sysc = {
1969 .rev_offs = 0x0000,
1970 .sysc_offs = 0x0010,
1971 .syss_offs = 0x0014,
1972 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1973 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1974 SYSS_HAS_RESET_STATUS),
1975 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1976 .sysc_fields = &omap_hwmod_sysc_type1,
1977 };
1979 static struct omap_hwmod_class dra7xx_mmu_hwmod_class = {
1980 .name = "mmu",
1981 .sysc = &dra7xx_mmu_sysc,
1982 };
1984 /* DSP MMUs */
1985 static struct omap_hwmod_rst_info dra7xx_mmu_dsp_resets[] = {
1986 { .name = "mmu_cache", .rst_shift = 1 },
1987 };
1989 /* mmu0 - dsp1 */
1990 static struct omap_hwmod dra7xx_mmu0_dsp1_hwmod = {
1991 .name = "mmu0_dsp1",
1992 .class = &dra7xx_mmu_hwmod_class,
1993 .clkdm_name = "dsp1_clkdm",
1994 .rst_lines = dra7xx_mmu_dsp_resets,
1995 .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_dsp_resets),
1996 .main_clk = "dpll_dsp_m2_ck",
1997 .prcm = {
1998 .omap4 = {
1999 .clkctrl_offs = DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET,
2000 .rstctrl_offs = DRA7XX_RM_DSP1_RSTCTRL_OFFSET,
2001 .context_offs = DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET,
2002 .modulemode = MODULEMODE_HWCTRL,
2003 },
2004 },
2005 };
2007 /* mmu1 - dsp1 */
2008 static struct omap_hwmod dra7xx_mmu1_dsp1_hwmod = {
2009 .name = "mmu1_dsp1",
2010 .class = &dra7xx_mmu_hwmod_class,
2011 .clkdm_name = "dsp1_clkdm",
2012 .rst_lines = dra7xx_mmu_dsp_resets,
2013 .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_dsp_resets),
2014 .main_clk = "dpll_dsp_m2_ck",
2015 .prcm = {
2016 .omap4 = {
2017 .clkctrl_offs = DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET,
2018 .rstctrl_offs = DRA7XX_RM_DSP1_RSTCTRL_OFFSET,
2019 .context_offs = DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET,
2020 .modulemode = MODULEMODE_HWCTRL,
2021 },
2022 },
2023 };
2025 /* mmu0 - dsp2 */
2026 static struct omap_hwmod dra7xx_mmu0_dsp2_hwmod = {
2027 .name = "mmu0_dsp2",
2028 .class = &dra7xx_mmu_hwmod_class,
2029 .clkdm_name = "dsp2_clkdm",
2030 .rst_lines = dra7xx_mmu_dsp_resets,
2031 .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_dsp_resets),
2032 .main_clk = "dpll_dsp_m2_ck",
2033 .prcm = {
2034 .omap4 = {
2035 .clkctrl_offs = DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET,
2036 .rstctrl_offs = DRA7XX_RM_DSP2_RSTCTRL_OFFSET,
2037 .context_offs = DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET,
2038 .modulemode = MODULEMODE_HWCTRL,
2039 },
2040 },
2041 };
2043 /* mmu1 - dsp2 */
2044 static struct omap_hwmod dra7xx_mmu1_dsp2_hwmod = {
2045 .name = "mmu1_dsp2",
2046 .class = &dra7xx_mmu_hwmod_class,
2047 .clkdm_name = "dsp2_clkdm",
2048 .rst_lines = dra7xx_mmu_dsp_resets,
2049 .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_dsp_resets),
2050 .main_clk = "dpll_dsp_m2_ck",
2051 .prcm = {
2052 .omap4 = {
2053 .clkctrl_offs = DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET,
2054 .rstctrl_offs = DRA7XX_RM_DSP2_RSTCTRL_OFFSET,
2055 .context_offs = DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET,
2056 .modulemode = MODULEMODE_HWCTRL,
2057 },
2058 },
2059 };
2061 /* IPU MMUs */
2062 static struct omap_hwmod_rst_info dra7xx_mmu_ipu_resets[] = {
2063 { .name = "mmu_cache", .rst_shift = 2 },
2064 };
2066 /* mmu ipu1 */
2067 static struct omap_hwmod dra7xx_mmu_ipu1_hwmod = {
2068 .name = "mmu_ipu1",
2069 .class = &dra7xx_mmu_hwmod_class,
2070 .clkdm_name = "ipu1_clkdm",
2071 .rst_lines = dra7xx_mmu_ipu_resets,
2072 .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_ipu_resets),
2073 .main_clk = "ipu1_gfclk_mux",
2074 .prcm = {
2075 .omap4 = {
2076 .clkctrl_offs = DRA7XX_CM_IPU1_IPU1_CLKCTRL_OFFSET,
2077 .rstctrl_offs = DRA7XX_RM_IPU1_RSTCTRL_OFFSET,
2078 .context_offs = DRA7XX_RM_IPU1_IPU1_CONTEXT_OFFSET,
2079 .modulemode = MODULEMODE_HWCTRL,
2080 },
2081 },
2082 };
2084 /* mmu ipu2 */
2085 static struct omap_hwmod dra7xx_mmu_ipu2_hwmod = {
2086 .name = "mmu_ipu2",
2087 .class = &dra7xx_mmu_hwmod_class,
2088 .clkdm_name = "ipu2_clkdm",
2089 .rst_lines = dra7xx_mmu_ipu_resets,
2090 .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_ipu_resets),
2091 .main_clk = "dpll_core_h22x2_ck",
2092 .prcm = {
2093 .omap4 = {
2094 .clkctrl_offs = DRA7XX_CM_IPU2_IPU2_CLKCTRL_OFFSET,
2095 .rstctrl_offs = DRA7XX_RM_IPU2_RSTCTRL_OFFSET,
2096 .context_offs = DRA7XX_RM_IPU2_IPU2_CONTEXT_OFFSET,
2097 .modulemode = MODULEMODE_HWCTRL,
2098 },
2099 },
2100 };
2102 /*
2103 * 'mpu' class
2104 *
2105 */
2107 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
2108 .name = "mpu",
2109 };
2111 /* mpu */
2112 static struct omap_hwmod dra7xx_mpu_hwmod = {
2113 .name = "mpu",
2114 .class = &dra7xx_mpu_hwmod_class,
2115 .clkdm_name = "mpu_clkdm",
2116 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2117 .main_clk = "dpll_mpu_m2_ck",
2118 .prcm = {
2119 .omap4 = {
2120 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
2121 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
2122 },
2123 },
2124 };
2126 /*
2127 * 'ocp2scp' class
2128 *
2129 */
2131 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
2132 .rev_offs = 0x0000,
2133 .sysc_offs = 0x0010,
2134 .syss_offs = 0x0014,
2135 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2136 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2137 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2138 SIDLE_SMART_WKUP),
2139 .sysc_fields = &omap_hwmod_sysc_type1,
2140 };
2142 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
2143 .name = "ocp2scp",
2144 .sysc = &dra7xx_ocp2scp_sysc,
2145 };
2147 /* ocp2scp1 */
2148 static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
2149 .name = "ocp2scp1",
2150 .class = &dra7xx_ocp2scp_hwmod_class,
2151 .clkdm_name = "l3init_clkdm",
2152 .main_clk = "l4_root_clk_div",
2153 .prcm = {
2154 .omap4 = {
2155 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
2156 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
2157 .modulemode = MODULEMODE_HWCTRL,
2158 },
2159 },
2160 };
2162 /* ocp2scp3 */
2163 static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
2164 .name = "ocp2scp3",
2165 .class = &dra7xx_ocp2scp_hwmod_class,
2166 .clkdm_name = "l3init_clkdm",
2167 .main_clk = "l4_root_clk_div",
2168 .prcm = {
2169 .omap4 = {
2170 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
2171 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
2172 .modulemode = MODULEMODE_HWCTRL,
2173 },
2174 },
2175 };
2177 /*
2178 * 'PCIE' class
2179 *
2180 */
2182 static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
2183 .name = "pcie",
2184 };
2186 /* pcie1 */
2187 static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = {
2188 { .name = "pcie", .rst_shift = 0 },
2189 };
2191 static struct omap_hwmod dra7xx_pciess1_hwmod = {
2192 .name = "pcie1",
2193 .class = &dra7xx_pciess_hwmod_class,
2194 .clkdm_name = "pcie_clkdm",
2195 .rst_lines = dra7xx_pciess1_resets,
2196 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess1_resets),
2197 .main_clk = "l4_root_clk_div",
2198 .prcm = {
2199 .omap4 = {
2200 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
2201 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
2202 .rstctrl_offs = DRA7XX_RM_L3INIT_RSTCTRL_OFFSET,
2203 .modulemode = MODULEMODE_SWCTRL,
2204 },
2205 },
2206 };
2208 /* pcie2 */
2209 static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = {
2210 { .name = "pcie", .rst_shift = 1 },
2211 };
2213 static struct omap_hwmod dra7xx_pciess2_hwmod = {
2214 .name = "pcie2",
2215 .class = &dra7xx_pciess_hwmod_class,
2216 .clkdm_name = "pcie_clkdm",
2217 .rst_lines = dra7xx_pciess2_resets,
2218 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess2_resets),
2219 .main_clk = "l4_root_clk_div",
2220 .prcm = {
2221 .omap4 = {
2222 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
2223 .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
2224 .rstctrl_offs = DRA7XX_RM_L3INIT_RSTCTRL_OFFSET,
2225 .modulemode = MODULEMODE_SWCTRL,
2226 },
2227 },
2228 };
2230 /*
2231 * 'pru-icss' class
2232 * Programmable Real-Time Unit and Industrial Communication Subsystem
2233 */
2234 static struct omap_hwmod_class dra7xx_pruss_hwmod_class = {
2235 .name = "pruss",
2236 };
2238 /* pru-icss1 */
2239 static struct omap_hwmod dra7xx_pruss1_hwmod = {
2240 .name = "pruss1",
2241 .class = &dra7xx_pruss_hwmod_class,
2242 .clkdm_name = "l4per2_clkdm",
2243 .prcm = {
2244 .omap4 = {
2245 .clkctrl_offs = DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL_OFFSET,
2246 .context_offs = DRA7XX_RM_L4PER2_PRUSS1_CONTEXT_OFFSET,
2247 .modulemode = MODULEMODE_SWCTRL,
2248 },
2249 },
2250 };
2252 /* pru-icss2 */
2253 static struct omap_hwmod dra7xx_pruss2_hwmod = {
2254 .name = "pruss2",
2255 .class = &dra7xx_pruss_hwmod_class,
2256 .clkdm_name = "l4per2_clkdm",
2257 .prcm = {
2258 .omap4 = {
2259 .clkctrl_offs = DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL_OFFSET,
2260 .context_offs = DRA7XX_RM_L4PER2_PRUSS2_CONTEXT_OFFSET,
2261 .modulemode = MODULEMODE_SWCTRL,
2262 },
2263 },
2264 };
2266 /*
2267 * 'qspi' class
2268 *
2269 */
2271 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
2272 .sysc_offs = 0x0010,
2273 .sysc_flags = SYSC_HAS_SIDLEMODE,
2274 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2275 SIDLE_SMART_WKUP),
2276 .sysc_fields = &omap_hwmod_sysc_type2,
2277 };
2279 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
2280 .name = "qspi",
2281 .sysc = &dra7xx_qspi_sysc,
2282 };
2284 /* qspi */
2285 static struct omap_hwmod dra7xx_qspi_hwmod = {
2286 .name = "qspi",
2287 .class = &dra7xx_qspi_hwmod_class,
2288 .clkdm_name = "l4per2_clkdm",
2289 .main_clk = "qspi_gfclk_div",
2290 .prcm = {
2291 .omap4 = {
2292 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
2293 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
2294 .modulemode = MODULEMODE_SWCTRL,
2295 },
2296 },
2297 };
2299 /*
2300 * 'rtcss' class
2301 *
2302 */
2303 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
2304 .sysc_offs = 0x0078,
2305 .sysc_flags = SYSC_HAS_SIDLEMODE,
2306 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2307 SIDLE_SMART_WKUP),
2308 .sysc_fields = &omap_hwmod_sysc_type3,
2309 };
2311 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
2312 .name = "rtcss",
2313 .sysc = &dra7xx_rtcss_sysc,
2314 .reset = &omap_hwmod_rtc_unlock,
2315 };
2317 /* rtcss */
2318 static struct omap_hwmod dra7xx_rtcss_hwmod = {
2319 .name = "rtcss",
2320 .class = &dra7xx_rtcss_hwmod_class,
2321 .clkdm_name = "rtc_clkdm",
2322 .main_clk = "sys_32k_ck",
2323 .prcm = {
2324 .omap4 = {
2325 .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
2326 .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
2327 .modulemode = MODULEMODE_SWCTRL,
2328 },
2329 },
2330 };
2332 /*
2333 * 'sata' class
2334 *
2335 */
2337 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
2338 .sysc_offs = 0x0000,
2339 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
2340 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2341 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2342 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2343 .sysc_fields = &omap_hwmod_sysc_type2,
2344 };
2346 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
2347 .name = "sata",
2348 .sysc = &dra7xx_sata_sysc,
2349 };
2351 /* sata */
2353 static struct omap_hwmod dra7xx_sata_hwmod = {
2354 .name = "sata",
2355 .class = &dra7xx_sata_hwmod_class,
2356 .clkdm_name = "l3init_clkdm",
2357 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2358 .main_clk = "func_48m_fclk",
2359 .mpu_rt_idx = 1,
2360 .prcm = {
2361 .omap4 = {
2362 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
2363 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
2364 .modulemode = MODULEMODE_SWCTRL,
2365 },
2366 },
2367 };
2369 /*
2370 * 'smartreflex' class
2371 *
2372 */
2374 /* The IP is not compliant to type1 / type2 scheme */
2375 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2376 .sidle_shift = 24,
2377 .enwkup_shift = 26,
2378 };
2380 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
2381 .sysc_offs = 0x0038,
2382 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2383 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2384 SIDLE_SMART_WKUP),
2385 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
2386 };
2388 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
2389 .name = "smartreflex",
2390 .sysc = &dra7xx_smartreflex_sysc,
2391 .rev = 2,
2392 };
2394 /* smartreflex_core */
2395 /* smartreflex_core dev_attr */
2396 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2397 .sensor_voltdm_name = "core",
2398 };
2400 static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
2401 .name = "smartreflex_core",
2402 .class = &dra7xx_smartreflex_hwmod_class,
2403 .clkdm_name = "coreaon_clkdm",
2404 .main_clk = "wkupaon_iclk_mux",
2405 .prcm = {
2406 .omap4 = {
2407 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
2408 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
2409 .modulemode = MODULEMODE_SWCTRL,
2410 },
2411 },
2412 .dev_attr = &smartreflex_core_dev_attr,
2413 };
2415 /* smartreflex_mpu */
2416 /* smartreflex_mpu dev_attr */
2417 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2418 .sensor_voltdm_name = "mpu",
2419 };
2421 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
2422 .name = "smartreflex_mpu",
2423 .class = &dra7xx_smartreflex_hwmod_class,
2424 .clkdm_name = "coreaon_clkdm",
2425 .main_clk = "wkupaon_iclk_mux",
2426 .prcm = {
2427 .omap4 = {
2428 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
2429 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
2430 .modulemode = MODULEMODE_SWCTRL,
2431 },
2432 },
2433 .dev_attr = &smartreflex_mpu_dev_attr,
2434 };
2436 /*
2437 * 'spinlock' class
2438 *
2439 */
2441 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
2442 .rev_offs = 0x0000,
2443 .sysc_offs = 0x0010,
2444 .syss_offs = 0x0014,
2445 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2446 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2447 SYSS_HAS_RESET_STATUS),
2448 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2449 .sysc_fields = &omap_hwmod_sysc_type1,
2450 };
2452 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
2453 .name = "spinlock",
2454 .sysc = &dra7xx_spinlock_sysc,
2455 };
2457 /* spinlock */
2458 static struct omap_hwmod dra7xx_spinlock_hwmod = {
2459 .name = "spinlock",
2460 .class = &dra7xx_spinlock_hwmod_class,
2461 .clkdm_name = "l4cfg_clkdm",
2462 .main_clk = "l3_iclk_div",
2463 .prcm = {
2464 .omap4 = {
2465 .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
2466 .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
2467 },
2468 },
2469 };
2471 /*
2472 * 'timer' class
2473 *
2474 * This class contains several variants: ['timer_1ms', 'timer_secure',
2475 * 'timer']
2476 */
2478 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
2479 .rev_offs = 0x0000,
2480 .sysc_offs = 0x0010,
2481 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2482 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2483 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2484 SIDLE_SMART_WKUP),
2485 .sysc_fields = &omap_hwmod_sysc_type2,
2486 };
2488 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
2489 .name = "timer",
2490 .sysc = &dra7xx_timer_1ms_sysc,
2491 };
2493 static struct omap_hwmod_class_sysconfig dra7xx_timer_secure_sysc = {
2494 .rev_offs = 0x0000,
2495 .sysc_offs = 0x0010,
2496 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2497 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2498 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2499 SIDLE_SMART_WKUP),
2500 .sysc_fields = &omap_hwmod_sysc_type2,
2501 };
2503 static struct omap_hwmod_class dra7xx_timer_secure_hwmod_class = {
2504 .name = "timer",
2505 .sysc = &dra7xx_timer_secure_sysc,
2506 };
2508 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
2509 .rev_offs = 0x0000,
2510 .sysc_offs = 0x0010,
2511 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2512 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2513 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2514 SIDLE_SMART_WKUP),
2515 .sysc_fields = &omap_hwmod_sysc_type2,
2516 };
2518 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
2519 .name = "timer",
2520 .sysc = &dra7xx_timer_sysc,
2521 };
2523 /* timer1 */
2524 static struct omap_hwmod dra7xx_timer1_hwmod = {
2525 .name = "timer1",
2526 .class = &dra7xx_timer_1ms_hwmod_class,
2527 .clkdm_name = "wkupaon_clkdm",
2528 .main_clk = "timer1_gfclk_mux",
2529 .prcm = {
2530 .omap4 = {
2531 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
2532 .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
2533 .modulemode = MODULEMODE_SWCTRL,
2534 },
2535 },
2536 };
2538 /* timer2 */
2539 static struct omap_hwmod dra7xx_timer2_hwmod = {
2540 .name = "timer2",
2541 .class = &dra7xx_timer_1ms_hwmod_class,
2542 .clkdm_name = "l4per_clkdm",
2543 .main_clk = "timer2_gfclk_mux",
2544 .prcm = {
2545 .omap4 = {
2546 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
2547 .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
2548 .modulemode = MODULEMODE_SWCTRL,
2549 },
2550 },
2551 };
2553 /* timer3 */
2554 static struct omap_hwmod dra7xx_timer3_hwmod = {
2555 .name = "timer3",
2556 .class = &dra7xx_timer_hwmod_class,
2557 .clkdm_name = "l4per_clkdm",
2558 .main_clk = "timer3_gfclk_mux",
2559 .prcm = {
2560 .omap4 = {
2561 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
2562 .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
2563 .modulemode = MODULEMODE_SWCTRL,
2564 },
2565 },
2566 };
2568 /* timer4 */
2569 static struct omap_hwmod dra7xx_timer4_hwmod = {
2570 .name = "timer4",
2571 .class = &dra7xx_timer_hwmod_class,
2572 .clkdm_name = "l4per_clkdm",
2573 .main_clk = "timer4_gfclk_mux",
2574 .prcm = {
2575 .omap4 = {
2576 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
2577 .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
2578 .modulemode = MODULEMODE_SWCTRL,
2579 },
2580 },
2581 };
2583 /* timer5 */
2584 static struct omap_hwmod dra7xx_timer5_hwmod = {
2585 .name = "timer5",
2586 .class = &dra7xx_timer_hwmod_class,
2587 .clkdm_name = "ipu_clkdm",
2588 .main_clk = "timer5_gfclk_mux",
2589 .prcm = {
2590 .omap4 = {
2591 .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
2592 .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
2593 .modulemode = MODULEMODE_SWCTRL,
2594 },
2595 },
2596 };
2598 /* timer6 */
2599 static struct omap_hwmod dra7xx_timer6_hwmod = {
2600 .name = "timer6",
2601 .class = &dra7xx_timer_hwmod_class,
2602 .clkdm_name = "ipu_clkdm",
2603 .main_clk = "timer6_gfclk_mux",
2604 .prcm = {
2605 .omap4 = {
2606 .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
2607 .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
2608 .modulemode = MODULEMODE_SWCTRL,
2609 },
2610 },
2611 };
2613 /* timer7 */
2614 static struct omap_hwmod dra7xx_timer7_hwmod = {
2615 .name = "timer7",
2616 .class = &dra7xx_timer_hwmod_class,
2617 .clkdm_name = "ipu_clkdm",
2618 .main_clk = "timer7_gfclk_mux",
2619 .prcm = {
2620 .omap4 = {
2621 .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
2622 .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
2623 .modulemode = MODULEMODE_SWCTRL,
2624 },
2625 },
2626 };
2628 /* timer8 */
2629 static struct omap_hwmod dra7xx_timer8_hwmod = {
2630 .name = "timer8",
2631 .class = &dra7xx_timer_hwmod_class,
2632 .clkdm_name = "ipu_clkdm",
2633 .main_clk = "timer8_gfclk_mux",
2634 .prcm = {
2635 .omap4 = {
2636 .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
2637 .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
2638 .modulemode = MODULEMODE_SWCTRL,
2639 },
2640 },
2641 };
2643 /* timer9 */
2644 static struct omap_hwmod dra7xx_timer9_hwmod = {
2645 .name = "timer9",
2646 .class = &dra7xx_timer_hwmod_class,
2647 .clkdm_name = "l4per_clkdm",
2648 .main_clk = "timer9_gfclk_mux",
2649 .prcm = {
2650 .omap4 = {
2651 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
2652 .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
2653 .modulemode = MODULEMODE_SWCTRL,
2654 },
2655 },
2656 };
2658 /* timer10 */
2659 static struct omap_hwmod dra7xx_timer10_hwmod = {
2660 .name = "timer10",
2661 .class = &dra7xx_timer_1ms_hwmod_class,
2662 .clkdm_name = "l4per_clkdm",
2663 .main_clk = "timer10_gfclk_mux",
2664 .prcm = {
2665 .omap4 = {
2666 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
2667 .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
2668 .modulemode = MODULEMODE_SWCTRL,
2669 },
2670 },
2671 };
2673 /* timer11 */
2674 static struct omap_hwmod dra7xx_timer11_hwmod = {
2675 .name = "timer11",
2676 .class = &dra7xx_timer_hwmod_class,
2677 .clkdm_name = "l4per_clkdm",
2678 .main_clk = "timer11_gfclk_mux",
2679 .prcm = {
2680 .omap4 = {
2681 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
2682 .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
2683 .modulemode = MODULEMODE_SWCTRL,
2684 },
2685 },
2686 };
2688 /* timer12 */
2689 static struct omap_hwmod dra7xx_timer12_hwmod = {
2690 .name = "timer12",
2691 .class = &dra7xx_timer_secure_hwmod_class,
2692 .clkdm_name = "wkupaon_clkdm",
2693 .main_clk = "secure_32k_clk_src_ck",
2694 .prcm = {
2695 .omap4 = {
2696 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET,
2697 .context_offs = DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET,
2698 },
2699 },
2700 };
2702 /* timer13 */
2703 static struct omap_hwmod dra7xx_timer13_hwmod = {
2704 .name = "timer13",
2705 .class = &dra7xx_timer_hwmod_class,
2706 .clkdm_name = "l4per3_clkdm",
2707 .main_clk = "timer13_gfclk_mux",
2708 .prcm = {
2709 .omap4 = {
2710 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
2711 .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
2712 .modulemode = MODULEMODE_SWCTRL,
2713 },
2714 },
2715 };
2717 /* timer14 */
2718 static struct omap_hwmod dra7xx_timer14_hwmod = {
2719 .name = "timer14",
2720 .class = &dra7xx_timer_hwmod_class,
2721 .clkdm_name = "l4per3_clkdm",
2722 .main_clk = "timer14_gfclk_mux",
2723 .prcm = {
2724 .omap4 = {
2725 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
2726 .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
2727 .modulemode = MODULEMODE_SWCTRL,
2728 },
2729 },
2730 };
2732 /* timer15 */
2733 static struct omap_hwmod dra7xx_timer15_hwmod = {
2734 .name = "timer15",
2735 .class = &dra7xx_timer_hwmod_class,
2736 .clkdm_name = "l4per3_clkdm",
2737 .main_clk = "timer15_gfclk_mux",
2738 .prcm = {
2739 .omap4 = {
2740 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
2741 .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
2742 .modulemode = MODULEMODE_SWCTRL,
2743 },
2744 },
2745 };
2747 /* timer16 */
2748 static struct omap_hwmod dra7xx_timer16_hwmod = {
2749 .name = "timer16",
2750 .class = &dra7xx_timer_hwmod_class,
2751 .clkdm_name = "l4per3_clkdm",
2752 .main_clk = "timer16_gfclk_mux",
2753 .prcm = {
2754 .omap4 = {
2755 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
2756 .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
2757 .modulemode = MODULEMODE_SWCTRL,
2758 },
2759 },
2760 };
2762 /*
2763 * 'uart' class
2764 *
2765 */
2767 static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
2768 .rev_offs = 0x0050,
2769 .sysc_offs = 0x0054,
2770 .syss_offs = 0x0058,
2771 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2772 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2773 SYSS_HAS_RESET_STATUS),
2774 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2775 SIDLE_SMART_WKUP),
2776 .sysc_fields = &omap_hwmod_sysc_type1,
2777 };
2779 static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
2780 .name = "uart",
2781 .sysc = &dra7xx_uart_sysc,
2782 };
2784 /* uart1 */
2785 static struct omap_hwmod dra7xx_uart1_hwmod = {
2786 .name = "uart1",
2787 .class = &dra7xx_uart_hwmod_class,
2788 .clkdm_name = "l4per_clkdm",
2789 .main_clk = "uart1_gfclk_mux",
2790 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
2791 .prcm = {
2792 .omap4 = {
2793 .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
2794 .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
2795 .modulemode = MODULEMODE_SWCTRL,
2796 },
2797 },
2798 };
2800 /* uart2 */
2801 static struct omap_hwmod dra7xx_uart2_hwmod = {
2802 .name = "uart2",
2803 .class = &dra7xx_uart_hwmod_class,
2804 .clkdm_name = "l4per_clkdm",
2805 .main_clk = "uart2_gfclk_mux",
2806 .flags = HWMOD_SWSUP_SIDLE_ACT,
2807 .prcm = {
2808 .omap4 = {
2809 .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
2810 .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
2811 .modulemode = MODULEMODE_SWCTRL,
2812 },
2813 },
2814 };
2816 /* uart3 */
2817 static struct omap_hwmod dra7xx_uart3_hwmod = {
2818 .name = "uart3",
2819 .class = &dra7xx_uart_hwmod_class,
2820 .clkdm_name = "l4per_clkdm",
2821 .main_clk = "uart3_gfclk_mux",
2822 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART3_FLAGS,
2823 .prcm = {
2824 .omap4 = {
2825 .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
2826 .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
2827 .modulemode = MODULEMODE_SWCTRL,
2828 },
2829 },
2830 };
2832 /* uart4 */
2833 static struct omap_hwmod dra7xx_uart4_hwmod = {
2834 .name = "uart4",
2835 .class = &dra7xx_uart_hwmod_class,
2836 .clkdm_name = "l4per_clkdm",
2837 .main_clk = "uart4_gfclk_mux",
2838 .flags = HWMOD_SWSUP_SIDLE_ACT,
2839 .prcm = {
2840 .omap4 = {
2841 .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
2842 .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
2843 .modulemode = MODULEMODE_SWCTRL,
2844 },
2845 },
2846 };
2848 /* uart5 */
2849 static struct omap_hwmod dra7xx_uart5_hwmod = {
2850 .name = "uart5",
2851 .class = &dra7xx_uart_hwmod_class,
2852 .clkdm_name = "l4per_clkdm",
2853 .main_clk = "uart5_gfclk_mux",
2854 .flags = HWMOD_SWSUP_SIDLE_ACT,
2855 .prcm = {
2856 .omap4 = {
2857 .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
2858 .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
2859 .modulemode = MODULEMODE_SWCTRL,
2860 },
2861 },
2862 };
2864 /* uart6 */
2865 static struct omap_hwmod dra7xx_uart6_hwmod = {
2866 .name = "uart6",
2867 .class = &dra7xx_uart_hwmod_class,
2868 .clkdm_name = "ipu_clkdm",
2869 .main_clk = "uart6_gfclk_mux",
2870 .flags = HWMOD_SWSUP_SIDLE_ACT,
2871 .prcm = {
2872 .omap4 = {
2873 .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
2874 .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
2875 .modulemode = MODULEMODE_SWCTRL,
2876 },
2877 },
2878 };
2880 /* uart7 */
2881 static struct omap_hwmod dra7xx_uart7_hwmod = {
2882 .name = "uart7",
2883 .class = &dra7xx_uart_hwmod_class,
2884 .clkdm_name = "l4per2_clkdm",
2885 .main_clk = "uart7_gfclk_mux",
2886 .flags = HWMOD_SWSUP_SIDLE_ACT,
2887 .prcm = {
2888 .omap4 = {
2889 .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
2890 .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
2891 .modulemode = MODULEMODE_SWCTRL,
2892 },
2893 },
2894 };
2896 /* uart8 */
2897 static struct omap_hwmod dra7xx_uart8_hwmod = {
2898 .name = "uart8",
2899 .class = &dra7xx_uart_hwmod_class,
2900 .clkdm_name = "l4per2_clkdm",
2901 .main_clk = "uart8_gfclk_mux",
2902 .flags = HWMOD_SWSUP_SIDLE_ACT,
2903 .prcm = {
2904 .omap4 = {
2905 .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
2906 .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
2907 .modulemode = MODULEMODE_SWCTRL,
2908 },
2909 },
2910 };
2912 /* uart9 */
2913 static struct omap_hwmod dra7xx_uart9_hwmod = {
2914 .name = "uart9",
2915 .class = &dra7xx_uart_hwmod_class,
2916 .clkdm_name = "l4per2_clkdm",
2917 .main_clk = "uart9_gfclk_mux",
2918 .flags = HWMOD_SWSUP_SIDLE_ACT,
2919 .prcm = {
2920 .omap4 = {
2921 .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
2922 .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
2923 .modulemode = MODULEMODE_SWCTRL,
2924 },
2925 },
2926 };
2928 /* uart10 */
2929 static struct omap_hwmod dra7xx_uart10_hwmod = {
2930 .name = "uart10",
2931 .class = &dra7xx_uart_hwmod_class,
2932 .clkdm_name = "wkupaon_clkdm",
2933 .main_clk = "uart10_gfclk_mux",
2934 .flags = HWMOD_SWSUP_SIDLE_ACT,
2935 .prcm = {
2936 .omap4 = {
2937 .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
2938 .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
2939 .modulemode = MODULEMODE_SWCTRL,
2940 },
2941 },
2942 };
2944 /* DES (the 'P' (public) device) */
2945 static struct omap_hwmod_class_sysconfig dra7xx_des_sysc = {
2946 .rev_offs = 0x0030,
2947 .sysc_offs = 0x0034,
2948 .syss_offs = 0x0038,
2949 .sysc_flags = SYSS_HAS_RESET_STATUS,
2950 };
2952 static struct omap_hwmod_class dra7xx_des_hwmod_class = {
2953 .name = "des",
2954 .sysc = &dra7xx_des_sysc,
2955 };
2957 /* DES */
2958 static struct omap_hwmod dra7xx_des_hwmod = {
2959 .name = "des",
2960 .class = &dra7xx_des_hwmod_class,
2961 .clkdm_name = "l4sec_clkdm",
2962 .main_clk = "l3_iclk_div",
2963 .prcm = {
2964 .omap4 = {
2965 .clkctrl_offs = DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
2966 .context_offs = DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
2967 .modulemode = MODULEMODE_HWCTRL,
2968 },
2969 },
2970 };
2972 /* rng */
2973 static struct omap_hwmod_class_sysconfig dra7xx_rng_sysc = {
2974 .rev_offs = 0x1fe0,
2975 .sysc_offs = 0x1fe4,
2976 .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
2977 .idlemodes = SIDLE_FORCE | SIDLE_NO,
2978 .sysc_fields = &omap_hwmod_sysc_type1,
2979 };
2981 static struct omap_hwmod_class dra7xx_rng_hwmod_class = {
2982 .name = "rng",
2983 .sysc = &dra7xx_rng_sysc,
2984 };
2986 static struct omap_hwmod dra7xx_rng_hwmod = {
2987 .name = "rng",
2988 .class = &dra7xx_rng_hwmod_class,
2989 .flags = HWMOD_SWSUP_SIDLE,
2990 .clkdm_name = "l4sec_clkdm",
2991 .prcm = {
2992 .omap4 = {
2993 .clkctrl_offs = DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET,
2994 .context_offs = DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET,
2995 .modulemode = MODULEMODE_HWCTRL,
2996 },
2997 },
2998 };
3000 /*
3001 * 'usb_otg_ss' class
3002 *
3003 */
3005 static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
3006 .rev_offs = 0x0000,
3007 .sysc_offs = 0x0010,
3008 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
3009 SYSC_HAS_SIDLEMODE),
3010 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3011 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3012 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3013 .sysc_fields = &omap_hwmod_sysc_type2,
3014 };
3016 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
3017 .name = "usb_otg_ss",
3018 .sysc = &dra7xx_usb_otg_ss_sysc,
3019 };
3021 /* usb_otg_ss1 */
3022 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
3023 { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
3024 };
3026 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
3027 .name = "usb_otg_ss1",
3028 .class = &dra7xx_usb_otg_ss_hwmod_class,
3029 .clkdm_name = "l3init_clkdm",
3030 .main_clk = "dpll_core_h13x2_ck",
3031 .prcm = {
3032 .omap4 = {
3033 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
3034 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
3035 .modulemode = MODULEMODE_HWCTRL,
3036 },
3037 },
3038 .opt_clks = usb_otg_ss1_opt_clks,
3039 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
3040 };
3042 /* usb_otg_ss2 */
3043 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
3044 { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
3045 };
3047 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
3048 .name = "usb_otg_ss2",
3049 .class = &dra7xx_usb_otg_ss_hwmod_class,
3050 .clkdm_name = "l3init_clkdm",
3051 .main_clk = "dpll_core_h13x2_ck",
3052 .prcm = {
3053 .omap4 = {
3054 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
3055 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
3056 .modulemode = MODULEMODE_HWCTRL,
3057 },
3058 },
3059 .opt_clks = usb_otg_ss2_opt_clks,
3060 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
3061 };
3063 /* usb_otg_ss3 */
3064 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
3065 .name = "usb_otg_ss3",
3066 .class = &dra7xx_usb_otg_ss_hwmod_class,
3067 .clkdm_name = "l3init_clkdm",
3068 .main_clk = "dpll_core_h13x2_ck",
3069 .prcm = {
3070 .omap4 = {
3071 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
3072 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
3073 .modulemode = MODULEMODE_HWCTRL,
3074 },
3075 },
3076 };
3078 /* usb_otg_ss4 */
3079 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
3080 .name = "usb_otg_ss4",
3081 .class = &dra7xx_usb_otg_ss_hwmod_class,
3082 .clkdm_name = "l3init_clkdm",
3083 .main_clk = "dpll_core_h13x2_ck",
3084 .prcm = {
3085 .omap4 = {
3086 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
3087 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
3088 .modulemode = MODULEMODE_HWCTRL,
3089 },
3090 },
3091 };
3093 /*
3094 * 'vcp' class
3095 *
3096 */
3098 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
3099 .name = "vcp",
3100 };
3102 /* vcp1 */
3103 static struct omap_hwmod dra7xx_vcp1_hwmod = {
3104 .name = "vcp1",
3105 .class = &dra7xx_vcp_hwmod_class,
3106 .clkdm_name = "l3main1_clkdm",
3107 .main_clk = "l3_iclk_div",
3108 .prcm = {
3109 .omap4 = {
3110 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
3111 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
3112 },
3113 },
3114 };
3116 /* vcp2 */
3117 static struct omap_hwmod dra7xx_vcp2_hwmod = {
3118 .name = "vcp2",
3119 .class = &dra7xx_vcp_hwmod_class,
3120 .clkdm_name = "l3main1_clkdm",
3121 .main_clk = "l3_iclk_div",
3122 .prcm = {
3123 .omap4 = {
3124 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
3125 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
3126 },
3127 },
3128 };
3130 /*
3131 * 'wd_timer' class
3132 *
3133 */
3135 static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
3136 .rev_offs = 0x0000,
3137 .sysc_offs = 0x0010,
3138 .syss_offs = 0x0014,
3139 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3140 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3141 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3142 SIDLE_SMART_WKUP),
3143 .sysc_fields = &omap_hwmod_sysc_type1,
3144 };
3146 static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
3147 .name = "wd_timer",
3148 .sysc = &dra7xx_wd_timer_sysc,
3149 .pre_shutdown = &omap2_wd_timer_disable,
3150 .reset = &omap2_wd_timer_reset,
3151 };
3153 /* wd_timer2 */
3154 static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
3155 .name = "wd_timer2",
3156 .class = &dra7xx_wd_timer_hwmod_class,
3157 .clkdm_name = "wkupaon_clkdm",
3158 .main_clk = "sys_32k_ck",
3159 .prcm = {
3160 .omap4 = {
3161 .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
3162 .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
3163 .modulemode = MODULEMODE_SWCTRL,
3164 },
3165 },
3166 };
3169 /*
3170 * Interfaces
3171 */
3173 /* l3_main_2 -> l3_instr */
3174 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
3175 .master = &dra7xx_l3_main_2_hwmod,
3176 .slave = &dra7xx_l3_instr_hwmod,
3177 .clk = "l3_iclk_div",
3178 .user = OCP_USER_MPU | OCP_USER_SDMA,
3179 };
3181 /* l4_cfg -> l3_main_1 */
3182 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
3183 .master = &dra7xx_l4_cfg_hwmod,
3184 .slave = &dra7xx_l3_main_1_hwmod,
3185 .clk = "l3_iclk_div",
3186 .user = OCP_USER_MPU | OCP_USER_SDMA,
3187 };
3189 /*
3190 * Interfaces
3191 */
3193 static struct omap_hwmod_addr_space dra7xx_dmm_addrs[] = {
3194 {
3195 .pa_start = 0x4e000000,
3196 .pa_end = 0x4e0007ff,
3197 .flags = ADDR_TYPE_RT
3198 },
3199 { }
3200 };
3202 /* l3_main_1 -> dmm */
3203 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
3204 .master = &dra7xx_l3_main_1_hwmod,
3205 .slave = &dra7xx_dmm_hwmod,
3206 .clk = "l3_iclk_div",
3207 .addr = dra7xx_dmm_addrs,
3208 .user = OCP_USER_SDMA,
3209 };
3211 /* dmm -> emif_ocp_fw */
3212 static struct omap_hwmod_ocp_if dra7xx_dmm__emif_ocp_fw = {
3213 .master = &dra7xx_dmm_hwmod,
3214 .slave = &dra7xx_emif_ocp_fw_hwmod,
3215 .clk = "l3_iclk_div",
3216 .user = OCP_USER_MPU | OCP_USER_SDMA,
3217 };
3219 /* mpu -> l3_main_1 */
3220 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
3221 .master = &dra7xx_mpu_hwmod,
3222 .slave = &dra7xx_l3_main_1_hwmod,
3223 .clk = "l3_iclk_div",
3224 .user = OCP_USER_MPU,
3225 };
3227 /* l3_main_1 -> l3_main_2 */
3228 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
3229 .master = &dra7xx_l3_main_1_hwmod,
3230 .slave = &dra7xx_l3_main_2_hwmod,
3231 .clk = "l3_iclk_div",
3232 .user = OCP_USER_MPU,
3233 };
3235 /* l4_cfg -> l3_main_2 */
3236 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
3237 .master = &dra7xx_l4_cfg_hwmod,
3238 .slave = &dra7xx_l3_main_2_hwmod,
3239 .clk = "l3_iclk_div",
3240 .user = OCP_USER_MPU | OCP_USER_SDMA,
3241 };
3243 /* l3_main_1 -> l4_cfg */
3244 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
3245 .master = &dra7xx_l3_main_1_hwmod,
3246 .slave = &dra7xx_l4_cfg_hwmod,
3247 .clk = "l3_iclk_div",
3248 .user = OCP_USER_MPU | OCP_USER_SDMA,
3249 };
3251 /* l3_main_1 -> mmu0_dsp1 */
3252 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu0_dsp1 = {
3253 .master = &dra7xx_l3_main_1_hwmod,
3254 .slave = &dra7xx_mmu0_dsp1_hwmod,
3255 .clk = "l3_iclk_div",
3256 .user = OCP_USER_MPU | OCP_USER_SDMA,
3257 };
3259 /* l3_main_1 -> mmu1_dsp1 */
3260 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu1_dsp1 = {
3261 .master = &dra7xx_l3_main_1_hwmod,
3262 .slave = &dra7xx_mmu1_dsp1_hwmod,
3263 .clk = "l3_iclk_div",
3264 .user = OCP_USER_MPU | OCP_USER_SDMA,
3265 };
3267 /* l3_main_1 -> mmu0_dsp2 */
3268 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu0_dsp2 = {
3269 .master = &dra7xx_l3_main_1_hwmod,
3270 .slave = &dra7xx_mmu0_dsp2_hwmod,
3271 .clk = "l3_iclk_div",
3272 .user = OCP_USER_MPU | OCP_USER_SDMA,
3273 };
3275 /* l3_main_1 -> mmu1_dsp2 */
3276 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu1_dsp2 = {
3277 .master = &dra7xx_l3_main_1_hwmod,
3278 .slave = &dra7xx_mmu1_dsp2_hwmod,
3279 .clk = "l3_iclk_div",
3280 .user = OCP_USER_MPU | OCP_USER_SDMA,
3281 };
3283 /* l3_main_1 -> mmu_ipu1 */
3284 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu_ipu1 = {
3285 .master = &dra7xx_l3_main_1_hwmod,
3286 .slave = &dra7xx_mmu_ipu1_hwmod,
3287 .clk = "l3_iclk_div",
3288 .user = OCP_USER_MPU | OCP_USER_SDMA,
3289 };
3291 /* l3_main_1 -> mmu_ipu2 */
3292 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu_ipu2 = {
3293 .master = &dra7xx_l3_main_1_hwmod,
3294 .slave = &dra7xx_mmu_ipu2_hwmod,
3295 .clk = "l3_iclk_div",
3296 .user = OCP_USER_MPU | OCP_USER_SDMA,
3297 };
3299 /* l3_main_1 -> l4_per1 */
3300 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
3301 .master = &dra7xx_l3_main_1_hwmod,
3302 .slave = &dra7xx_l4_per1_hwmod,
3303 .clk = "l3_iclk_div",
3304 .user = OCP_USER_MPU | OCP_USER_SDMA,
3305 };
3307 /* l3_main_1 -> l4_per2 */
3308 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
3309 .master = &dra7xx_l3_main_1_hwmod,
3310 .slave = &dra7xx_l4_per2_hwmod,
3311 .clk = "l3_iclk_div",
3312 .user = OCP_USER_MPU | OCP_USER_SDMA,
3313 };
3315 /* l3_main_1 -> l4_per3 */
3316 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
3317 .master = &dra7xx_l3_main_1_hwmod,
3318 .slave = &dra7xx_l4_per3_hwmod,
3319 .clk = "l3_iclk_div",
3320 .user = OCP_USER_MPU | OCP_USER_SDMA,
3321 };
3323 /* l3_main_1 -> l4_wkup */
3324 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
3325 .master = &dra7xx_l3_main_1_hwmod,
3326 .slave = &dra7xx_l4_wkup_hwmod,
3327 .clk = "wkupaon_iclk_mux",
3328 .user = OCP_USER_MPU | OCP_USER_SDMA,
3329 };
3331 /* l4_per2 -> atl */
3332 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
3333 .master = &dra7xx_l4_per2_hwmod,
3334 .slave = &dra7xx_atl_hwmod,
3335 .clk = "l3_iclk_div",
3336 .user = OCP_USER_MPU | OCP_USER_SDMA,
3337 };
3339 /* l3_main_1 -> bb2d */
3340 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
3341 .master = &dra7xx_l3_main_1_hwmod,
3342 .slave = &dra7xx_bb2d_hwmod,
3343 .clk = "l3_iclk_div",
3344 .user = OCP_USER_MPU | OCP_USER_SDMA,
3345 };
3347 /* l4_wkup -> counter_32k */
3348 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
3349 .master = &dra7xx_l4_wkup_hwmod,
3350 .slave = &dra7xx_counter_32k_hwmod,
3351 .clk = "wkupaon_iclk_mux",
3352 .user = OCP_USER_MPU | OCP_USER_SDMA,
3353 };
3355 /* l4_wkup -> ctrl_module_wkup */
3356 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
3357 .master = &dra7xx_l4_wkup_hwmod,
3358 .slave = &dra7xx_ctrl_module_wkup_hwmod,
3359 .clk = "wkupaon_iclk_mux",
3360 .user = OCP_USER_MPU | OCP_USER_SDMA,
3361 };
3363 static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
3364 .master = &dra7xx_l4_per2_hwmod,
3365 .slave = &dra7xx_gmac_hwmod,
3366 .clk = "dpll_gmac_ck",
3367 .user = OCP_USER_MPU,
3368 };
3370 static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
3371 .master = &dra7xx_gmac_hwmod,
3372 .slave = &dra7xx_mdio_hwmod,
3373 .user = OCP_USER_MPU,
3374 };
3376 /* l4_wkup -> dcan1 */
3377 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
3378 .master = &dra7xx_l4_wkup_hwmod,
3379 .slave = &dra7xx_dcan1_hwmod,
3380 .clk = "wkupaon_iclk_mux",
3381 .user = OCP_USER_MPU | OCP_USER_SDMA,
3382 };
3384 /* l4_per2 -> dcan2 */
3385 static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
3386 .master = &dra7xx_l4_per2_hwmod,
3387 .slave = &dra7xx_dcan2_hwmod,
3388 .clk = "l3_iclk_div",
3389 .user = OCP_USER_MPU | OCP_USER_SDMA,
3390 };
3392 static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
3393 {
3394 .pa_start = 0x4a056000,
3395 .pa_end = 0x4a056fff,
3396 .flags = ADDR_TYPE_RT
3397 },
3398 { }
3399 };
3401 /* l4_cfg -> dma_system */
3402 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
3403 .master = &dra7xx_l4_cfg_hwmod,
3404 .slave = &dra7xx_dma_system_hwmod,
3405 .clk = "l3_iclk_div",
3406 .addr = dra7xx_dma_system_addrs,
3407 .user = OCP_USER_MPU | OCP_USER_SDMA,
3408 };
3410 /* dsp1 -> l3_main_1 */
3411 static struct omap_hwmod_ocp_if dra7xx_dsp1__l3_main_1 = {
3412 .master = &dra7xx_dsp1_hwmod,
3413 .slave = &dra7xx_l3_main_1_hwmod,
3414 .clk = "l3_iclk_div",
3415 .user = OCP_USER_MPU | OCP_USER_SDMA,
3416 };
3418 /* dsp2 -> l3_main_1 */
3419 static struct omap_hwmod_ocp_if dra7xx_dsp2__l3_main_1 = {
3420 .master = &dra7xx_dsp2_hwmod,
3421 .slave = &dra7xx_l3_main_1_hwmod,
3422 .clk = "l3_iclk_div",
3423 .user = OCP_USER_MPU | OCP_USER_SDMA,
3424 };
3426 static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
3427 {
3428 .name = "family",
3429 .pa_start = 0x58000000,
3430 .pa_end = 0x5800007f,
3431 .flags = ADDR_TYPE_RT
3432 },
3433 };
3435 /* l3_main_1 -> dss */
3436 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
3437 .master = &dra7xx_l3_main_1_hwmod,
3438 .slave = &dra7xx_dss_hwmod,
3439 .clk = "l3_iclk_div",
3440 .addr = dra7xx_dss_addrs,
3441 .user = OCP_USER_MPU | OCP_USER_SDMA,
3442 };
3444 static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = {
3445 {
3446 .name = "dispc",
3447 .pa_start = 0x58001000,
3448 .pa_end = 0x58001fff,
3449 .flags = ADDR_TYPE_RT
3450 },
3451 };
3453 /* l3_main_1 -> dispc */
3454 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
3455 .master = &dra7xx_l3_main_1_hwmod,
3456 .slave = &dra7xx_dss_dispc_hwmod,
3457 .clk = "l3_iclk_div",
3458 .addr = dra7xx_dss_dispc_addrs,
3459 .user = OCP_USER_MPU | OCP_USER_SDMA,
3460 };
3462 static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = {
3463 {
3464 .name = "hdmi_wp",
3465 .pa_start = 0x58040000,
3466 .pa_end = 0x580400ff,
3467 .flags = ADDR_TYPE_RT
3468 },
3469 { }
3470 };
3472 /* l3_main_1 -> dispc */
3473 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
3474 .master = &dra7xx_l3_main_1_hwmod,
3475 .slave = &dra7xx_dss_hdmi_hwmod,
3476 .clk = "l3_iclk_div",
3477 .addr = dra7xx_dss_hdmi_addrs,
3478 .user = OCP_USER_MPU | OCP_USER_SDMA,
3479 };
3481 /* l3_main_1 -> aes */
3482 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes = {
3483 .master = &dra7xx_l3_main_1_hwmod,
3484 .slave = &dra7xx_aes_hwmod,
3485 .clk = "l3_iclk_div",
3486 .user = OCP_USER_MPU | OCP_USER_SDMA,
3487 };
3489 /* l3_main_1 -> sha0 */
3490 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__sha0 = {
3491 .master = &dra7xx_l3_main_1_hwmod,
3492 .slave = &dra7xx_sha0_hwmod,
3493 .clk = "l3_iclk_div",
3494 .user = OCP_USER_MPU | OCP_USER_SDMA,
3495 };
3497 /* l4_per2 -> mcasp2 */
3498 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp2 = {
3499 .master = &dra7xx_l4_per2_hwmod,
3500 .slave = &dra7xx_mcasp2_hwmod,
3501 .clk = "l3_iclk_div",
3502 .user = OCP_USER_MPU,
3503 };
3505 /* l4_per2 -> mcasp3 */
3506 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = {
3507 .master = &dra7xx_l4_per2_hwmod,
3508 .slave = &dra7xx_mcasp3_hwmod,
3509 .clk = "l3_iclk_div",
3510 .user = OCP_USER_MPU | OCP_USER_SDMA,
3511 };
3513 /* l4_per2 -> mcasp6 */
3514 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = {
3515 .master = &dra7xx_l4_per2_hwmod,
3516 .slave = &dra7xx_mcasp6_hwmod,
3517 .clk = "l3_iclk_div",
3518 .user = OCP_USER_MPU | OCP_USER_SDMA,
3519 };
3521 static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = {
3522 {
3523 .pa_start = 0x48078000,
3524 .pa_end = 0x48078fff,
3525 .flags = ADDR_TYPE_RT
3526 },
3527 { }
3528 };
3530 /* l4_per1 -> elm */
3531 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
3532 .master = &dra7xx_l4_per1_hwmod,
3533 .slave = &dra7xx_elm_hwmod,
3534 .clk = "l3_iclk_div",
3535 .addr = dra7xx_elm_addrs,
3536 .user = OCP_USER_MPU | OCP_USER_SDMA,
3537 };
3539 /* l4_wkup -> gpio1 */
3540 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
3541 .master = &dra7xx_l4_wkup_hwmod,
3542 .slave = &dra7xx_gpio1_hwmod,
3543 .clk = "wkupaon_iclk_mux",
3544 .user = OCP_USER_MPU | OCP_USER_SDMA,
3545 };
3547 /* l4_per1 -> gpio2 */
3548 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
3549 .master = &dra7xx_l4_per1_hwmod,
3550 .slave = &dra7xx_gpio2_hwmod,
3551 .clk = "l3_iclk_div",
3552 .user = OCP_USER_MPU | OCP_USER_SDMA,
3553 };
3555 /* l4_per1 -> gpio3 */
3556 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
3557 .master = &dra7xx_l4_per1_hwmod,
3558 .slave = &dra7xx_gpio3_hwmod,
3559 .clk = "l3_iclk_div",
3560 .user = OCP_USER_MPU | OCP_USER_SDMA,
3561 };
3563 /* l4_per1 -> gpio4 */
3564 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
3565 .master = &dra7xx_l4_per1_hwmod,
3566 .slave = &dra7xx_gpio4_hwmod,
3567 .clk = "l3_iclk_div",
3568 .user = OCP_USER_MPU | OCP_USER_SDMA,
3569 };
3571 /* l4_per1 -> gpio5 */
3572 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
3573 .master = &dra7xx_l4_per1_hwmod,
3574 .slave = &dra7xx_gpio5_hwmod,
3575 .clk = "l3_iclk_div",
3576 .user = OCP_USER_MPU | OCP_USER_SDMA,
3577 };
3579 /* l4_per1 -> gpio6 */
3580 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
3581 .master = &dra7xx_l4_per1_hwmod,
3582 .slave = &dra7xx_gpio6_hwmod,
3583 .clk = "l3_iclk_div",
3584 .user = OCP_USER_MPU | OCP_USER_SDMA,
3585 };
3587 struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss0 = {
3588 .master = &dra7xx_l4_per2_hwmod,
3589 .slave = &dra7xx_epwmss0_hwmod,
3590 .clk = "l4_root_clk_div",
3591 .user = OCP_USER_MPU,
3592 };
3594 struct omap_hwmod_ocp_if dra7xx_epwmss0__ecap0 = {
3595 .master = &dra7xx_epwmss0_hwmod,
3596 .slave = &dra7xx_ecap0_hwmod,
3597 .clk = "l4_root_clk_div",
3598 .user = OCP_USER_MPU,
3599 };
3601 struct omap_hwmod_ocp_if dra7xx_epwmss0__eqep0 = {
3602 .master = &dra7xx_epwmss0_hwmod,
3603 .slave = &dra7xx_eqep0_hwmod,
3604 .clk = "l4_root_clk_div",
3605 .user = OCP_USER_MPU,
3606 };
3608 struct omap_hwmod_ocp_if dra7xx_epwmss0__ehrpwm0 = {
3609 .master = &dra7xx_epwmss0_hwmod,
3610 .slave = &dra7xx_ehrpwm0_hwmod,
3611 .clk = "l4_root_clk_div",
3612 .user = OCP_USER_MPU,
3613 };
3615 struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss1 = {
3616 .master = &dra7xx_l4_per2_hwmod,
3617 .slave = &dra7xx_epwmss1_hwmod,
3618 .clk = "l4_root_clk_div",
3619 .user = OCP_USER_MPU,
3620 };
3622 struct omap_hwmod_ocp_if dra7xx_epwmss1__ecap1 = {
3623 .master = &dra7xx_epwmss1_hwmod,
3624 .slave = &dra7xx_ecap1_hwmod,
3625 .clk = "l4_root_clk_div",
3626 .user = OCP_USER_MPU,
3627 };
3629 struct omap_hwmod_ocp_if dra7xx_epwmss1__eqep1 = {
3630 .master = &dra7xx_epwmss1_hwmod,
3631 .slave = &dra7xx_eqep1_hwmod,
3632 .clk = "l4_root_clk_div",
3633 .user = OCP_USER_MPU,
3634 };
3636 struct omap_hwmod_ocp_if dra7xx_epwmss1__ehrpwm1 = {
3637 .master = &dra7xx_epwmss1_hwmod,
3638 .slave = &dra7xx_ehrpwm1_hwmod,
3639 .clk = "l4_root_clk_div",
3640 .user = OCP_USER_MPU,
3641 };
3643 struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss2 = {
3644 .master = &dra7xx_l4_per2_hwmod,
3645 .slave = &dra7xx_epwmss2_hwmod,
3646 .clk = "l4_root_clk_div",
3647 .user = OCP_USER_MPU,
3648 };
3650 struct omap_hwmod_ocp_if dra7xx_epwmss2__ecap2 = {
3651 .master = &dra7xx_epwmss2_hwmod,
3652 .slave = &dra7xx_ecap2_hwmod,
3653 .clk = "l4_root_clk_div",
3654 .user = OCP_USER_MPU,
3655 };
3657 struct omap_hwmod_ocp_if dra7xx_epwmss2__eqep2 = {
3658 .master = &dra7xx_epwmss2_hwmod,
3659 .slave = &dra7xx_eqep2_hwmod,
3660 .clk = "l4_root_clk_div",
3661 .user = OCP_USER_MPU,
3662 };
3664 struct omap_hwmod_ocp_if dra7xx_epwmss2__ehrpwm2 = {
3665 .master = &dra7xx_epwmss2_hwmod,
3666 .slave = &dra7xx_ehrpwm2_hwmod,
3667 .clk = "l4_root_clk_div",
3668 .user = OCP_USER_MPU,
3669 };
3671 /* l4_per1 -> gpio7 */
3672 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
3673 .master = &dra7xx_l4_per1_hwmod,
3674 .slave = &dra7xx_gpio7_hwmod,
3675 .clk = "l3_iclk_div",
3676 .user = OCP_USER_MPU | OCP_USER_SDMA,
3677 };
3679 /* l4_per1 -> gpio8 */
3680 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
3681 .master = &dra7xx_l4_per1_hwmod,
3682 .slave = &dra7xx_gpio8_hwmod,
3683 .clk = "l3_iclk_div",
3684 .user = OCP_USER_MPU | OCP_USER_SDMA,
3685 };
3687 static struct omap_hwmod_addr_space dra7xx_gpmc_addrs[] = {
3688 {
3689 .pa_start = 0x50000000,
3690 .pa_end = 0x500003ff,
3691 .flags = ADDR_TYPE_RT
3692 },
3693 { }
3694 };
3696 /* l3_main_1 -> gpmc */
3697 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
3698 .master = &dra7xx_l3_main_1_hwmod,
3699 .slave = &dra7xx_gpmc_hwmod,
3700 .clk = "l3_iclk_div",
3701 .addr = dra7xx_gpmc_addrs,
3702 .user = OCP_USER_MPU | OCP_USER_SDMA,
3703 };
3705 static struct omap_hwmod_addr_space dra7xx_gpu_addrs[] = {
3706 {
3707 .name = "klio",
3708 .pa_start = 0x56000000,
3709 .pa_end = 0x56001fff,
3710 },
3711 {
3712 .name = "hydra2",
3713 .pa_start = 0x56004000,
3714 .pa_end = 0x56004fff,
3715 },
3716 {
3717 .name = "klio_0",
3718 .pa_start = 0x56008000,
3719 .pa_end = 0x56009fff,
3720 },
3721 {
3722 .name = "klio_1",
3723 .pa_start = 0x5600c000,
3724 .pa_end = 0x5600dfff,
3725 },
3726 {
3727 .name = "klio_hl",
3728 .pa_start = 0x5600fe00,
3729 .pa_end = 0x5600ffff,
3730 .flags = ADDR_TYPE_RT
3731 },
3732 { }
3733 };
3735 /* l3_main_1 -> gpu */
3736 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpu = {
3737 .master = &dra7xx_l3_main_1_hwmod,
3738 .slave = &dra7xx_gpu_hwmod,
3739 .clk = "l3_iclk_div",
3740 .addr = dra7xx_gpu_addrs,
3741 .user = OCP_USER_MPU | OCP_USER_SDMA,
3742 };
3744 static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
3745 {
3746 .pa_start = 0x480b2000,
3747 .pa_end = 0x480b201f,
3748 .flags = ADDR_TYPE_RT
3749 },
3750 { }
3751 };
3753 /* l4_per1 -> hdq1w */
3754 static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
3755 .master = &dra7xx_l4_per1_hwmod,
3756 .slave = &dra7xx_hdq1w_hwmod,
3757 .clk = "l3_iclk_div",
3758 .addr = dra7xx_hdq1w_addrs,
3759 .user = OCP_USER_MPU | OCP_USER_SDMA,
3760 };
3762 /* l4_per1 -> i2c1 */
3763 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
3764 .master = &dra7xx_l4_per1_hwmod,
3765 .slave = &dra7xx_i2c1_hwmod,
3766 .clk = "l3_iclk_div",
3767 .user = OCP_USER_MPU | OCP_USER_SDMA,
3768 };
3770 /* l4_per1 -> i2c2 */
3771 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
3772 .master = &dra7xx_l4_per1_hwmod,
3773 .slave = &dra7xx_i2c2_hwmod,
3774 .clk = "l3_iclk_div",
3775 .user = OCP_USER_MPU | OCP_USER_SDMA,
3776 };
3778 /* l4_per1 -> i2c3 */
3779 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
3780 .master = &dra7xx_l4_per1_hwmod,
3781 .slave = &dra7xx_i2c3_hwmod,
3782 .clk = "l3_iclk_div",
3783 .user = OCP_USER_MPU | OCP_USER_SDMA,
3784 };
3786 /* l4_per1 -> i2c4 */
3787 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
3788 .master = &dra7xx_l4_per1_hwmod,
3789 .slave = &dra7xx_i2c4_hwmod,
3790 .clk = "l3_iclk_div",
3791 .user = OCP_USER_MPU | OCP_USER_SDMA,
3792 };
3794 /* l4_per1 -> i2c5 */
3795 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
3796 .master = &dra7xx_l4_per1_hwmod,
3797 .slave = &dra7xx_i2c5_hwmod,
3798 .clk = "l3_iclk_div",
3799 .user = OCP_USER_MPU | OCP_USER_SDMA,
3800 };
3802 /* ipu1 -> l3_main_1 */
3803 static struct omap_hwmod_ocp_if dra7xx_ipu1__l3_main_1 = {
3804 .master = &dra7xx_ipu1_hwmod,
3805 .slave = &dra7xx_l3_main_1_hwmod,
3806 .clk = "l3_iclk_div",
3807 .user = OCP_USER_MPU | OCP_USER_SDMA,
3808 };
3810 /* ipu2 -> l3_main_1 */
3811 static struct omap_hwmod_ocp_if dra7xx_ipu2__l3_main_1 = {
3812 .master = &dra7xx_ipu2_hwmod,
3813 .slave = &dra7xx_l3_main_1_hwmod,
3814 .clk = "l3_iclk_div",
3815 .user = OCP_USER_MPU | OCP_USER_SDMA,
3816 };
3818 /* l4_cfg -> mailbox1 */
3819 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
3820 .master = &dra7xx_l4_cfg_hwmod,
3821 .slave = &dra7xx_mailbox1_hwmod,
3822 .clk = "l3_iclk_div",
3823 .user = OCP_USER_MPU | OCP_USER_SDMA,
3824 };
3826 /* l4_per3 -> mailbox2 */
3827 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
3828 .master = &dra7xx_l4_per3_hwmod,
3829 .slave = &dra7xx_mailbox2_hwmod,
3830 .clk = "l3_iclk_div",
3831 .user = OCP_USER_MPU | OCP_USER_SDMA,
3832 };
3834 /* l4_per3 -> mailbox3 */
3835 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
3836 .master = &dra7xx_l4_per3_hwmod,
3837 .slave = &dra7xx_mailbox3_hwmod,
3838 .clk = "l3_iclk_div",
3839 .user = OCP_USER_MPU | OCP_USER_SDMA,
3840 };
3842 /* l4_per3 -> mailbox4 */
3843 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
3844 .master = &dra7xx_l4_per3_hwmod,
3845 .slave = &dra7xx_mailbox4_hwmod,
3846 .clk = "l3_iclk_div",
3847 .user = OCP_USER_MPU | OCP_USER_SDMA,
3848 };
3850 /* l4_per3 -> mailbox5 */
3851 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
3852 .master = &dra7xx_l4_per3_hwmod,
3853 .slave = &dra7xx_mailbox5_hwmod,
3854 .clk = "l3_iclk_div",
3855 .user = OCP_USER_MPU | OCP_USER_SDMA,
3856 };
3858 /* l4_per3 -> mailbox6 */
3859 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
3860 .master = &dra7xx_l4_per3_hwmod,
3861 .slave = &dra7xx_mailbox6_hwmod,
3862 .clk = "l3_iclk_div",
3863 .user = OCP_USER_MPU | OCP_USER_SDMA,
3864 };
3866 /* l4_per3 -> mailbox7 */
3867 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
3868 .master = &dra7xx_l4_per3_hwmod,
3869 .slave = &dra7xx_mailbox7_hwmod,
3870 .clk = "l3_iclk_div",
3871 .user = OCP_USER_MPU | OCP_USER_SDMA,
3872 };
3874 /* l4_per3 -> mailbox8 */
3875 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
3876 .master = &dra7xx_l4_per3_hwmod,
3877 .slave = &dra7xx_mailbox8_hwmod,
3878 .clk = "l3_iclk_div",
3879 .user = OCP_USER_MPU | OCP_USER_SDMA,
3880 };
3882 /* l4_per3 -> mailbox9 */
3883 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
3884 .master = &dra7xx_l4_per3_hwmod,
3885 .slave = &dra7xx_mailbox9_hwmod,
3886 .clk = "l3_iclk_div",
3887 .user = OCP_USER_MPU | OCP_USER_SDMA,
3888 };
3890 /* l4_per3 -> mailbox10 */
3891 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
3892 .master = &dra7xx_l4_per3_hwmod,
3893 .slave = &dra7xx_mailbox10_hwmod,
3894 .clk = "l3_iclk_div",
3895 .user = OCP_USER_MPU | OCP_USER_SDMA,
3896 };
3898 /* l4_per3 -> mailbox11 */
3899 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
3900 .master = &dra7xx_l4_per3_hwmod,
3901 .slave = &dra7xx_mailbox11_hwmod,
3902 .clk = "l3_iclk_div",
3903 .user = OCP_USER_MPU | OCP_USER_SDMA,
3904 };
3906 /* l4_per3 -> mailbox12 */
3907 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
3908 .master = &dra7xx_l4_per3_hwmod,
3909 .slave = &dra7xx_mailbox12_hwmod,
3910 .clk = "l3_iclk_div",
3911 .user = OCP_USER_MPU | OCP_USER_SDMA,
3912 };
3914 /* l4_per3 -> mailbox13 */
3915 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
3916 .master = &dra7xx_l4_per3_hwmod,
3917 .slave = &dra7xx_mailbox13_hwmod,
3918 .clk = "l3_iclk_div",
3919 .user = OCP_USER_MPU | OCP_USER_SDMA,
3920 };
3922 /* l4_per1 -> mcspi1 */
3923 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
3924 .master = &dra7xx_l4_per1_hwmod,
3925 .slave = &dra7xx_mcspi1_hwmod,
3926 .clk = "l3_iclk_div",
3927 .user = OCP_USER_MPU | OCP_USER_SDMA,
3928 };
3930 /* l4_per1 -> mcspi2 */
3931 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
3932 .master = &dra7xx_l4_per1_hwmod,
3933 .slave = &dra7xx_mcspi2_hwmod,
3934 .clk = "l3_iclk_div",
3935 .user = OCP_USER_MPU | OCP_USER_SDMA,
3936 };
3938 /* l4_per1 -> mcspi3 */
3939 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
3940 .master = &dra7xx_l4_per1_hwmod,
3941 .slave = &dra7xx_mcspi3_hwmod,
3942 .clk = "l3_iclk_div",
3943 .user = OCP_USER_MPU | OCP_USER_SDMA,
3944 };
3946 /* l4_per1 -> mcspi4 */
3947 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
3948 .master = &dra7xx_l4_per1_hwmod,
3949 .slave = &dra7xx_mcspi4_hwmod,
3950 .clk = "l3_iclk_div",
3951 .user = OCP_USER_MPU | OCP_USER_SDMA,
3952 };
3954 /* l4_per1 -> mmc1 */
3955 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
3956 .master = &dra7xx_l4_per1_hwmod,
3957 .slave = &dra7xx_mmc1_hwmod,
3958 .clk = "l3_iclk_div",
3959 .user = OCP_USER_MPU | OCP_USER_SDMA,
3960 };
3962 /* l4_per1 -> mmc2 */
3963 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
3964 .master = &dra7xx_l4_per1_hwmod,
3965 .slave = &dra7xx_mmc2_hwmod,
3966 .clk = "l3_iclk_div",
3967 .user = OCP_USER_MPU | OCP_USER_SDMA,
3968 };
3970 /* l4_per1 -> mmc3 */
3971 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
3972 .master = &dra7xx_l4_per1_hwmod,
3973 .slave = &dra7xx_mmc3_hwmod,
3974 .clk = "l3_iclk_div",
3975 .user = OCP_USER_MPU | OCP_USER_SDMA,
3976 };
3978 /* l4_per1 -> mmc4 */
3979 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
3980 .master = &dra7xx_l4_per1_hwmod,
3981 .slave = &dra7xx_mmc4_hwmod,
3982 .clk = "l3_iclk_div",
3983 .user = OCP_USER_MPU | OCP_USER_SDMA,
3984 };
3986 /* l4_cfg -> mpu */
3987 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
3988 .master = &dra7xx_l4_cfg_hwmod,
3989 .slave = &dra7xx_mpu_hwmod,
3990 .clk = "l3_iclk_div",
3991 .user = OCP_USER_MPU | OCP_USER_SDMA,
3992 };
3994 /* l4_cfg -> ocp2scp1 */
3995 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
3996 .master = &dra7xx_l4_cfg_hwmod,
3997 .slave = &dra7xx_ocp2scp1_hwmod,
3998 .clk = "l4_root_clk_div",
3999 .user = OCP_USER_MPU | OCP_USER_SDMA,
4000 };
4002 /* l4_cfg -> ocp2scp3 */
4003 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
4004 .master = &dra7xx_l4_cfg_hwmod,
4005 .slave = &dra7xx_ocp2scp3_hwmod,
4006 .clk = "l4_root_clk_div",
4007 .user = OCP_USER_MPU | OCP_USER_SDMA,
4008 };
4010 /* l3_main_1 -> pcie1 */
4011 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
4012 .master = &dra7xx_l3_main_1_hwmod,
4013 .slave = &dra7xx_pciess1_hwmod,
4014 .clk = "l3_iclk_div",
4015 .user = OCP_USER_MPU | OCP_USER_SDMA,
4016 };
4018 /* l4_cfg -> pcie1 */
4019 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
4020 .master = &dra7xx_l4_cfg_hwmod,
4021 .slave = &dra7xx_pciess1_hwmod,
4022 .clk = "l4_root_clk_div",
4023 .user = OCP_USER_MPU | OCP_USER_SDMA,
4024 };
4026 /* l3_main_1 -> pcie2 */
4027 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
4028 .master = &dra7xx_l3_main_1_hwmod,
4029 .slave = &dra7xx_pciess2_hwmod,
4030 .clk = "l3_iclk_div",
4031 .user = OCP_USER_MPU | OCP_USER_SDMA,
4032 };
4034 /* l4_cfg -> pcie2 */
4035 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
4036 .master = &dra7xx_l4_cfg_hwmod,
4037 .slave = &dra7xx_pciess2_hwmod,
4038 .clk = "l4_root_clk_div",
4039 .user = OCP_USER_MPU | OCP_USER_SDMA,
4040 };
4042 /* l4_cfg -> pruss1 */
4043 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pruss1 = {
4044 .master = &dra7xx_l4_cfg_hwmod,
4045 .slave = &dra7xx_pruss1_hwmod,
4046 .clk = "dpll_gmac_h13x2_ck",
4047 .user = OCP_USER_MPU | OCP_USER_SDMA,
4048 };
4050 /* l4_cfg -> pruss2 */
4051 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pruss2 = {
4052 .master = &dra7xx_l4_cfg_hwmod,
4053 .slave = &dra7xx_pruss2_hwmod,
4054 .clk = "dpll_gmac_h13x2_ck",
4055 .user = OCP_USER_MPU | OCP_USER_SDMA,
4056 };
4058 static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
4059 {
4060 .pa_start = 0x4b300000,
4061 .pa_end = 0x4b30007f,
4062 .flags = ADDR_TYPE_RT
4063 },
4064 { }
4065 };
4067 /* l3_main_1 -> qspi */
4068 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
4069 .master = &dra7xx_l3_main_1_hwmod,
4070 .slave = &dra7xx_qspi_hwmod,
4071 .clk = "l3_iclk_div",
4072 .addr = dra7xx_qspi_addrs,
4073 .user = OCP_USER_MPU | OCP_USER_SDMA,
4074 };
4076 /* l4_per3 -> rtcss */
4077 static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
4078 .master = &dra7xx_l4_per3_hwmod,
4079 .slave = &dra7xx_rtcss_hwmod,
4080 .clk = "l4_root_clk_div",
4081 .user = OCP_USER_MPU | OCP_USER_SDMA,
4082 };
4084 static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
4085 {
4086 .name = "sysc",
4087 .pa_start = 0x4a141100,
4088 .pa_end = 0x4a141107,
4089 .flags = ADDR_TYPE_RT
4090 },
4091 { }
4092 };
4094 /* l4_cfg -> sata */
4095 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
4096 .master = &dra7xx_l4_cfg_hwmod,
4097 .slave = &dra7xx_sata_hwmod,
4098 .clk = "l3_iclk_div",
4099 .addr = dra7xx_sata_addrs,
4100 .user = OCP_USER_MPU | OCP_USER_SDMA,
4101 };
4103 static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
4104 {
4105 .pa_start = 0x4a0dd000,
4106 .pa_end = 0x4a0dd07f,
4107 .flags = ADDR_TYPE_RT
4108 },
4109 { }
4110 };
4112 /* l4_cfg -> smartreflex_core */
4113 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
4114 .master = &dra7xx_l4_cfg_hwmod,
4115 .slave = &dra7xx_smartreflex_core_hwmod,
4116 .clk = "l4_root_clk_div",
4117 .addr = dra7xx_smartreflex_core_addrs,
4118 .user = OCP_USER_MPU | OCP_USER_SDMA,
4119 };
4121 static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
4122 {
4123 .pa_start = 0x4a0d9000,
4124 .pa_end = 0x4a0d907f,
4125 .flags = ADDR_TYPE_RT
4126 },
4127 { }
4128 };
4130 /* l4_cfg -> smartreflex_mpu */
4131 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
4132 .master = &dra7xx_l4_cfg_hwmod,
4133 .slave = &dra7xx_smartreflex_mpu_hwmod,
4134 .clk = "l4_root_clk_div",
4135 .addr = dra7xx_smartreflex_mpu_addrs,
4136 .user = OCP_USER_MPU | OCP_USER_SDMA,
4137 };
4139 static struct omap_hwmod_addr_space dra7xx_spinlock_addrs[] = {
4140 {
4141 .pa_start = 0x4a0f6000,
4142 .pa_end = 0x4a0f6fff,
4143 .flags = ADDR_TYPE_RT
4144 },
4145 { }
4146 };
4148 /* l4_cfg -> spinlock */
4149 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
4150 .master = &dra7xx_l4_cfg_hwmod,
4151 .slave = &dra7xx_spinlock_hwmod,
4152 .clk = "l3_iclk_div",
4153 .addr = dra7xx_spinlock_addrs,
4154 .user = OCP_USER_MPU | OCP_USER_SDMA,
4155 };
4157 /* l4_wkup -> timer1 */
4158 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
4159 .master = &dra7xx_l4_wkup_hwmod,
4160 .slave = &dra7xx_timer1_hwmod,
4161 .clk = "wkupaon_iclk_mux",
4162 .user = OCP_USER_MPU | OCP_USER_SDMA,
4163 };
4165 /* l4_per1 -> timer2 */
4166 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
4167 .master = &dra7xx_l4_per1_hwmod,
4168 .slave = &dra7xx_timer2_hwmod,
4169 .clk = "l3_iclk_div",
4170 .user = OCP_USER_MPU | OCP_USER_SDMA,
4171 };
4173 /* l4_per1 -> timer3 */
4174 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
4175 .master = &dra7xx_l4_per1_hwmod,
4176 .slave = &dra7xx_timer3_hwmod,
4177 .clk = "l3_iclk_div",
4178 .user = OCP_USER_MPU | OCP_USER_SDMA,
4179 };
4181 /* l4_per1 -> timer4 */
4182 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
4183 .master = &dra7xx_l4_per1_hwmod,
4184 .slave = &dra7xx_timer4_hwmod,
4185 .clk = "l3_iclk_div",
4186 .user = OCP_USER_MPU | OCP_USER_SDMA,
4187 };
4189 /* l4_per3 -> timer5 */
4190 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
4191 .master = &dra7xx_l4_per3_hwmod,
4192 .slave = &dra7xx_timer5_hwmod,
4193 .clk = "l3_iclk_div",
4194 .user = OCP_USER_MPU | OCP_USER_SDMA,
4195 };
4197 /* l4_per3 -> timer6 */
4198 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
4199 .master = &dra7xx_l4_per3_hwmod,
4200 .slave = &dra7xx_timer6_hwmod,
4201 .clk = "l3_iclk_div",
4202 .user = OCP_USER_MPU | OCP_USER_SDMA,
4203 };
4205 /* l4_per3 -> timer7 */
4206 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
4207 .master = &dra7xx_l4_per3_hwmod,
4208 .slave = &dra7xx_timer7_hwmod,
4209 .clk = "l3_iclk_div",
4210 .user = OCP_USER_MPU | OCP_USER_SDMA,
4211 };
4213 /* l4_per3 -> timer8 */
4214 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
4215 .master = &dra7xx_l4_per3_hwmod,
4216 .slave = &dra7xx_timer8_hwmod,
4217 .clk = "l3_iclk_div",
4218 .user = OCP_USER_MPU | OCP_USER_SDMA,
4219 };
4221 /* l4_per1 -> timer9 */
4222 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
4223 .master = &dra7xx_l4_per1_hwmod,
4224 .slave = &dra7xx_timer9_hwmod,
4225 .clk = "l3_iclk_div",
4226 .user = OCP_USER_MPU | OCP_USER_SDMA,
4227 };
4229 /* l4_per1 -> timer10 */
4230 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
4231 .master = &dra7xx_l4_per1_hwmod,
4232 .slave = &dra7xx_timer10_hwmod,
4233 .clk = "l3_iclk_div",
4234 .user = OCP_USER_MPU | OCP_USER_SDMA,
4235 };
4237 /* l4_per1 -> timer11 */
4238 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
4239 .master = &dra7xx_l4_per1_hwmod,
4240 .slave = &dra7xx_timer11_hwmod,
4241 .clk = "l3_iclk_div",
4242 .user = OCP_USER_MPU | OCP_USER_SDMA,
4243 };
4245 /* l4_wkup -> timer12 */
4246 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer12 = {
4247 .master = &dra7xx_l4_wkup_hwmod,
4248 .slave = &dra7xx_timer12_hwmod,
4249 .clk = "wkupaon_iclk_mux",
4250 .user = OCP_USER_MPU | OCP_USER_SDMA,
4251 };
4253 /* l4_per3 -> timer13 */
4254 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
4255 .master = &dra7xx_l4_per3_hwmod,
4256 .slave = &dra7xx_timer13_hwmod,
4257 .clk = "l3_iclk_div",
4258 .user = OCP_USER_MPU | OCP_USER_SDMA,
4259 };
4261 /* l4_per3 -> timer14 */
4262 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
4263 .master = &dra7xx_l4_per3_hwmod,
4264 .slave = &dra7xx_timer14_hwmod,
4265 .clk = "l3_iclk_div",
4266 .user = OCP_USER_MPU | OCP_USER_SDMA,
4267 };
4269 /* l4_per3 -> timer15 */
4270 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
4271 .master = &dra7xx_l4_per3_hwmod,
4272 .slave = &dra7xx_timer15_hwmod,
4273 .clk = "l3_iclk_div",
4274 .user = OCP_USER_MPU | OCP_USER_SDMA,
4275 };
4277 /* l4_per3 -> timer16 */
4278 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
4279 .master = &dra7xx_l4_per3_hwmod,
4280 .slave = &dra7xx_timer16_hwmod,
4281 .clk = "l3_iclk_div",
4282 .user = OCP_USER_MPU | OCP_USER_SDMA,
4283 };
4285 /* l4_per1 -> uart1 */
4286 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
4287 .master = &dra7xx_l4_per1_hwmod,
4288 .slave = &dra7xx_uart1_hwmod,
4289 .clk = "l3_iclk_div",
4290 .user = OCP_USER_MPU | OCP_USER_SDMA,
4291 };
4293 /* l4_per1 -> uart2 */
4294 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
4295 .master = &dra7xx_l4_per1_hwmod,
4296 .slave = &dra7xx_uart2_hwmod,
4297 .clk = "l3_iclk_div",
4298 .user = OCP_USER_MPU | OCP_USER_SDMA,
4299 };
4301 /* l4_per1 -> uart3 */
4302 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
4303 .master = &dra7xx_l4_per1_hwmod,
4304 .slave = &dra7xx_uart3_hwmod,
4305 .clk = "l3_iclk_div",
4306 .user = OCP_USER_MPU | OCP_USER_SDMA,
4307 };
4309 /* l4_per1 -> uart4 */
4310 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
4311 .master = &dra7xx_l4_per1_hwmod,
4312 .slave = &dra7xx_uart4_hwmod,
4313 .clk = "l3_iclk_div",
4314 .user = OCP_USER_MPU | OCP_USER_SDMA,
4315 };
4317 /* l4_per1 -> uart5 */
4318 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
4319 .master = &dra7xx_l4_per1_hwmod,
4320 .slave = &dra7xx_uart5_hwmod,
4321 .clk = "l3_iclk_div",
4322 .user = OCP_USER_MPU | OCP_USER_SDMA,
4323 };
4325 /* l4_per1 -> uart6 */
4326 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
4327 .master = &dra7xx_l4_per1_hwmod,
4328 .slave = &dra7xx_uart6_hwmod,
4329 .clk = "l3_iclk_div",
4330 .user = OCP_USER_MPU | OCP_USER_SDMA,
4331 };
4333 /* l4_per2 -> uart7 */
4334 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
4335 .master = &dra7xx_l4_per2_hwmod,
4336 .slave = &dra7xx_uart7_hwmod,
4337 .clk = "l3_iclk_div",
4338 .user = OCP_USER_MPU | OCP_USER_SDMA,
4339 };
4341 /* l4_per2 -> uart8 */
4342 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
4343 .master = &dra7xx_l4_per2_hwmod,
4344 .slave = &dra7xx_uart8_hwmod,
4345 .clk = "l3_iclk_div",
4346 .user = OCP_USER_MPU | OCP_USER_SDMA,
4347 };
4349 /* l4_per2 -> uart9 */
4350 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
4351 .master = &dra7xx_l4_per2_hwmod,
4352 .slave = &dra7xx_uart9_hwmod,
4353 .clk = "l3_iclk_div",
4354 .user = OCP_USER_MPU | OCP_USER_SDMA,
4355 };
4357 /* l4_wkup -> uart10 */
4358 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
4359 .master = &dra7xx_l4_wkup_hwmod,
4360 .slave = &dra7xx_uart10_hwmod,
4361 .clk = "wkupaon_iclk_mux",
4362 .user = OCP_USER_MPU | OCP_USER_SDMA,
4363 };
4365 /* l4_per1 -> des */
4366 static struct omap_hwmod_ocp_if dra7xx_l4_per1__des = {
4367 .master = &dra7xx_l4_per1_hwmod,
4368 .slave = &dra7xx_des_hwmod,
4369 .clk = "l3_iclk_div",
4370 .user = OCP_USER_MPU | OCP_USER_SDMA,
4371 };
4373 /* l4_per1 -> rng */
4374 static struct omap_hwmod_ocp_if dra7xx_l4_per1__rng = {
4375 .master = &dra7xx_l4_per1_hwmod,
4376 .slave = &dra7xx_rng_hwmod,
4377 .user = OCP_USER_MPU,
4378 };
4380 /* l4_per3 -> usb_otg_ss1 */
4381 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
4382 .master = &dra7xx_l4_per3_hwmod,
4383 .slave = &dra7xx_usb_otg_ss1_hwmod,
4384 .clk = "dpll_core_h13x2_ck",
4385 .user = OCP_USER_MPU | OCP_USER_SDMA,
4386 };
4388 /* l4_per3 -> usb_otg_ss2 */
4389 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
4390 .master = &dra7xx_l4_per3_hwmod,
4391 .slave = &dra7xx_usb_otg_ss2_hwmod,
4392 .clk = "dpll_core_h13x2_ck",
4393 .user = OCP_USER_MPU | OCP_USER_SDMA,
4394 };
4396 /* l4_per3 -> usb_otg_ss3 */
4397 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
4398 .master = &dra7xx_l4_per3_hwmod,
4399 .slave = &dra7xx_usb_otg_ss3_hwmod,
4400 .clk = "dpll_core_h13x2_ck",
4401 .user = OCP_USER_MPU | OCP_USER_SDMA,
4402 };
4404 /* l4_per3 -> usb_otg_ss4 */
4405 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
4406 .master = &dra7xx_l4_per3_hwmod,
4407 .slave = &dra7xx_usb_otg_ss4_hwmod,
4408 .clk = "dpll_core_h13x2_ck",
4409 .user = OCP_USER_MPU | OCP_USER_SDMA,
4410 };
4412 /* l3_main_1 -> vcp1 */
4413 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
4414 .master = &dra7xx_l3_main_1_hwmod,
4415 .slave = &dra7xx_vcp1_hwmod,
4416 .clk = "l3_iclk_div",
4417 .user = OCP_USER_MPU | OCP_USER_SDMA,
4418 };
4420 /* l4_per2 -> vcp1 */
4421 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
4422 .master = &dra7xx_l4_per2_hwmod,
4423 .slave = &dra7xx_vcp1_hwmod,
4424 .clk = "l3_iclk_div",
4425 .user = OCP_USER_MPU | OCP_USER_SDMA,
4426 };
4428 /* l3_main_1 -> vcp2 */
4429 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
4430 .master = &dra7xx_l3_main_1_hwmod,
4431 .slave = &dra7xx_vcp2_hwmod,
4432 .clk = "l3_iclk_div",
4433 .user = OCP_USER_MPU | OCP_USER_SDMA,
4434 };
4436 /* l4_per2 -> vcp2 */
4437 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
4438 .master = &dra7xx_l4_per2_hwmod,
4439 .slave = &dra7xx_vcp2_hwmod,
4440 .clk = "l3_iclk_div",
4441 .user = OCP_USER_MPU | OCP_USER_SDMA,
4442 };
4444 /* l4_per3 -> vpe */
4445 static struct omap_hwmod_ocp_if dra7xx_l4_per3__vpe = {
4446 .master = &dra7xx_l4_per3_hwmod,
4447 .slave = &dra7xx_vpe_hwmod,
4448 .clk = "l3_iclk_div",
4449 .user = OCP_USER_MPU | OCP_USER_SDMA,
4450 };
4452 /* l4_per3 -> vip1 */
4453 static struct omap_hwmod_ocp_if dra7xx_l4_per3__vip1 = {
4454 .master = &dra7xx_l4_per3_hwmod,
4455 .slave = &dra7xx_vip1_hwmod,
4456 .clk = "l3_iclk_div",
4457 .user = OCP_USER_MPU | OCP_USER_SDMA,
4458 };
4460 /* l4_per3 -> vip2 */
4461 static struct omap_hwmod_ocp_if dra7xx_l4_per3__vip2 = {
4462 .master = &dra7xx_l4_per3_hwmod,
4463 .slave = &dra7xx_vip2_hwmod,
4464 .clk = "l3_iclk_div",
4465 .user = OCP_USER_MPU | OCP_USER_SDMA,
4466 };
4468 /* l4_per3 -> vip3 */
4469 static struct omap_hwmod_ocp_if dra7xx_l4_per3__vip3 = {
4470 .master = &dra7xx_l4_per3_hwmod,
4471 .slave = &dra7xx_vip3_hwmod,
4472 .clk = "l3_iclk_div",
4473 .user = OCP_USER_MPU | OCP_USER_SDMA,
4474 };
4476 /* l4_per3 -> cal */
4477 static struct omap_hwmod_ocp_if dra7xx_l4_per3__cal = {
4478 .master = &dra7xx_l4_per3_hwmod,
4479 .slave = &dra7xx_cal_hwmod,
4480 .clk = "l3_iclk_div",
4481 .user = OCP_USER_MPU | OCP_USER_SDMA,
4482 };
4484 /* l4_wkup -> wd_timer2 */
4485 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
4486 .master = &dra7xx_l4_wkup_hwmod,
4487 .slave = &dra7xx_wd_timer2_hwmod,
4488 .clk = "wkupaon_iclk_mux",
4489 .user = OCP_USER_MPU | OCP_USER_SDMA,
4490 };
4492 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
4493 &dra7xx_l3_main_1__dmm,
4494 &dra7xx_dmm__emif_ocp_fw,
4495 &dra7xx_l3_main_2__l3_instr,
4496 &dra7xx_l4_cfg__l3_main_1,
4497 &dra7xx_mpu__l3_main_1,
4498 &dra7xx_l3_main_1__l3_main_2,
4499 &dra7xx_l4_cfg__l3_main_2,
4500 &dra7xx_l3_main_1__l4_cfg,
4501 &dra7xx_l3_main_1__l4_per1,
4502 &dra7xx_l3_main_1__l4_per2,
4503 &dra7xx_l3_main_1__l4_per3,
4504 &dra7xx_l3_main_1__l4_wkup,
4505 &dra7xx_l4_per2__atl,
4506 &dra7xx_l3_main_1__bb2d,
4507 &dra7xx_l4_wkup__counter_32k,
4508 &dra7xx_l4_wkup__ctrl_module_wkup,
4509 &dra7xx_l4_wkup__dcan1,
4510 &dra7xx_l4_per2__dcan2,
4511 &dra7xx_l4_per2__cpgmac0,
4512 &dra7xx_gmac__mdio,
4513 &dra7xx_l4_cfg__dma_system,
4514 &dra7xx_l3_main_1__dss,
4515 &dra7xx_l3_main_1__dispc,
4516 &dra7xx_dsp1__l3_main_1,
4517 &dra7xx_l3_main_1__hdmi,
4518 &dra7xx_l3_main_1__aes,
4519 &dra7xx_l3_main_1__sha0,
4520 &dra7xx_l4_per2__mcasp2,
4521 &dra7xx_l4_per2__mcasp3,
4522 &dra7xx_l4_per2__mcasp6,
4523 &dra7xx_l4_per1__elm,
4524 &dra7xx_l4_wkup__gpio1,
4525 &dra7xx_l4_per1__gpio2,
4526 &dra7xx_l4_per1__gpio3,
4527 &dra7xx_l4_per1__gpio4,
4528 &dra7xx_l4_per1__gpio5,
4529 &dra7xx_l4_per1__gpio6,
4530 &dra7xx_l4_per1__gpio7,
4531 &dra7xx_l4_per1__gpio8,
4532 &dra7xx_l3_main_1__gpmc,
4533 &dra7xx_l3_main_1__gpu,
4534 &dra7xx_l4_per1__hdq1w,
4535 &dra7xx_l4_per1__i2c1,
4536 &dra7xx_l4_per1__i2c2,
4537 &dra7xx_l4_per1__i2c3,
4538 &dra7xx_l4_per1__i2c4,
4539 &dra7xx_l4_per1__i2c5,
4540 &dra7xx_ipu1__l3_main_1,
4541 &dra7xx_ipu2__l3_main_1,
4542 &dra7xx_l4_cfg__mailbox1,
4543 &dra7xx_l4_per3__mailbox2,
4544 &dra7xx_l4_per3__mailbox3,
4545 &dra7xx_l4_per3__mailbox4,
4546 &dra7xx_l4_per3__mailbox5,
4547 &dra7xx_l4_per3__mailbox6,
4548 &dra7xx_l4_per3__mailbox7,
4549 &dra7xx_l4_per3__mailbox8,
4550 &dra7xx_l4_per3__mailbox9,
4551 &dra7xx_l4_per3__mailbox10,
4552 &dra7xx_l4_per3__mailbox11,
4553 &dra7xx_l4_per3__mailbox12,
4554 &dra7xx_l4_per3__mailbox13,
4555 &dra7xx_l4_per1__mcspi1,
4556 &dra7xx_l4_per1__mcspi2,
4557 &dra7xx_l4_per1__mcspi3,
4558 &dra7xx_l4_per1__mcspi4,
4559 &dra7xx_l4_per1__mmc1,
4560 &dra7xx_l4_per1__mmc2,
4561 &dra7xx_l4_per1__mmc3,
4562 &dra7xx_l4_per1__mmc4,
4563 &dra7xx_l3_main_1__mmu0_dsp1,
4564 &dra7xx_l3_main_1__mmu1_dsp1,
4565 &dra7xx_l3_main_1__mmu_ipu1,
4566 &dra7xx_l3_main_1__mmu_ipu2,
4567 &dra7xx_l4_cfg__mpu,
4568 &dra7xx_l4_cfg__ocp2scp1,
4569 &dra7xx_l4_cfg__ocp2scp3,
4570 &dra7xx_l3_main_1__pciess1,
4571 &dra7xx_l4_cfg__pciess1,
4572 &dra7xx_l3_main_1__pciess2,
4573 &dra7xx_l4_cfg__pciess2,
4574 &dra7xx_l4_cfg__pruss1, /* AM57xx only */
4575 &dra7xx_l4_cfg__pruss2, /* AM57xx only */
4576 &dra7xx_l3_main_1__qspi,
4577 &dra7xx_l4_per3__rtcss,
4578 &dra7xx_l4_cfg__sata,
4579 &dra7xx_l4_cfg__smartreflex_core,
4580 &dra7xx_l4_cfg__smartreflex_mpu,
4581 &dra7xx_l4_cfg__spinlock,
4582 &dra7xx_l4_wkup__timer1,
4583 &dra7xx_l4_per1__timer2,
4584 &dra7xx_l4_per1__timer3,
4585 &dra7xx_l4_per1__timer4,
4586 &dra7xx_l4_per3__timer5,
4587 &dra7xx_l4_per3__timer6,
4588 &dra7xx_l4_per3__timer7,
4589 &dra7xx_l4_per3__timer8,
4590 &dra7xx_l4_per1__timer9,
4591 &dra7xx_l4_per1__timer10,
4592 &dra7xx_l4_per1__timer11,
4593 &dra7xx_l4_wkup__timer12,
4594 &dra7xx_l4_per3__timer13,
4595 &dra7xx_l4_per3__timer14,
4596 &dra7xx_l4_per3__timer15,
4597 &dra7xx_l4_per3__timer16,
4598 &dra7xx_l4_per1__uart1,
4599 &dra7xx_l4_per1__uart2,
4600 &dra7xx_l4_per1__uart3,
4601 &dra7xx_l4_per1__uart4,
4602 &dra7xx_l4_per1__uart5,
4603 &dra7xx_l4_per1__uart6,
4604 &dra7xx_l4_per2__uart7,
4605 &dra7xx_l4_per2__uart8,
4606 &dra7xx_l4_per2__uart9,
4607 &dra7xx_l4_wkup__uart10,
4608 &dra7xx_l4_per1__des,
4609 &dra7xx_l4_per1__rng,
4610 &dra7xx_l4_per3__usb_otg_ss1,
4611 &dra7xx_l4_per3__usb_otg_ss2,
4612 &dra7xx_l4_per3__usb_otg_ss3,
4613 &dra7xx_l3_main_1__vcp1,
4614 &dra7xx_l4_per2__vcp1,
4615 &dra7xx_l3_main_1__vcp2,
4616 &dra7xx_l4_per2__vcp2,
4617 &dra7xx_l4_per3__vpe,
4618 &dra7xx_l4_per3__vip1,
4619 &dra7xx_l4_wkup__wd_timer2,
4620 &dra7xx_l4_per2__epwmss0,
4621 &dra7xx_epwmss0__ecap0,
4622 &dra7xx_epwmss0__eqep0,
4623 &dra7xx_epwmss0__ehrpwm0,
4624 &dra7xx_l4_per2__epwmss1,
4625 &dra7xx_epwmss1__ecap1,
4626 &dra7xx_epwmss1__eqep1,
4627 &dra7xx_epwmss1__ehrpwm1,
4628 &dra7xx_l4_per2__epwmss2,
4629 &dra7xx_epwmss2__ecap2,
4630 &dra7xx_epwmss2__eqep2,
4631 &dra7xx_epwmss2__ehrpwm2,
4632 NULL,
4633 };
4635 static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
4636 &dra7xx_l4_per3__usb_otg_ss4,
4637 &dra7xx_l3_main_1__mmu0_dsp2,
4638 &dra7xx_l3_main_1__mmu1_dsp2,
4639 &dra7xx_dsp2__l3_main_1,
4640 &dra7xx_l4_per3__vip2,
4641 &dra7xx_l4_per3__vip3,
4642 NULL,
4643 };
4645 static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
4646 &dra7xx_l4_per3__cal,
4647 NULL,
4648 };
4650 int __init dra7xx_hwmod_init(void)
4651 {
4652 int ret;
4654 omap_hwmod_init();
4656 if (OMAP2_DEVICE_TYPE_GP != omap_type()) {
4657 /* AES, DES, SHAM and RNG HWAs are shared between secure and public
4658 worlds for a HS/EMU device. In this case the module clocks are
4659 already enabled and should not be touched by the kernel driver.
4660 */
4661 dra7xx_aes_hwmod_class.sysc = NULL;
4662 dra7xx_aes_hwmod_class.rev = 0;
4663 dra7xx_aes_hwmod.prcm.omap4.modulemode = 0;
4665 dra7xx_des_hwmod_class.sysc = NULL;
4666 dra7xx_des_hwmod_class.rev = 0;
4667 dra7xx_des_hwmod.prcm.omap4.modulemode = 0;
4669 dra7xx_sha0_hwmod_class.sysc = NULL;
4670 dra7xx_sha0_hwmod_class.rev = 0;
4671 dra7xx_sha0_hwmod.prcm.omap4.modulemode = 0;
4673 dra7xx_rng_hwmod_class.sysc = NULL;
4674 dra7xx_rng_hwmod_class.rev = 0;
4675 dra7xx_rng_hwmod.prcm.omap4.modulemode = 0;
4676 }
4678 ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
4680 if (!ret && soc_is_dra74x())
4681 return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
4682 else if (!ret && soc_is_dra72x())
4683 return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
4685 return ret;
4686 }