1 /*
2 * Hardware modules present on the DRA7xx chips
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley
7 * Benoit Cousson
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
20 #include <linux/io.h>
21 #include <linux/platform_data/gpio-omap.h>
22 #include <linux/power/smartreflex.h>
23 #include <linux/i2c-omap.h>
25 #include <linux/omap-dma.h>
26 #include <linux/platform_data/spi-omap2-mcspi.h>
27 #include <linux/platform_data/asoc-ti-mcbsp.h>
28 #include <linux/platform_data/iommu-omap.h>
29 #include <plat/dmtimer.h>
31 #include "omap_hwmod.h"
32 #include "omap_hwmod_common_data.h"
33 #include "cm1_7xx.h"
34 #include "cm2_7xx.h"
35 #include "prm7xx.h"
36 #include "i2c.h"
37 #include "mmc.h"
38 #include "wd_timer.h"
39 #include "soc.h"
41 /* Base offset for all DRA7XX interrupts external to MPUSS */
42 #define DRA7XX_IRQ_GIC_START 32
44 /* Base offset for all DRA7XX dma requests */
45 #define DRA7XX_DMA_REQ_START 1
48 /*
49 * IP blocks
50 */
52 /*
53 * 'dmm' class
54 * instance(s): dmm
55 */
56 static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
57 .name = "dmm",
58 };
60 /* dmm */
61 static struct omap_hwmod dra7xx_dmm_hwmod = {
62 .name = "dmm",
63 .class = &dra7xx_dmm_hwmod_class,
64 .clkdm_name = "emif_clkdm",
65 .prcm = {
66 .omap4 = {
67 .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
68 .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
69 },
70 },
71 };
73 /*
74 * 'emif_ocp_fw' class
75 * instance(s): emif_ocp_fw
76 */
77 static struct omap_hwmod_class dra7xx_emif_ocp_fw_hwmod_class = {
78 .name = "emif_ocp_fw",
79 };
81 /* emif_ocp_fw */
82 static struct omap_hwmod dra7xx_emif_ocp_fw_hwmod = {
83 .name = "emif_ocp_fw",
84 .class = &dra7xx_emif_ocp_fw_hwmod_class,
85 .clkdm_name = "emif_clkdm",
86 .prcm = {
87 .omap4 = {
88 .clkctrl_offs = DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET,
89 .context_offs = DRA7XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET,
90 },
91 },
92 };
94 /*
95 * 'l3' class
96 * instance(s): l3_instr, l3_main_1, l3_main_2
97 */
98 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
99 .name = "l3",
100 };
102 /* l3_instr */
103 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
104 .name = "l3_instr",
105 .class = &dra7xx_l3_hwmod_class,
106 .clkdm_name = "l3instr_clkdm",
107 .prcm = {
108 .omap4 = {
109 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
110 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
111 .modulemode = MODULEMODE_HWCTRL,
112 },
113 },
114 };
116 /* l3_main_1 */
117 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
118 .name = "l3_main_1",
119 .class = &dra7xx_l3_hwmod_class,
120 .clkdm_name = "l3main1_clkdm",
121 .prcm = {
122 .omap4 = {
123 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
124 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
125 },
126 },
127 };
129 /* l3_main_2 */
130 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
131 .name = "l3_main_2",
132 .class = &dra7xx_l3_hwmod_class,
133 .clkdm_name = "l3instr_clkdm",
134 .prcm = {
135 .omap4 = {
136 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
137 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
138 .modulemode = MODULEMODE_HWCTRL,
139 },
140 },
141 };
143 /*
144 * 'l4' class
145 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
146 */
147 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
148 .name = "l4",
149 };
151 /* l4_cfg */
152 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
153 .name = "l4_cfg",
154 .class = &dra7xx_l4_hwmod_class,
155 .clkdm_name = "l4cfg_clkdm",
156 .prcm = {
157 .omap4 = {
158 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
159 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
160 },
161 },
162 };
164 /* l4_per1 */
165 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
166 .name = "l4_per1",
167 .class = &dra7xx_l4_hwmod_class,
168 .clkdm_name = "l4per_clkdm",
169 .prcm = {
170 .omap4 = {
171 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
172 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
173 },
174 },
175 };
177 /* l4_per2 */
178 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
179 .name = "l4_per2",
180 .class = &dra7xx_l4_hwmod_class,
181 .clkdm_name = "l4per2_clkdm",
182 .prcm = {
183 .omap4 = {
184 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
185 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
186 },
187 },
188 };
190 /* l4_per3 */
191 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
192 .name = "l4_per3",
193 .class = &dra7xx_l4_hwmod_class,
194 .clkdm_name = "l4per3_clkdm",
195 .prcm = {
196 .omap4 = {
197 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
198 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
199 },
200 },
201 };
203 /* l4_wkup */
204 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
205 .name = "l4_wkup",
206 .class = &dra7xx_l4_hwmod_class,
207 .clkdm_name = "wkupaon_clkdm",
208 .prcm = {
209 .omap4 = {
210 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
211 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
212 },
213 },
214 };
216 /*
217 * 'atl' class
218 *
219 */
221 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
222 .name = "atl",
223 };
225 /* atl */
226 static struct omap_hwmod dra7xx_atl_hwmod = {
227 .name = "atl",
228 .class = &dra7xx_atl_hwmod_class,
229 .clkdm_name = "atl_clkdm",
230 .main_clk = "atl_gfclk_mux",
231 .lockdep_class = HWMOD_LOCKDEP_SUBCLASS_CLASS1,
232 .prcm = {
233 .omap4 = {
234 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
235 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
236 .modulemode = MODULEMODE_SWCTRL,
237 },
238 },
239 };
241 /*
242 * 'bb2d' class
243 *
244 */
246 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
247 .name = "bb2d",
248 };
250 /* bb2d */
251 static struct omap_hwmod dra7xx_bb2d_hwmod = {
252 .name = "bb2d",
253 .class = &dra7xx_bb2d_hwmod_class,
254 .clkdm_name = "dss_clkdm",
255 .main_clk = "dpll_core_h24x2_ck",
256 .prcm = {
257 .omap4 = {
258 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
259 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
260 .modulemode = MODULEMODE_SWCTRL,
261 },
262 },
263 };
265 /*
266 * 'vpe' class
267 *
268 */
270 static struct omap_hwmod_class_sysconfig dra7xx_vpe_sysc = {
271 .sysc_offs = 0x0010,
272 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
273 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
274 MSTANDBY_FORCE | MSTANDBY_NO |
275 MSTANDBY_SMART),
276 .sysc_fields = &omap_hwmod_sysc_type2,
277 };
279 static struct omap_hwmod_class dra7xx_vpe_hwmod_class = {
280 .name = "vpe",
281 .sysc = &dra7xx_vpe_sysc,
282 };
284 /* vpe */
285 static struct omap_hwmod dra7xx_vpe_hwmod = {
286 .name = "vpe",
287 .class = &dra7xx_vpe_hwmod_class,
288 .clkdm_name = "vpe_clkdm",
289 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
290 .prcm = {
291 .omap4 = {
292 .clkctrl_offs = DRA7XX_CM_VPE_VPE_CLKCTRL_OFFSET,
293 .context_offs = DRA7XX_RM_VPE_VPE_CONTEXT_OFFSET,
294 .modulemode = MODULEMODE_HWCTRL,
295 },
296 },
297 };
299 /*
300 * 'vip' class
301 *
302 */
304 static struct omap_hwmod_class_sysconfig dra7xx_vip_sysc = {
305 .sysc_offs = 0x0010,
306 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
307 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
308 MSTANDBY_FORCE | MSTANDBY_NO |
309 MSTANDBY_SMART),
310 .sysc_fields = &omap_hwmod_sysc_type2,
311 };
313 static struct omap_hwmod_class dra7xx_vip_hwmod_class = {
314 .name = "vip",
315 .sysc = &dra7xx_vip_sysc,
316 };
318 /* vip1 */
319 static struct omap_hwmod dra7xx_vip1_hwmod = {
320 .name = "vip1",
321 .class = &dra7xx_vip_hwmod_class,
322 .clkdm_name = "cam_clkdm",
323 .main_clk = "vip1_gclk_mux",
324 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
325 .prcm = {
326 .omap4 = {
327 .clkctrl_offs = DRA7XX_CM_CAM_VIP1_CLKCTRL_OFFSET,
328 .context_offs = DRA7XX_RM_CAM_VIP1_CONTEXT_OFFSET,
329 .modulemode = MODULEMODE_HWCTRL,
330 },
331 },
332 };
334 /* vip2 */
335 static struct omap_hwmod dra7xx_vip2_hwmod = {
336 .name = "vip2",
337 .class = &dra7xx_vip_hwmod_class,
338 .clkdm_name = "cam_clkdm",
339 .main_clk = "vip2_gclk_mux",
340 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
341 .prcm = {
342 .omap4 = {
343 .clkctrl_offs = DRA7XX_CM_CAM_VIP2_CLKCTRL_OFFSET,
344 .context_offs = DRA7XX_RM_CAM_VIP2_CONTEXT_OFFSET,
345 .modulemode = MODULEMODE_HWCTRL,
346 },
347 },
348 };
350 /* vip3 */
351 static struct omap_hwmod dra7xx_vip3_hwmod = {
352 .name = "vip3",
353 .class = &dra7xx_vip_hwmod_class,
354 .clkdm_name = "cam_clkdm",
355 .main_clk = "vip3_gclk_mux",
356 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
357 .prcm = {
358 .omap4 = {
359 .clkctrl_offs = DRA7XX_CM_CAM_VIP3_CLKCTRL_OFFSET,
360 .context_offs = DRA7XX_RM_CAM_VIP3_CONTEXT_OFFSET,
361 .modulemode = MODULEMODE_HWCTRL,
362 },
363 },
364 };
366 /*
367 * 'cal' class
368 *
369 */
371 static struct omap_hwmod_class_sysconfig dra7xx_cal_sysc = {
372 .sysc_offs = 0x0010,
373 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_RESET_STATUS |
374 SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE),
375 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
376 MSTANDBY_FORCE | MSTANDBY_NO),
377 .sysc_fields = &omap_hwmod_sysc_type2,
378 };
380 static struct omap_hwmod_class dra7xx_cal_hwmod_class = {
381 .name = "cal",
382 .sysc = &dra7xx_cal_sysc,
383 };
385 /* cal */
386 static struct omap_hwmod dra7xx_cal_hwmod = {
387 .name = "cal",
388 .class = &dra7xx_cal_hwmod_class,
389 .clkdm_name = "cam_clkdm",
390 .main_clk = "vip2_gclk_mux",
391 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
392 .prcm = {
393 .omap4 = {
394 .clkctrl_offs = DRA7XX_CM_CAM_VIP2_CLKCTRL_OFFSET,
395 .context_offs = DRA7XX_RM_CAM_VIP2_CONTEXT_OFFSET,
396 .modulemode = MODULEMODE_HWCTRL,
397 },
398 },
399 };
401 /*
402 * 'counter' class
403 *
404 */
406 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
407 .rev_offs = 0x0000,
408 .sysc_offs = 0x0010,
409 .sysc_flags = SYSC_HAS_SIDLEMODE,
410 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
411 SIDLE_SMART_WKUP),
412 .sysc_fields = &omap_hwmod_sysc_type1,
413 };
415 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
416 .name = "counter",
417 .sysc = &dra7xx_counter_sysc,
418 };
420 /* counter_32k */
421 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
422 .name = "counter_32k",
423 .class = &dra7xx_counter_hwmod_class,
424 .clkdm_name = "wkupaon_clkdm",
425 .flags = HWMOD_SWSUP_SIDLE,
426 .main_clk = "wkupaon_iclk_mux",
427 .prcm = {
428 .omap4 = {
429 .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
430 .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
431 },
432 },
433 };
435 /*
436 * 'ctrl_module' class
437 *
438 */
440 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
441 .name = "ctrl_module",
442 };
444 /* ctrl_module_wkup */
445 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
446 .name = "ctrl_module_wkup",
447 .class = &dra7xx_ctrl_module_hwmod_class,
448 .clkdm_name = "wkupaon_clkdm",
449 .prcm = {
450 .omap4 = {
451 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
452 },
453 },
454 };
456 /*
457 * 'gmac' class
458 * cpsw/gmac sub system
459 */
460 static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
461 .rev_offs = 0x0,
462 .sysc_offs = 0x8,
463 .syss_offs = 0x4,
464 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
465 SYSS_HAS_RESET_STATUS),
466 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
467 MSTANDBY_NO),
468 .sysc_fields = &omap_hwmod_sysc_type3,
469 };
471 static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
472 .name = "gmac",
473 .sysc = &dra7xx_gmac_sysc,
474 };
476 static struct omap_hwmod dra7xx_gmac_hwmod = {
477 .name = "gmac",
478 .class = &dra7xx_gmac_hwmod_class,
479 .clkdm_name = "gmac_clkdm",
480 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
481 .main_clk = "dpll_gmac_ck",
482 .mpu_rt_idx = 1,
483 .prcm = {
484 .omap4 = {
485 .clkctrl_offs = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
486 .context_offs = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
487 .modulemode = MODULEMODE_SWCTRL,
488 },
489 },
490 };
492 /*
493 * 'mdio' class
494 */
495 static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
496 .name = "davinci_mdio",
497 };
499 static struct omap_hwmod dra7xx_mdio_hwmod = {
500 .name = "davinci_mdio",
501 .class = &dra7xx_mdio_hwmod_class,
502 .clkdm_name = "gmac_clkdm",
503 .main_clk = "dpll_gmac_ck",
504 };
506 /*
507 * 'dcan' class
508 *
509 */
511 static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
512 .name = "dcan",
513 };
515 /* dcan1 */
516 static struct omap_hwmod dra7xx_dcan1_hwmod = {
517 .name = "dcan1",
518 .class = &dra7xx_dcan_hwmod_class,
519 .clkdm_name = "wkupaon_clkdm",
520 .prcm = {
521 .omap4 = {
522 .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
523 .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
524 .modulemode = MODULEMODE_SWCTRL,
525 },
526 },
527 };
529 /* dcan2 */
530 static struct omap_hwmod dra7xx_dcan2_hwmod = {
531 .name = "dcan2",
532 .class = &dra7xx_dcan_hwmod_class,
533 .clkdm_name = "l4per2_clkdm",
534 .prcm = {
535 .omap4 = {
536 .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
537 .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
538 .modulemode = MODULEMODE_SWCTRL,
539 },
540 },
541 };
543 /* pwmss */
544 static struct omap_hwmod_class_sysconfig dra7xx_epwmss_sysc = {
545 .rev_offs = 0x0,
546 .sysc_offs = 0x4,
547 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_RESET_STATUS,
548 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
549 .sysc_fields = &omap_hwmod_sysc_type2,
550 };
552 struct omap_hwmod_class dra7xx_epwmss_hwmod_class = {
553 .name = "epwmss",
554 .sysc = &dra7xx_epwmss_sysc,
555 };
557 static struct omap_hwmod_class dra7xx_ecap_hwmod_class = {
558 .name = "ecap",
559 };
561 static struct omap_hwmod_class dra7xx_eqep_hwmod_class = {
562 .name = "eqep",
563 };
565 struct omap_hwmod_class dra7xx_ehrpwm_hwmod_class = {
566 .name = "ehrpwm",
567 };
569 /* epwmss0 */
570 struct omap_hwmod dra7xx_epwmss0_hwmod = {
571 .name = "epwmss0",
572 .class = &dra7xx_epwmss_hwmod_class,
573 .clkdm_name = "l4per2_clkdm",
574 .main_clk = "l4_root_clk_div",
575 .prcm = {
576 .omap4 = {
577 .modulemode = MODULEMODE_SWCTRL,
578 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET,
579 .context_offs = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET,
580 },
581 },
582 };
584 /* ecap0 */
585 struct omap_hwmod dra7xx_ecap0_hwmod = {
586 .name = "ecap0",
587 .class = &dra7xx_ecap_hwmod_class,
588 .clkdm_name = "l4per2_clkdm",
589 .main_clk = "l4_root_clk_div",
590 };
592 /* eqep0 */
593 struct omap_hwmod dra7xx_eqep0_hwmod = {
594 .name = "eqep0",
595 .class = &dra7xx_eqep_hwmod_class,
596 .clkdm_name = "l4per2_clkdm",
597 .main_clk = "l4_root_clk_div",
598 };
600 /* ehrpwm0 */
601 struct omap_hwmod dra7xx_ehrpwm0_hwmod = {
602 .name = "ehrpwm0",
603 .class = &dra7xx_ehrpwm_hwmod_class,
604 .clkdm_name = "l4per2_clkdm",
605 .main_clk = "l4_root_clk_div",
606 };
608 /* epwmss1 */
609 struct omap_hwmod dra7xx_epwmss1_hwmod = {
610 .name = "epwmss1",
611 .class = &dra7xx_epwmss_hwmod_class,
612 .clkdm_name = "l4per2_clkdm",
613 .main_clk = "l4_root_clk_div",
614 .prcm = {
615 .omap4 = {
616 .modulemode = MODULEMODE_SWCTRL,
617 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET,
618 .context_offs = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET,
619 },
620 },
621 };
623 /* ecap1 */
624 struct omap_hwmod dra7xx_ecap1_hwmod = {
625 .name = "ecap1",
626 .class = &dra7xx_ecap_hwmod_class,
627 .clkdm_name = "l4per2_clkdm",
628 .main_clk = "l4_root_clk_div",
629 };
631 /* eqep1 */
632 struct omap_hwmod dra7xx_eqep1_hwmod = {
633 .name = "eqep1",
634 .class = &dra7xx_eqep_hwmod_class,
635 .clkdm_name = "l4per2_clkdm",
636 .main_clk = "l4_root_clk_div",
637 };
639 /* ehrpwm1 */
640 struct omap_hwmod dra7xx_ehrpwm1_hwmod = {
641 .name = "ehrpwm1",
642 .class = &dra7xx_ehrpwm_hwmod_class,
643 .clkdm_name = "l4per2_clkdm",
644 .main_clk = "l4_root_clk_div",
645 };
647 /* epwmss2 */
648 struct omap_hwmod dra7xx_epwmss2_hwmod = {
649 .name = "epwmss2",
650 .class = &dra7xx_epwmss_hwmod_class,
651 .clkdm_name = "l4per2_clkdm",
652 .main_clk = "l4_root_clk_div",
653 .prcm = {
654 .omap4 = {
655 .modulemode = MODULEMODE_SWCTRL,
656 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET,
657 .context_offs = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET,
658 },
659 },
660 };
662 /* ecap2 */
663 struct omap_hwmod dra7xx_ecap2_hwmod = {
664 .name = "ecap2",
665 .class = &dra7xx_ecap_hwmod_class,
666 .clkdm_name = "l4per2_clkdm",
667 .main_clk = "l4_root_clk_div",
668 };
670 /* eqep2 */
671 struct omap_hwmod dra7xx_eqep2_hwmod = {
672 .name = "eqep2",
673 .class = &dra7xx_eqep_hwmod_class,
674 .clkdm_name = "l4per2_clkdm",
675 .main_clk = "l4_root_clk_div",
676 };
678 /* ehrpwm2 */
679 struct omap_hwmod dra7xx_ehrpwm2_hwmod = {
680 .name = "ehrpwm2",
681 .class = &dra7xx_ehrpwm_hwmod_class,
682 .clkdm_name = "l4per2_clkdm",
683 .main_clk = "l4_root_clk_div",
684 };
686 /*
687 * 'dma' class
688 *
689 */
691 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
692 .rev_offs = 0x0000,
693 .sysc_offs = 0x002c,
694 .syss_offs = 0x0028,
695 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
696 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
697 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
698 SYSS_HAS_RESET_STATUS),
699 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
700 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
701 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
702 .sysc_fields = &omap_hwmod_sysc_type1,
703 };
705 static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
706 .name = "dma",
707 .sysc = &dra7xx_dma_sysc,
708 };
710 /* dma dev_attr */
711 static struct omap_dma_dev_attr dma_dev_attr = {
712 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
713 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
714 .lch_count = 32,
715 };
717 /* dma_system */
718 static struct omap_hwmod dra7xx_dma_system_hwmod = {
719 .name = "dma_system",
720 .class = &dra7xx_dma_hwmod_class,
721 .clkdm_name = "dma_clkdm",
722 .main_clk = "l3_iclk_div",
723 .prcm = {
724 .omap4 = {
725 .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
726 .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
727 },
728 },
729 .dev_attr = &dma_dev_attr,
730 };
732 /*
733 * 'dsp' class
734 * dsp sub-system
735 */
737 static struct omap_hwmod_class dra7xx_dsp_hwmod_class = {
738 .name = "dsp",
739 };
741 static struct omap_hwmod_rst_info dra7xx_dsp_resets[] = {
742 { .name = "dsp", .rst_shift = 0 },
743 };
745 /* dsp1 processor */
746 static struct omap_hwmod dra7xx_dsp1_hwmod = {
747 .name = "dsp1",
748 .class = &dra7xx_dsp_hwmod_class,
749 .clkdm_name = "dsp1_clkdm",
750 .rst_lines = dra7xx_dsp_resets,
751 .rst_lines_cnt = ARRAY_SIZE(dra7xx_dsp_resets),
752 .main_clk = "dpll_dsp_m2_ck",
753 .prcm = {
754 .omap4 = {
755 .clkctrl_offs = DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET,
756 .rstctrl_offs = DRA7XX_RM_DSP1_RSTCTRL_OFFSET,
757 .context_offs = DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET,
758 },
759 },
760 };
762 /* dsp2 processor */
763 static struct omap_hwmod dra7xx_dsp2_hwmod = {
764 .name = "dsp2",
765 .class = &dra7xx_dsp_hwmod_class,
766 .clkdm_name = "dsp2_clkdm",
767 .rst_lines = dra7xx_dsp_resets,
768 .rst_lines_cnt = ARRAY_SIZE(dra7xx_dsp_resets),
769 .main_clk = "dpll_dsp_m2_ck",
770 .prcm = {
771 .omap4 = {
772 .clkctrl_offs = DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET,
773 .rstctrl_offs = DRA7XX_RM_DSP2_RSTCTRL_OFFSET,
774 .context_offs = DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET,
775 },
776 },
777 };
779 /*
780 * 'dss' class
781 *
782 */
784 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
785 .rev_offs = 0x0000,
786 .syss_offs = 0x0014,
787 .sysc_flags = SYSS_HAS_RESET_STATUS,
788 };
790 static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
791 .name = "dss",
792 .sysc = &dra7xx_dss_sysc,
793 .reset = omap_dss_reset,
794 };
796 /* dss */
797 static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
798 { .dma_req = 75 + DRA7XX_DMA_REQ_START },
799 { .dma_req = -1 }
800 };
802 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
803 { .role = "dss_clk", .clk = "dss_dss_clk" },
804 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
805 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
806 { .role = "video2_clk", .clk = "dss_video2_clk" },
807 { .role = "video1_clk", .clk = "dss_video1_clk" },
808 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
809 };
811 static struct omap_hwmod dra7xx_dss_hwmod = {
812 .name = "dss_core",
813 .class = &dra7xx_dss_hwmod_class,
814 .clkdm_name = "dss_clkdm",
815 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
816 .sdma_reqs = dra7xx_dss_sdma_reqs,
817 .main_clk = "dss_dss_clk",
818 .prcm = {
819 .omap4 = {
820 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
821 .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
822 .modulemode = MODULEMODE_SWCTRL,
823 },
824 },
825 .opt_clks = dss_opt_clks,
826 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
827 };
829 /*
830 * 'dispc' class
831 * display controller
832 */
834 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
835 .rev_offs = 0x0000,
836 .sysc_offs = 0x0010,
837 .syss_offs = 0x0014,
838 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
839 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
840 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
841 SYSS_HAS_RESET_STATUS),
842 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
843 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
844 .sysc_fields = &omap_hwmod_sysc_type1,
845 };
847 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
848 .name = "dispc",
849 .sysc = &dra7xx_dispc_sysc,
850 };
852 /* dss_dispc */
853 /* dss_dispc dev_attr */
854 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
855 .has_framedonetv_irq = 1,
856 .manager_count = 4,
857 };
859 static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
860 .name = "dss_dispc",
861 .class = &dra7xx_dispc_hwmod_class,
862 .clkdm_name = "dss_clkdm",
863 .main_clk = "dss_dss_clk",
864 .prcm = {
865 .omap4 = {
866 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
867 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
868 },
869 },
870 .dev_attr = &dss_dispc_dev_attr,
871 .parent_hwmod = &dra7xx_dss_hwmod,
872 };
874 /*
875 * 'hdmi' class
876 * hdmi controller
877 */
879 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
880 .rev_offs = 0x0000,
881 .sysc_offs = 0x0010,
882 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
883 SYSC_HAS_SOFTRESET),
884 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
885 SIDLE_SMART_WKUP),
886 .sysc_fields = &omap_hwmod_sysc_type2,
887 };
889 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
890 .name = "hdmi",
891 .sysc = &dra7xx_hdmi_sysc,
892 };
894 /* dss_hdmi */
896 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
897 { .role = "sys_clk", .clk = "dss_hdmi_clk" },
898 };
900 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
901 .name = "dss_hdmi",
902 .class = &dra7xx_hdmi_hwmod_class,
903 .clkdm_name = "dss_clkdm",
904 .main_clk = "dss_48mhz_clk",
905 .prcm = {
906 .omap4 = {
907 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
908 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
909 },
910 },
911 .opt_clks = dss_hdmi_opt_clks,
912 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
913 .parent_hwmod = &dra7xx_dss_hwmod,
914 };
916 /* AES (the 'P' (public) device) */
917 static struct omap_hwmod_class_sysconfig dra7xx_aes_sysc = {
918 .rev_offs = 0x0080,
919 .sysc_offs = 0x0084,
920 .syss_offs = 0x0088,
921 .sysc_flags = SYSS_HAS_RESET_STATUS,
922 };
924 static struct omap_hwmod_class dra7xx_aes_hwmod_class = {
925 .name = "aes",
926 .sysc = &dra7xx_aes_sysc,
927 .rev = 2,
928 };
930 /* AES */
931 static struct omap_hwmod dra7xx_aes_hwmod = {
932 .name = "aes",
933 .class = &dra7xx_aes_hwmod_class,
934 .clkdm_name = "l4sec_clkdm",
935 .main_clk = "l3_iclk_div",
936 .prcm = {
937 .omap4 = {
938 .clkctrl_offs = DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET,
939 .context_offs = DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET,
940 .modulemode = MODULEMODE_HWCTRL,
941 },
942 },
943 };
945 /* sha0 HIB2 (the 'P' (public) device) */
946 static struct omap_hwmod_class_sysconfig dra7xx_sha0_sysc = {
947 .rev_offs = 0x100,
948 .sysc_offs = 0x110,
949 .syss_offs = 0x114,
950 .sysc_flags = SYSS_HAS_RESET_STATUS,
951 };
953 static struct omap_hwmod_class dra7xx_sha0_hwmod_class = {
954 .name = "sham",
955 .sysc = &dra7xx_sha0_sysc,
956 .rev = 2,
957 };
959 struct omap_hwmod dra7xx_sha0_hwmod = {
960 .name = "sham",
961 .class = &dra7xx_sha0_hwmod_class,
962 .clkdm_name = "l4sec_clkdm",
963 .main_clk = "l3_iclk_div",
964 .prcm = {
965 .omap4 = {
966 .clkctrl_offs = DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
967 .context_offs = DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
968 .modulemode = MODULEMODE_HWCTRL,
969 },
970 },
971 };
973 /*
974 * 'elm' class
975 *
976 */
978 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
979 .rev_offs = 0x0000,
980 .sysc_offs = 0x0010,
981 .syss_offs = 0x0014,
982 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
983 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
984 SYSS_HAS_RESET_STATUS),
985 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
986 SIDLE_SMART_WKUP),
987 .sysc_fields = &omap_hwmod_sysc_type1,
988 };
990 static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
991 .name = "elm",
992 .sysc = &dra7xx_elm_sysc,
993 };
995 /* elm */
997 static struct omap_hwmod dra7xx_elm_hwmod = {
998 .name = "elm",
999 .class = &dra7xx_elm_hwmod_class,
1000 .clkdm_name = "l4per_clkdm",
1001 .main_clk = "l3_iclk_div",
1002 .prcm = {
1003 .omap4 = {
1004 .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
1005 .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
1006 },
1007 },
1008 };
1010 /*
1011 * 'gpio' class
1012 *
1013 */
1015 static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
1016 .rev_offs = 0x0000,
1017 .sysc_offs = 0x0010,
1018 .syss_offs = 0x0114,
1019 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1020 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1021 SYSS_HAS_RESET_STATUS),
1022 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1023 SIDLE_SMART_WKUP),
1024 .sysc_fields = &omap_hwmod_sysc_type1,
1025 };
1027 static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
1028 .name = "gpio",
1029 .sysc = &dra7xx_gpio_sysc,
1030 .rev = 2,
1031 };
1033 /* gpio dev_attr */
1034 static struct omap_gpio_dev_attr gpio_dev_attr = {
1035 .bank_width = 32,
1036 .dbck_flag = true,
1037 };
1039 /* gpio1 */
1040 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1041 { .role = "dbclk", .clk = "gpio1_dbclk" },
1042 };
1044 static struct omap_hwmod dra7xx_gpio1_hwmod = {
1045 .name = "gpio1",
1046 .class = &dra7xx_gpio_hwmod_class,
1047 .clkdm_name = "wkupaon_clkdm",
1048 .main_clk = "wkupaon_iclk_mux",
1049 .prcm = {
1050 .omap4 = {
1051 .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
1052 .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
1053 .modulemode = MODULEMODE_HWCTRL,
1054 },
1055 },
1056 .opt_clks = gpio1_opt_clks,
1057 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1058 .dev_attr = &gpio_dev_attr,
1059 };
1061 /* gpio2 */
1062 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1063 { .role = "dbclk", .clk = "gpio2_dbclk" },
1064 };
1066 static struct omap_hwmod dra7xx_gpio2_hwmod = {
1067 .name = "gpio2",
1068 .class = &dra7xx_gpio_hwmod_class,
1069 .clkdm_name = "l4per_clkdm",
1070 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1071 .main_clk = "l3_iclk_div",
1072 .prcm = {
1073 .omap4 = {
1074 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1075 .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1076 .modulemode = MODULEMODE_HWCTRL,
1077 },
1078 },
1079 .opt_clks = gpio2_opt_clks,
1080 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1081 .dev_attr = &gpio_dev_attr,
1082 };
1084 /* gpio3 */
1085 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1086 { .role = "dbclk", .clk = "gpio3_dbclk" },
1087 };
1089 static struct omap_hwmod dra7xx_gpio3_hwmod = {
1090 .name = "gpio3",
1091 .class = &dra7xx_gpio_hwmod_class,
1092 .clkdm_name = "l4per_clkdm",
1093 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1094 .main_clk = "l3_iclk_div",
1095 .prcm = {
1096 .omap4 = {
1097 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1098 .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1099 .modulemode = MODULEMODE_HWCTRL,
1100 },
1101 },
1102 .opt_clks = gpio3_opt_clks,
1103 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1104 .dev_attr = &gpio_dev_attr,
1105 };
1107 /* gpio4 */
1108 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1109 { .role = "dbclk", .clk = "gpio4_dbclk" },
1110 };
1112 static struct omap_hwmod dra7xx_gpio4_hwmod = {
1113 .name = "gpio4",
1114 .class = &dra7xx_gpio_hwmod_class,
1115 .clkdm_name = "l4per_clkdm",
1116 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1117 .main_clk = "l3_iclk_div",
1118 .prcm = {
1119 .omap4 = {
1120 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1121 .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1122 .modulemode = MODULEMODE_HWCTRL,
1123 },
1124 },
1125 .opt_clks = gpio4_opt_clks,
1126 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1127 .dev_attr = &gpio_dev_attr,
1128 };
1130 /* gpio5 */
1131 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1132 { .role = "dbclk", .clk = "gpio5_dbclk" },
1133 };
1135 static struct omap_hwmod dra7xx_gpio5_hwmod = {
1136 .name = "gpio5",
1137 .class = &dra7xx_gpio_hwmod_class,
1138 .clkdm_name = "l4per_clkdm",
1139 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1140 .main_clk = "l3_iclk_div",
1141 .prcm = {
1142 .omap4 = {
1143 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1144 .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1145 .modulemode = MODULEMODE_HWCTRL,
1146 },
1147 },
1148 .opt_clks = gpio5_opt_clks,
1149 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1150 .dev_attr = &gpio_dev_attr,
1151 };
1153 /* gpio6 */
1154 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1155 { .role = "dbclk", .clk = "gpio6_dbclk" },
1156 };
1158 static struct omap_hwmod dra7xx_gpio6_hwmod = {
1159 .name = "gpio6",
1160 .class = &dra7xx_gpio_hwmod_class,
1161 .clkdm_name = "l4per_clkdm",
1162 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1163 .main_clk = "l3_iclk_div",
1164 .prcm = {
1165 .omap4 = {
1166 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1167 .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1168 .modulemode = MODULEMODE_HWCTRL,
1169 },
1170 },
1171 .opt_clks = gpio6_opt_clks,
1172 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1173 .dev_attr = &gpio_dev_attr,
1174 };
1176 /* gpio7 */
1177 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
1178 { .role = "dbclk", .clk = "gpio7_dbclk" },
1179 };
1181 static struct omap_hwmod dra7xx_gpio7_hwmod = {
1182 .name = "gpio7",
1183 .class = &dra7xx_gpio_hwmod_class,
1184 .clkdm_name = "l4per_clkdm",
1185 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1186 .main_clk = "l3_iclk_div",
1187 .prcm = {
1188 .omap4 = {
1189 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
1190 .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
1191 .modulemode = MODULEMODE_HWCTRL,
1192 },
1193 },
1194 .opt_clks = gpio7_opt_clks,
1195 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
1196 .dev_attr = &gpio_dev_attr,
1197 };
1199 /* gpio8 */
1200 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
1201 { .role = "dbclk", .clk = "gpio8_dbclk" },
1202 };
1204 static struct omap_hwmod dra7xx_gpio8_hwmod = {
1205 .name = "gpio8",
1206 .class = &dra7xx_gpio_hwmod_class,
1207 .clkdm_name = "l4per_clkdm",
1208 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1209 .main_clk = "l3_iclk_div",
1210 .prcm = {
1211 .omap4 = {
1212 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
1213 .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
1214 .modulemode = MODULEMODE_HWCTRL,
1215 },
1216 },
1217 .opt_clks = gpio8_opt_clks,
1218 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
1219 .dev_attr = &gpio_dev_attr,
1220 };
1222 /*
1223 * 'gpmc' class
1224 *
1225 */
1227 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
1228 .rev_offs = 0x0000,
1229 .sysc_offs = 0x0010,
1230 .syss_offs = 0x0014,
1231 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1232 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1233 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1234 SIDLE_SMART_WKUP),
1235 .sysc_fields = &omap_hwmod_sysc_type1,
1236 };
1238 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
1239 .name = "gpmc",
1240 .sysc = &dra7xx_gpmc_sysc,
1241 };
1243 /* gpmc */
1245 static struct omap_hwmod dra7xx_gpmc_hwmod = {
1246 .name = "gpmc",
1247 .class = &dra7xx_gpmc_hwmod_class,
1248 .clkdm_name = "l3main1_clkdm",
1249 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
1250 HWMOD_SWSUP_SIDLE),
1251 .main_clk = "l3_iclk_div",
1252 .prcm = {
1253 .omap4 = {
1254 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
1255 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
1256 .modulemode = MODULEMODE_HWCTRL,
1257 },
1258 },
1259 };
1261 /*
1262 * 'hdq1w' class
1263 *
1264 */
1266 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
1267 .rev_offs = 0x0000,
1268 .sysc_offs = 0x0014,
1269 .syss_offs = 0x0018,
1270 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1271 SYSS_HAS_RESET_STATUS),
1272 .sysc_fields = &omap_hwmod_sysc_type1,
1273 };
1275 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
1276 .name = "hdq1w",
1277 .sysc = &dra7xx_hdq1w_sysc,
1278 };
1280 /* hdq1w */
1282 static struct omap_hwmod dra7xx_hdq1w_hwmod = {
1283 .name = "hdq1w",
1284 .class = &dra7xx_hdq1w_hwmod_class,
1285 .clkdm_name = "l4per_clkdm",
1286 .flags = HWMOD_INIT_NO_RESET,
1287 .main_clk = "func_12m_fclk",
1288 .prcm = {
1289 .omap4 = {
1290 .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1291 .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1292 .modulemode = MODULEMODE_SWCTRL,
1293 },
1294 },
1295 };
1297 /*
1298 * 'i2c' class
1299 *
1300 */
1302 static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
1303 .sysc_offs = 0x0010,
1304 .syss_offs = 0x0090,
1305 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1306 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1307 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1308 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1309 SIDLE_SMART_WKUP),
1310 .clockact = CLOCKACT_TEST_ICLK,
1311 .sysc_fields = &omap_hwmod_sysc_type1,
1312 };
1314 static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
1315 .name = "i2c",
1316 .sysc = &dra7xx_i2c_sysc,
1317 .reset = &omap_i2c_reset,
1318 .rev = OMAP_I2C_IP_VERSION_2,
1319 };
1321 /* i2c dev_attr */
1322 static struct omap_i2c_dev_attr i2c_dev_attr = {
1323 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1324 };
1326 /* i2c1 */
1327 static struct omap_hwmod dra7xx_i2c1_hwmod = {
1328 .name = "i2c1",
1329 .class = &dra7xx_i2c_hwmod_class,
1330 .clkdm_name = "l4per_clkdm",
1331 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1332 .main_clk = "func_96m_fclk",
1333 .prcm = {
1334 .omap4 = {
1335 .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1336 .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
1337 .modulemode = MODULEMODE_SWCTRL,
1338 },
1339 },
1340 .dev_attr = &i2c_dev_attr,
1341 };
1343 /* i2c2 */
1344 static struct omap_hwmod dra7xx_i2c2_hwmod = {
1345 .name = "i2c2",
1346 .class = &dra7xx_i2c_hwmod_class,
1347 .clkdm_name = "l4per_clkdm",
1348 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1349 .main_clk = "func_96m_fclk",
1350 .prcm = {
1351 .omap4 = {
1352 .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1353 .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
1354 .modulemode = MODULEMODE_SWCTRL,
1355 },
1356 },
1357 .dev_attr = &i2c_dev_attr,
1358 };
1360 /* i2c3 */
1361 static struct omap_hwmod dra7xx_i2c3_hwmod = {
1362 .name = "i2c3",
1363 .class = &dra7xx_i2c_hwmod_class,
1364 .clkdm_name = "l4per_clkdm",
1365 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1366 .main_clk = "func_96m_fclk",
1367 .prcm = {
1368 .omap4 = {
1369 .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1370 .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
1371 .modulemode = MODULEMODE_SWCTRL,
1372 },
1373 },
1374 .dev_attr = &i2c_dev_attr,
1375 };
1377 /* i2c4 */
1378 static struct omap_hwmod dra7xx_i2c4_hwmod = {
1379 .name = "i2c4",
1380 .class = &dra7xx_i2c_hwmod_class,
1381 .clkdm_name = "l4per_clkdm",
1382 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1383 .main_clk = "func_96m_fclk",
1384 .prcm = {
1385 .omap4 = {
1386 .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1387 .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
1388 .modulemode = MODULEMODE_SWCTRL,
1389 },
1390 },
1391 .dev_attr = &i2c_dev_attr,
1392 };
1394 /* i2c5 */
1395 static struct omap_hwmod dra7xx_i2c5_hwmod = {
1396 .name = "i2c5",
1397 .class = &dra7xx_i2c_hwmod_class,
1398 .clkdm_name = "ipu_clkdm",
1399 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1400 .main_clk = "func_96m_fclk",
1401 .prcm = {
1402 .omap4 = {
1403 .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
1404 .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
1405 .modulemode = MODULEMODE_SWCTRL,
1406 },
1407 },
1408 .dev_attr = &i2c_dev_attr,
1409 };
1411 /*
1412 * 'ipu' class
1413 * imaging processor unit
1414 */
1416 static struct omap_hwmod_class dra7xx_ipu_hwmod_class = {
1417 .name = "ipu",
1418 };
1420 static struct omap_hwmod_rst_info dra7xx_ipu_resets[] = {
1421 { .name = "cpu0", .rst_shift = 0 },
1422 { .name = "cpu1", .rst_shift = 1 },
1423 };
1425 /* ipu1 processor */
1426 static struct omap_hwmod dra7xx_ipu1_hwmod = {
1427 .name = "ipu1",
1428 .class = &dra7xx_ipu_hwmod_class,
1429 .clkdm_name = "ipu1_clkdm",
1430 .rst_lines = dra7xx_ipu_resets,
1431 .rst_lines_cnt = ARRAY_SIZE(dra7xx_ipu_resets),
1432 .main_clk = "ipu1_gfclk_mux",
1433 .prcm = {
1434 .omap4 = {
1435 .clkctrl_offs = DRA7XX_CM_IPU1_IPU1_CLKCTRL_OFFSET,
1436 .rstctrl_offs = DRA7XX_RM_IPU1_RSTCTRL_OFFSET,
1437 .context_offs = DRA7XX_RM_IPU1_IPU1_CONTEXT_OFFSET,
1438 },
1439 },
1440 };
1442 /* ipu2 processor */
1443 static struct omap_hwmod dra7xx_ipu2_hwmod = {
1444 .name = "ipu2",
1445 .class = &dra7xx_ipu_hwmod_class,
1446 .clkdm_name = "ipu2_clkdm",
1447 .rst_lines = dra7xx_ipu_resets,
1448 .rst_lines_cnt = ARRAY_SIZE(dra7xx_ipu_resets),
1449 .main_clk = "dpll_core_h22x2_ck",
1450 .prcm = {
1451 .omap4 = {
1452 .clkctrl_offs = DRA7XX_CM_IPU2_IPU2_CLKCTRL_OFFSET,
1453 .rstctrl_offs = DRA7XX_RM_IPU2_RSTCTRL_OFFSET,
1454 .context_offs = DRA7XX_RM_IPU2_IPU2_CONTEXT_OFFSET,
1455 },
1456 },
1457 };
1459 /*
1460 * 'mailbox' class
1461 *
1462 */
1464 static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
1465 .rev_offs = 0x0000,
1466 .sysc_offs = 0x0010,
1467 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1468 SYSC_HAS_SOFTRESET),
1469 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1470 .sysc_fields = &omap_hwmod_sysc_type2,
1471 };
1473 static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
1474 .name = "mailbox",
1475 .sysc = &dra7xx_mailbox_sysc,
1476 };
1478 /* mailbox1 */
1479 static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1480 .name = "mailbox1",
1481 .class = &dra7xx_mailbox_hwmod_class,
1482 .clkdm_name = "l4cfg_clkdm",
1483 .prcm = {
1484 .omap4 = {
1485 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1486 .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1487 },
1488 },
1489 };
1491 /* mailbox2 */
1492 static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1493 .name = "mailbox2",
1494 .class = &dra7xx_mailbox_hwmod_class,
1495 .clkdm_name = "l4cfg_clkdm",
1496 .prcm = {
1497 .omap4 = {
1498 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1499 .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1500 },
1501 },
1502 };
1504 /* mailbox3 */
1505 static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1506 .name = "mailbox3",
1507 .class = &dra7xx_mailbox_hwmod_class,
1508 .clkdm_name = "l4cfg_clkdm",
1509 .prcm = {
1510 .omap4 = {
1511 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1512 .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1513 },
1514 },
1515 };
1517 /* mailbox4 */
1518 static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1519 .name = "mailbox4",
1520 .class = &dra7xx_mailbox_hwmod_class,
1521 .clkdm_name = "l4cfg_clkdm",
1522 .prcm = {
1523 .omap4 = {
1524 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1525 .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1526 },
1527 },
1528 };
1530 /* mailbox5 */
1531 static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1532 .name = "mailbox5",
1533 .class = &dra7xx_mailbox_hwmod_class,
1534 .clkdm_name = "l4cfg_clkdm",
1535 .prcm = {
1536 .omap4 = {
1537 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1538 .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1539 },
1540 },
1541 };
1543 /* mailbox6 */
1544 static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1545 .name = "mailbox6",
1546 .class = &dra7xx_mailbox_hwmod_class,
1547 .clkdm_name = "l4cfg_clkdm",
1548 .prcm = {
1549 .omap4 = {
1550 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1551 .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1552 },
1553 },
1554 };
1556 /* mailbox7 */
1557 static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1558 .name = "mailbox7",
1559 .class = &dra7xx_mailbox_hwmod_class,
1560 .clkdm_name = "l4cfg_clkdm",
1561 .prcm = {
1562 .omap4 = {
1563 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1564 .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1565 },
1566 },
1567 };
1569 /* mailbox8 */
1570 static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1571 .name = "mailbox8",
1572 .class = &dra7xx_mailbox_hwmod_class,
1573 .clkdm_name = "l4cfg_clkdm",
1574 .prcm = {
1575 .omap4 = {
1576 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1577 .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1578 },
1579 },
1580 };
1582 /* mailbox9 */
1583 static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1584 .name = "mailbox9",
1585 .class = &dra7xx_mailbox_hwmod_class,
1586 .clkdm_name = "l4cfg_clkdm",
1587 .prcm = {
1588 .omap4 = {
1589 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1590 .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1591 },
1592 },
1593 };
1595 /* mailbox10 */
1596 static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1597 .name = "mailbox10",
1598 .class = &dra7xx_mailbox_hwmod_class,
1599 .clkdm_name = "l4cfg_clkdm",
1600 .prcm = {
1601 .omap4 = {
1602 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1603 .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1604 },
1605 },
1606 };
1608 /* mailbox11 */
1609 static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1610 .name = "mailbox11",
1611 .class = &dra7xx_mailbox_hwmod_class,
1612 .clkdm_name = "l4cfg_clkdm",
1613 .prcm = {
1614 .omap4 = {
1615 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1616 .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1617 },
1618 },
1619 };
1621 /* mailbox12 */
1622 static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1623 .name = "mailbox12",
1624 .class = &dra7xx_mailbox_hwmod_class,
1625 .clkdm_name = "l4cfg_clkdm",
1626 .prcm = {
1627 .omap4 = {
1628 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1629 .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1630 },
1631 },
1632 };
1634 /* mailbox13 */
1635 static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1636 .name = "mailbox13",
1637 .class = &dra7xx_mailbox_hwmod_class,
1638 .clkdm_name = "l4cfg_clkdm",
1639 .prcm = {
1640 .omap4 = {
1641 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1642 .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1643 },
1644 },
1645 };
1647 /*
1648 * 'mcspi' class
1649 *
1650 */
1652 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1653 .rev_offs = 0x0000,
1654 .sysc_offs = 0x0010,
1655 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1656 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1657 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1658 SIDLE_SMART_WKUP),
1659 .sysc_fields = &omap_hwmod_sysc_type2,
1660 };
1662 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1663 .name = "mcspi",
1664 .sysc = &dra7xx_mcspi_sysc,
1665 .rev = OMAP4_MCSPI_REV,
1666 };
1668 /* mcspi1 */
1669 /* mcspi1 dev_attr */
1670 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1671 .num_chipselect = 4,
1672 };
1674 static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1675 .name = "mcspi1",
1676 .class = &dra7xx_mcspi_hwmod_class,
1677 .clkdm_name = "l4per_clkdm",
1678 .main_clk = "func_48m_fclk",
1679 .prcm = {
1680 .omap4 = {
1681 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1682 .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1683 .modulemode = MODULEMODE_SWCTRL,
1684 },
1685 },
1686 .dev_attr = &mcspi1_dev_attr,
1687 };
1689 /* mcspi2 */
1690 /* mcspi2 dev_attr */
1691 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1692 .num_chipselect = 2,
1693 };
1695 static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1696 .name = "mcspi2",
1697 .class = &dra7xx_mcspi_hwmod_class,
1698 .clkdm_name = "l4per_clkdm",
1699 .main_clk = "func_48m_fclk",
1700 .prcm = {
1701 .omap4 = {
1702 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1703 .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1704 .modulemode = MODULEMODE_SWCTRL,
1705 },
1706 },
1707 .dev_attr = &mcspi2_dev_attr,
1708 };
1710 /* mcspi3 */
1711 /* mcspi3 dev_attr */
1712 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1713 .num_chipselect = 2,
1714 };
1716 static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1717 .name = "mcspi3",
1718 .class = &dra7xx_mcspi_hwmod_class,
1719 .clkdm_name = "l4per_clkdm",
1720 .main_clk = "func_48m_fclk",
1721 .prcm = {
1722 .omap4 = {
1723 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1724 .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1725 .modulemode = MODULEMODE_SWCTRL,
1726 },
1727 },
1728 .dev_attr = &mcspi3_dev_attr,
1729 };
1731 /* mcspi4 */
1732 /* mcspi4 dev_attr */
1733 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1734 .num_chipselect = 1,
1735 };
1737 static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1738 .name = "mcspi4",
1739 .class = &dra7xx_mcspi_hwmod_class,
1740 .clkdm_name = "l4per_clkdm",
1741 .main_clk = "func_48m_fclk",
1742 .prcm = {
1743 .omap4 = {
1744 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1745 .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1746 .modulemode = MODULEMODE_SWCTRL,
1747 },
1748 },
1749 .dev_attr = &mcspi4_dev_attr,
1750 };
1752 /*
1753 * 'mcasp' class
1754 *
1755 */
1756 static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc = {
1757 .sysc_offs = 0x0004,
1758 .sysc_flags = SYSC_HAS_SIDLEMODE,
1759 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1760 .sysc_fields = &omap_hwmod_sysc_type3,
1761 };
1763 static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
1764 .name = "mcasp",
1765 .sysc = &dra7xx_mcasp_sysc,
1766 };
1768 /* mcasp3 */
1769 static struct omap_hwmod dra7xx_mcasp3_hwmod = {
1770 .name = "mcasp3",
1771 .class = &dra7xx_mcasp_hwmod_class,
1772 .clkdm_name = "l4per2_clkdm",
1773 .main_clk = "mcasp3_ahclkx_mux",
1774 .flags = HWMOD_SWSUP_SIDLE,
1775 .prcm = {
1776 .omap4 = {
1777 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET,
1778 .context_offs = DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET,
1779 .modulemode = MODULEMODE_SWCTRL,
1780 },
1781 },
1782 };
1784 /*
1785 * 'mmc' class
1786 *
1787 */
1789 static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1790 .rev_offs = 0x0000,
1791 .sysc_offs = 0x0010,
1792 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1793 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1794 SYSC_HAS_SOFTRESET),
1795 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1796 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1797 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1798 .sysc_fields = &omap_hwmod_sysc_type2,
1799 };
1801 static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1802 .name = "mmc",
1803 .sysc = &dra7xx_mmc_sysc,
1804 };
1806 /* mmc1 */
1807 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1808 { .role = "clk32k", .clk = "mmc1_clk32k" },
1809 };
1811 /* mmc1 dev_attr */
1812 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1813 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1814 };
1816 static struct omap_hwmod dra7xx_mmc1_hwmod = {
1817 .name = "mmc1",
1818 .class = &dra7xx_mmc_hwmod_class,
1819 .clkdm_name = "l3init_clkdm",
1820 .main_clk = "mmc1_fclk_div",
1821 .prcm = {
1822 .omap4 = {
1823 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1824 .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1825 .modulemode = MODULEMODE_SWCTRL,
1826 },
1827 },
1828 .opt_clks = mmc1_opt_clks,
1829 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1830 .dev_attr = &mmc1_dev_attr,
1831 };
1833 /* mmc2 */
1834 static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1835 { .role = "clk32k", .clk = "mmc2_clk32k" },
1836 };
1838 static struct omap_hwmod dra7xx_mmc2_hwmod = {
1839 .name = "mmc2",
1840 .class = &dra7xx_mmc_hwmod_class,
1841 .clkdm_name = "l3init_clkdm",
1842 .main_clk = "mmc2_fclk_div",
1843 .prcm = {
1844 .omap4 = {
1845 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1846 .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1847 .modulemode = MODULEMODE_SWCTRL,
1848 },
1849 },
1850 .opt_clks = mmc2_opt_clks,
1851 .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks),
1852 };
1854 /* mmc3 */
1855 static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1856 { .role = "clk32k", .clk = "mmc3_clk32k" },
1857 };
1859 static struct omap_hwmod dra7xx_mmc3_hwmod = {
1860 .name = "mmc3",
1861 .class = &dra7xx_mmc_hwmod_class,
1862 .clkdm_name = "l4per_clkdm",
1863 .main_clk = "mmc3_gfclk_div",
1864 .prcm = {
1865 .omap4 = {
1866 .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1867 .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1868 .modulemode = MODULEMODE_SWCTRL,
1869 },
1870 },
1871 .opt_clks = mmc3_opt_clks,
1872 .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks),
1873 };
1875 /* mmc4 */
1876 static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1877 { .role = "clk32k", .clk = "mmc4_clk32k" },
1878 };
1880 static struct omap_hwmod dra7xx_mmc4_hwmod = {
1881 .name = "mmc4",
1882 .class = &dra7xx_mmc_hwmod_class,
1883 .clkdm_name = "l4per_clkdm",
1884 .main_clk = "mmc4_gfclk_div",
1885 .prcm = {
1886 .omap4 = {
1887 .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1888 .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1889 .modulemode = MODULEMODE_SWCTRL,
1890 },
1891 },
1892 .opt_clks = mmc4_opt_clks,
1893 .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks),
1894 };
1896 /*
1897 * 'mmu' class
1898 * The memory management unit performs virtual to physical address translation
1899 * for its requestors.
1900 */
1902 static struct omap_hwmod_class_sysconfig dra7xx_mmu_sysc = {
1903 .rev_offs = 0x0000,
1904 .sysc_offs = 0x0010,
1905 .syss_offs = 0x0014,
1906 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1907 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1908 SYSS_HAS_RESET_STATUS),
1909 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1910 .sysc_fields = &omap_hwmod_sysc_type1,
1911 };
1913 static struct omap_hwmod_class dra7xx_mmu_hwmod_class = {
1914 .name = "mmu",
1915 .sysc = &dra7xx_mmu_sysc,
1916 };
1918 /* DSP MMUs */
1919 static struct omap_hwmod_rst_info dra7xx_mmu_dsp_resets[] = {
1920 { .name = "mmu_cache", .rst_shift = 1 },
1921 };
1923 /* mmu0 - dsp1 */
1924 static struct omap_hwmod dra7xx_mmu0_dsp1_hwmod = {
1925 .name = "mmu0_dsp1",
1926 .class = &dra7xx_mmu_hwmod_class,
1927 .clkdm_name = "dsp1_clkdm",
1928 .rst_lines = dra7xx_mmu_dsp_resets,
1929 .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_dsp_resets),
1930 .main_clk = "dpll_dsp_m2_ck",
1931 .prcm = {
1932 .omap4 = {
1933 .clkctrl_offs = DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET,
1934 .rstctrl_offs = DRA7XX_RM_DSP1_RSTCTRL_OFFSET,
1935 .context_offs = DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET,
1936 .modulemode = MODULEMODE_HWCTRL,
1937 },
1938 },
1939 };
1941 /* mmu1 - dsp1 */
1942 static struct omap_hwmod dra7xx_mmu1_dsp1_hwmod = {
1943 .name = "mmu1_dsp1",
1944 .class = &dra7xx_mmu_hwmod_class,
1945 .clkdm_name = "dsp1_clkdm",
1946 .rst_lines = dra7xx_mmu_dsp_resets,
1947 .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_dsp_resets),
1948 .main_clk = "dpll_dsp_m2_ck",
1949 .prcm = {
1950 .omap4 = {
1951 .clkctrl_offs = DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET,
1952 .rstctrl_offs = DRA7XX_RM_DSP1_RSTCTRL_OFFSET,
1953 .context_offs = DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET,
1954 .modulemode = MODULEMODE_HWCTRL,
1955 },
1956 },
1957 };
1959 /* mmu0 - dsp2 */
1960 static struct omap_hwmod dra7xx_mmu0_dsp2_hwmod = {
1961 .name = "mmu0_dsp2",
1962 .class = &dra7xx_mmu_hwmod_class,
1963 .clkdm_name = "dsp2_clkdm",
1964 .rst_lines = dra7xx_mmu_dsp_resets,
1965 .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_dsp_resets),
1966 .main_clk = "dpll_dsp_m2_ck",
1967 .prcm = {
1968 .omap4 = {
1969 .clkctrl_offs = DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET,
1970 .rstctrl_offs = DRA7XX_RM_DSP2_RSTCTRL_OFFSET,
1971 .context_offs = DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET,
1972 .modulemode = MODULEMODE_HWCTRL,
1973 },
1974 },
1975 };
1977 /* mmu1 - dsp2 */
1978 static struct omap_hwmod dra7xx_mmu1_dsp2_hwmod = {
1979 .name = "mmu1_dsp2",
1980 .class = &dra7xx_mmu_hwmod_class,
1981 .clkdm_name = "dsp2_clkdm",
1982 .rst_lines = dra7xx_mmu_dsp_resets,
1983 .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_dsp_resets),
1984 .main_clk = "dpll_dsp_m2_ck",
1985 .prcm = {
1986 .omap4 = {
1987 .clkctrl_offs = DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET,
1988 .rstctrl_offs = DRA7XX_RM_DSP2_RSTCTRL_OFFSET,
1989 .context_offs = DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET,
1990 .modulemode = MODULEMODE_HWCTRL,
1991 },
1992 },
1993 };
1995 /* IPU MMUs */
1996 static struct omap_hwmod_rst_info dra7xx_mmu_ipu_resets[] = {
1997 { .name = "mmu_cache", .rst_shift = 2 },
1998 };
2000 /* mmu ipu1 */
2001 static struct omap_hwmod dra7xx_mmu_ipu1_hwmod = {
2002 .name = "mmu_ipu1",
2003 .class = &dra7xx_mmu_hwmod_class,
2004 .clkdm_name = "ipu1_clkdm",
2005 .rst_lines = dra7xx_mmu_ipu_resets,
2006 .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_ipu_resets),
2007 .main_clk = "ipu1_gfclk_mux",
2008 .prcm = {
2009 .omap4 = {
2010 .clkctrl_offs = DRA7XX_CM_IPU1_IPU1_CLKCTRL_OFFSET,
2011 .rstctrl_offs = DRA7XX_RM_IPU1_RSTCTRL_OFFSET,
2012 .context_offs = DRA7XX_RM_IPU1_IPU1_CONTEXT_OFFSET,
2013 .modulemode = MODULEMODE_HWCTRL,
2014 },
2015 },
2016 };
2018 /* mmu ipu2 */
2019 static struct omap_hwmod dra7xx_mmu_ipu2_hwmod = {
2020 .name = "mmu_ipu2",
2021 .class = &dra7xx_mmu_hwmod_class,
2022 .clkdm_name = "ipu2_clkdm",
2023 .rst_lines = dra7xx_mmu_ipu_resets,
2024 .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_ipu_resets),
2025 .main_clk = "dpll_core_h22x2_ck",
2026 .prcm = {
2027 .omap4 = {
2028 .clkctrl_offs = DRA7XX_CM_IPU2_IPU2_CLKCTRL_OFFSET,
2029 .rstctrl_offs = DRA7XX_RM_IPU2_RSTCTRL_OFFSET,
2030 .context_offs = DRA7XX_RM_IPU2_IPU2_CONTEXT_OFFSET,
2031 .modulemode = MODULEMODE_HWCTRL,
2032 },
2033 },
2034 };
2036 /*
2037 * 'mpu' class
2038 *
2039 */
2041 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
2042 .name = "mpu",
2043 };
2045 /* mpu */
2046 static struct omap_hwmod dra7xx_mpu_hwmod = {
2047 .name = "mpu",
2048 .class = &dra7xx_mpu_hwmod_class,
2049 .clkdm_name = "mpu_clkdm",
2050 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2051 .main_clk = "dpll_mpu_m2_ck",
2052 .prcm = {
2053 .omap4 = {
2054 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
2055 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
2056 },
2057 },
2058 };
2060 /*
2061 * 'ocp2scp' class
2062 *
2063 */
2065 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
2066 .rev_offs = 0x0000,
2067 .sysc_offs = 0x0010,
2068 .syss_offs = 0x0014,
2069 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2070 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2071 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2072 SIDLE_SMART_WKUP),
2073 .sysc_fields = &omap_hwmod_sysc_type1,
2074 };
2076 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
2077 .name = "ocp2scp",
2078 .sysc = &dra7xx_ocp2scp_sysc,
2079 };
2081 /* ocp2scp1 */
2082 static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
2083 .name = "ocp2scp1",
2084 .class = &dra7xx_ocp2scp_hwmod_class,
2085 .clkdm_name = "l3init_clkdm",
2086 .main_clk = "l4_root_clk_div",
2087 .prcm = {
2088 .omap4 = {
2089 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
2090 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
2091 .modulemode = MODULEMODE_HWCTRL,
2092 },
2093 },
2094 };
2096 /* ocp2scp3 */
2097 static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
2098 .name = "ocp2scp3",
2099 .class = &dra7xx_ocp2scp_hwmod_class,
2100 .clkdm_name = "l3init_clkdm",
2101 .main_clk = "l4_root_clk_div",
2102 .prcm = {
2103 .omap4 = {
2104 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
2105 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
2106 .modulemode = MODULEMODE_HWCTRL,
2107 },
2108 },
2109 };
2111 /*
2112 * 'PCIE' class
2113 *
2114 */
2116 static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
2117 .name = "pcie",
2118 };
2120 /* pcie1 */
2121 static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = {
2122 { .name = "pcie", .rst_shift = 0 },
2123 };
2125 static struct omap_hwmod dra7xx_pciess1_hwmod = {
2126 .name = "pcie1",
2127 .class = &dra7xx_pciess_hwmod_class,
2128 .clkdm_name = "pcie_clkdm",
2129 .rst_lines = dra7xx_pciess1_resets,
2130 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess1_resets),
2131 .main_clk = "l4_root_clk_div",
2132 .prcm = {
2133 .omap4 = {
2134 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
2135 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
2136 .rstctrl_offs = DRA7XX_RM_L3INIT_RSTCTRL_OFFSET,
2137 .modulemode = MODULEMODE_SWCTRL,
2138 },
2139 },
2140 };
2142 /* pcie2 */
2143 static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = {
2144 { .name = "pcie", .rst_shift = 1 },
2145 };
2147 static struct omap_hwmod dra7xx_pciess2_hwmod = {
2148 .name = "pcie2",
2149 .class = &dra7xx_pciess_hwmod_class,
2150 .clkdm_name = "pcie_clkdm",
2151 .rst_lines = dra7xx_pciess2_resets,
2152 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess2_resets),
2153 .main_clk = "l4_root_clk_div",
2154 .prcm = {
2155 .omap4 = {
2156 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
2157 .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
2158 .rstctrl_offs = DRA7XX_RM_L3INIT_RSTCTRL_OFFSET,
2159 .modulemode = MODULEMODE_SWCTRL,
2160 },
2161 },
2162 };
2164 /*
2165 * 'pru-icss' class
2166 * Programmable Real-Time Unit and Industrial Communication Subsystem
2167 */
2168 static struct omap_hwmod_class dra7xx_pruss_hwmod_class = {
2169 .name = "pruss",
2170 };
2172 /* pru-icss1 */
2173 static struct omap_hwmod dra7xx_pruss1_hwmod = {
2174 .name = "pruss1",
2175 .class = &dra7xx_pruss_hwmod_class,
2176 .clkdm_name = "l4per2_clkdm",
2177 .prcm = {
2178 .omap4 = {
2179 .clkctrl_offs = DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL_OFFSET,
2180 .context_offs = DRA7XX_RM_L4PER2_PRUSS1_CONTEXT_OFFSET,
2181 .modulemode = MODULEMODE_SWCTRL,
2182 },
2183 },
2184 };
2186 /* pru-icss2 */
2187 static struct omap_hwmod dra7xx_pruss2_hwmod = {
2188 .name = "pruss2",
2189 .class = &dra7xx_pruss_hwmod_class,
2190 .clkdm_name = "l4per2_clkdm",
2191 .prcm = {
2192 .omap4 = {
2193 .clkctrl_offs = DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL_OFFSET,
2194 .context_offs = DRA7XX_RM_L4PER2_PRUSS2_CONTEXT_OFFSET,
2195 .modulemode = MODULEMODE_SWCTRL,
2196 },
2197 },
2198 };
2200 /*
2201 * 'qspi' class
2202 *
2203 */
2205 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
2206 .sysc_offs = 0x0010,
2207 .sysc_flags = SYSC_HAS_SIDLEMODE,
2208 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2209 SIDLE_SMART_WKUP),
2210 .sysc_fields = &omap_hwmod_sysc_type2,
2211 };
2213 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
2214 .name = "qspi",
2215 .sysc = &dra7xx_qspi_sysc,
2216 };
2218 /* qspi */
2219 static struct omap_hwmod dra7xx_qspi_hwmod = {
2220 .name = "qspi",
2221 .class = &dra7xx_qspi_hwmod_class,
2222 .clkdm_name = "l4per2_clkdm",
2223 .main_clk = "qspi_gfclk_div",
2224 .prcm = {
2225 .omap4 = {
2226 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
2227 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
2228 .modulemode = MODULEMODE_SWCTRL,
2229 },
2230 },
2231 };
2233 /*
2234 * 'rtcss' class
2235 *
2236 */
2237 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
2238 .sysc_offs = 0x0078,
2239 .sysc_flags = SYSC_HAS_SIDLEMODE,
2240 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2241 SIDLE_SMART_WKUP),
2242 .sysc_fields = &omap_hwmod_sysc_type3,
2243 };
2245 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
2246 .name = "rtcss",
2247 .sysc = &dra7xx_rtcss_sysc,
2248 .reset = &omap_hwmod_rtc_unlock,
2249 };
2251 /* rtcss */
2252 static struct omap_hwmod dra7xx_rtcss_hwmod = {
2253 .name = "rtcss",
2254 .class = &dra7xx_rtcss_hwmod_class,
2255 .clkdm_name = "rtc_clkdm",
2256 .main_clk = "sys_32k_ck",
2257 .prcm = {
2258 .omap4 = {
2259 .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
2260 .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
2261 .modulemode = MODULEMODE_SWCTRL,
2262 },
2263 },
2264 };
2266 /*
2267 * 'sata' class
2268 *
2269 */
2271 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
2272 .sysc_offs = 0x0000,
2273 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
2274 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2275 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2276 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2277 .sysc_fields = &omap_hwmod_sysc_type2,
2278 };
2280 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
2281 .name = "sata",
2282 .sysc = &dra7xx_sata_sysc,
2283 };
2285 /* sata */
2287 static struct omap_hwmod dra7xx_sata_hwmod = {
2288 .name = "sata",
2289 .class = &dra7xx_sata_hwmod_class,
2290 .clkdm_name = "l3init_clkdm",
2291 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2292 .main_clk = "func_48m_fclk",
2293 .mpu_rt_idx = 1,
2294 .prcm = {
2295 .omap4 = {
2296 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
2297 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
2298 .modulemode = MODULEMODE_SWCTRL,
2299 },
2300 },
2301 };
2303 /*
2304 * 'smartreflex' class
2305 *
2306 */
2308 /* The IP is not compliant to type1 / type2 scheme */
2309 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2310 .sidle_shift = 24,
2311 .enwkup_shift = 26,
2312 };
2314 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
2315 .sysc_offs = 0x0038,
2316 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2317 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2318 SIDLE_SMART_WKUP),
2319 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
2320 };
2322 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
2323 .name = "smartreflex",
2324 .sysc = &dra7xx_smartreflex_sysc,
2325 .rev = 2,
2326 };
2328 /* smartreflex_core */
2329 /* smartreflex_core dev_attr */
2330 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2331 .sensor_voltdm_name = "core",
2332 };
2334 static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
2335 .name = "smartreflex_core",
2336 .class = &dra7xx_smartreflex_hwmod_class,
2337 .clkdm_name = "coreaon_clkdm",
2338 .main_clk = "wkupaon_iclk_mux",
2339 .prcm = {
2340 .omap4 = {
2341 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
2342 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
2343 .modulemode = MODULEMODE_SWCTRL,
2344 },
2345 },
2346 .dev_attr = &smartreflex_core_dev_attr,
2347 };
2349 /* smartreflex_mpu */
2350 /* smartreflex_mpu dev_attr */
2351 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2352 .sensor_voltdm_name = "mpu",
2353 };
2355 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
2356 .name = "smartreflex_mpu",
2357 .class = &dra7xx_smartreflex_hwmod_class,
2358 .clkdm_name = "coreaon_clkdm",
2359 .main_clk = "wkupaon_iclk_mux",
2360 .prcm = {
2361 .omap4 = {
2362 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
2363 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
2364 .modulemode = MODULEMODE_SWCTRL,
2365 },
2366 },
2367 .dev_attr = &smartreflex_mpu_dev_attr,
2368 };
2370 /*
2371 * 'spinlock' class
2372 *
2373 */
2375 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
2376 .rev_offs = 0x0000,
2377 .sysc_offs = 0x0010,
2378 .syss_offs = 0x0014,
2379 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2380 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2381 SYSS_HAS_RESET_STATUS),
2382 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2383 .sysc_fields = &omap_hwmod_sysc_type1,
2384 };
2386 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
2387 .name = "spinlock",
2388 .sysc = &dra7xx_spinlock_sysc,
2389 };
2391 /* spinlock */
2392 static struct omap_hwmod dra7xx_spinlock_hwmod = {
2393 .name = "spinlock",
2394 .class = &dra7xx_spinlock_hwmod_class,
2395 .clkdm_name = "l4cfg_clkdm",
2396 .main_clk = "l3_iclk_div",
2397 .prcm = {
2398 .omap4 = {
2399 .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
2400 .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
2401 },
2402 },
2403 };
2405 /*
2406 * 'timer' class
2407 *
2408 * This class contains several variants: ['timer_1ms', 'timer_secure',
2409 * 'timer']
2410 */
2412 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
2413 .rev_offs = 0x0000,
2414 .sysc_offs = 0x0010,
2415 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2416 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2417 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2418 SIDLE_SMART_WKUP),
2419 .sysc_fields = &omap_hwmod_sysc_type2,
2420 };
2422 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
2423 .name = "timer",
2424 .sysc = &dra7xx_timer_1ms_sysc,
2425 };
2427 static struct omap_hwmod_class_sysconfig dra7xx_timer_secure_sysc = {
2428 .rev_offs = 0x0000,
2429 .sysc_offs = 0x0010,
2430 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2431 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2432 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2433 SIDLE_SMART_WKUP),
2434 .sysc_fields = &omap_hwmod_sysc_type2,
2435 };
2437 static struct omap_hwmod_class dra7xx_timer_secure_hwmod_class = {
2438 .name = "timer",
2439 .sysc = &dra7xx_timer_secure_sysc,
2440 };
2442 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
2443 .rev_offs = 0x0000,
2444 .sysc_offs = 0x0010,
2445 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2446 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2447 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2448 SIDLE_SMART_WKUP),
2449 .sysc_fields = &omap_hwmod_sysc_type2,
2450 };
2452 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
2453 .name = "timer",
2454 .sysc = &dra7xx_timer_sysc,
2455 };
2457 /* timer1 */
2458 static struct omap_hwmod dra7xx_timer1_hwmod = {
2459 .name = "timer1",
2460 .class = &dra7xx_timer_1ms_hwmod_class,
2461 .clkdm_name = "wkupaon_clkdm",
2462 .main_clk = "timer1_gfclk_mux",
2463 .prcm = {
2464 .omap4 = {
2465 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
2466 .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
2467 .modulemode = MODULEMODE_SWCTRL,
2468 },
2469 },
2470 };
2472 /* timer2 */
2473 static struct omap_hwmod dra7xx_timer2_hwmod = {
2474 .name = "timer2",
2475 .class = &dra7xx_timer_1ms_hwmod_class,
2476 .clkdm_name = "l4per_clkdm",
2477 .main_clk = "timer2_gfclk_mux",
2478 .prcm = {
2479 .omap4 = {
2480 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
2481 .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
2482 .modulemode = MODULEMODE_SWCTRL,
2483 },
2484 },
2485 };
2487 /* timer3 */
2488 static struct omap_hwmod dra7xx_timer3_hwmod = {
2489 .name = "timer3",
2490 .class = &dra7xx_timer_hwmod_class,
2491 .clkdm_name = "l4per_clkdm",
2492 .main_clk = "timer3_gfclk_mux",
2493 .prcm = {
2494 .omap4 = {
2495 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
2496 .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
2497 .modulemode = MODULEMODE_SWCTRL,
2498 },
2499 },
2500 };
2502 /* timer4 */
2503 static struct omap_hwmod dra7xx_timer4_hwmod = {
2504 .name = "timer4",
2505 .class = &dra7xx_timer_hwmod_class,
2506 .clkdm_name = "l4per_clkdm",
2507 .main_clk = "timer4_gfclk_mux",
2508 .prcm = {
2509 .omap4 = {
2510 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
2511 .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
2512 .modulemode = MODULEMODE_SWCTRL,
2513 },
2514 },
2515 };
2517 /* timer5 */
2518 static struct omap_hwmod dra7xx_timer5_hwmod = {
2519 .name = "timer5",
2520 .class = &dra7xx_timer_hwmod_class,
2521 .clkdm_name = "ipu_clkdm",
2522 .main_clk = "timer5_gfclk_mux",
2523 .prcm = {
2524 .omap4 = {
2525 .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
2526 .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
2527 .modulemode = MODULEMODE_SWCTRL,
2528 },
2529 },
2530 };
2532 /* timer6 */
2533 static struct omap_hwmod dra7xx_timer6_hwmod = {
2534 .name = "timer6",
2535 .class = &dra7xx_timer_hwmod_class,
2536 .clkdm_name = "ipu_clkdm",
2537 .main_clk = "timer6_gfclk_mux",
2538 .prcm = {
2539 .omap4 = {
2540 .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
2541 .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
2542 .modulemode = MODULEMODE_SWCTRL,
2543 },
2544 },
2545 };
2547 /* timer7 */
2548 static struct omap_hwmod dra7xx_timer7_hwmod = {
2549 .name = "timer7",
2550 .class = &dra7xx_timer_hwmod_class,
2551 .clkdm_name = "ipu_clkdm",
2552 .main_clk = "timer7_gfclk_mux",
2553 .prcm = {
2554 .omap4 = {
2555 .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
2556 .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
2557 .modulemode = MODULEMODE_SWCTRL,
2558 },
2559 },
2560 };
2562 /* timer8 */
2563 static struct omap_hwmod dra7xx_timer8_hwmod = {
2564 .name = "timer8",
2565 .class = &dra7xx_timer_hwmod_class,
2566 .clkdm_name = "ipu_clkdm",
2567 .main_clk = "timer8_gfclk_mux",
2568 .prcm = {
2569 .omap4 = {
2570 .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
2571 .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
2572 .modulemode = MODULEMODE_SWCTRL,
2573 },
2574 },
2575 };
2577 /* timer9 */
2578 static struct omap_hwmod dra7xx_timer9_hwmod = {
2579 .name = "timer9",
2580 .class = &dra7xx_timer_hwmod_class,
2581 .clkdm_name = "l4per_clkdm",
2582 .main_clk = "timer9_gfclk_mux",
2583 .prcm = {
2584 .omap4 = {
2585 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
2586 .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
2587 .modulemode = MODULEMODE_SWCTRL,
2588 },
2589 },
2590 };
2592 /* timer10 */
2593 static struct omap_hwmod dra7xx_timer10_hwmod = {
2594 .name = "timer10",
2595 .class = &dra7xx_timer_1ms_hwmod_class,
2596 .clkdm_name = "l4per_clkdm",
2597 .main_clk = "timer10_gfclk_mux",
2598 .prcm = {
2599 .omap4 = {
2600 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
2601 .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
2602 .modulemode = MODULEMODE_SWCTRL,
2603 },
2604 },
2605 };
2607 /* timer11 */
2608 static struct omap_hwmod dra7xx_timer11_hwmod = {
2609 .name = "timer11",
2610 .class = &dra7xx_timer_hwmod_class,
2611 .clkdm_name = "l4per_clkdm",
2612 .main_clk = "timer11_gfclk_mux",
2613 .prcm = {
2614 .omap4 = {
2615 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
2616 .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
2617 .modulemode = MODULEMODE_SWCTRL,
2618 },
2619 },
2620 };
2622 /* timer12 */
2623 static struct omap_hwmod dra7xx_timer12_hwmod = {
2624 .name = "timer12",
2625 .class = &dra7xx_timer_secure_hwmod_class,
2626 .clkdm_name = "wkupaon_clkdm",
2627 .main_clk = "secure_32k_clk_src_ck",
2628 .prcm = {
2629 .omap4 = {
2630 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET,
2631 .context_offs = DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET,
2632 },
2633 },
2634 };
2636 /* timer13 */
2637 static struct omap_hwmod dra7xx_timer13_hwmod = {
2638 .name = "timer13",
2639 .class = &dra7xx_timer_hwmod_class,
2640 .clkdm_name = "l4per3_clkdm",
2641 .main_clk = "timer13_gfclk_mux",
2642 .prcm = {
2643 .omap4 = {
2644 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
2645 .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
2646 .modulemode = MODULEMODE_SWCTRL,
2647 },
2648 },
2649 };
2651 /* timer14 */
2652 static struct omap_hwmod dra7xx_timer14_hwmod = {
2653 .name = "timer14",
2654 .class = &dra7xx_timer_hwmod_class,
2655 .clkdm_name = "l4per3_clkdm",
2656 .main_clk = "timer14_gfclk_mux",
2657 .prcm = {
2658 .omap4 = {
2659 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
2660 .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
2661 .modulemode = MODULEMODE_SWCTRL,
2662 },
2663 },
2664 };
2666 /* timer15 */
2667 static struct omap_hwmod dra7xx_timer15_hwmod = {
2668 .name = "timer15",
2669 .class = &dra7xx_timer_hwmod_class,
2670 .clkdm_name = "l4per3_clkdm",
2671 .main_clk = "timer15_gfclk_mux",
2672 .prcm = {
2673 .omap4 = {
2674 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
2675 .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
2676 .modulemode = MODULEMODE_SWCTRL,
2677 },
2678 },
2679 };
2681 /* timer16 */
2682 static struct omap_hwmod dra7xx_timer16_hwmod = {
2683 .name = "timer16",
2684 .class = &dra7xx_timer_hwmod_class,
2685 .clkdm_name = "l4per3_clkdm",
2686 .main_clk = "timer16_gfclk_mux",
2687 .prcm = {
2688 .omap4 = {
2689 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
2690 .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
2691 .modulemode = MODULEMODE_SWCTRL,
2692 },
2693 },
2694 };
2696 /*
2697 * 'uart' class
2698 *
2699 */
2701 static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
2702 .rev_offs = 0x0050,
2703 .sysc_offs = 0x0054,
2704 .syss_offs = 0x0058,
2705 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2706 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2707 SYSS_HAS_RESET_STATUS),
2708 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2709 SIDLE_SMART_WKUP),
2710 .sysc_fields = &omap_hwmod_sysc_type1,
2711 };
2713 static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
2714 .name = "uart",
2715 .sysc = &dra7xx_uart_sysc,
2716 };
2718 /* uart1 */
2719 static struct omap_hwmod dra7xx_uart1_hwmod = {
2720 .name = "uart1",
2721 .class = &dra7xx_uart_hwmod_class,
2722 .clkdm_name = "l4per_clkdm",
2723 .main_clk = "uart1_gfclk_mux",
2724 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
2725 .prcm = {
2726 .omap4 = {
2727 .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
2728 .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
2729 .modulemode = MODULEMODE_SWCTRL,
2730 },
2731 },
2732 };
2734 /* uart2 */
2735 static struct omap_hwmod dra7xx_uart2_hwmod = {
2736 .name = "uart2",
2737 .class = &dra7xx_uart_hwmod_class,
2738 .clkdm_name = "l4per_clkdm",
2739 .main_clk = "uart2_gfclk_mux",
2740 .flags = HWMOD_SWSUP_SIDLE_ACT,
2741 .prcm = {
2742 .omap4 = {
2743 .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
2744 .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
2745 .modulemode = MODULEMODE_SWCTRL,
2746 },
2747 },
2748 };
2750 /* uart3 */
2751 static struct omap_hwmod dra7xx_uart3_hwmod = {
2752 .name = "uart3",
2753 .class = &dra7xx_uart_hwmod_class,
2754 .clkdm_name = "l4per_clkdm",
2755 .main_clk = "uart3_gfclk_mux",
2756 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART3_FLAGS,
2757 .prcm = {
2758 .omap4 = {
2759 .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
2760 .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
2761 .modulemode = MODULEMODE_SWCTRL,
2762 },
2763 },
2764 };
2766 /* uart4 */
2767 static struct omap_hwmod dra7xx_uart4_hwmod = {
2768 .name = "uart4",
2769 .class = &dra7xx_uart_hwmod_class,
2770 .clkdm_name = "l4per_clkdm",
2771 .main_clk = "uart4_gfclk_mux",
2772 .flags = HWMOD_SWSUP_SIDLE_ACT,
2773 .prcm = {
2774 .omap4 = {
2775 .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
2776 .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
2777 .modulemode = MODULEMODE_SWCTRL,
2778 },
2779 },
2780 };
2782 /* uart5 */
2783 static struct omap_hwmod dra7xx_uart5_hwmod = {
2784 .name = "uart5",
2785 .class = &dra7xx_uart_hwmod_class,
2786 .clkdm_name = "l4per_clkdm",
2787 .main_clk = "uart5_gfclk_mux",
2788 .flags = HWMOD_SWSUP_SIDLE_ACT,
2789 .prcm = {
2790 .omap4 = {
2791 .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
2792 .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
2793 .modulemode = MODULEMODE_SWCTRL,
2794 },
2795 },
2796 };
2798 /* uart6 */
2799 static struct omap_hwmod dra7xx_uart6_hwmod = {
2800 .name = "uart6",
2801 .class = &dra7xx_uart_hwmod_class,
2802 .clkdm_name = "ipu_clkdm",
2803 .main_clk = "uart6_gfclk_mux",
2804 .flags = HWMOD_SWSUP_SIDLE_ACT,
2805 .prcm = {
2806 .omap4 = {
2807 .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
2808 .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
2809 .modulemode = MODULEMODE_SWCTRL,
2810 },
2811 },
2812 };
2814 /* uart7 */
2815 static struct omap_hwmod dra7xx_uart7_hwmod = {
2816 .name = "uart7",
2817 .class = &dra7xx_uart_hwmod_class,
2818 .clkdm_name = "l4per2_clkdm",
2819 .main_clk = "uart7_gfclk_mux",
2820 .flags = HWMOD_SWSUP_SIDLE_ACT,
2821 .prcm = {
2822 .omap4 = {
2823 .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
2824 .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
2825 .modulemode = MODULEMODE_SWCTRL,
2826 },
2827 },
2828 };
2830 /* uart8 */
2831 static struct omap_hwmod dra7xx_uart8_hwmod = {
2832 .name = "uart8",
2833 .class = &dra7xx_uart_hwmod_class,
2834 .clkdm_name = "l4per2_clkdm",
2835 .main_clk = "uart8_gfclk_mux",
2836 .flags = HWMOD_SWSUP_SIDLE_ACT,
2837 .prcm = {
2838 .omap4 = {
2839 .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
2840 .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
2841 .modulemode = MODULEMODE_SWCTRL,
2842 },
2843 },
2844 };
2846 /* uart9 */
2847 static struct omap_hwmod dra7xx_uart9_hwmod = {
2848 .name = "uart9",
2849 .class = &dra7xx_uart_hwmod_class,
2850 .clkdm_name = "l4per2_clkdm",
2851 .main_clk = "uart9_gfclk_mux",
2852 .flags = HWMOD_SWSUP_SIDLE_ACT,
2853 .prcm = {
2854 .omap4 = {
2855 .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
2856 .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
2857 .modulemode = MODULEMODE_SWCTRL,
2858 },
2859 },
2860 };
2862 /* uart10 */
2863 static struct omap_hwmod dra7xx_uart10_hwmod = {
2864 .name = "uart10",
2865 .class = &dra7xx_uart_hwmod_class,
2866 .clkdm_name = "wkupaon_clkdm",
2867 .main_clk = "uart10_gfclk_mux",
2868 .flags = HWMOD_SWSUP_SIDLE_ACT,
2869 .prcm = {
2870 .omap4 = {
2871 .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
2872 .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
2873 .modulemode = MODULEMODE_SWCTRL,
2874 },
2875 },
2876 };
2878 /* DES (the 'P' (public) device) */
2879 static struct omap_hwmod_class_sysconfig dra7xx_des_sysc = {
2880 .rev_offs = 0x0030,
2881 .sysc_offs = 0x0034,
2882 .syss_offs = 0x0038,
2883 .sysc_flags = SYSS_HAS_RESET_STATUS,
2884 };
2886 static struct omap_hwmod_class dra7xx_des_hwmod_class = {
2887 .name = "des",
2888 .sysc = &dra7xx_des_sysc,
2889 };
2891 /* DES */
2892 static struct omap_hwmod dra7xx_des_hwmod = {
2893 .name = "des",
2894 .class = &dra7xx_des_hwmod_class,
2895 .clkdm_name = "l4sec_clkdm",
2896 .main_clk = "l3_iclk_div",
2897 .prcm = {
2898 .omap4 = {
2899 .clkctrl_offs = DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
2900 .context_offs = DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
2901 .modulemode = MODULEMODE_HWCTRL,
2902 },
2903 },
2904 };
2906 /* rng */
2907 static struct omap_hwmod_class_sysconfig dra7xx_rng_sysc = {
2908 .rev_offs = 0x1fe0,
2909 .sysc_offs = 0x1fe4,
2910 .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
2911 .idlemodes = SIDLE_FORCE | SIDLE_NO,
2912 .sysc_fields = &omap_hwmod_sysc_type1,
2913 };
2915 static struct omap_hwmod_class dra7xx_rng_hwmod_class = {
2916 .name = "rng",
2917 .sysc = &dra7xx_rng_sysc,
2918 };
2920 static struct omap_hwmod dra7xx_rng_hwmod = {
2921 .name = "rng",
2922 .class = &dra7xx_rng_hwmod_class,
2923 .flags = HWMOD_SWSUP_SIDLE,
2924 .clkdm_name = "l4sec_clkdm",
2925 .prcm = {
2926 .omap4 = {
2927 .clkctrl_offs = DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET,
2928 .context_offs = DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET,
2929 .modulemode = MODULEMODE_HWCTRL,
2930 },
2931 },
2932 };
2934 /*
2935 * 'usb_otg_ss' class
2936 *
2937 */
2939 static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
2940 .rev_offs = 0x0000,
2941 .sysc_offs = 0x0010,
2942 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
2943 SYSC_HAS_SIDLEMODE),
2944 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2945 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2946 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2947 .sysc_fields = &omap_hwmod_sysc_type2,
2948 };
2950 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
2951 .name = "usb_otg_ss",
2952 .sysc = &dra7xx_usb_otg_ss_sysc,
2953 };
2955 /* usb_otg_ss1 */
2956 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
2957 { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
2958 };
2960 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
2961 .name = "usb_otg_ss1",
2962 .class = &dra7xx_usb_otg_ss_hwmod_class,
2963 .clkdm_name = "l3init_clkdm",
2964 .main_clk = "dpll_core_h13x2_ck",
2965 .prcm = {
2966 .omap4 = {
2967 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
2968 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
2969 .modulemode = MODULEMODE_HWCTRL,
2970 },
2971 },
2972 .opt_clks = usb_otg_ss1_opt_clks,
2973 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
2974 };
2976 /* usb_otg_ss2 */
2977 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
2978 { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
2979 };
2981 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
2982 .name = "usb_otg_ss2",
2983 .class = &dra7xx_usb_otg_ss_hwmod_class,
2984 .clkdm_name = "l3init_clkdm",
2985 .main_clk = "dpll_core_h13x2_ck",
2986 .prcm = {
2987 .omap4 = {
2988 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
2989 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
2990 .modulemode = MODULEMODE_HWCTRL,
2991 },
2992 },
2993 .opt_clks = usb_otg_ss2_opt_clks,
2994 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
2995 };
2997 /* usb_otg_ss3 */
2998 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
2999 .name = "usb_otg_ss3",
3000 .class = &dra7xx_usb_otg_ss_hwmod_class,
3001 .clkdm_name = "l3init_clkdm",
3002 .main_clk = "dpll_core_h13x2_ck",
3003 .prcm = {
3004 .omap4 = {
3005 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
3006 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
3007 .modulemode = MODULEMODE_HWCTRL,
3008 },
3009 },
3010 };
3012 /* usb_otg_ss4 */
3013 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
3014 .name = "usb_otg_ss4",
3015 .class = &dra7xx_usb_otg_ss_hwmod_class,
3016 .clkdm_name = "l3init_clkdm",
3017 .main_clk = "dpll_core_h13x2_ck",
3018 .prcm = {
3019 .omap4 = {
3020 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
3021 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
3022 .modulemode = MODULEMODE_HWCTRL,
3023 },
3024 },
3025 };
3027 /*
3028 * 'vcp' class
3029 *
3030 */
3032 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
3033 .name = "vcp",
3034 };
3036 /* vcp1 */
3037 static struct omap_hwmod dra7xx_vcp1_hwmod = {
3038 .name = "vcp1",
3039 .class = &dra7xx_vcp_hwmod_class,
3040 .clkdm_name = "l3main1_clkdm",
3041 .main_clk = "l3_iclk_div",
3042 .prcm = {
3043 .omap4 = {
3044 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
3045 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
3046 },
3047 },
3048 };
3050 /* vcp2 */
3051 static struct omap_hwmod dra7xx_vcp2_hwmod = {
3052 .name = "vcp2",
3053 .class = &dra7xx_vcp_hwmod_class,
3054 .clkdm_name = "l3main1_clkdm",
3055 .main_clk = "l3_iclk_div",
3056 .prcm = {
3057 .omap4 = {
3058 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
3059 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
3060 },
3061 },
3062 };
3064 /*
3065 * 'wd_timer' class
3066 *
3067 */
3069 static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
3070 .rev_offs = 0x0000,
3071 .sysc_offs = 0x0010,
3072 .syss_offs = 0x0014,
3073 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3074 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3075 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3076 SIDLE_SMART_WKUP),
3077 .sysc_fields = &omap_hwmod_sysc_type1,
3078 };
3080 static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
3081 .name = "wd_timer",
3082 .sysc = &dra7xx_wd_timer_sysc,
3083 .pre_shutdown = &omap2_wd_timer_disable,
3084 .reset = &omap2_wd_timer_reset,
3085 };
3087 /* wd_timer2 */
3088 static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
3089 .name = "wd_timer2",
3090 .class = &dra7xx_wd_timer_hwmod_class,
3091 .clkdm_name = "wkupaon_clkdm",
3092 .main_clk = "sys_32k_ck",
3093 .prcm = {
3094 .omap4 = {
3095 .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
3096 .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
3097 .modulemode = MODULEMODE_SWCTRL,
3098 },
3099 },
3100 };
3103 /*
3104 * Interfaces
3105 */
3107 /* l3_main_2 -> l3_instr */
3108 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
3109 .master = &dra7xx_l3_main_2_hwmod,
3110 .slave = &dra7xx_l3_instr_hwmod,
3111 .clk = "l3_iclk_div",
3112 .user = OCP_USER_MPU | OCP_USER_SDMA,
3113 };
3115 /* l4_cfg -> l3_main_1 */
3116 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
3117 .master = &dra7xx_l4_cfg_hwmod,
3118 .slave = &dra7xx_l3_main_1_hwmod,
3119 .clk = "l3_iclk_div",
3120 .user = OCP_USER_MPU | OCP_USER_SDMA,
3121 };
3123 /*
3124 * Interfaces
3125 */
3127 static struct omap_hwmod_addr_space dra7xx_dmm_addrs[] = {
3128 {
3129 .pa_start = 0x4e000000,
3130 .pa_end = 0x4e0007ff,
3131 .flags = ADDR_TYPE_RT
3132 },
3133 { }
3134 };
3136 /* l3_main_1 -> dmm */
3137 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
3138 .master = &dra7xx_l3_main_1_hwmod,
3139 .slave = &dra7xx_dmm_hwmod,
3140 .clk = "l3_iclk_div",
3141 .addr = dra7xx_dmm_addrs,
3142 .user = OCP_USER_SDMA,
3143 };
3145 /* dmm -> emif_ocp_fw */
3146 static struct omap_hwmod_ocp_if dra7xx_dmm__emif_ocp_fw = {
3147 .master = &dra7xx_dmm_hwmod,
3148 .slave = &dra7xx_emif_ocp_fw_hwmod,
3149 .clk = "l3_iclk_div",
3150 .user = OCP_USER_MPU | OCP_USER_SDMA,
3151 };
3153 /* mpu -> l3_main_1 */
3154 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
3155 .master = &dra7xx_mpu_hwmod,
3156 .slave = &dra7xx_l3_main_1_hwmod,
3157 .clk = "l3_iclk_div",
3158 .user = OCP_USER_MPU,
3159 };
3161 /* l3_main_1 -> l3_main_2 */
3162 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
3163 .master = &dra7xx_l3_main_1_hwmod,
3164 .slave = &dra7xx_l3_main_2_hwmod,
3165 .clk = "l3_iclk_div",
3166 .user = OCP_USER_MPU,
3167 };
3169 /* l4_cfg -> l3_main_2 */
3170 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
3171 .master = &dra7xx_l4_cfg_hwmod,
3172 .slave = &dra7xx_l3_main_2_hwmod,
3173 .clk = "l3_iclk_div",
3174 .user = OCP_USER_MPU | OCP_USER_SDMA,
3175 };
3177 /* l3_main_1 -> l4_cfg */
3178 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
3179 .master = &dra7xx_l3_main_1_hwmod,
3180 .slave = &dra7xx_l4_cfg_hwmod,
3181 .clk = "l3_iclk_div",
3182 .user = OCP_USER_MPU | OCP_USER_SDMA,
3183 };
3185 /* l3_main_1 -> mmu0_dsp1 */
3186 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu0_dsp1 = {
3187 .master = &dra7xx_l3_main_1_hwmod,
3188 .slave = &dra7xx_mmu0_dsp1_hwmod,
3189 .clk = "l3_iclk_div",
3190 .user = OCP_USER_MPU | OCP_USER_SDMA,
3191 };
3193 /* l3_main_1 -> mmu1_dsp1 */
3194 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu1_dsp1 = {
3195 .master = &dra7xx_l3_main_1_hwmod,
3196 .slave = &dra7xx_mmu1_dsp1_hwmod,
3197 .clk = "l3_iclk_div",
3198 .user = OCP_USER_MPU | OCP_USER_SDMA,
3199 };
3201 /* l3_main_1 -> mmu0_dsp2 */
3202 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu0_dsp2 = {
3203 .master = &dra7xx_l3_main_1_hwmod,
3204 .slave = &dra7xx_mmu0_dsp2_hwmod,
3205 .clk = "l3_iclk_div",
3206 .user = OCP_USER_MPU | OCP_USER_SDMA,
3207 };
3209 /* l3_main_1 -> mmu1_dsp2 */
3210 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu1_dsp2 = {
3211 .master = &dra7xx_l3_main_1_hwmod,
3212 .slave = &dra7xx_mmu1_dsp2_hwmod,
3213 .clk = "l3_iclk_div",
3214 .user = OCP_USER_MPU | OCP_USER_SDMA,
3215 };
3217 /* l3_main_1 -> mmu_ipu1 */
3218 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu_ipu1 = {
3219 .master = &dra7xx_l3_main_1_hwmod,
3220 .slave = &dra7xx_mmu_ipu1_hwmod,
3221 .clk = "l3_iclk_div",
3222 .user = OCP_USER_MPU | OCP_USER_SDMA,
3223 };
3225 /* l3_main_1 -> mmu_ipu2 */
3226 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu_ipu2 = {
3227 .master = &dra7xx_l3_main_1_hwmod,
3228 .slave = &dra7xx_mmu_ipu2_hwmod,
3229 .clk = "l3_iclk_div",
3230 .user = OCP_USER_MPU | OCP_USER_SDMA,
3231 };
3233 /* l3_main_1 -> l4_per1 */
3234 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
3235 .master = &dra7xx_l3_main_1_hwmod,
3236 .slave = &dra7xx_l4_per1_hwmod,
3237 .clk = "l3_iclk_div",
3238 .user = OCP_USER_MPU | OCP_USER_SDMA,
3239 };
3241 /* l3_main_1 -> l4_per2 */
3242 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
3243 .master = &dra7xx_l3_main_1_hwmod,
3244 .slave = &dra7xx_l4_per2_hwmod,
3245 .clk = "l3_iclk_div",
3246 .user = OCP_USER_MPU | OCP_USER_SDMA,
3247 };
3249 /* l3_main_1 -> l4_per3 */
3250 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
3251 .master = &dra7xx_l3_main_1_hwmod,
3252 .slave = &dra7xx_l4_per3_hwmod,
3253 .clk = "l3_iclk_div",
3254 .user = OCP_USER_MPU | OCP_USER_SDMA,
3255 };
3257 /* l3_main_1 -> l4_wkup */
3258 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
3259 .master = &dra7xx_l3_main_1_hwmod,
3260 .slave = &dra7xx_l4_wkup_hwmod,
3261 .clk = "wkupaon_iclk_mux",
3262 .user = OCP_USER_MPU | OCP_USER_SDMA,
3263 };
3265 /* l4_per2 -> atl */
3266 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
3267 .master = &dra7xx_l4_per2_hwmod,
3268 .slave = &dra7xx_atl_hwmod,
3269 .clk = "l3_iclk_div",
3270 .user = OCP_USER_MPU | OCP_USER_SDMA,
3271 };
3273 /* l3_main_1 -> bb2d */
3274 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
3275 .master = &dra7xx_l3_main_1_hwmod,
3276 .slave = &dra7xx_bb2d_hwmod,
3277 .clk = "l3_iclk_div",
3278 .user = OCP_USER_MPU | OCP_USER_SDMA,
3279 };
3281 /* l4_wkup -> counter_32k */
3282 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
3283 .master = &dra7xx_l4_wkup_hwmod,
3284 .slave = &dra7xx_counter_32k_hwmod,
3285 .clk = "wkupaon_iclk_mux",
3286 .user = OCP_USER_MPU | OCP_USER_SDMA,
3287 };
3289 /* l4_wkup -> ctrl_module_wkup */
3290 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
3291 .master = &dra7xx_l4_wkup_hwmod,
3292 .slave = &dra7xx_ctrl_module_wkup_hwmod,
3293 .clk = "wkupaon_iclk_mux",
3294 .user = OCP_USER_MPU | OCP_USER_SDMA,
3295 };
3297 static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
3298 .master = &dra7xx_l4_per2_hwmod,
3299 .slave = &dra7xx_gmac_hwmod,
3300 .clk = "dpll_gmac_ck",
3301 .user = OCP_USER_MPU,
3302 };
3304 static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
3305 .master = &dra7xx_gmac_hwmod,
3306 .slave = &dra7xx_mdio_hwmod,
3307 .user = OCP_USER_MPU,
3308 };
3310 /* l4_wkup -> dcan1 */
3311 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
3312 .master = &dra7xx_l4_wkup_hwmod,
3313 .slave = &dra7xx_dcan1_hwmod,
3314 .clk = "wkupaon_iclk_mux",
3315 .user = OCP_USER_MPU | OCP_USER_SDMA,
3316 };
3318 /* l4_per2 -> dcan2 */
3319 static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
3320 .master = &dra7xx_l4_per2_hwmod,
3321 .slave = &dra7xx_dcan2_hwmod,
3322 .clk = "l3_iclk_div",
3323 .user = OCP_USER_MPU | OCP_USER_SDMA,
3324 };
3326 static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
3327 {
3328 .pa_start = 0x4a056000,
3329 .pa_end = 0x4a056fff,
3330 .flags = ADDR_TYPE_RT
3331 },
3332 { }
3333 };
3335 /* l4_cfg -> dma_system */
3336 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
3337 .master = &dra7xx_l4_cfg_hwmod,
3338 .slave = &dra7xx_dma_system_hwmod,
3339 .clk = "l3_iclk_div",
3340 .addr = dra7xx_dma_system_addrs,
3341 .user = OCP_USER_MPU | OCP_USER_SDMA,
3342 };
3344 /* dsp1 -> l3_main_1 */
3345 static struct omap_hwmod_ocp_if dra7xx_dsp1__l3_main_1 = {
3346 .master = &dra7xx_dsp1_hwmod,
3347 .slave = &dra7xx_l3_main_1_hwmod,
3348 .clk = "l3_iclk_div",
3349 .user = OCP_USER_MPU | OCP_USER_SDMA,
3350 };
3352 /* dsp2 -> l3_main_1 */
3353 static struct omap_hwmod_ocp_if dra7xx_dsp2__l3_main_1 = {
3354 .master = &dra7xx_dsp2_hwmod,
3355 .slave = &dra7xx_l3_main_1_hwmod,
3356 .clk = "l3_iclk_div",
3357 .user = OCP_USER_MPU | OCP_USER_SDMA,
3358 };
3360 static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
3361 {
3362 .name = "family",
3363 .pa_start = 0x58000000,
3364 .pa_end = 0x5800007f,
3365 .flags = ADDR_TYPE_RT
3366 },
3367 };
3369 /* l3_main_1 -> dss */
3370 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
3371 .master = &dra7xx_l3_main_1_hwmod,
3372 .slave = &dra7xx_dss_hwmod,
3373 .clk = "l3_iclk_div",
3374 .addr = dra7xx_dss_addrs,
3375 .user = OCP_USER_MPU | OCP_USER_SDMA,
3376 };
3378 static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = {
3379 {
3380 .name = "dispc",
3381 .pa_start = 0x58001000,
3382 .pa_end = 0x58001fff,
3383 .flags = ADDR_TYPE_RT
3384 },
3385 };
3387 /* l3_main_1 -> dispc */
3388 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
3389 .master = &dra7xx_l3_main_1_hwmod,
3390 .slave = &dra7xx_dss_dispc_hwmod,
3391 .clk = "l3_iclk_div",
3392 .addr = dra7xx_dss_dispc_addrs,
3393 .user = OCP_USER_MPU | OCP_USER_SDMA,
3394 };
3396 static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = {
3397 {
3398 .name = "hdmi_wp",
3399 .pa_start = 0x58040000,
3400 .pa_end = 0x580400ff,
3401 .flags = ADDR_TYPE_RT
3402 },
3403 { }
3404 };
3406 /* l3_main_1 -> dispc */
3407 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
3408 .master = &dra7xx_l3_main_1_hwmod,
3409 .slave = &dra7xx_dss_hdmi_hwmod,
3410 .clk = "l3_iclk_div",
3411 .addr = dra7xx_dss_hdmi_addrs,
3412 .user = OCP_USER_MPU | OCP_USER_SDMA,
3413 };
3415 /* l3_main_1 -> aes */
3416 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes = {
3417 .master = &dra7xx_l3_main_1_hwmod,
3418 .slave = &dra7xx_aes_hwmod,
3419 .clk = "l3_iclk_div",
3420 .user = OCP_USER_MPU | OCP_USER_SDMA,
3421 };
3423 /* l3_main_1 -> sha0 */
3424 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__sha0 = {
3425 .master = &dra7xx_l3_main_1_hwmod,
3426 .slave = &dra7xx_sha0_hwmod,
3427 .clk = "l3_iclk_div",
3428 .user = OCP_USER_MPU | OCP_USER_SDMA,
3429 };
3431 /* l4_per2 -> mcasp3 */
3432 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = {
3433 .master = &dra7xx_l4_per2_hwmod,
3434 .slave = &dra7xx_mcasp3_hwmod,
3435 .clk = "l3_iclk_div",
3436 .user = OCP_USER_MPU | OCP_USER_SDMA,
3437 };
3439 static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = {
3440 {
3441 .pa_start = 0x48078000,
3442 .pa_end = 0x48078fff,
3443 .flags = ADDR_TYPE_RT
3444 },
3445 { }
3446 };
3448 /* l4_per1 -> elm */
3449 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
3450 .master = &dra7xx_l4_per1_hwmod,
3451 .slave = &dra7xx_elm_hwmod,
3452 .clk = "l3_iclk_div",
3453 .addr = dra7xx_elm_addrs,
3454 .user = OCP_USER_MPU | OCP_USER_SDMA,
3455 };
3457 /* l4_wkup -> gpio1 */
3458 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
3459 .master = &dra7xx_l4_wkup_hwmod,
3460 .slave = &dra7xx_gpio1_hwmod,
3461 .clk = "wkupaon_iclk_mux",
3462 .user = OCP_USER_MPU | OCP_USER_SDMA,
3463 };
3465 /* l4_per1 -> gpio2 */
3466 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
3467 .master = &dra7xx_l4_per1_hwmod,
3468 .slave = &dra7xx_gpio2_hwmod,
3469 .clk = "l3_iclk_div",
3470 .user = OCP_USER_MPU | OCP_USER_SDMA,
3471 };
3473 /* l4_per1 -> gpio3 */
3474 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
3475 .master = &dra7xx_l4_per1_hwmod,
3476 .slave = &dra7xx_gpio3_hwmod,
3477 .clk = "l3_iclk_div",
3478 .user = OCP_USER_MPU | OCP_USER_SDMA,
3479 };
3481 /* l4_per1 -> gpio4 */
3482 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
3483 .master = &dra7xx_l4_per1_hwmod,
3484 .slave = &dra7xx_gpio4_hwmod,
3485 .clk = "l3_iclk_div",
3486 .user = OCP_USER_MPU | OCP_USER_SDMA,
3487 };
3489 /* l4_per1 -> gpio5 */
3490 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
3491 .master = &dra7xx_l4_per1_hwmod,
3492 .slave = &dra7xx_gpio5_hwmod,
3493 .clk = "l3_iclk_div",
3494 .user = OCP_USER_MPU | OCP_USER_SDMA,
3495 };
3497 /* l4_per1 -> gpio6 */
3498 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
3499 .master = &dra7xx_l4_per1_hwmod,
3500 .slave = &dra7xx_gpio6_hwmod,
3501 .clk = "l3_iclk_div",
3502 .user = OCP_USER_MPU | OCP_USER_SDMA,
3503 };
3505 struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss0 = {
3506 .master = &dra7xx_l4_per2_hwmod,
3507 .slave = &dra7xx_epwmss0_hwmod,
3508 .clk = "l4_root_clk_div",
3509 .user = OCP_USER_MPU,
3510 };
3512 struct omap_hwmod_ocp_if dra7xx_epwmss0__ecap0 = {
3513 .master = &dra7xx_epwmss0_hwmod,
3514 .slave = &dra7xx_ecap0_hwmod,
3515 .clk = "l4_root_clk_div",
3516 .user = OCP_USER_MPU,
3517 };
3519 struct omap_hwmod_ocp_if dra7xx_epwmss0__eqep0 = {
3520 .master = &dra7xx_epwmss0_hwmod,
3521 .slave = &dra7xx_eqep0_hwmod,
3522 .clk = "l4_root_clk_div",
3523 .user = OCP_USER_MPU,
3524 };
3526 struct omap_hwmod_ocp_if dra7xx_epwmss0__ehrpwm0 = {
3527 .master = &dra7xx_epwmss0_hwmod,
3528 .slave = &dra7xx_ehrpwm0_hwmod,
3529 .clk = "l4_root_clk_div",
3530 .user = OCP_USER_MPU,
3531 };
3533 struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss1 = {
3534 .master = &dra7xx_l4_per2_hwmod,
3535 .slave = &dra7xx_epwmss1_hwmod,
3536 .clk = "l4_root_clk_div",
3537 .user = OCP_USER_MPU,
3538 };
3540 struct omap_hwmod_ocp_if dra7xx_epwmss1__ecap1 = {
3541 .master = &dra7xx_epwmss1_hwmod,
3542 .slave = &dra7xx_ecap1_hwmod,
3543 .clk = "l4_root_clk_div",
3544 .user = OCP_USER_MPU,
3545 };
3547 struct omap_hwmod_ocp_if dra7xx_epwmss1__eqep1 = {
3548 .master = &dra7xx_epwmss1_hwmod,
3549 .slave = &dra7xx_eqep1_hwmod,
3550 .clk = "l4_root_clk_div",
3551 .user = OCP_USER_MPU,
3552 };
3554 struct omap_hwmod_ocp_if dra7xx_epwmss1__ehrpwm1 = {
3555 .master = &dra7xx_epwmss1_hwmod,
3556 .slave = &dra7xx_ehrpwm1_hwmod,
3557 .clk = "l4_root_clk_div",
3558 .user = OCP_USER_MPU,
3559 };
3561 struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss2 = {
3562 .master = &dra7xx_l4_per2_hwmod,
3563 .slave = &dra7xx_epwmss2_hwmod,
3564 .clk = "l4_root_clk_div",
3565 .user = OCP_USER_MPU,
3566 };
3568 struct omap_hwmod_ocp_if dra7xx_epwmss2__ecap2 = {
3569 .master = &dra7xx_epwmss2_hwmod,
3570 .slave = &dra7xx_ecap2_hwmod,
3571 .clk = "l4_root_clk_div",
3572 .user = OCP_USER_MPU,
3573 };
3575 struct omap_hwmod_ocp_if dra7xx_epwmss2__eqep2 = {
3576 .master = &dra7xx_epwmss2_hwmod,
3577 .slave = &dra7xx_eqep2_hwmod,
3578 .clk = "l4_root_clk_div",
3579 .user = OCP_USER_MPU,
3580 };
3582 struct omap_hwmod_ocp_if dra7xx_epwmss2__ehrpwm2 = {
3583 .master = &dra7xx_epwmss2_hwmod,
3584 .slave = &dra7xx_ehrpwm2_hwmod,
3585 .clk = "l4_root_clk_div",
3586 .user = OCP_USER_MPU,
3587 };
3589 /* l4_per1 -> gpio7 */
3590 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
3591 .master = &dra7xx_l4_per1_hwmod,
3592 .slave = &dra7xx_gpio7_hwmod,
3593 .clk = "l3_iclk_div",
3594 .user = OCP_USER_MPU | OCP_USER_SDMA,
3595 };
3597 /* l4_per1 -> gpio8 */
3598 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
3599 .master = &dra7xx_l4_per1_hwmod,
3600 .slave = &dra7xx_gpio8_hwmod,
3601 .clk = "l3_iclk_div",
3602 .user = OCP_USER_MPU | OCP_USER_SDMA,
3603 };
3605 static struct omap_hwmod_addr_space dra7xx_gpmc_addrs[] = {
3606 {
3607 .pa_start = 0x50000000,
3608 .pa_end = 0x500003ff,
3609 .flags = ADDR_TYPE_RT
3610 },
3611 { }
3612 };
3614 /* l3_main_1 -> gpmc */
3615 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
3616 .master = &dra7xx_l3_main_1_hwmod,
3617 .slave = &dra7xx_gpmc_hwmod,
3618 .clk = "l3_iclk_div",
3619 .addr = dra7xx_gpmc_addrs,
3620 .user = OCP_USER_MPU | OCP_USER_SDMA,
3621 };
3623 static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
3624 {
3625 .pa_start = 0x480b2000,
3626 .pa_end = 0x480b201f,
3627 .flags = ADDR_TYPE_RT
3628 },
3629 { }
3630 };
3632 /* l4_per1 -> hdq1w */
3633 static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
3634 .master = &dra7xx_l4_per1_hwmod,
3635 .slave = &dra7xx_hdq1w_hwmod,
3636 .clk = "l3_iclk_div",
3637 .addr = dra7xx_hdq1w_addrs,
3638 .user = OCP_USER_MPU | OCP_USER_SDMA,
3639 };
3641 /* l4_per1 -> i2c1 */
3642 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
3643 .master = &dra7xx_l4_per1_hwmod,
3644 .slave = &dra7xx_i2c1_hwmod,
3645 .clk = "l3_iclk_div",
3646 .user = OCP_USER_MPU | OCP_USER_SDMA,
3647 };
3649 /* l4_per1 -> i2c2 */
3650 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
3651 .master = &dra7xx_l4_per1_hwmod,
3652 .slave = &dra7xx_i2c2_hwmod,
3653 .clk = "l3_iclk_div",
3654 .user = OCP_USER_MPU | OCP_USER_SDMA,
3655 };
3657 /* l4_per1 -> i2c3 */
3658 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
3659 .master = &dra7xx_l4_per1_hwmod,
3660 .slave = &dra7xx_i2c3_hwmod,
3661 .clk = "l3_iclk_div",
3662 .user = OCP_USER_MPU | OCP_USER_SDMA,
3663 };
3665 /* l4_per1 -> i2c4 */
3666 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
3667 .master = &dra7xx_l4_per1_hwmod,
3668 .slave = &dra7xx_i2c4_hwmod,
3669 .clk = "l3_iclk_div",
3670 .user = OCP_USER_MPU | OCP_USER_SDMA,
3671 };
3673 /* l4_per1 -> i2c5 */
3674 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
3675 .master = &dra7xx_l4_per1_hwmod,
3676 .slave = &dra7xx_i2c5_hwmod,
3677 .clk = "l3_iclk_div",
3678 .user = OCP_USER_MPU | OCP_USER_SDMA,
3679 };
3681 /* ipu1 -> l3_main_1 */
3682 static struct omap_hwmod_ocp_if dra7xx_ipu1__l3_main_1 = {
3683 .master = &dra7xx_ipu1_hwmod,
3684 .slave = &dra7xx_l3_main_1_hwmod,
3685 .clk = "l3_iclk_div",
3686 .user = OCP_USER_MPU | OCP_USER_SDMA,
3687 };
3689 /* ipu2 -> l3_main_1 */
3690 static struct omap_hwmod_ocp_if dra7xx_ipu2__l3_main_1 = {
3691 .master = &dra7xx_ipu2_hwmod,
3692 .slave = &dra7xx_l3_main_1_hwmod,
3693 .clk = "l3_iclk_div",
3694 .user = OCP_USER_MPU | OCP_USER_SDMA,
3695 };
3697 /* l4_cfg -> mailbox1 */
3698 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
3699 .master = &dra7xx_l4_cfg_hwmod,
3700 .slave = &dra7xx_mailbox1_hwmod,
3701 .clk = "l3_iclk_div",
3702 .user = OCP_USER_MPU | OCP_USER_SDMA,
3703 };
3705 /* l4_per3 -> mailbox2 */
3706 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
3707 .master = &dra7xx_l4_per3_hwmod,
3708 .slave = &dra7xx_mailbox2_hwmod,
3709 .clk = "l3_iclk_div",
3710 .user = OCP_USER_MPU | OCP_USER_SDMA,
3711 };
3713 /* l4_per3 -> mailbox3 */
3714 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
3715 .master = &dra7xx_l4_per3_hwmod,
3716 .slave = &dra7xx_mailbox3_hwmod,
3717 .clk = "l3_iclk_div",
3718 .user = OCP_USER_MPU | OCP_USER_SDMA,
3719 };
3721 /* l4_per3 -> mailbox4 */
3722 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
3723 .master = &dra7xx_l4_per3_hwmod,
3724 .slave = &dra7xx_mailbox4_hwmod,
3725 .clk = "l3_iclk_div",
3726 .user = OCP_USER_MPU | OCP_USER_SDMA,
3727 };
3729 /* l4_per3 -> mailbox5 */
3730 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
3731 .master = &dra7xx_l4_per3_hwmod,
3732 .slave = &dra7xx_mailbox5_hwmod,
3733 .clk = "l3_iclk_div",
3734 .user = OCP_USER_MPU | OCP_USER_SDMA,
3735 };
3737 /* l4_per3 -> mailbox6 */
3738 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
3739 .master = &dra7xx_l4_per3_hwmod,
3740 .slave = &dra7xx_mailbox6_hwmod,
3741 .clk = "l3_iclk_div",
3742 .user = OCP_USER_MPU | OCP_USER_SDMA,
3743 };
3745 /* l4_per3 -> mailbox7 */
3746 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
3747 .master = &dra7xx_l4_per3_hwmod,
3748 .slave = &dra7xx_mailbox7_hwmod,
3749 .clk = "l3_iclk_div",
3750 .user = OCP_USER_MPU | OCP_USER_SDMA,
3751 };
3753 /* l4_per3 -> mailbox8 */
3754 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
3755 .master = &dra7xx_l4_per3_hwmod,
3756 .slave = &dra7xx_mailbox8_hwmod,
3757 .clk = "l3_iclk_div",
3758 .user = OCP_USER_MPU | OCP_USER_SDMA,
3759 };
3761 /* l4_per3 -> mailbox9 */
3762 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
3763 .master = &dra7xx_l4_per3_hwmod,
3764 .slave = &dra7xx_mailbox9_hwmod,
3765 .clk = "l3_iclk_div",
3766 .user = OCP_USER_MPU | OCP_USER_SDMA,
3767 };
3769 /* l4_per3 -> mailbox10 */
3770 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
3771 .master = &dra7xx_l4_per3_hwmod,
3772 .slave = &dra7xx_mailbox10_hwmod,
3773 .clk = "l3_iclk_div",
3774 .user = OCP_USER_MPU | OCP_USER_SDMA,
3775 };
3777 /* l4_per3 -> mailbox11 */
3778 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
3779 .master = &dra7xx_l4_per3_hwmod,
3780 .slave = &dra7xx_mailbox11_hwmod,
3781 .clk = "l3_iclk_div",
3782 .user = OCP_USER_MPU | OCP_USER_SDMA,
3783 };
3785 /* l4_per3 -> mailbox12 */
3786 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
3787 .master = &dra7xx_l4_per3_hwmod,
3788 .slave = &dra7xx_mailbox12_hwmod,
3789 .clk = "l3_iclk_div",
3790 .user = OCP_USER_MPU | OCP_USER_SDMA,
3791 };
3793 /* l4_per3 -> mailbox13 */
3794 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
3795 .master = &dra7xx_l4_per3_hwmod,
3796 .slave = &dra7xx_mailbox13_hwmod,
3797 .clk = "l3_iclk_div",
3798 .user = OCP_USER_MPU | OCP_USER_SDMA,
3799 };
3801 /* l4_per1 -> mcspi1 */
3802 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
3803 .master = &dra7xx_l4_per1_hwmod,
3804 .slave = &dra7xx_mcspi1_hwmod,
3805 .clk = "l3_iclk_div",
3806 .user = OCP_USER_MPU | OCP_USER_SDMA,
3807 };
3809 /* l4_per1 -> mcspi2 */
3810 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
3811 .master = &dra7xx_l4_per1_hwmod,
3812 .slave = &dra7xx_mcspi2_hwmod,
3813 .clk = "l3_iclk_div",
3814 .user = OCP_USER_MPU | OCP_USER_SDMA,
3815 };
3817 /* l4_per1 -> mcspi3 */
3818 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
3819 .master = &dra7xx_l4_per1_hwmod,
3820 .slave = &dra7xx_mcspi3_hwmod,
3821 .clk = "l3_iclk_div",
3822 .user = OCP_USER_MPU | OCP_USER_SDMA,
3823 };
3825 /* l4_per1 -> mcspi4 */
3826 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
3827 .master = &dra7xx_l4_per1_hwmod,
3828 .slave = &dra7xx_mcspi4_hwmod,
3829 .clk = "l3_iclk_div",
3830 .user = OCP_USER_MPU | OCP_USER_SDMA,
3831 };
3833 /* l4_per1 -> mmc1 */
3834 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
3835 .master = &dra7xx_l4_per1_hwmod,
3836 .slave = &dra7xx_mmc1_hwmod,
3837 .clk = "l3_iclk_div",
3838 .user = OCP_USER_MPU | OCP_USER_SDMA,
3839 };
3841 /* l4_per1 -> mmc2 */
3842 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
3843 .master = &dra7xx_l4_per1_hwmod,
3844 .slave = &dra7xx_mmc2_hwmod,
3845 .clk = "l3_iclk_div",
3846 .user = OCP_USER_MPU | OCP_USER_SDMA,
3847 };
3849 /* l4_per1 -> mmc3 */
3850 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
3851 .master = &dra7xx_l4_per1_hwmod,
3852 .slave = &dra7xx_mmc3_hwmod,
3853 .clk = "l3_iclk_div",
3854 .user = OCP_USER_MPU | OCP_USER_SDMA,
3855 };
3857 /* l4_per1 -> mmc4 */
3858 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
3859 .master = &dra7xx_l4_per1_hwmod,
3860 .slave = &dra7xx_mmc4_hwmod,
3861 .clk = "l3_iclk_div",
3862 .user = OCP_USER_MPU | OCP_USER_SDMA,
3863 };
3865 /* l4_cfg -> mpu */
3866 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
3867 .master = &dra7xx_l4_cfg_hwmod,
3868 .slave = &dra7xx_mpu_hwmod,
3869 .clk = "l3_iclk_div",
3870 .user = OCP_USER_MPU | OCP_USER_SDMA,
3871 };
3873 /* l4_cfg -> ocp2scp1 */
3874 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
3875 .master = &dra7xx_l4_cfg_hwmod,
3876 .slave = &dra7xx_ocp2scp1_hwmod,
3877 .clk = "l4_root_clk_div",
3878 .user = OCP_USER_MPU | OCP_USER_SDMA,
3879 };
3881 /* l4_cfg -> ocp2scp3 */
3882 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
3883 .master = &dra7xx_l4_cfg_hwmod,
3884 .slave = &dra7xx_ocp2scp3_hwmod,
3885 .clk = "l4_root_clk_div",
3886 .user = OCP_USER_MPU | OCP_USER_SDMA,
3887 };
3889 /* l3_main_1 -> pcie1 */
3890 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
3891 .master = &dra7xx_l3_main_1_hwmod,
3892 .slave = &dra7xx_pciess1_hwmod,
3893 .clk = "l3_iclk_div",
3894 .user = OCP_USER_MPU | OCP_USER_SDMA,
3895 };
3897 /* l4_cfg -> pcie1 */
3898 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
3899 .master = &dra7xx_l4_cfg_hwmod,
3900 .slave = &dra7xx_pciess1_hwmod,
3901 .clk = "l4_root_clk_div",
3902 .user = OCP_USER_MPU | OCP_USER_SDMA,
3903 };
3905 /* l3_main_1 -> pcie2 */
3906 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
3907 .master = &dra7xx_l3_main_1_hwmod,
3908 .slave = &dra7xx_pciess2_hwmod,
3909 .clk = "l3_iclk_div",
3910 .user = OCP_USER_MPU | OCP_USER_SDMA,
3911 };
3913 /* l4_cfg -> pcie2 */
3914 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
3915 .master = &dra7xx_l4_cfg_hwmod,
3916 .slave = &dra7xx_pciess2_hwmod,
3917 .clk = "l4_root_clk_div",
3918 .user = OCP_USER_MPU | OCP_USER_SDMA,
3919 };
3921 /* l4_cfg -> pruss1 */
3922 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pruss1 = {
3923 .master = &dra7xx_l4_cfg_hwmod,
3924 .slave = &dra7xx_pruss1_hwmod,
3925 .clk = "dpll_gmac_h13x2_ck",
3926 .user = OCP_USER_MPU | OCP_USER_SDMA,
3927 };
3929 /* l4_cfg -> pruss2 */
3930 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pruss2 = {
3931 .master = &dra7xx_l4_cfg_hwmod,
3932 .slave = &dra7xx_pruss2_hwmod,
3933 .clk = "dpll_gmac_h13x2_ck",
3934 .user = OCP_USER_MPU | OCP_USER_SDMA,
3935 };
3937 static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
3938 {
3939 .pa_start = 0x4b300000,
3940 .pa_end = 0x4b30007f,
3941 .flags = ADDR_TYPE_RT
3942 },
3943 { }
3944 };
3946 /* l3_main_1 -> qspi */
3947 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
3948 .master = &dra7xx_l3_main_1_hwmod,
3949 .slave = &dra7xx_qspi_hwmod,
3950 .clk = "l3_iclk_div",
3951 .addr = dra7xx_qspi_addrs,
3952 .user = OCP_USER_MPU | OCP_USER_SDMA,
3953 };
3955 /* l4_per3 -> rtcss */
3956 static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
3957 .master = &dra7xx_l4_per3_hwmod,
3958 .slave = &dra7xx_rtcss_hwmod,
3959 .clk = "l4_root_clk_div",
3960 .user = OCP_USER_MPU | OCP_USER_SDMA,
3961 };
3963 static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
3964 {
3965 .name = "sysc",
3966 .pa_start = 0x4a141100,
3967 .pa_end = 0x4a141107,
3968 .flags = ADDR_TYPE_RT
3969 },
3970 { }
3971 };
3973 /* l4_cfg -> sata */
3974 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
3975 .master = &dra7xx_l4_cfg_hwmod,
3976 .slave = &dra7xx_sata_hwmod,
3977 .clk = "l3_iclk_div",
3978 .addr = dra7xx_sata_addrs,
3979 .user = OCP_USER_MPU | OCP_USER_SDMA,
3980 };
3982 static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
3983 {
3984 .pa_start = 0x4a0dd000,
3985 .pa_end = 0x4a0dd07f,
3986 .flags = ADDR_TYPE_RT
3987 },
3988 { }
3989 };
3991 /* l4_cfg -> smartreflex_core */
3992 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
3993 .master = &dra7xx_l4_cfg_hwmod,
3994 .slave = &dra7xx_smartreflex_core_hwmod,
3995 .clk = "l4_root_clk_div",
3996 .addr = dra7xx_smartreflex_core_addrs,
3997 .user = OCP_USER_MPU | OCP_USER_SDMA,
3998 };
4000 static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
4001 {
4002 .pa_start = 0x4a0d9000,
4003 .pa_end = 0x4a0d907f,
4004 .flags = ADDR_TYPE_RT
4005 },
4006 { }
4007 };
4009 /* l4_cfg -> smartreflex_mpu */
4010 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
4011 .master = &dra7xx_l4_cfg_hwmod,
4012 .slave = &dra7xx_smartreflex_mpu_hwmod,
4013 .clk = "l4_root_clk_div",
4014 .addr = dra7xx_smartreflex_mpu_addrs,
4015 .user = OCP_USER_MPU | OCP_USER_SDMA,
4016 };
4018 static struct omap_hwmod_addr_space dra7xx_spinlock_addrs[] = {
4019 {
4020 .pa_start = 0x4a0f6000,
4021 .pa_end = 0x4a0f6fff,
4022 .flags = ADDR_TYPE_RT
4023 },
4024 { }
4025 };
4027 /* l4_cfg -> spinlock */
4028 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
4029 .master = &dra7xx_l4_cfg_hwmod,
4030 .slave = &dra7xx_spinlock_hwmod,
4031 .clk = "l3_iclk_div",
4032 .addr = dra7xx_spinlock_addrs,
4033 .user = OCP_USER_MPU | OCP_USER_SDMA,
4034 };
4036 /* l4_wkup -> timer1 */
4037 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
4038 .master = &dra7xx_l4_wkup_hwmod,
4039 .slave = &dra7xx_timer1_hwmod,
4040 .clk = "wkupaon_iclk_mux",
4041 .user = OCP_USER_MPU | OCP_USER_SDMA,
4042 };
4044 /* l4_per1 -> timer2 */
4045 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
4046 .master = &dra7xx_l4_per1_hwmod,
4047 .slave = &dra7xx_timer2_hwmod,
4048 .clk = "l3_iclk_div",
4049 .user = OCP_USER_MPU | OCP_USER_SDMA,
4050 };
4052 /* l4_per1 -> timer3 */
4053 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
4054 .master = &dra7xx_l4_per1_hwmod,
4055 .slave = &dra7xx_timer3_hwmod,
4056 .clk = "l3_iclk_div",
4057 .user = OCP_USER_MPU | OCP_USER_SDMA,
4058 };
4060 /* l4_per1 -> timer4 */
4061 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
4062 .master = &dra7xx_l4_per1_hwmod,
4063 .slave = &dra7xx_timer4_hwmod,
4064 .clk = "l3_iclk_div",
4065 .user = OCP_USER_MPU | OCP_USER_SDMA,
4066 };
4068 /* l4_per3 -> timer5 */
4069 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
4070 .master = &dra7xx_l4_per3_hwmod,
4071 .slave = &dra7xx_timer5_hwmod,
4072 .clk = "l3_iclk_div",
4073 .user = OCP_USER_MPU | OCP_USER_SDMA,
4074 };
4076 /* l4_per3 -> timer6 */
4077 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
4078 .master = &dra7xx_l4_per3_hwmod,
4079 .slave = &dra7xx_timer6_hwmod,
4080 .clk = "l3_iclk_div",
4081 .user = OCP_USER_MPU | OCP_USER_SDMA,
4082 };
4084 /* l4_per3 -> timer7 */
4085 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
4086 .master = &dra7xx_l4_per3_hwmod,
4087 .slave = &dra7xx_timer7_hwmod,
4088 .clk = "l3_iclk_div",
4089 .user = OCP_USER_MPU | OCP_USER_SDMA,
4090 };
4092 /* l4_per3 -> timer8 */
4093 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
4094 .master = &dra7xx_l4_per3_hwmod,
4095 .slave = &dra7xx_timer8_hwmod,
4096 .clk = "l3_iclk_div",
4097 .user = OCP_USER_MPU | OCP_USER_SDMA,
4098 };
4100 /* l4_per1 -> timer9 */
4101 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
4102 .master = &dra7xx_l4_per1_hwmod,
4103 .slave = &dra7xx_timer9_hwmod,
4104 .clk = "l3_iclk_div",
4105 .user = OCP_USER_MPU | OCP_USER_SDMA,
4106 };
4108 /* l4_per1 -> timer10 */
4109 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
4110 .master = &dra7xx_l4_per1_hwmod,
4111 .slave = &dra7xx_timer10_hwmod,
4112 .clk = "l3_iclk_div",
4113 .user = OCP_USER_MPU | OCP_USER_SDMA,
4114 };
4116 /* l4_per1 -> timer11 */
4117 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
4118 .master = &dra7xx_l4_per1_hwmod,
4119 .slave = &dra7xx_timer11_hwmod,
4120 .clk = "l3_iclk_div",
4121 .user = OCP_USER_MPU | OCP_USER_SDMA,
4122 };
4124 /* l4_wkup -> timer12 */
4125 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer12 = {
4126 .master = &dra7xx_l4_wkup_hwmod,
4127 .slave = &dra7xx_timer12_hwmod,
4128 .clk = "wkupaon_iclk_mux",
4129 .user = OCP_USER_MPU | OCP_USER_SDMA,
4130 };
4132 /* l4_per3 -> timer13 */
4133 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
4134 .master = &dra7xx_l4_per3_hwmod,
4135 .slave = &dra7xx_timer13_hwmod,
4136 .clk = "l3_iclk_div",
4137 .user = OCP_USER_MPU | OCP_USER_SDMA,
4138 };
4140 /* l4_per3 -> timer14 */
4141 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
4142 .master = &dra7xx_l4_per3_hwmod,
4143 .slave = &dra7xx_timer14_hwmod,
4144 .clk = "l3_iclk_div",
4145 .user = OCP_USER_MPU | OCP_USER_SDMA,
4146 };
4148 /* l4_per3 -> timer15 */
4149 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
4150 .master = &dra7xx_l4_per3_hwmod,
4151 .slave = &dra7xx_timer15_hwmod,
4152 .clk = "l3_iclk_div",
4153 .user = OCP_USER_MPU | OCP_USER_SDMA,
4154 };
4156 /* l4_per3 -> timer16 */
4157 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
4158 .master = &dra7xx_l4_per3_hwmod,
4159 .slave = &dra7xx_timer16_hwmod,
4160 .clk = "l3_iclk_div",
4161 .user = OCP_USER_MPU | OCP_USER_SDMA,
4162 };
4164 /* l4_per1 -> uart1 */
4165 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
4166 .master = &dra7xx_l4_per1_hwmod,
4167 .slave = &dra7xx_uart1_hwmod,
4168 .clk = "l3_iclk_div",
4169 .user = OCP_USER_MPU | OCP_USER_SDMA,
4170 };
4172 /* l4_per1 -> uart2 */
4173 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
4174 .master = &dra7xx_l4_per1_hwmod,
4175 .slave = &dra7xx_uart2_hwmod,
4176 .clk = "l3_iclk_div",
4177 .user = OCP_USER_MPU | OCP_USER_SDMA,
4178 };
4180 /* l4_per1 -> uart3 */
4181 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
4182 .master = &dra7xx_l4_per1_hwmod,
4183 .slave = &dra7xx_uart3_hwmod,
4184 .clk = "l3_iclk_div",
4185 .user = OCP_USER_MPU | OCP_USER_SDMA,
4186 };
4188 /* l4_per1 -> uart4 */
4189 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
4190 .master = &dra7xx_l4_per1_hwmod,
4191 .slave = &dra7xx_uart4_hwmod,
4192 .clk = "l3_iclk_div",
4193 .user = OCP_USER_MPU | OCP_USER_SDMA,
4194 };
4196 /* l4_per1 -> uart5 */
4197 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
4198 .master = &dra7xx_l4_per1_hwmod,
4199 .slave = &dra7xx_uart5_hwmod,
4200 .clk = "l3_iclk_div",
4201 .user = OCP_USER_MPU | OCP_USER_SDMA,
4202 };
4204 /* l4_per1 -> uart6 */
4205 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
4206 .master = &dra7xx_l4_per1_hwmod,
4207 .slave = &dra7xx_uart6_hwmod,
4208 .clk = "l3_iclk_div",
4209 .user = OCP_USER_MPU | OCP_USER_SDMA,
4210 };
4212 /* l4_per2 -> uart7 */
4213 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
4214 .master = &dra7xx_l4_per2_hwmod,
4215 .slave = &dra7xx_uart7_hwmod,
4216 .clk = "l3_iclk_div",
4217 .user = OCP_USER_MPU | OCP_USER_SDMA,
4218 };
4220 /* l4_per2 -> uart8 */
4221 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
4222 .master = &dra7xx_l4_per2_hwmod,
4223 .slave = &dra7xx_uart8_hwmod,
4224 .clk = "l3_iclk_div",
4225 .user = OCP_USER_MPU | OCP_USER_SDMA,
4226 };
4228 /* l4_per2 -> uart9 */
4229 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
4230 .master = &dra7xx_l4_per2_hwmod,
4231 .slave = &dra7xx_uart9_hwmod,
4232 .clk = "l3_iclk_div",
4233 .user = OCP_USER_MPU | OCP_USER_SDMA,
4234 };
4236 /* l4_wkup -> uart10 */
4237 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
4238 .master = &dra7xx_l4_wkup_hwmod,
4239 .slave = &dra7xx_uart10_hwmod,
4240 .clk = "wkupaon_iclk_mux",
4241 .user = OCP_USER_MPU | OCP_USER_SDMA,
4242 };
4244 /* l4_per1 -> des */
4245 static struct omap_hwmod_ocp_if dra7xx_l4_per1__des = {
4246 .master = &dra7xx_l4_per1_hwmod,
4247 .slave = &dra7xx_des_hwmod,
4248 .clk = "l3_iclk_div",
4249 .user = OCP_USER_MPU | OCP_USER_SDMA,
4250 };
4252 /* l4_per1 -> rng */
4253 static struct omap_hwmod_ocp_if dra7xx_l4_per1__rng = {
4254 .master = &dra7xx_l4_per1_hwmod,
4255 .slave = &dra7xx_rng_hwmod,
4256 .user = OCP_USER_MPU,
4257 };
4259 /* l4_per3 -> usb_otg_ss1 */
4260 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
4261 .master = &dra7xx_l4_per3_hwmod,
4262 .slave = &dra7xx_usb_otg_ss1_hwmod,
4263 .clk = "dpll_core_h13x2_ck",
4264 .user = OCP_USER_MPU | OCP_USER_SDMA,
4265 };
4267 /* l4_per3 -> usb_otg_ss2 */
4268 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
4269 .master = &dra7xx_l4_per3_hwmod,
4270 .slave = &dra7xx_usb_otg_ss2_hwmod,
4271 .clk = "dpll_core_h13x2_ck",
4272 .user = OCP_USER_MPU | OCP_USER_SDMA,
4273 };
4275 /* l4_per3 -> usb_otg_ss3 */
4276 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
4277 .master = &dra7xx_l4_per3_hwmod,
4278 .slave = &dra7xx_usb_otg_ss3_hwmod,
4279 .clk = "dpll_core_h13x2_ck",
4280 .user = OCP_USER_MPU | OCP_USER_SDMA,
4281 };
4283 /* l4_per3 -> usb_otg_ss4 */
4284 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
4285 .master = &dra7xx_l4_per3_hwmod,
4286 .slave = &dra7xx_usb_otg_ss4_hwmod,
4287 .clk = "dpll_core_h13x2_ck",
4288 .user = OCP_USER_MPU | OCP_USER_SDMA,
4289 };
4291 /* l3_main_1 -> vcp1 */
4292 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
4293 .master = &dra7xx_l3_main_1_hwmod,
4294 .slave = &dra7xx_vcp1_hwmod,
4295 .clk = "l3_iclk_div",
4296 .user = OCP_USER_MPU | OCP_USER_SDMA,
4297 };
4299 /* l4_per2 -> vcp1 */
4300 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
4301 .master = &dra7xx_l4_per2_hwmod,
4302 .slave = &dra7xx_vcp1_hwmod,
4303 .clk = "l3_iclk_div",
4304 .user = OCP_USER_MPU | OCP_USER_SDMA,
4305 };
4307 /* l3_main_1 -> vcp2 */
4308 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
4309 .master = &dra7xx_l3_main_1_hwmod,
4310 .slave = &dra7xx_vcp2_hwmod,
4311 .clk = "l3_iclk_div",
4312 .user = OCP_USER_MPU | OCP_USER_SDMA,
4313 };
4315 /* l4_per2 -> vcp2 */
4316 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
4317 .master = &dra7xx_l4_per2_hwmod,
4318 .slave = &dra7xx_vcp2_hwmod,
4319 .clk = "l3_iclk_div",
4320 .user = OCP_USER_MPU | OCP_USER_SDMA,
4321 };
4323 /* l4_per3 -> vpe */
4324 static struct omap_hwmod_ocp_if dra7xx_l4_per3__vpe = {
4325 .master = &dra7xx_l4_per3_hwmod,
4326 .slave = &dra7xx_vpe_hwmod,
4327 .clk = "l3_iclk_div",
4328 .user = OCP_USER_MPU | OCP_USER_SDMA,
4329 };
4331 /* l4_per3 -> vip1 */
4332 static struct omap_hwmod_ocp_if dra7xx_l4_per3__vip1 = {
4333 .master = &dra7xx_l4_per3_hwmod,
4334 .slave = &dra7xx_vip1_hwmod,
4335 .clk = "l3_iclk_div",
4336 .user = OCP_USER_MPU | OCP_USER_SDMA,
4337 };
4339 /* l4_per3 -> vip2 */
4340 static struct omap_hwmod_ocp_if dra7xx_l4_per3__vip2 = {
4341 .master = &dra7xx_l4_per3_hwmod,
4342 .slave = &dra7xx_vip2_hwmod,
4343 .clk = "l3_iclk_div",
4344 .user = OCP_USER_MPU | OCP_USER_SDMA,
4345 };
4347 /* l4_per3 -> vip3 */
4348 static struct omap_hwmod_ocp_if dra7xx_l4_per3__vip3 = {
4349 .master = &dra7xx_l4_per3_hwmod,
4350 .slave = &dra7xx_vip3_hwmod,
4351 .clk = "l3_iclk_div",
4352 .user = OCP_USER_MPU | OCP_USER_SDMA,
4353 };
4355 /* l4_per3 -> cal */
4356 static struct omap_hwmod_ocp_if dra7xx_l4_per3__cal = {
4357 .master = &dra7xx_l4_per3_hwmod,
4358 .slave = &dra7xx_cal_hwmod,
4359 .clk = "l3_iclk_div",
4360 .user = OCP_USER_MPU | OCP_USER_SDMA,
4361 };
4363 /* l4_wkup -> wd_timer2 */
4364 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
4365 .master = &dra7xx_l4_wkup_hwmod,
4366 .slave = &dra7xx_wd_timer2_hwmod,
4367 .clk = "wkupaon_iclk_mux",
4368 .user = OCP_USER_MPU | OCP_USER_SDMA,
4369 };
4371 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
4372 &dra7xx_l3_main_1__dmm,
4373 &dra7xx_dmm__emif_ocp_fw,
4374 &dra7xx_l3_main_2__l3_instr,
4375 &dra7xx_l4_cfg__l3_main_1,
4376 &dra7xx_mpu__l3_main_1,
4377 &dra7xx_l3_main_1__l3_main_2,
4378 &dra7xx_l4_cfg__l3_main_2,
4379 &dra7xx_l3_main_1__l4_cfg,
4380 &dra7xx_l3_main_1__l4_per1,
4381 &dra7xx_l3_main_1__l4_per2,
4382 &dra7xx_l3_main_1__l4_per3,
4383 &dra7xx_l3_main_1__l4_wkup,
4384 &dra7xx_l4_per2__atl,
4385 &dra7xx_l3_main_1__bb2d,
4386 &dra7xx_l4_wkup__counter_32k,
4387 &dra7xx_l4_wkup__ctrl_module_wkup,
4388 &dra7xx_l4_wkup__dcan1,
4389 &dra7xx_l4_per2__dcan2,
4390 &dra7xx_l4_per2__cpgmac0,
4391 &dra7xx_gmac__mdio,
4392 &dra7xx_l4_cfg__dma_system,
4393 &dra7xx_l3_main_1__dss,
4394 &dra7xx_l3_main_1__dispc,
4395 &dra7xx_dsp1__l3_main_1,
4396 &dra7xx_l3_main_1__hdmi,
4397 &dra7xx_l3_main_1__aes,
4398 &dra7xx_l3_main_1__sha0,
4399 &dra7xx_l4_per2__mcasp3,
4400 &dra7xx_l4_per1__elm,
4401 &dra7xx_l4_wkup__gpio1,
4402 &dra7xx_l4_per1__gpio2,
4403 &dra7xx_l4_per1__gpio3,
4404 &dra7xx_l4_per1__gpio4,
4405 &dra7xx_l4_per1__gpio5,
4406 &dra7xx_l4_per1__gpio6,
4407 &dra7xx_l4_per1__gpio7,
4408 &dra7xx_l4_per1__gpio8,
4409 &dra7xx_l3_main_1__gpmc,
4410 &dra7xx_l4_per1__hdq1w,
4411 &dra7xx_l4_per1__i2c1,
4412 &dra7xx_l4_per1__i2c2,
4413 &dra7xx_l4_per1__i2c3,
4414 &dra7xx_l4_per1__i2c4,
4415 &dra7xx_l4_per1__i2c5,
4416 &dra7xx_ipu1__l3_main_1,
4417 &dra7xx_ipu2__l3_main_1,
4418 &dra7xx_l4_cfg__mailbox1,
4419 &dra7xx_l4_per3__mailbox2,
4420 &dra7xx_l4_per3__mailbox3,
4421 &dra7xx_l4_per3__mailbox4,
4422 &dra7xx_l4_per3__mailbox5,
4423 &dra7xx_l4_per3__mailbox6,
4424 &dra7xx_l4_per3__mailbox7,
4425 &dra7xx_l4_per3__mailbox8,
4426 &dra7xx_l4_per3__mailbox9,
4427 &dra7xx_l4_per3__mailbox10,
4428 &dra7xx_l4_per3__mailbox11,
4429 &dra7xx_l4_per3__mailbox12,
4430 &dra7xx_l4_per3__mailbox13,
4431 &dra7xx_l4_per1__mcspi1,
4432 &dra7xx_l4_per1__mcspi2,
4433 &dra7xx_l4_per1__mcspi3,
4434 &dra7xx_l4_per1__mcspi4,
4435 &dra7xx_l4_per1__mmc1,
4436 &dra7xx_l4_per1__mmc2,
4437 &dra7xx_l4_per1__mmc3,
4438 &dra7xx_l4_per1__mmc4,
4439 &dra7xx_l3_main_1__mmu0_dsp1,
4440 &dra7xx_l3_main_1__mmu1_dsp1,
4441 &dra7xx_l3_main_1__mmu_ipu1,
4442 &dra7xx_l3_main_1__mmu_ipu2,
4443 &dra7xx_l4_cfg__mpu,
4444 &dra7xx_l4_cfg__ocp2scp1,
4445 &dra7xx_l4_cfg__ocp2scp3,
4446 &dra7xx_l3_main_1__pciess1,
4447 &dra7xx_l4_cfg__pciess1,
4448 &dra7xx_l3_main_1__pciess2,
4449 &dra7xx_l4_cfg__pciess2,
4450 &dra7xx_l4_cfg__pruss1, /* AM57xx only */
4451 &dra7xx_l4_cfg__pruss2, /* AM57xx only */
4452 &dra7xx_l3_main_1__qspi,
4453 &dra7xx_l4_per3__rtcss,
4454 &dra7xx_l4_cfg__sata,
4455 &dra7xx_l4_cfg__smartreflex_core,
4456 &dra7xx_l4_cfg__smartreflex_mpu,
4457 &dra7xx_l4_cfg__spinlock,
4458 &dra7xx_l4_wkup__timer1,
4459 &dra7xx_l4_per1__timer2,
4460 &dra7xx_l4_per1__timer3,
4461 &dra7xx_l4_per1__timer4,
4462 &dra7xx_l4_per3__timer5,
4463 &dra7xx_l4_per3__timer6,
4464 &dra7xx_l4_per3__timer7,
4465 &dra7xx_l4_per3__timer8,
4466 &dra7xx_l4_per1__timer9,
4467 &dra7xx_l4_per1__timer10,
4468 &dra7xx_l4_per1__timer11,
4469 &dra7xx_l4_wkup__timer12,
4470 &dra7xx_l4_per3__timer13,
4471 &dra7xx_l4_per3__timer14,
4472 &dra7xx_l4_per3__timer15,
4473 &dra7xx_l4_per3__timer16,
4474 &dra7xx_l4_per1__uart1,
4475 &dra7xx_l4_per1__uart2,
4476 &dra7xx_l4_per1__uart3,
4477 &dra7xx_l4_per1__uart4,
4478 &dra7xx_l4_per1__uart5,
4479 &dra7xx_l4_per1__uart6,
4480 &dra7xx_l4_per2__uart7,
4481 &dra7xx_l4_per2__uart8,
4482 &dra7xx_l4_per2__uart9,
4483 &dra7xx_l4_wkup__uart10,
4484 &dra7xx_l4_per1__des,
4485 &dra7xx_l4_per1__rng,
4486 &dra7xx_l4_per3__usb_otg_ss1,
4487 &dra7xx_l4_per3__usb_otg_ss2,
4488 &dra7xx_l4_per3__usb_otg_ss3,
4489 &dra7xx_l3_main_1__vcp1,
4490 &dra7xx_l4_per2__vcp1,
4491 &dra7xx_l3_main_1__vcp2,
4492 &dra7xx_l4_per2__vcp2,
4493 &dra7xx_l4_per3__vpe,
4494 &dra7xx_l4_per3__vip1,
4495 &dra7xx_l4_wkup__wd_timer2,
4496 &dra7xx_l4_per2__epwmss0,
4497 &dra7xx_epwmss0__ecap0,
4498 &dra7xx_epwmss0__eqep0,
4499 &dra7xx_epwmss0__ehrpwm0,
4500 &dra7xx_l4_per2__epwmss1,
4501 &dra7xx_epwmss1__ecap1,
4502 &dra7xx_epwmss1__eqep1,
4503 &dra7xx_epwmss1__ehrpwm1,
4504 &dra7xx_l4_per2__epwmss2,
4505 &dra7xx_epwmss2__ecap2,
4506 &dra7xx_epwmss2__eqep2,
4507 &dra7xx_epwmss2__ehrpwm2,
4508 NULL,
4509 };
4511 static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
4512 &dra7xx_l4_per3__usb_otg_ss4,
4513 &dra7xx_l3_main_1__mmu0_dsp2,
4514 &dra7xx_l3_main_1__mmu1_dsp2,
4515 &dra7xx_dsp2__l3_main_1,
4516 &dra7xx_l4_per3__vip2,
4517 &dra7xx_l4_per3__vip3,
4518 NULL,
4519 };
4521 static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
4522 &dra7xx_l4_per3__cal,
4523 NULL,
4524 };
4526 int __init dra7xx_hwmod_init(void)
4527 {
4528 int ret;
4530 omap_hwmod_init();
4531 ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
4533 if (!ret && soc_is_dra74x())
4534 return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
4535 else if (!ret && soc_is_dra72x())
4536 return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
4538 return ret;
4539 }