1 /*
2 * Hardware modules present on the DRA7xx chips
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley
7 * Benoit Cousson
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
20 #include <linux/io.h>
21 #include <linux/platform_data/gpio-omap.h>
22 #include <linux/power/smartreflex.h>
23 #include <linux/platform_data/omap_ocp2scp.h>
24 #include <linux/i2c-omap.h>
26 #include <linux/omap-dma.h>
27 #include <linux/platform_data/spi-omap2-mcspi.h>
28 #include <linux/platform_data/asoc-ti-mcbsp.h>
29 #include <plat/dmtimer.h>
31 #include "omap_hwmod.h"
32 #include "omap_hwmod_common_data.h"
33 #include "cm1_7xx.h"
34 #include "cm2_7xx.h"
35 #include "prm7xx.h"
36 #include "prm-regbits-7xx.h"
37 #include "i2c.h"
38 #include "mmc.h"
39 #include "wd_timer.h"
41 /* Base offset for all DRA7XX interrupts external to MPUSS */
42 #define DRA7XX_IRQ_GIC_START 32
44 /* Base offset for all DRA7XX dma requests */
45 #define DRA7XX_DMA_REQ_START 1
48 /*
49 * IP blocks
50 */
52 /*
53 * 'dmm' class
54 * instance(s): dmm
55 */
56 static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
57 .name = "dmm",
58 };
60 /* dmm */
61 static struct omap_hwmod_irq_info dra7xx_dmm_irqs[] = {
62 { .irq = 113 + DRA7XX_IRQ_GIC_START },
63 { .irq = -1 }
64 };
66 static struct omap_hwmod dra7xx_dmm_hwmod = {
67 .name = "dmm",
68 .class = &dra7xx_dmm_hwmod_class,
69 .clkdm_name = "emif_clkdm",
70 .mpu_irqs = dra7xx_dmm_irqs,
71 .prcm = {
72 .omap4 = {
73 .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
74 .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
75 },
76 },
77 };
79 /*
80 * 'emif_ocp_fw' class
81 * instance(s): emif_ocp_fw
82 */
83 static struct omap_hwmod_class dra7xx_emif_ocp_fw_hwmod_class = {
84 .name = "emif_ocp_fw",
85 };
87 /* emif_ocp_fw */
88 static struct omap_hwmod dra7xx_emif_ocp_fw_hwmod = {
89 .name = "emif_ocp_fw",
90 .class = &dra7xx_emif_ocp_fw_hwmod_class,
91 .clkdm_name = "emif_clkdm",
92 .prcm = {
93 .omap4 = {
94 .clkctrl_offs = DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET,
95 .context_offs = DRA7XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET,
96 },
97 },
98 };
100 /*
101 * 'l3' class
102 * instance(s): l3_instr, l3_main_1, l3_main_2
103 */
104 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
105 .name = "l3",
106 };
108 /* l3_instr */
109 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
110 .name = "l3_instr",
111 .class = &dra7xx_l3_hwmod_class,
112 .clkdm_name = "l3instr_clkdm",
113 .prcm = {
114 .omap4 = {
115 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
116 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
117 .modulemode = MODULEMODE_HWCTRL,
118 },
119 },
120 };
122 /* l3_main_1 */
123 static struct omap_hwmod_irq_info dra7xx_l3_main_1_irqs[] = {
124 { .name = "dbg_err", .irq = 9 + DRA7XX_IRQ_GIC_START },
125 { .name = "app_err", .irq = 10 + DRA7XX_IRQ_GIC_START },
126 { .name = "stat_alarm", .irq = 16 + DRA7XX_IRQ_GIC_START },
127 { .irq = -1 }
128 };
130 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
131 .name = "l3_main_1",
132 .class = &dra7xx_l3_hwmod_class,
133 .clkdm_name = "l3main1_clkdm",
134 .mpu_irqs = dra7xx_l3_main_1_irqs,
135 .prcm = {
136 .omap4 = {
137 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
138 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
139 },
140 },
141 };
143 /* l3_main_2 */
144 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
145 .name = "l3_main_2",
146 .class = &dra7xx_l3_hwmod_class,
147 .clkdm_name = "l3instr_clkdm",
148 .prcm = {
149 .omap4 = {
150 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
151 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
152 .modulemode = MODULEMODE_HWCTRL,
153 },
154 },
155 };
157 /*
158 * 'l4' class
159 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
160 */
161 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
162 .name = "l4",
163 };
165 /* l4_cfg */
166 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
167 .name = "l4_cfg",
168 .class = &dra7xx_l4_hwmod_class,
169 .clkdm_name = "l4cfg_clkdm",
170 .prcm = {
171 .omap4 = {
172 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
173 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
174 },
175 },
176 };
178 /* l4_per1 */
179 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
180 .name = "l4_per1",
181 .class = &dra7xx_l4_hwmod_class,
182 .clkdm_name = "l4per_clkdm",
183 .prcm = {
184 .omap4 = {
185 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
186 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
187 },
188 },
189 };
191 /* l4_per2 */
192 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
193 .name = "l4_per2",
194 .class = &dra7xx_l4_hwmod_class,
195 .clkdm_name = "l4per2_clkdm",
196 .prcm = {
197 .omap4 = {
198 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
199 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
200 },
201 },
202 };
204 /* l4_per3 */
205 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
206 .name = "l4_per3",
207 .class = &dra7xx_l4_hwmod_class,
208 .clkdm_name = "l4per3_clkdm",
209 .prcm = {
210 .omap4 = {
211 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
212 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
213 },
214 },
215 };
217 /* l4_wkup */
218 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
219 .name = "l4_wkup",
220 .class = &dra7xx_l4_hwmod_class,
221 .clkdm_name = "wkupaon_clkdm",
222 .prcm = {
223 .omap4 = {
224 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
225 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
226 },
227 },
228 };
230 /*
231 * 'mpu_bus' class
232 * instance(s): mpu_private
233 */
234 static struct omap_hwmod_class dra7xx_mpu_bus_hwmod_class = {
235 .name = "mpu_bus",
236 };
238 /* mpu_private */
239 static struct omap_hwmod dra7xx_mpu_private_hwmod = {
240 .name = "mpu_private",
241 .class = &dra7xx_mpu_bus_hwmod_class,
242 .clkdm_name = "mpu_clkdm",
243 .prcm = {
244 .omap4 = {
245 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
246 },
247 },
248 };
250 /*
251 * 'ocp_wp_noc' class
252 * instance(s): ocp_wp_noc
253 */
254 static struct omap_hwmod_class dra7xx_ocp_wp_noc_hwmod_class = {
255 .name = "ocp_wp_noc",
256 };
258 /* ocp_wp_noc */
259 static struct omap_hwmod dra7xx_ocp_wp_noc_hwmod = {
260 .name = "ocp_wp_noc",
261 .class = &dra7xx_ocp_wp_noc_hwmod_class,
262 .clkdm_name = "l3instr_clkdm",
263 .prcm = {
264 .omap4 = {
265 .clkctrl_offs = DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET,
266 .context_offs = DRA7XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET,
267 .modulemode = MODULEMODE_HWCTRL,
268 },
269 },
270 };
272 /*
273 * 'atl' class
274 *
275 */
277 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
278 .name = "atl",
279 };
281 /* atl */
282 static struct omap_hwmod dra7xx_atl_hwmod = {
283 .name = "atl",
284 .class = &dra7xx_atl_hwmod_class,
285 .clkdm_name = "atl_clkdm",
286 .main_clk = "atl_gfclk_mux",
287 .prcm = {
288 .omap4 = {
289 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
290 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
291 .modulemode = MODULEMODE_SWCTRL,
292 },
293 },
294 };
296 /*
297 * 'bb2d' class
298 *
299 */
301 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
302 .name = "bb2d",
303 };
305 /* bb2d */
306 static struct omap_hwmod_irq_info dra7xx_bb2d_irqs[] = {
307 { .irq = 125 + DRA7XX_IRQ_GIC_START },
308 { .irq = -1 }
309 };
311 static struct omap_hwmod dra7xx_bb2d_hwmod = {
312 .name = "bb2d",
313 .class = &dra7xx_bb2d_hwmod_class,
314 .clkdm_name = "dss_clkdm",
315 .mpu_irqs = dra7xx_bb2d_irqs,
316 .main_clk = "dpll_core_h24x2_ck",
317 .prcm = {
318 .omap4 = {
319 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
320 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
321 .modulemode = MODULEMODE_SWCTRL,
322 },
323 },
324 };
326 /*
327 * 'counter' class
328 *
329 */
331 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
332 .rev_offs = 0x0000,
333 .sysc_offs = 0x0010,
334 .sysc_flags = SYSC_HAS_SIDLEMODE,
335 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
336 SIDLE_SMART_WKUP),
337 .sysc_fields = &omap_hwmod_sysc_type1,
338 };
340 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
341 .name = "counter",
342 .sysc = &dra7xx_counter_sysc,
343 };
345 /* counter_32k */
346 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
347 .name = "counter_32k",
348 .class = &dra7xx_counter_hwmod_class,
349 .clkdm_name = "wkupaon_clkdm",
350 .flags = HWMOD_SWSUP_SIDLE,
351 .main_clk = "wkupaon_iclk_mux",
352 .prcm = {
353 .omap4 = {
354 .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
355 .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
356 },
357 },
358 };
360 /*
361 * 'ctrl_module' class
362 *
363 */
365 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
366 .name = "ctrl_module",
367 };
369 /* ctrl_module_wkup */
370 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
371 .name = "ctrl_module_wkup",
372 .class = &dra7xx_ctrl_module_hwmod_class,
373 .clkdm_name = "wkupaon_clkdm",
374 .prcm = {
375 .omap4 = {
376 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
377 },
378 },
379 };
381 /*
382 * 'dcan' class
383 *
384 */
386 static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
387 .name = "dcan",
388 };
390 /* dcan1 */
391 static struct omap_hwmod dra7xx_dcan1_hwmod = {
392 .name = "dcan1",
393 .class = &dra7xx_dcan_hwmod_class,
394 .clkdm_name = "wkupaon_clkdm",
395 .main_clk = "dcan1_sys_clk_mux",
396 .prcm = {
397 .omap4 = {
398 .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
399 .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
400 .modulemode = MODULEMODE_SWCTRL,
401 },
402 },
403 };
405 /* dcan2 */
406 static struct omap_hwmod dra7xx_dcan2_hwmod = {
407 .name = "dcan2",
408 .class = &dra7xx_dcan_hwmod_class,
409 .clkdm_name = "l4per2_clkdm",
410 .main_clk = "sys_clkin1",
411 .prcm = {
412 .omap4 = {
413 .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
414 .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
415 .modulemode = MODULEMODE_SWCTRL,
416 },
417 },
418 };
420 /*
421 * 'dma' class
422 *
423 */
425 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
426 .rev_offs = 0x0000,
427 .sysc_offs = 0x002c,
428 .syss_offs = 0x0028,
429 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
430 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
431 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
432 SYSS_HAS_RESET_STATUS),
433 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
434 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
435 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
436 .sysc_fields = &omap_hwmod_sysc_type1,
437 };
439 static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
440 .name = "dma",
441 .sysc = &dra7xx_dma_sysc,
442 };
444 /* dma dev_attr */
445 static struct omap_dma_dev_attr dma_dev_attr = {
446 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
447 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
448 .lch_count = 32,
449 };
451 /* dma_system */
452 static struct omap_hwmod_irq_info dra7xx_dma_system_irqs[] = {
453 { .name = "0", .irq = 12 + DRA7XX_IRQ_GIC_START },
454 { .name = "1", .irq = 13 + DRA7XX_IRQ_GIC_START },
455 { .name = "2", .irq = 14 + DRA7XX_IRQ_GIC_START },
456 { .name = "3", .irq = 15 + DRA7XX_IRQ_GIC_START },
457 { .irq = -1 }
458 };
460 static struct omap_hwmod dra7xx_dma_system_hwmod = {
461 .name = "dma_system",
462 .class = &dra7xx_dma_hwmod_class,
463 .clkdm_name = "dma_clkdm",
464 .mpu_irqs = dra7xx_dma_system_irqs,
465 .main_clk = "l3_iclk_div",
466 .prcm = {
467 .omap4 = {
468 .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
469 .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
470 },
471 },
472 .dev_attr = &dma_dev_attr,
473 };
475 /*
476 * 'dss' class
477 *
478 */
480 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
481 .rev_offs = 0x0000,
482 .syss_offs = 0x0014,
483 .sysc_flags = SYSS_HAS_RESET_STATUS,
484 };
486 static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
487 .name = "dss",
488 .sysc = &dra7xx_dss_sysc,
489 .reset = omap_dss_reset,
490 };
492 /* dss */
493 static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
494 { .dma_req = 75 + DRA7XX_DMA_REQ_START },
495 { .dma_req = -1 }
496 };
498 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
499 { .role = "dss_clk", .clk = "dss_dss_clk" },
500 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
501 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
502 { .role = "video2_clk", .clk = "dss_video2_clk" },
503 { .role = "video1_clk", .clk = "dss_video1_clk" },
504 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
505 };
507 static struct omap_hwmod dra7xx_dss_hwmod = {
508 .name = "dss_core",
509 .class = &dra7xx_dss_hwmod_class,
510 .clkdm_name = "dss_clkdm",
511 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
512 .sdma_reqs = dra7xx_dss_sdma_reqs,
513 .main_clk = "dss_dss_clk",
514 .prcm = {
515 .omap4 = {
516 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
517 .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
518 .modulemode = MODULEMODE_SWCTRL,
519 },
520 },
521 .opt_clks = dss_opt_clks,
522 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
523 };
525 /*
526 * 'dispc' class
527 * display controller
528 */
530 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
531 .rev_offs = 0x0000,
532 .sysc_offs = 0x0010,
533 .syss_offs = 0x0014,
534 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
535 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
536 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
537 SYSS_HAS_RESET_STATUS),
538 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
539 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
540 .sysc_fields = &omap_hwmod_sysc_type1,
541 };
543 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
544 .name = "dispc",
545 .sysc = &dra7xx_dispc_sysc,
546 };
548 /* dss_dispc */
549 static struct omap_hwmod_irq_info dra7xx_dss_dispc_irqs[] = {
550 { .irq = 25 + DRA7XX_IRQ_GIC_START },
551 { .irq = -1 }
552 };
554 static struct omap_hwmod_dma_info dra7xx_dss_dispc_sdma_reqs[] = {
555 { .dma_req = 5 + DRA7XX_DMA_REQ_START },
556 { .dma_req = -1 }
557 };
559 /* dss_dispc dev_attr */
560 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
561 .has_framedonetv_irq = 1,
562 .manager_count = 4,
563 };
565 static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
566 .name = "dss_dispc",
567 .class = &dra7xx_dispc_hwmod_class,
568 .clkdm_name = "dss_clkdm",
569 .mpu_irqs = dra7xx_dss_dispc_irqs,
570 .sdma_reqs = dra7xx_dss_dispc_sdma_reqs,
571 .main_clk = "dss_dss_clk",
572 .prcm = {
573 .omap4 = {
574 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
575 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
576 },
577 },
578 .dev_attr = &dss_dispc_dev_attr,
579 };
581 /*
582 * 'hdmi' class
583 * hdmi controller
584 */
586 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
587 .rev_offs = 0x0000,
588 .sysc_offs = 0x0010,
589 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
590 SYSC_HAS_SOFTRESET),
591 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
592 SIDLE_SMART_WKUP),
593 .sysc_fields = &omap_hwmod_sysc_type2,
594 };
596 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
597 .name = "hdmi",
598 .sysc = &dra7xx_hdmi_sysc,
599 };
601 /* dss_hdmi */
602 static struct omap_hwmod_irq_info dra7xx_dss_hdmi_irqs[] = {
603 { .irq = 101 + DRA7XX_IRQ_GIC_START },
604 { .irq = -1 }
605 };
607 static struct omap_hwmod_dma_info dra7xx_dss_hdmi_sdma_reqs[] = {
608 { .dma_req = 75 + DRA7XX_DMA_REQ_START },
609 { .dma_req = -1 }
610 };
612 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
613 { .role = "sys_clk", .clk = "dss_hdmi_clk" },
614 };
616 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
617 .name = "dss_hdmi",
618 .class = &dra7xx_hdmi_hwmod_class,
619 .clkdm_name = "dss_clkdm",
620 .mpu_irqs = dra7xx_dss_hdmi_irqs,
621 .sdma_reqs = dra7xx_dss_hdmi_sdma_reqs,
622 .main_clk = "dss_48mhz_clk",
623 .prcm = {
624 .omap4 = {
625 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
626 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
627 },
628 },
629 .opt_clks = dss_hdmi_opt_clks,
630 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
631 };
633 /*
634 * 'elm' class
635 *
636 */
638 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
639 .rev_offs = 0x0000,
640 .sysc_offs = 0x0010,
641 .syss_offs = 0x0014,
642 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
643 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
644 SYSS_HAS_RESET_STATUS),
645 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
646 SIDLE_SMART_WKUP),
647 .sysc_fields = &omap_hwmod_sysc_type1,
648 };
650 static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
651 .name = "elm",
652 .sysc = &dra7xx_elm_sysc,
653 };
655 /* elm */
656 static struct omap_hwmod_irq_info dra7xx_elm_irqs[] = {
657 { .irq = 4 + DRA7XX_IRQ_GIC_START },
658 { .irq = -1 }
659 };
661 static struct omap_hwmod dra7xx_elm_hwmod = {
662 .name = "elm",
663 .class = &dra7xx_elm_hwmod_class,
664 .clkdm_name = "l4per_clkdm",
665 .mpu_irqs = dra7xx_elm_irqs,
666 .main_clk = "l3_iclk_div",
667 .prcm = {
668 .omap4 = {
669 .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
670 .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
671 },
672 },
673 };
675 /*
676 * 'emif' class
677 *
678 */
680 static struct omap_hwmod_class_sysconfig dra7xx_emif_sysc = {
681 .rev_offs = 0x0000,
682 };
684 static struct omap_hwmod_class dra7xx_emif_hwmod_class = {
685 .name = "emif",
686 .sysc = &dra7xx_emif_sysc,
687 };
689 /* emif1 */
690 static struct omap_hwmod_irq_info dra7xx_emif1_irqs[] = {
691 { .irq = 110 + DRA7XX_IRQ_GIC_START },
692 { .irq = -1 }
693 };
695 static struct omap_hwmod dra7xx_emif1_hwmod = {
696 .name = "emif1",
697 .class = &dra7xx_emif_hwmod_class,
698 .clkdm_name = "emif_clkdm",
699 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
700 .mpu_irqs = dra7xx_emif1_irqs,
701 .main_clk = "dpll_ddr_h11x2_ck",
702 .prcm = {
703 .omap4 = {
704 .clkctrl_offs = DRA7XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
705 .context_offs = DRA7XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
706 .modulemode = MODULEMODE_HWCTRL,
707 },
708 },
709 };
711 /* emif2 */
712 static struct omap_hwmod_irq_info dra7xx_emif2_irqs[] = {
713 { .irq = 111 + DRA7XX_IRQ_GIC_START },
714 { .irq = -1 }
715 };
717 static struct omap_hwmod dra7xx_emif2_hwmod = {
718 .name = "emif2",
719 .class = &dra7xx_emif_hwmod_class,
720 .clkdm_name = "emif_clkdm",
721 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
722 .mpu_irqs = dra7xx_emif2_irqs,
723 .main_clk = "dpll_ddr_h11x2_ck",
724 .prcm = {
725 .omap4 = {
726 .clkctrl_offs = DRA7XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
727 .context_offs = DRA7XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
728 .modulemode = MODULEMODE_HWCTRL,
729 },
730 },
731 };
733 /*
734 * 'gpio' class
735 *
736 */
738 static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
739 .rev_offs = 0x0000,
740 .sysc_offs = 0x0010,
741 .syss_offs = 0x0114,
742 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
743 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
744 SYSS_HAS_RESET_STATUS),
745 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
746 SIDLE_SMART_WKUP),
747 .sysc_fields = &omap_hwmod_sysc_type1,
748 };
750 static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
751 .name = "gpio",
752 .sysc = &dra7xx_gpio_sysc,
753 .rev = 2,
754 };
756 /* gpio dev_attr */
757 static struct omap_gpio_dev_attr gpio_dev_attr = {
758 .bank_width = 32,
759 .dbck_flag = true,
760 };
762 /* gpio1 */
763 static struct omap_hwmod_irq_info dra7xx_gpio1_irqs[] = {
764 { .irq = 29 + DRA7XX_IRQ_GIC_START },
765 { .irq = -1 }
766 };
768 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
769 { .role = "dbclk", .clk = "gpio1_dbclk" },
770 };
772 static struct omap_hwmod dra7xx_gpio1_hwmod = {
773 .name = "gpio1",
774 .class = &dra7xx_gpio_hwmod_class,
775 .clkdm_name = "wkupaon_clkdm",
776 .mpu_irqs = dra7xx_gpio1_irqs,
777 .main_clk = "wkupaon_iclk_mux",
778 .prcm = {
779 .omap4 = {
780 .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
781 .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
782 .modulemode = MODULEMODE_HWCTRL,
783 },
784 },
785 .opt_clks = gpio1_opt_clks,
786 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
787 .dev_attr = &gpio_dev_attr,
788 };
790 /* gpio2 */
791 static struct omap_hwmod_irq_info dra7xx_gpio2_irqs[] = {
792 { .irq = 30 + DRA7XX_IRQ_GIC_START },
793 { .irq = -1 }
794 };
796 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
797 { .role = "dbclk", .clk = "gpio2_dbclk" },
798 };
800 static struct omap_hwmod dra7xx_gpio2_hwmod = {
801 .name = "gpio2",
802 .class = &dra7xx_gpio_hwmod_class,
803 .clkdm_name = "l4per_clkdm",
804 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
805 .mpu_irqs = dra7xx_gpio2_irqs,
806 .main_clk = "l3_iclk_div",
807 .prcm = {
808 .omap4 = {
809 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
810 .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
811 .modulemode = MODULEMODE_HWCTRL,
812 },
813 },
814 .opt_clks = gpio2_opt_clks,
815 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
816 .dev_attr = &gpio_dev_attr,
817 };
819 /* gpio3 */
820 static struct omap_hwmod_irq_info dra7xx_gpio3_irqs[] = {
821 { .irq = 31 + DRA7XX_IRQ_GIC_START },
822 { .irq = -1 }
823 };
825 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
826 { .role = "dbclk", .clk = "gpio3_dbclk" },
827 };
829 static struct omap_hwmod dra7xx_gpio3_hwmod = {
830 .name = "gpio3",
831 .class = &dra7xx_gpio_hwmod_class,
832 .clkdm_name = "l4per_clkdm",
833 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
834 .mpu_irqs = dra7xx_gpio3_irqs,
835 .main_clk = "l3_iclk_div",
836 .prcm = {
837 .omap4 = {
838 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
839 .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
840 .modulemode = MODULEMODE_HWCTRL,
841 },
842 },
843 .opt_clks = gpio3_opt_clks,
844 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
845 .dev_attr = &gpio_dev_attr,
846 };
848 /* gpio4 */
849 static struct omap_hwmod_irq_info dra7xx_gpio4_irqs[] = {
850 { .irq = 32 + DRA7XX_IRQ_GIC_START },
851 { .irq = -1 }
852 };
854 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
855 { .role = "dbclk", .clk = "gpio4_dbclk" },
856 };
858 static struct omap_hwmod dra7xx_gpio4_hwmod = {
859 .name = "gpio4",
860 .class = &dra7xx_gpio_hwmod_class,
861 .clkdm_name = "l4per_clkdm",
862 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
863 .mpu_irqs = dra7xx_gpio4_irqs,
864 .main_clk = "l3_iclk_div",
865 .prcm = {
866 .omap4 = {
867 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
868 .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
869 .modulemode = MODULEMODE_HWCTRL,
870 },
871 },
872 .opt_clks = gpio4_opt_clks,
873 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
874 .dev_attr = &gpio_dev_attr,
875 };
877 /* gpio5 */
878 static struct omap_hwmod_irq_info dra7xx_gpio5_irqs[] = {
879 { .irq = 33 + DRA7XX_IRQ_GIC_START },
880 { .irq = -1 }
881 };
883 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
884 { .role = "dbclk", .clk = "gpio5_dbclk" },
885 };
887 static struct omap_hwmod dra7xx_gpio5_hwmod = {
888 .name = "gpio5",
889 .class = &dra7xx_gpio_hwmod_class,
890 .clkdm_name = "l4per_clkdm",
891 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
892 .mpu_irqs = dra7xx_gpio5_irqs,
893 .main_clk = "l3_iclk_div",
894 .prcm = {
895 .omap4 = {
896 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
897 .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
898 .modulemode = MODULEMODE_HWCTRL,
899 },
900 },
901 .opt_clks = gpio5_opt_clks,
902 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
903 .dev_attr = &gpio_dev_attr,
904 };
906 /* gpio6 */
907 static struct omap_hwmod_irq_info dra7xx_gpio6_irqs[] = {
908 { .irq = 34 + DRA7XX_IRQ_GIC_START },
909 { .irq = -1 }
910 };
912 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
913 { .role = "dbclk", .clk = "gpio6_dbclk" },
914 };
916 static struct omap_hwmod dra7xx_gpio6_hwmod = {
917 .name = "gpio6",
918 .class = &dra7xx_gpio_hwmod_class,
919 .clkdm_name = "l4per_clkdm",
920 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
921 .mpu_irqs = dra7xx_gpio6_irqs,
922 .main_clk = "l3_iclk_div",
923 .prcm = {
924 .omap4 = {
925 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
926 .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
927 .modulemode = MODULEMODE_HWCTRL,
928 },
929 },
930 .opt_clks = gpio6_opt_clks,
931 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
932 .dev_attr = &gpio_dev_attr,
933 };
935 /* gpio7 */
936 static struct omap_hwmod_irq_info dra7xx_gpio7_irqs[] = {
937 { .irq = 35 + DRA7XX_IRQ_GIC_START },
938 { .irq = -1 }
939 };
941 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
942 { .role = "dbclk", .clk = "gpio7_dbclk" },
943 };
945 static struct omap_hwmod dra7xx_gpio7_hwmod = {
946 .name = "gpio7",
947 .class = &dra7xx_gpio_hwmod_class,
948 .clkdm_name = "l4per_clkdm",
949 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
950 .mpu_irqs = dra7xx_gpio7_irqs,
951 .main_clk = "l3_iclk_div",
952 .prcm = {
953 .omap4 = {
954 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
955 .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
956 .modulemode = MODULEMODE_HWCTRL,
957 },
958 },
959 .opt_clks = gpio7_opt_clks,
960 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
961 .dev_attr = &gpio_dev_attr,
962 };
964 /* gpio8 */
965 static struct omap_hwmod_irq_info dra7xx_gpio8_irqs[] = {
966 { .irq = 121 + DRA7XX_IRQ_GIC_START },
967 { .irq = -1 }
968 };
970 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
971 { .role = "dbclk", .clk = "gpio8_dbclk" },
972 };
974 static struct omap_hwmod dra7xx_gpio8_hwmod = {
975 .name = "gpio8",
976 .class = &dra7xx_gpio_hwmod_class,
977 .clkdm_name = "l4per_clkdm",
978 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
979 .mpu_irqs = dra7xx_gpio8_irqs,
980 .main_clk = "l3_iclk_div",
981 .prcm = {
982 .omap4 = {
983 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
984 .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
985 .modulemode = MODULEMODE_HWCTRL,
986 },
987 },
988 .opt_clks = gpio8_opt_clks,
989 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
990 .dev_attr = &gpio_dev_attr,
991 };
993 /*
994 * 'gpmc' class
995 *
996 */
998 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
999 .rev_offs = 0x0000,
1000 .sysc_offs = 0x0010,
1001 .syss_offs = 0x0014,
1002 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1003 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1004 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1005 SIDLE_SMART_WKUP),
1006 .sysc_fields = &omap_hwmod_sysc_type1,
1007 };
1009 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
1010 .name = "gpmc",
1011 .sysc = &dra7xx_gpmc_sysc,
1012 };
1014 /* gpmc */
1015 static struct omap_hwmod_irq_info dra7xx_gpmc_irqs[] = {
1016 { .irq = 20 + DRA7XX_IRQ_GIC_START },
1017 { .irq = -1 }
1018 };
1020 static struct omap_hwmod_dma_info dra7xx_gpmc_sdma_reqs[] = {
1021 { .dma_req = 3 + DRA7XX_DMA_REQ_START },
1022 { .dma_req = -1 }
1023 };
1025 static struct omap_hwmod dra7xx_gpmc_hwmod = {
1026 .name = "gpmc",
1027 .class = &dra7xx_gpmc_hwmod_class,
1028 .clkdm_name = "l3main1_clkdm",
1029 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1030 .mpu_irqs = dra7xx_gpmc_irqs,
1031 .sdma_reqs = dra7xx_gpmc_sdma_reqs,
1032 .main_clk = "l3_iclk_div",
1033 .prcm = {
1034 .omap4 = {
1035 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
1036 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
1037 .modulemode = MODULEMODE_HWCTRL,
1038 },
1039 },
1040 };
1042 /*
1043 * 'gpu' class
1044 * 2d/3d graphics accelerator
1045 */
1047 static struct omap_hwmod_class_sysconfig dra7xx_gpu_sysc = {
1048 .rev_offs = 0x0000,
1049 .sysc_offs = 0x0010,
1050 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1051 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1052 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1053 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1054 .sysc_fields = &omap_hwmod_sysc_type2,
1055 };
1057 static struct omap_hwmod_class dra7xx_gpu_hwmod_class = {
1058 .name = "gpu",
1059 .sysc = &dra7xx_gpu_sysc,
1060 };
1062 /* gpu */
1063 static struct omap_hwmod_irq_info dra7xx_gpu_irqs[] = {
1064 { .irq = 21 + DRA7XX_IRQ_GIC_START },
1065 { .irq = -1 }
1066 };
1068 static struct omap_hwmod dra7xx_gpu_hwmod = {
1069 .name = "gpu",
1070 .class = &dra7xx_gpu_hwmod_class,
1071 .clkdm_name = "gpu_clkdm",
1072 .mpu_irqs = dra7xx_gpu_irqs,
1073 .main_clk = "gpu_core_gclk_mux",
1074 .prcm = {
1075 .omap4 = {
1076 .clkctrl_offs = DRA7XX_CM_GPU_GPU_CLKCTRL_OFFSET,
1077 .context_offs = DRA7XX_RM_GPU_GPU_CONTEXT_OFFSET,
1078 .modulemode = MODULEMODE_SWCTRL,
1079 },
1080 },
1081 };
1083 /*
1084 * 'hdq1w' class
1085 *
1086 */
1088 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
1089 .rev_offs = 0x0000,
1090 .sysc_offs = 0x0014,
1091 .syss_offs = 0x0018,
1092 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1093 SYSS_HAS_RESET_STATUS),
1094 .sysc_fields = &omap_hwmod_sysc_type1,
1095 };
1097 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
1098 .name = "hdq1w",
1099 .sysc = &dra7xx_hdq1w_sysc,
1100 };
1102 /* hdq1w */
1103 static struct omap_hwmod_irq_info dra7xx_hdq1w_irqs[] = {
1104 { .irq = 58 + DRA7XX_IRQ_GIC_START },
1105 { .irq = -1 }
1106 };
1108 static struct omap_hwmod dra7xx_hdq1w_hwmod = {
1109 .name = "hdq1w",
1110 .class = &dra7xx_hdq1w_hwmod_class,
1111 .clkdm_name = "l4per_clkdm",
1112 .flags = HWMOD_INIT_NO_RESET,
1113 .mpu_irqs = dra7xx_hdq1w_irqs,
1114 .main_clk = "func_12m_fclk",
1115 .prcm = {
1116 .omap4 = {
1117 .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1118 .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1119 .modulemode = MODULEMODE_SWCTRL,
1120 },
1121 },
1122 };
1124 /*
1125 * 'i2c' class
1126 *
1127 */
1129 static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
1130 .sysc_offs = 0x0010,
1131 .syss_offs = 0x0090,
1132 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1133 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1134 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1135 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1136 SIDLE_SMART_WKUP),
1137 .clockact = CLOCKACT_TEST_ICLK,
1138 .sysc_fields = &omap_hwmod_sysc_type1,
1139 };
1141 static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
1142 .name = "i2c",
1143 .sysc = &dra7xx_i2c_sysc,
1144 .reset = &omap_i2c_reset,
1145 .rev = OMAP_I2C_IP_VERSION_2,
1146 };
1148 /* i2c dev_attr */
1149 static struct omap_i2c_dev_attr i2c_dev_attr = {
1150 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1151 };
1153 /* i2c1 */
1154 static struct omap_hwmod_irq_info dra7xx_i2c1_irqs[] = {
1155 { .irq = 56 + DRA7XX_IRQ_GIC_START },
1156 { .irq = -1 }
1157 };
1159 static struct omap_hwmod_dma_info dra7xx_i2c1_sdma_reqs[] = {
1160 { .name = "27", .dma_req = 26 + DRA7XX_DMA_REQ_START },
1161 { .name = "28", .dma_req = 27 + DRA7XX_DMA_REQ_START },
1162 { .dma_req = -1 }
1163 };
1165 static struct omap_hwmod dra7xx_i2c1_hwmod = {
1166 .name = "i2c1",
1167 .class = &dra7xx_i2c_hwmod_class,
1168 .clkdm_name = "l4per_clkdm",
1169 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1170 .mpu_irqs = dra7xx_i2c1_irqs,
1171 .sdma_reqs = dra7xx_i2c1_sdma_reqs,
1172 .main_clk = "func_96m_fclk",
1173 .prcm = {
1174 .omap4 = {
1175 .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1176 .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
1177 .modulemode = MODULEMODE_SWCTRL,
1178 },
1179 },
1180 .dev_attr = &i2c_dev_attr,
1181 };
1183 /* i2c2 */
1184 static struct omap_hwmod_irq_info dra7xx_i2c2_irqs[] = {
1185 { .irq = 57 + DRA7XX_IRQ_GIC_START },
1186 { .irq = -1 }
1187 };
1189 static struct omap_hwmod_dma_info dra7xx_i2c2_sdma_reqs[] = {
1190 { .name = "29", .dma_req = 28 + DRA7XX_DMA_REQ_START },
1191 { .name = "30", .dma_req = 29 + DRA7XX_DMA_REQ_START },
1192 { .dma_req = -1 }
1193 };
1195 static struct omap_hwmod dra7xx_i2c2_hwmod = {
1196 .name = "i2c2",
1197 .class = &dra7xx_i2c_hwmod_class,
1198 .clkdm_name = "l4per_clkdm",
1199 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1200 .mpu_irqs = dra7xx_i2c2_irqs,
1201 .sdma_reqs = dra7xx_i2c2_sdma_reqs,
1202 .main_clk = "func_96m_fclk",
1203 .prcm = {
1204 .omap4 = {
1205 .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1206 .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
1207 .modulemode = MODULEMODE_SWCTRL,
1208 },
1209 },
1210 .dev_attr = &i2c_dev_attr,
1211 };
1213 /* i2c3 */
1214 static struct omap_hwmod_irq_info dra7xx_i2c3_irqs[] = {
1215 { .irq = 61 + DRA7XX_IRQ_GIC_START },
1216 { .irq = -1 }
1217 };
1219 static struct omap_hwmod_dma_info dra7xx_i2c3_sdma_reqs[] = {
1220 { .name = "25", .dma_req = 24 + DRA7XX_DMA_REQ_START },
1221 { .name = "26", .dma_req = 25 + DRA7XX_DMA_REQ_START },
1222 { .dma_req = -1 }
1223 };
1225 static struct omap_hwmod dra7xx_i2c3_hwmod = {
1226 .name = "i2c3",
1227 .class = &dra7xx_i2c_hwmod_class,
1228 .clkdm_name = "l4per_clkdm",
1229 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1230 .mpu_irqs = dra7xx_i2c3_irqs,
1231 .sdma_reqs = dra7xx_i2c3_sdma_reqs,
1232 .main_clk = "func_96m_fclk",
1233 .prcm = {
1234 .omap4 = {
1235 .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1236 .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
1237 .modulemode = MODULEMODE_SWCTRL,
1238 },
1239 },
1240 .dev_attr = &i2c_dev_attr,
1241 };
1243 /* i2c4 */
1244 static struct omap_hwmod_irq_info dra7xx_i2c4_irqs[] = {
1245 { .irq = 62 + DRA7XX_IRQ_GIC_START },
1246 { .irq = -1 }
1247 };
1249 static struct omap_hwmod_dma_info dra7xx_i2c4_sdma_reqs[] = {
1250 { .name = "124", .dma_req = 123 + DRA7XX_DMA_REQ_START },
1251 { .name = "125", .dma_req = 124 + DRA7XX_DMA_REQ_START },
1252 { .dma_req = -1 }
1253 };
1255 static struct omap_hwmod dra7xx_i2c4_hwmod = {
1256 .name = "i2c4",
1257 .class = &dra7xx_i2c_hwmod_class,
1258 .clkdm_name = "l4per_clkdm",
1259 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1260 .mpu_irqs = dra7xx_i2c4_irqs,
1261 .sdma_reqs = dra7xx_i2c4_sdma_reqs,
1262 .main_clk = "func_96m_fclk",
1263 .prcm = {
1264 .omap4 = {
1265 .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1266 .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
1267 .modulemode = MODULEMODE_SWCTRL,
1268 },
1269 },
1270 .dev_attr = &i2c_dev_attr,
1271 };
1273 /* i2c5 */
1274 static struct omap_hwmod_irq_info dra7xx_i2c5_irqs[] = {
1275 { .irq = 60 + DRA7XX_IRQ_GIC_START },
1276 { .irq = -1 }
1277 };
1279 static struct omap_hwmod dra7xx_i2c5_hwmod = {
1280 .name = "i2c5",
1281 .class = &dra7xx_i2c_hwmod_class,
1282 .clkdm_name = "ipu_clkdm",
1283 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1284 .mpu_irqs = dra7xx_i2c5_irqs,
1285 .main_clk = "func_96m_fclk",
1286 .prcm = {
1287 .omap4 = {
1288 .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
1289 .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
1290 .modulemode = MODULEMODE_SWCTRL,
1291 },
1292 },
1293 .dev_attr = &i2c_dev_attr,
1294 };
1296 /*
1297 * 'mailbox' class
1298 *
1299 */
1301 static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
1302 .rev_offs = 0x0000,
1303 .sysc_offs = 0x0010,
1304 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1305 SYSC_HAS_SOFTRESET),
1306 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1307 SIDLE_SMART_WKUP),
1308 .sysc_fields = &omap_hwmod_sysc_type2,
1309 };
1311 static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
1312 .name = "mailbox",
1313 .sysc = &dra7xx_mailbox_sysc,
1314 };
1316 /* mailbox1 */
1317 static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1318 .name = "mailbox1",
1319 .class = &dra7xx_mailbox_hwmod_class,
1320 .clkdm_name = "l4cfg_clkdm",
1321 .main_clk = "l3_iclk_div",
1322 .prcm = {
1323 .omap4 = {
1324 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1325 .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1326 },
1327 },
1328 };
1330 /* mailbox2 */
1331 static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1332 .name = "mailbox2",
1333 .class = &dra7xx_mailbox_hwmod_class,
1334 .clkdm_name = "l4cfg_clkdm",
1335 .main_clk = "l3_iclk_div",
1336 .prcm = {
1337 .omap4 = {
1338 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1339 .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1340 },
1341 },
1342 };
1344 /* mailbox3 */
1345 static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1346 .name = "mailbox3",
1347 .class = &dra7xx_mailbox_hwmod_class,
1348 .clkdm_name = "l4cfg_clkdm",
1349 .main_clk = "l3_iclk_div",
1350 .prcm = {
1351 .omap4 = {
1352 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1353 .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1354 },
1355 },
1356 };
1358 /* mailbox4 */
1359 static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1360 .name = "mailbox4",
1361 .class = &dra7xx_mailbox_hwmod_class,
1362 .clkdm_name = "l4cfg_clkdm",
1363 .main_clk = "l3_iclk_div",
1364 .prcm = {
1365 .omap4 = {
1366 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1367 .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1368 },
1369 },
1370 };
1372 /* mailbox5 */
1373 static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1374 .name = "mailbox5",
1375 .class = &dra7xx_mailbox_hwmod_class,
1376 .clkdm_name = "l4cfg_clkdm",
1377 .main_clk = "l3_iclk_div",
1378 .prcm = {
1379 .omap4 = {
1380 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1381 .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1382 },
1383 },
1384 };
1386 /* mailbox6 */
1387 static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1388 .name = "mailbox6",
1389 .class = &dra7xx_mailbox_hwmod_class,
1390 .clkdm_name = "l4cfg_clkdm",
1391 .main_clk = "l3_iclk_div",
1392 .prcm = {
1393 .omap4 = {
1394 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1395 .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1396 },
1397 },
1398 };
1400 /* mailbox7 */
1401 static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1402 .name = "mailbox7",
1403 .class = &dra7xx_mailbox_hwmod_class,
1404 .clkdm_name = "l4cfg_clkdm",
1405 .main_clk = "l3_iclk_div",
1406 .prcm = {
1407 .omap4 = {
1408 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1409 .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1410 },
1411 },
1412 };
1414 /* mailbox8 */
1415 static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1416 .name = "mailbox8",
1417 .class = &dra7xx_mailbox_hwmod_class,
1418 .clkdm_name = "l4cfg_clkdm",
1419 .main_clk = "l3_iclk_div",
1420 .prcm = {
1421 .omap4 = {
1422 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1423 .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1424 },
1425 },
1426 };
1428 /* mailbox9 */
1429 static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1430 .name = "mailbox9",
1431 .class = &dra7xx_mailbox_hwmod_class,
1432 .clkdm_name = "l4cfg_clkdm",
1433 .main_clk = "l3_iclk_div",
1434 .prcm = {
1435 .omap4 = {
1436 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1437 .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1438 },
1439 },
1440 };
1442 /* mailbox10 */
1443 static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1444 .name = "mailbox10",
1445 .class = &dra7xx_mailbox_hwmod_class,
1446 .clkdm_name = "l4cfg_clkdm",
1447 .main_clk = "l3_iclk_div",
1448 .prcm = {
1449 .omap4 = {
1450 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1451 .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1452 },
1453 },
1454 };
1456 /* mailbox11 */
1457 static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1458 .name = "mailbox11",
1459 .class = &dra7xx_mailbox_hwmod_class,
1460 .clkdm_name = "l4cfg_clkdm",
1461 .main_clk = "l3_iclk_div",
1462 .prcm = {
1463 .omap4 = {
1464 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1465 .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1466 },
1467 },
1468 };
1470 /* mailbox12 */
1471 static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1472 .name = "mailbox12",
1473 .class = &dra7xx_mailbox_hwmod_class,
1474 .clkdm_name = "l4cfg_clkdm",
1475 .main_clk = "l3_iclk_div",
1476 .prcm = {
1477 .omap4 = {
1478 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1479 .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1480 },
1481 },
1482 };
1484 /* mailbox13 */
1485 static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1486 .name = "mailbox13",
1487 .class = &dra7xx_mailbox_hwmod_class,
1488 .clkdm_name = "l4cfg_clkdm",
1489 .main_clk = "l3_iclk_div",
1490 .prcm = {
1491 .omap4 = {
1492 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1493 .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1494 },
1495 },
1496 };
1498 /*
1499 * 'mcasp' class
1500 *
1501 */
1503 static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc = {
1504 .sysc_offs = 0x0004,
1505 .sysc_flags = SYSC_HAS_SIDLEMODE,
1506 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1507 .sysc_fields = &omap_hwmod_sysc_type3,
1508 };
1510 static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
1511 .name = "mcasp",
1512 .sysc = &dra7xx_mcasp_sysc,
1513 };
1515 /* mcasp1 */
1516 static struct omap_hwmod dra7xx_mcasp1_hwmod = {
1517 .name = "mcasp1",
1518 .class = &dra7xx_mcasp_hwmod_class,
1519 .clkdm_name = "ipu_clkdm",
1520 .main_clk = "mcasp1_ahclkx_mux",
1521 .prcm = {
1522 .omap4 = {
1523 .clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET,
1524 .context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET,
1525 .modulemode = MODULEMODE_SWCTRL,
1526 },
1527 },
1528 };
1530 /* mcasp2 */
1531 static struct omap_hwmod dra7xx_mcasp2_hwmod = {
1532 .name = "mcasp2",
1533 .class = &dra7xx_mcasp_hwmod_class,
1534 .clkdm_name = "l4per2_clkdm",
1535 .main_clk = "mcasp2_ahclkr_mux",
1536 .prcm = {
1537 .omap4 = {
1538 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,
1539 .context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
1540 .modulemode = MODULEMODE_SWCTRL,
1541 },
1542 },
1543 };
1545 /* mcasp3 */
1546 static struct omap_hwmod dra7xx_mcasp3_hwmod = {
1547 .name = "mcasp3",
1548 .class = &dra7xx_mcasp_hwmod_class,
1549 .clkdm_name = "l4per2_clkdm",
1550 .main_clk = "mcasp3_ahclkx_mux",
1551 .prcm = {
1552 .omap4 = {
1553 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET,
1554 .context_offs = DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET,
1555 .modulemode = MODULEMODE_SWCTRL,
1556 },
1557 },
1558 };
1560 /* mcasp4 */
1561 static struct omap_hwmod dra7xx_mcasp4_hwmod = {
1562 .name = "mcasp4",
1563 .class = &dra7xx_mcasp_hwmod_class,
1564 .clkdm_name = "l4per2_clkdm",
1565 .main_clk = "mcasp4_ahclkx_mux",
1566 .prcm = {
1567 .omap4 = {
1568 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET,
1569 .context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET,
1570 .modulemode = MODULEMODE_SWCTRL,
1571 },
1572 },
1573 };
1575 /* mcasp5 */
1576 static struct omap_hwmod dra7xx_mcasp5_hwmod = {
1577 .name = "mcasp5",
1578 .class = &dra7xx_mcasp_hwmod_class,
1579 .clkdm_name = "l4per2_clkdm",
1580 .main_clk = "mcasp5_ahclkx_mux",
1581 .prcm = {
1582 .omap4 = {
1583 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET,
1584 .context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET,
1585 .modulemode = MODULEMODE_SWCTRL,
1586 },
1587 },
1588 };
1590 /* mcasp6 */
1591 static struct omap_hwmod dra7xx_mcasp6_hwmod = {
1592 .name = "mcasp6",
1593 .class = &dra7xx_mcasp_hwmod_class,
1594 .clkdm_name = "l4per2_clkdm",
1595 .main_clk = "mcasp6_ahclkx_mux",
1596 .prcm = {
1597 .omap4 = {
1598 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,
1599 .context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
1600 .modulemode = MODULEMODE_SWCTRL,
1601 },
1602 },
1603 };
1605 /* mcasp7 */
1606 static struct omap_hwmod dra7xx_mcasp7_hwmod = {
1607 .name = "mcasp7",
1608 .class = &dra7xx_mcasp_hwmod_class,
1609 .clkdm_name = "l4per2_clkdm",
1610 .main_clk = "mcasp7_ahclkx_mux",
1611 .prcm = {
1612 .omap4 = {
1613 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET,
1614 .context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,
1615 .modulemode = MODULEMODE_SWCTRL,
1616 },
1617 },
1618 };
1620 /* mcasp8 */
1621 static struct omap_hwmod dra7xx_mcasp8_hwmod = {
1622 .name = "mcasp8",
1623 .class = &dra7xx_mcasp_hwmod_class,
1624 .clkdm_name = "l4per2_clkdm",
1625 .main_clk = "mcasp8_ahclk_mux",
1626 .prcm = {
1627 .omap4 = {
1628 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,
1629 .context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
1630 .modulemode = MODULEMODE_SWCTRL,
1631 },
1632 },
1633 };
1635 /*
1636 * 'mcspi' class
1637 *
1638 */
1640 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1641 .rev_offs = 0x0000,
1642 .sysc_offs = 0x0010,
1643 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1644 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1645 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1646 SIDLE_SMART_WKUP),
1647 .sysc_fields = &omap_hwmod_sysc_type2,
1648 };
1650 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1651 .name = "mcspi",
1652 .sysc = &dra7xx_mcspi_sysc,
1653 .rev = OMAP4_MCSPI_REV,
1654 };
1656 /* mcspi1 */
1657 static struct omap_hwmod_irq_info dra7xx_mcspi1_irqs[] = {
1658 { .irq = 65 + DRA7XX_IRQ_GIC_START },
1659 { .irq = -1 }
1660 };
1662 static struct omap_hwmod_dma_info dra7xx_mcspi1_sdma_reqs[] = {
1663 { .name = "35", .dma_req = 34 + DRA7XX_DMA_REQ_START },
1664 { .name = "36", .dma_req = 35 + DRA7XX_DMA_REQ_START },
1665 { .name = "37", .dma_req = 36 + DRA7XX_DMA_REQ_START },
1666 { .name = "38", .dma_req = 37 + DRA7XX_DMA_REQ_START },
1667 { .name = "39", .dma_req = 38 + DRA7XX_DMA_REQ_START },
1668 { .name = "40", .dma_req = 39 + DRA7XX_DMA_REQ_START },
1669 { .name = "41", .dma_req = 40 + DRA7XX_DMA_REQ_START },
1670 { .name = "42", .dma_req = 41 + DRA7XX_DMA_REQ_START },
1671 { .dma_req = -1 }
1672 };
1674 /* mcspi1 dev_attr */
1675 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1676 .num_chipselect = 4,
1677 };
1679 static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1680 .name = "mcspi1",
1681 .class = &dra7xx_mcspi_hwmod_class,
1682 .clkdm_name = "l4per_clkdm",
1683 .mpu_irqs = dra7xx_mcspi1_irqs,
1684 .sdma_reqs = dra7xx_mcspi1_sdma_reqs,
1685 .main_clk = "func_48m_fclk",
1686 .prcm = {
1687 .omap4 = {
1688 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1689 .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1690 .modulemode = MODULEMODE_SWCTRL,
1691 },
1692 },
1693 .dev_attr = &mcspi1_dev_attr,
1694 };
1696 /* mcspi2 */
1697 static struct omap_hwmod_irq_info dra7xx_mcspi2_irqs[] = {
1698 { .irq = 66 + DRA7XX_IRQ_GIC_START },
1699 { .irq = -1 }
1700 };
1702 static struct omap_hwmod_dma_info dra7xx_mcspi2_sdma_reqs[] = {
1703 { .name = "43", .dma_req = 42 + DRA7XX_DMA_REQ_START },
1704 { .name = "44", .dma_req = 43 + DRA7XX_DMA_REQ_START },
1705 { .name = "45", .dma_req = 44 + DRA7XX_DMA_REQ_START },
1706 { .name = "46", .dma_req = 45 + DRA7XX_DMA_REQ_START },
1707 { .dma_req = -1 }
1708 };
1710 /* mcspi2 dev_attr */
1711 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1712 .num_chipselect = 2,
1713 };
1715 static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1716 .name = "mcspi2",
1717 .class = &dra7xx_mcspi_hwmod_class,
1718 .clkdm_name = "l4per_clkdm",
1719 .mpu_irqs = dra7xx_mcspi2_irqs,
1720 .sdma_reqs = dra7xx_mcspi2_sdma_reqs,
1721 .main_clk = "func_48m_fclk",
1722 .prcm = {
1723 .omap4 = {
1724 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1725 .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1726 .modulemode = MODULEMODE_SWCTRL,
1727 },
1728 },
1729 .dev_attr = &mcspi2_dev_attr,
1730 };
1732 /* mcspi3 */
1733 static struct omap_hwmod_irq_info dra7xx_mcspi3_irqs[] = {
1734 { .irq = 91 + DRA7XX_IRQ_GIC_START },
1735 { .irq = -1 }
1736 };
1738 static struct omap_hwmod_dma_info dra7xx_mcspi3_sdma_reqs[] = {
1739 { .name = "15", .dma_req = 14 + DRA7XX_DMA_REQ_START },
1740 { .name = "16", .dma_req = 15 + DRA7XX_DMA_REQ_START },
1741 { .name = "23", .dma_req = 22 + DRA7XX_DMA_REQ_START },
1742 { .name = "24", .dma_req = 23 + DRA7XX_DMA_REQ_START },
1743 { .dma_req = -1 }
1744 };
1746 /* mcspi3 dev_attr */
1747 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1748 .num_chipselect = 2,
1749 };
1751 static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1752 .name = "mcspi3",
1753 .class = &dra7xx_mcspi_hwmod_class,
1754 .clkdm_name = "l4per_clkdm",
1755 .mpu_irqs = dra7xx_mcspi3_irqs,
1756 .sdma_reqs = dra7xx_mcspi3_sdma_reqs,
1757 .main_clk = "func_48m_fclk",
1758 .prcm = {
1759 .omap4 = {
1760 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1761 .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1762 .modulemode = MODULEMODE_SWCTRL,
1763 },
1764 },
1765 .dev_attr = &mcspi3_dev_attr,
1766 };
1768 /* mcspi4 */
1769 static struct omap_hwmod_irq_info dra7xx_mcspi4_irqs[] = {
1770 { .irq = 48 + DRA7XX_IRQ_GIC_START },
1771 { .irq = -1 }
1772 };
1774 static struct omap_hwmod_dma_info dra7xx_mcspi4_sdma_reqs[] = {
1775 { .name = "70", .dma_req = 69 + DRA7XX_DMA_REQ_START },
1776 { .name = "71", .dma_req = 70 + DRA7XX_DMA_REQ_START },
1777 { .dma_req = -1 }
1778 };
1780 /* mcspi4 dev_attr */
1781 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1782 .num_chipselect = 1,
1783 };
1785 static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1786 .name = "mcspi4",
1787 .class = &dra7xx_mcspi_hwmod_class,
1788 .clkdm_name = "l4per_clkdm",
1789 .mpu_irqs = dra7xx_mcspi4_irqs,
1790 .sdma_reqs = dra7xx_mcspi4_sdma_reqs,
1791 .main_clk = "func_48m_fclk",
1792 .prcm = {
1793 .omap4 = {
1794 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1795 .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1796 .modulemode = MODULEMODE_SWCTRL,
1797 },
1798 },
1799 .dev_attr = &mcspi4_dev_attr,
1800 };
1802 /*
1803 * 'mmc' class
1804 *
1805 */
1807 static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1808 .rev_offs = 0x0000,
1809 .sysc_offs = 0x0010,
1810 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1811 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1812 SYSC_HAS_SOFTRESET),
1813 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1814 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1815 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1816 .sysc_fields = &omap_hwmod_sysc_type2,
1817 };
1819 static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1820 .name = "mmc",
1821 .sysc = &dra7xx_mmc_sysc,
1822 };
1824 /* mmc1 */
1825 static struct omap_hwmod_irq_info dra7xx_mmc1_irqs[] = {
1826 { .irq = 83 + DRA7XX_IRQ_GIC_START },
1827 { .irq = -1 }
1828 };
1830 static struct omap_hwmod_dma_info dra7xx_mmc1_sdma_reqs[] = {
1831 { .name = "tx", .dma_req = 60 + DRA7XX_DMA_REQ_START },
1832 { .name = "rx", .dma_req = 61 + DRA7XX_DMA_REQ_START },
1833 { .dma_req = -1 }
1834 };
1836 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1837 { .role = "clk32k", .clk = "mmc1_clk32k" },
1838 };
1840 /* mmc1 dev_attr */
1841 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1842 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1843 };
1845 static struct omap_hwmod dra7xx_mmc1_hwmod = {
1846 .name = "mmc1",
1847 .class = &dra7xx_mmc_hwmod_class,
1848 .clkdm_name = "l3init_clkdm",
1849 .mpu_irqs = dra7xx_mmc1_irqs,
1850 .sdma_reqs = dra7xx_mmc1_sdma_reqs,
1851 .main_clk = "mmc1_fclk_div",
1852 .prcm = {
1853 .omap4 = {
1854 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1855 .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1856 .modulemode = MODULEMODE_SWCTRL,
1857 },
1858 },
1859 .opt_clks = mmc1_opt_clks,
1860 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1861 .dev_attr = &mmc1_dev_attr,
1862 };
1864 /* mmc2 */
1865 static struct omap_hwmod_irq_info dra7xx_mmc2_irqs[] = {
1866 { .irq = 86 + DRA7XX_IRQ_GIC_START },
1867 { .irq = -1 }
1868 };
1870 static struct omap_hwmod_dma_info dra7xx_mmc2_sdma_reqs[] = {
1871 { .name = "tx", .dma_req = 46 + DRA7XX_DMA_REQ_START },
1872 { .name = "rx", .dma_req = 47 + DRA7XX_DMA_REQ_START },
1873 { .dma_req = -1 }
1874 };
1876 static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1877 { .role = "clk32k", .clk = "mmc2_clk32k" },
1878 };
1880 static struct omap_hwmod dra7xx_mmc2_hwmod = {
1881 .name = "mmc2",
1882 .class = &dra7xx_mmc_hwmod_class,
1883 .clkdm_name = "l3init_clkdm",
1884 .mpu_irqs = dra7xx_mmc2_irqs,
1885 .sdma_reqs = dra7xx_mmc2_sdma_reqs,
1886 .main_clk = "mmc2_fclk_div",
1887 .prcm = {
1888 .omap4 = {
1889 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1890 .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1891 .modulemode = MODULEMODE_SWCTRL,
1892 },
1893 },
1894 .opt_clks = mmc2_opt_clks,
1895 .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks),
1896 };
1898 /* mmc3 */
1899 static struct omap_hwmod_irq_info dra7xx_mmc3_irqs[] = {
1900 { .irq = 94 + DRA7XX_IRQ_GIC_START },
1901 { .irq = -1 }
1902 };
1904 static struct omap_hwmod_dma_info dra7xx_mmc3_sdma_reqs[] = {
1905 { .name = "77", .dma_req = 76 + DRA7XX_DMA_REQ_START },
1906 { .name = "78", .dma_req = 77 + DRA7XX_DMA_REQ_START },
1907 { .dma_req = -1 }
1908 };
1910 static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1911 { .role = "clk32k", .clk = "mmc3_clk32k" },
1912 };
1914 static struct omap_hwmod dra7xx_mmc3_hwmod = {
1915 .name = "mmc3",
1916 .class = &dra7xx_mmc_hwmod_class,
1917 .clkdm_name = "l4per_clkdm",
1918 .mpu_irqs = dra7xx_mmc3_irqs,
1919 .sdma_reqs = dra7xx_mmc3_sdma_reqs,
1920 .main_clk = "mmc3_gfclk_div",
1921 .prcm = {
1922 .omap4 = {
1923 .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1924 .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1925 .modulemode = MODULEMODE_SWCTRL,
1926 },
1927 },
1928 .opt_clks = mmc3_opt_clks,
1929 .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks),
1930 };
1932 /* mmc4 */
1933 static struct omap_hwmod_irq_info dra7xx_mmc4_irqs[] = {
1934 { .irq = 96 + DRA7XX_IRQ_GIC_START },
1935 { .irq = -1 }
1936 };
1938 static struct omap_hwmod_dma_info dra7xx_mmc4_sdma_reqs[] = {
1939 { .name = "57", .dma_req = 56 + DRA7XX_DMA_REQ_START },
1940 { .name = "58", .dma_req = 57 + DRA7XX_DMA_REQ_START },
1941 { .dma_req = -1 }
1942 };
1944 static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1945 { .role = "clk32k", .clk = "mmc4_clk32k" },
1946 };
1948 static struct omap_hwmod dra7xx_mmc4_hwmod = {
1949 .name = "mmc4",
1950 .class = &dra7xx_mmc_hwmod_class,
1951 .clkdm_name = "l4per_clkdm",
1952 .mpu_irqs = dra7xx_mmc4_irqs,
1953 .sdma_reqs = dra7xx_mmc4_sdma_reqs,
1954 .main_clk = "mmc4_gfclk_div",
1955 .prcm = {
1956 .omap4 = {
1957 .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1958 .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1959 .modulemode = MODULEMODE_SWCTRL,
1960 },
1961 },
1962 .opt_clks = mmc4_opt_clks,
1963 .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks),
1964 };
1966 /*
1967 * 'mpu' class
1968 *
1969 */
1971 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1972 .name = "mpu",
1973 };
1975 /* mpu */
1976 static struct omap_hwmod_irq_info dra7xx_mpu_irqs[] = {
1977 { .irq = 132 + DRA7XX_IRQ_GIC_START },
1978 { .irq = -1 }
1979 };
1981 static struct omap_hwmod dra7xx_mpu_hwmod = {
1982 .name = "mpu",
1983 .class = &dra7xx_mpu_hwmod_class,
1984 .clkdm_name = "mpu_clkdm",
1985 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1986 .mpu_irqs = dra7xx_mpu_irqs,
1987 .main_clk = "dpll_mpu_m2_ck",
1988 .prcm = {
1989 .omap4 = {
1990 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1991 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1992 },
1993 },
1994 };
1996 /*
1997 * 'ocmc_ram' class
1998 *
1999 */
2001 static struct omap_hwmod_class dra7xx_ocmc_ram_hwmod_class = {
2002 .name = "ocmc_ram",
2003 };
2005 /* ocmc_ram1 */
2006 static struct omap_hwmod dra7xx_ocmc_ram1_hwmod = {
2007 .name = "ocmc_ram1",
2008 .class = &dra7xx_ocmc_ram_hwmod_class,
2009 .clkdm_name = "l3main1_clkdm",
2010 .main_clk = "l3_iclk_div",
2011 .prcm = {
2012 .omap4 = {
2013 .clkctrl_offs = DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL_OFFSET,
2014 .context_offs = DRA7XX_RM_L3MAIN1_OCMC_RAM1_CONTEXT_OFFSET,
2015 },
2016 },
2017 };
2019 /* ocmc_ram2 */
2020 static struct omap_hwmod dra7xx_ocmc_ram2_hwmod = {
2021 .name = "ocmc_ram2",
2022 .class = &dra7xx_ocmc_ram_hwmod_class,
2023 .clkdm_name = "l3main1_clkdm",
2024 .main_clk = "l3_iclk_div",
2025 .prcm = {
2026 .omap4 = {
2027 .clkctrl_offs = DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL_OFFSET,
2028 .context_offs = DRA7XX_RM_L3MAIN1_OCMC_RAM2_CONTEXT_OFFSET,
2029 },
2030 },
2031 };
2033 /* ocmc_ram3 */
2034 static struct omap_hwmod dra7xx_ocmc_ram3_hwmod = {
2035 .name = "ocmc_ram3",
2036 .class = &dra7xx_ocmc_ram_hwmod_class,
2037 .clkdm_name = "l3main1_clkdm",
2038 .main_clk = "l3_iclk_div",
2039 .prcm = {
2040 .omap4 = {
2041 .clkctrl_offs = DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL_OFFSET,
2042 .context_offs = DRA7XX_RM_L3MAIN1_OCMC_RAM3_CONTEXT_OFFSET,
2043 },
2044 },
2045 };
2047 /*
2048 * 'ocmc_rom' class
2049 *
2050 */
2052 static struct omap_hwmod_class dra7xx_ocmc_rom_hwmod_class = {
2053 .name = "ocmc_rom",
2054 };
2056 /* ocmc_rom */
2057 static struct omap_hwmod dra7xx_ocmc_rom_hwmod = {
2058 .name = "ocmc_rom",
2059 .class = &dra7xx_ocmc_rom_hwmod_class,
2060 .clkdm_name = "l3main1_clkdm",
2061 .main_clk = "l3_iclk_div",
2062 .prcm = {
2063 .omap4 = {
2064 .clkctrl_offs = DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL_OFFSET,
2065 .context_offs = DRA7XX_RM_L3MAIN1_OCMC_ROM_CONTEXT_OFFSET,
2066 },
2067 },
2068 };
2070 /*
2071 * 'ocp2scp' class
2072 *
2073 */
2075 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
2076 .rev_offs = 0x0000,
2077 .sysc_offs = 0x0010,
2078 .syss_offs = 0x0014,
2079 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2080 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2081 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2082 SIDLE_SMART_WKUP),
2083 .sysc_fields = &omap_hwmod_sysc_type1,
2084 };
2086 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
2087 .name = "ocp2scp",
2088 .sysc = &dra7xx_ocp2scp_sysc,
2089 };
2091 /* ocp2scp1 */
2092 static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
2093 .name = "ocp2scp1",
2094 .class = &dra7xx_ocp2scp_hwmod_class,
2095 .clkdm_name = "l3init_clkdm",
2096 .main_clk = "l4_root_clk_div",
2097 .prcm = {
2098 .omap4 = {
2099 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
2100 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
2101 .modulemode = MODULEMODE_HWCTRL,
2102 },
2103 },
2104 };
2106 /*
2107 * 'pruss' class
2108 *
2109 */
2111 static struct omap_hwmod_class dra7xx_pruss_hwmod_class = {
2112 .name = "pruss",
2113 };
2115 /* pruss1 */
2116 static struct omap_hwmod dra7xx_pruss1_hwmod = {
2117 .name = "pruss1",
2118 .class = &dra7xx_pruss_hwmod_class,
2119 .clkdm_name = "l4per2_clkdm",
2120 .main_clk = "dpll_per_m2x2_ck",
2121 .prcm = {
2122 .omap4 = {
2123 .clkctrl_offs = DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL_OFFSET,
2124 .context_offs = DRA7XX_RM_L4PER2_PRUSS1_CONTEXT_OFFSET,
2125 .modulemode = MODULEMODE_SWCTRL,
2126 },
2127 },
2128 };
2130 /* pruss2 */
2131 static struct omap_hwmod dra7xx_pruss2_hwmod = {
2132 .name = "pruss2",
2133 .class = &dra7xx_pruss_hwmod_class,
2134 .clkdm_name = "l4per2_clkdm",
2135 .main_clk = "dpll_per_m2x2_ck",
2136 .prcm = {
2137 .omap4 = {
2138 .clkctrl_offs = DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL_OFFSET,
2139 .context_offs = DRA7XX_RM_L4PER2_PRUSS2_CONTEXT_OFFSET,
2140 .modulemode = MODULEMODE_SWCTRL,
2141 },
2142 },
2143 };
2145 /*
2146 * 'pwmss' class
2147 *
2148 */
2150 static struct omap_hwmod_class dra7xx_pwmss_hwmod_class = {
2151 .name = "pwmss",
2152 };
2154 /* pwmss1 */
2155 static struct omap_hwmod dra7xx_pwmss1_hwmod = {
2156 .name = "pwmss1",
2157 .class = &dra7xx_pwmss_hwmod_class,
2158 .clkdm_name = "l4per2_clkdm",
2159 .main_clk = "l3_iclk_div",
2160 .prcm = {
2161 .omap4 = {
2162 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET,
2163 .context_offs = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET,
2164 .modulemode = MODULEMODE_SWCTRL,
2165 },
2166 },
2167 };
2169 /* pwmss2 */
2170 static struct omap_hwmod dra7xx_pwmss2_hwmod = {
2171 .name = "pwmss2",
2172 .class = &dra7xx_pwmss_hwmod_class,
2173 .clkdm_name = "l4per2_clkdm",
2174 .main_clk = "l3_iclk_div",
2175 .prcm = {
2176 .omap4 = {
2177 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET,
2178 .context_offs = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET,
2179 .modulemode = MODULEMODE_SWCTRL,
2180 },
2181 },
2182 };
2184 /* pwmss3 */
2185 static struct omap_hwmod dra7xx_pwmss3_hwmod = {
2186 .name = "pwmss3",
2187 .class = &dra7xx_pwmss_hwmod_class,
2188 .clkdm_name = "l4per2_clkdm",
2189 .main_clk = "l3_iclk_div",
2190 .prcm = {
2191 .omap4 = {
2192 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET,
2193 .context_offs = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET,
2194 .modulemode = MODULEMODE_SWCTRL,
2195 },
2196 },
2197 };
2199 /*
2200 * 'qspi' class
2201 *
2202 */
2204 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
2205 .sysc_offs = 0x0010,
2206 .sysc_flags = SYSC_HAS_SIDLEMODE,
2207 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2208 SIDLE_SMART_WKUP),
2209 .sysc_fields = &omap_hwmod_sysc_type2,
2210 };
2212 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
2213 .name = "qspi",
2214 .sysc = &dra7xx_qspi_sysc,
2215 };
2217 /* qspi */
2218 static struct omap_hwmod dra7xx_qspi_hwmod = {
2219 .name = "qspi",
2220 .class = &dra7xx_qspi_hwmod_class,
2221 .clkdm_name = "l4per2_clkdm",
2222 .main_clk = "qspi_gfclk_div",
2223 .prcm = {
2224 .omap4 = {
2225 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
2226 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
2227 .modulemode = MODULEMODE_SWCTRL,
2228 },
2229 },
2230 };
2232 /*
2233 * 'rtcss' class
2234 *
2235 */
2237 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
2238 .sysc_offs = 0x0078,
2239 .sysc_flags = SYSC_HAS_SIDLEMODE,
2240 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2241 .sysc_fields = &omap_hwmod_sysc_type3,
2242 };
2244 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
2245 .name = "rtcss",
2246 .sysc = &dra7xx_rtcss_sysc,
2247 };
2249 /* rtcss */
2250 static struct omap_hwmod dra7xx_rtcss_hwmod = {
2251 .name = "rtcss",
2252 .class = &dra7xx_rtcss_hwmod_class,
2253 .clkdm_name = "rtc_clkdm",
2254 .main_clk = "sys_32k_ck",
2255 .prcm = {
2256 .omap4 = {
2257 .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
2258 .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
2259 .modulemode = MODULEMODE_SWCTRL,
2260 },
2261 },
2262 };
2264 /*
2265 * 'sata' class
2266 *
2267 */
2269 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
2270 .sysc_offs = 0x0000,
2271 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
2272 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2273 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2274 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2275 .sysc_fields = &omap_hwmod_sysc_type2,
2276 };
2278 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
2279 .name = "sata",
2280 .sysc = &dra7xx_sata_sysc,
2281 };
2283 /* sata */
2284 static struct omap_hwmod_irq_info dra7xx_sata_irqs[] = {
2285 { .irq = 54 + DRA7XX_IRQ_GIC_START },
2286 { .irq = -1 }
2287 };
2289 static struct omap_hwmod_opt_clk sata_opt_clks[] = {
2290 { .role = "ref_clk", .clk = "sata_ref_clk" },
2291 };
2293 static struct omap_hwmod dra7xx_sata_hwmod = {
2294 .name = "sata",
2295 .class = &dra7xx_sata_hwmod_class,
2296 .clkdm_name = "l3init_clkdm",
2297 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2298 .mpu_irqs = dra7xx_sata_irqs,
2299 .main_clk = "func_48m_fclk",
2300 .prcm = {
2301 .omap4 = {
2302 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
2303 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
2304 .modulemode = MODULEMODE_SWCTRL,
2305 },
2306 },
2307 .opt_clks = sata_opt_clks,
2308 .opt_clks_cnt = ARRAY_SIZE(sata_opt_clks),
2309 };
2311 /*
2312 * 'smartreflex' class
2313 *
2314 */
2316 /* The IP is not compliant to type1 / type2 scheme */
2317 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2318 .sidle_shift = 24,
2319 .enwkup_shift = 26,
2320 };
2322 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
2323 .sysc_offs = 0x0038,
2324 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2325 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2326 SIDLE_SMART_WKUP),
2327 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
2328 };
2330 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
2331 .name = "smartreflex",
2332 .sysc = &dra7xx_smartreflex_sysc,
2333 .rev = 2,
2334 };
2336 /* smartreflex_core */
2337 static struct omap_hwmod_irq_info dra7xx_smartreflex_core_irqs[] = {
2338 { .irq = 19 + DRA7XX_IRQ_GIC_START },
2339 { .irq = -1 }
2340 };
2342 /* smartreflex_core dev_attr */
2343 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2344 .sensor_voltdm_name = "core",
2345 };
2347 static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
2348 .name = "smartreflex_core",
2349 .class = &dra7xx_smartreflex_hwmod_class,
2350 .clkdm_name = "coreaon_clkdm",
2351 .mpu_irqs = dra7xx_smartreflex_core_irqs,
2352 .main_clk = "wkupaon_iclk_mux",
2353 .prcm = {
2354 .omap4 = {
2355 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
2356 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
2357 .modulemode = MODULEMODE_SWCTRL,
2358 },
2359 },
2360 .dev_attr = &smartreflex_core_dev_attr,
2361 };
2363 /* smartreflex_dspeve */
2364 static struct omap_hwmod dra7xx_smartreflex_dspeve_hwmod = {
2365 .name = "smartreflex_dspeve",
2366 .class = &dra7xx_smartreflex_hwmod_class,
2367 .clkdm_name = "coreaon_clkdm",
2368 .main_clk = "wkupaon_iclk_mux",
2369 .prcm = {
2370 .omap4 = {
2371 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL_OFFSET,
2372 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_DSPEVE_CONTEXT_OFFSET,
2373 .modulemode = MODULEMODE_SWCTRL,
2374 },
2375 },
2376 };
2378 /* smartreflex_gpu */
2379 static struct omap_hwmod dra7xx_smartreflex_gpu_hwmod = {
2380 .name = "smartreflex_gpu",
2381 .class = &dra7xx_smartreflex_hwmod_class,
2382 .clkdm_name = "coreaon_clkdm",
2383 .main_clk = "wkupaon_iclk_mux",
2384 .prcm = {
2385 .omap4 = {
2386 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL_OFFSET,
2387 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_GPU_CONTEXT_OFFSET,
2388 .modulemode = MODULEMODE_SWCTRL,
2389 },
2390 },
2391 };
2393 /* smartreflex_mpu */
2394 static struct omap_hwmod_irq_info dra7xx_smartreflex_mpu_irqs[] = {
2395 { .irq = 18 + DRA7XX_IRQ_GIC_START },
2396 { .irq = -1 }
2397 };
2399 /* smartreflex_mpu dev_attr */
2400 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2401 .sensor_voltdm_name = "mpu",
2402 };
2404 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
2405 .name = "smartreflex_mpu",
2406 .class = &dra7xx_smartreflex_hwmod_class,
2407 .clkdm_name = "coreaon_clkdm",
2408 .mpu_irqs = dra7xx_smartreflex_mpu_irqs,
2409 .main_clk = "wkupaon_iclk_mux",
2410 .prcm = {
2411 .omap4 = {
2412 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
2413 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
2414 .modulemode = MODULEMODE_SWCTRL,
2415 },
2416 },
2417 .dev_attr = &smartreflex_mpu_dev_attr,
2418 };
2420 /*
2421 * 'spare' class
2422 *
2423 */
2425 static struct omap_hwmod_class dra7xx_spare_hwmod_class = {
2426 .name = "spare",
2427 };
2429 /* spare_cme */
2430 static struct omap_hwmod dra7xx_spare_cme_hwmod = {
2431 .name = "spare_cme",
2432 .class = &dra7xx_spare_hwmod_class,
2433 .clkdm_name = "l3main1_clkdm",
2434 .main_clk = "l4_root_clk_div",
2435 .prcm = {
2436 .omap4 = {
2437 .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL_OFFSET,
2438 .context_offs = DRA7XX_RM_L3MAIN1_SPARE_CME_CONTEXT_OFFSET,
2439 },
2440 },
2441 };
2443 /* spare_icm */
2444 static struct omap_hwmod dra7xx_spare_icm_hwmod = {
2445 .name = "spare_icm",
2446 .class = &dra7xx_spare_hwmod_class,
2447 .clkdm_name = "l3main1_clkdm",
2448 .main_clk = "l4_root_clk_div",
2449 .prcm = {
2450 .omap4 = {
2451 .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL_OFFSET,
2452 .context_offs = DRA7XX_RM_L3MAIN1_SPARE_ICM_CONTEXT_OFFSET,
2453 },
2454 },
2455 };
2457 /* spare_iva2 */
2458 static struct omap_hwmod dra7xx_spare_iva2_hwmod = {
2459 .name = "spare_iva2",
2460 .class = &dra7xx_spare_hwmod_class,
2461 .clkdm_name = "l3main1_clkdm",
2462 .main_clk = "l3_iclk_div",
2463 .prcm = {
2464 .omap4 = {
2465 .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL_OFFSET,
2466 .context_offs = DRA7XX_RM_L3MAIN1_SPARE_IVA2_CONTEXT_OFFSET,
2467 },
2468 },
2469 };
2471 /* spare_safety1 */
2472 static struct omap_hwmod dra7xx_spare_safety1_hwmod = {
2473 .name = "spare_safety1",
2474 .class = &dra7xx_spare_hwmod_class,
2475 .clkdm_name = "wkupaon_clkdm",
2476 .main_clk = "wkupaon_iclk_mux",
2477 .prcm = {
2478 .omap4 = {
2479 .clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL_OFFSET,
2480 .context_offs = DRA7XX_RM_WKUPAON_SPARE_SAFETY1_CONTEXT_OFFSET,
2481 },
2482 },
2483 };
2485 /* spare_safety2 */
2486 static struct omap_hwmod dra7xx_spare_safety2_hwmod = {
2487 .name = "spare_safety2",
2488 .class = &dra7xx_spare_hwmod_class,
2489 .clkdm_name = "wkupaon_clkdm",
2490 .main_clk = "wkupaon_iclk_mux",
2491 .prcm = {
2492 .omap4 = {
2493 .clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL_OFFSET,
2494 .context_offs = DRA7XX_RM_WKUPAON_SPARE_SAFETY2_CONTEXT_OFFSET,
2495 },
2496 },
2497 };
2499 /* spare_safety3 */
2500 static struct omap_hwmod dra7xx_spare_safety3_hwmod = {
2501 .name = "spare_safety3",
2502 .class = &dra7xx_spare_hwmod_class,
2503 .clkdm_name = "wkupaon_clkdm",
2504 .main_clk = "wkupaon_iclk_mux",
2505 .prcm = {
2506 .omap4 = {
2507 .clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL_OFFSET,
2508 .context_offs = DRA7XX_RM_WKUPAON_SPARE_SAFETY3_CONTEXT_OFFSET,
2509 },
2510 },
2511 };
2513 /* spare_safety4 */
2514 static struct omap_hwmod dra7xx_spare_safety4_hwmod = {
2515 .name = "spare_safety4",
2516 .class = &dra7xx_spare_hwmod_class,
2517 .clkdm_name = "wkupaon_clkdm",
2518 .main_clk = "wkupaon_iclk_mux",
2519 .prcm = {
2520 .omap4 = {
2521 .clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL_OFFSET,
2522 .context_offs = DRA7XX_RM_WKUPAON_SPARE_SAFETY4_CONTEXT_OFFSET,
2523 },
2524 },
2525 };
2527 /* spare_unknown2 */
2528 static struct omap_hwmod dra7xx_spare_unknown2_hwmod = {
2529 .name = "spare_unknown2",
2530 .class = &dra7xx_spare_hwmod_class,
2531 .clkdm_name = "wkupaon_clkdm",
2532 .main_clk = "wkupaon_iclk_mux",
2533 .prcm = {
2534 .omap4 = {
2535 .clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL_OFFSET,
2536 .context_offs = DRA7XX_RM_WKUPAON_SPARE_UNKNOWN2_CONTEXT_OFFSET,
2537 },
2538 },
2539 };
2541 /* spare_unknown3 */
2542 static struct omap_hwmod dra7xx_spare_unknown3_hwmod = {
2543 .name = "spare_unknown3",
2544 .class = &dra7xx_spare_hwmod_class,
2545 .clkdm_name = "wkupaon_clkdm",
2546 .main_clk = "wkupaon_iclk_mux",
2547 .prcm = {
2548 .omap4 = {
2549 .clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL_OFFSET,
2550 .context_offs = DRA7XX_RM_WKUPAON_SPARE_UNKNOWN3_CONTEXT_OFFSET,
2551 },
2552 },
2553 };
2555 /* spare_unknown4 */
2556 static struct omap_hwmod dra7xx_spare_unknown4_hwmod = {
2557 .name = "spare_unknown4",
2558 .class = &dra7xx_spare_hwmod_class,
2559 .clkdm_name = "l3main1_clkdm",
2560 .main_clk = "l4_root_clk_div",
2561 .prcm = {
2562 .omap4 = {
2563 .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL_OFFSET,
2564 .context_offs = DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN4_CONTEXT_OFFSET,
2565 },
2566 },
2567 };
2569 /* spare_unknown5 */
2570 static struct omap_hwmod dra7xx_spare_unknown5_hwmod = {
2571 .name = "spare_unknown5",
2572 .class = &dra7xx_spare_hwmod_class,
2573 .clkdm_name = "l3main1_clkdm",
2574 .main_clk = "l4_root_clk_div",
2575 .prcm = {
2576 .omap4 = {
2577 .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL_OFFSET,
2578 .context_offs = DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN5_CONTEXT_OFFSET,
2579 },
2580 },
2581 };
2583 /* spare_unknown6 */
2584 static struct omap_hwmod dra7xx_spare_unknown6_hwmod = {
2585 .name = "spare_unknown6",
2586 .class = &dra7xx_spare_hwmod_class,
2587 .clkdm_name = "l3main1_clkdm",
2588 .main_clk = "l4_root_clk_div",
2589 .prcm = {
2590 .omap4 = {
2591 .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL_OFFSET,
2592 .context_offs = DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN6_CONTEXT_OFFSET,
2593 },
2594 },
2595 };
2597 /* spare_videopll1 */
2598 static struct omap_hwmod dra7xx_spare_videopll1_hwmod = {
2599 .name = "spare_videopll1",
2600 .class = &dra7xx_spare_hwmod_class,
2601 .clkdm_name = "l3main1_clkdm",
2602 .main_clk = "l4_root_clk_div",
2603 .prcm = {
2604 .omap4 = {
2605 .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL_OFFSET,
2606 .context_offs = DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL1_CONTEXT_OFFSET,
2607 },
2608 },
2609 };
2611 /* spare_videopll2 */
2612 static struct omap_hwmod dra7xx_spare_videopll2_hwmod = {
2613 .name = "spare_videopll2",
2614 .class = &dra7xx_spare_hwmod_class,
2615 .clkdm_name = "l3main1_clkdm",
2616 .main_clk = "l4_root_clk_div",
2617 .prcm = {
2618 .omap4 = {
2619 .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL_OFFSET,
2620 .context_offs = DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL2_CONTEXT_OFFSET,
2621 },
2622 },
2623 };
2625 /* spare_videopll3 */
2626 static struct omap_hwmod dra7xx_spare_videopll3_hwmod = {
2627 .name = "spare_videopll3",
2628 .class = &dra7xx_spare_hwmod_class,
2629 .clkdm_name = "l3main1_clkdm",
2630 .main_clk = "l4_root_clk_div",
2631 .prcm = {
2632 .omap4 = {
2633 .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL_OFFSET,
2634 .context_offs = DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL3_CONTEXT_OFFSET,
2635 },
2636 },
2637 };
2639 /*
2640 * 'spare_sata2' class
2641 *
2642 */
2644 static struct omap_hwmod_class dra7xx_spare_sata2_hwmod_class = {
2645 .name = "spare_sata2",
2646 };
2648 /* spare_sata2 */
2649 static struct omap_hwmod dra7xx_spare_sata2_hwmod = {
2650 .name = "spare_sata2",
2651 .class = &dra7xx_spare_sata2_hwmod_class,
2652 .clkdm_name = "l3main1_clkdm",
2653 .main_clk = "l4_root_clk_div",
2654 .prcm = {
2655 .omap4 = {
2656 .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL_OFFSET,
2657 .context_offs = DRA7XX_RM_L3MAIN1_SPARE_SATA2_CONTEXT_OFFSET,
2658 },
2659 },
2660 };
2662 /*
2663 * 'spare_smartreflex' class
2664 *
2665 */
2667 static struct omap_hwmod_class dra7xx_spare_smartreflex_hwmod_class = {
2668 .name = "spare_smartreflex",
2669 };
2671 /* spare_smartreflex_rtc */
2672 static struct omap_hwmod dra7xx_spare_smartreflex_rtc_hwmod = {
2673 .name = "spare_smartreflex_rtc",
2674 .class = &dra7xx_spare_smartreflex_hwmod_class,
2675 .clkdm_name = "l4cfg_clkdm",
2676 .main_clk = "l4_root_clk_div",
2677 .prcm = {
2678 .omap4 = {
2679 .clkctrl_offs = DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL_OFFSET,
2680 .context_offs = DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_RTC_CONTEXT_OFFSET,
2681 },
2682 },
2683 };
2685 /* spare_smartreflex_sdram */
2686 static struct omap_hwmod dra7xx_spare_smartreflex_sdram_hwmod = {
2687 .name = "spare_smartreflex_sdram",
2688 .class = &dra7xx_spare_smartreflex_hwmod_class,
2689 .clkdm_name = "l4cfg_clkdm",
2690 .main_clk = "l4_root_clk_div",
2691 .prcm = {
2692 .omap4 = {
2693 .clkctrl_offs = DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL_OFFSET,
2694 .context_offs = DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CONTEXT_OFFSET,
2695 },
2696 },
2697 };
2699 /* spare_smartreflex_wkup */
2700 static struct omap_hwmod dra7xx_spare_smartreflex_wkup_hwmod = {
2701 .name = "spare_smartreflex_wkup",
2702 .class = &dra7xx_spare_smartreflex_hwmod_class,
2703 .clkdm_name = "l4cfg_clkdm",
2704 .main_clk = "l4_root_clk_div",
2705 .prcm = {
2706 .omap4 = {
2707 .clkctrl_offs = DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL_OFFSET,
2708 .context_offs = DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_WKUP_CONTEXT_OFFSET,
2709 },
2710 },
2711 };
2713 /*
2714 * 'spinlock' class
2715 *
2716 */
2718 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
2719 .rev_offs = 0x0000,
2720 .sysc_offs = 0x0010,
2721 .syss_offs = 0x0014,
2722 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2723 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2724 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2725 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2726 SIDLE_SMART_WKUP),
2727 .sysc_fields = &omap_hwmod_sysc_type1,
2728 };
2730 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
2731 .name = "spinlock",
2732 .sysc = &dra7xx_spinlock_sysc,
2733 };
2735 /* spinlock */
2736 static struct omap_hwmod dra7xx_spinlock_hwmod = {
2737 .name = "spinlock",
2738 .class = &dra7xx_spinlock_hwmod_class,
2739 .clkdm_name = "l4cfg_clkdm",
2740 .main_clk = "l3_iclk_div",
2741 .prcm = {
2742 .omap4 = {
2743 .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
2744 .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
2745 },
2746 },
2747 };
2749 /*
2750 * 'timer' class
2751 *
2752 * This class contains several variants: ['timer_1ms', 'timer_secure',
2753 * 'timer']
2754 */
2756 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
2757 .rev_offs = 0x0000,
2758 .sysc_offs = 0x0010,
2759 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2760 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2761 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2762 SIDLE_SMART_WKUP),
2763 .sysc_fields = &omap_hwmod_sysc_type2,
2764 };
2766 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
2767 .name = "timer",
2768 .sysc = &dra7xx_timer_1ms_sysc,
2769 };
2771 static struct omap_hwmod_class_sysconfig dra7xx_timer_secure_sysc = {
2772 .rev_offs = 0x0000,
2773 .sysc_offs = 0x0010,
2774 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2775 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2776 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2777 SIDLE_SMART_WKUP),
2778 .sysc_fields = &omap_hwmod_sysc_type2,
2779 };
2781 static struct omap_hwmod_class dra7xx_timer_secure_hwmod_class = {
2782 .name = "timer",
2783 .sysc = &dra7xx_timer_secure_sysc,
2784 };
2786 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
2787 .rev_offs = 0x0000,
2788 .sysc_offs = 0x0010,
2789 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2790 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2791 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2792 SIDLE_SMART_WKUP),
2793 .sysc_fields = &omap_hwmod_sysc_type2,
2794 };
2796 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
2797 .name = "timer",
2798 .sysc = &dra7xx_timer_sysc,
2799 };
2801 /* timer1 */
2802 static struct omap_hwmod_irq_info dra7xx_timer1_irqs[] = {
2803 { .irq = 37 + DRA7XX_IRQ_GIC_START },
2804 { .irq = -1 }
2805 };
2807 static struct omap_hwmod dra7xx_timer1_hwmod = {
2808 .name = "timer1",
2809 .class = &dra7xx_timer_1ms_hwmod_class,
2810 .clkdm_name = "wkupaon_clkdm",
2811 .mpu_irqs = dra7xx_timer1_irqs,
2812 .main_clk = "timer1_gfclk_mux",
2813 .prcm = {
2814 .omap4 = {
2815 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
2816 .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
2817 .modulemode = MODULEMODE_SWCTRL,
2818 },
2819 },
2820 };
2822 /* timer2 */
2823 static struct omap_hwmod_irq_info dra7xx_timer2_irqs[] = {
2824 { .irq = 38 + DRA7XX_IRQ_GIC_START },
2825 { .irq = -1 }
2826 };
2828 static struct omap_hwmod dra7xx_timer2_hwmod = {
2829 .name = "timer2",
2830 .class = &dra7xx_timer_1ms_hwmod_class,
2831 .clkdm_name = "l4per_clkdm",
2832 .mpu_irqs = dra7xx_timer2_irqs,
2833 .main_clk = "timer2_gfclk_mux",
2834 .prcm = {
2835 .omap4 = {
2836 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
2837 .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
2838 .modulemode = MODULEMODE_SWCTRL,
2839 },
2840 },
2841 };
2843 /* timer3 */
2844 static struct omap_hwmod_irq_info dra7xx_timer3_irqs[] = {
2845 { .irq = 39 + DRA7XX_IRQ_GIC_START },
2846 { .irq = -1 }
2847 };
2849 static struct omap_hwmod dra7xx_timer3_hwmod = {
2850 .name = "timer3",
2851 .class = &dra7xx_timer_hwmod_class,
2852 .clkdm_name = "l4per_clkdm",
2853 .mpu_irqs = dra7xx_timer3_irqs,
2854 .main_clk = "timer3_gfclk_mux",
2855 .prcm = {
2856 .omap4 = {
2857 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
2858 .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
2859 .modulemode = MODULEMODE_SWCTRL,
2860 },
2861 },
2862 };
2864 /* timer4 */
2865 static struct omap_hwmod_irq_info dra7xx_timer4_irqs[] = {
2866 { .irq = 40 + DRA7XX_IRQ_GIC_START },
2867 { .irq = -1 }
2868 };
2870 static struct omap_hwmod dra7xx_timer4_hwmod = {
2871 .name = "timer4",
2872 .class = &dra7xx_timer_secure_hwmod_class,
2873 .clkdm_name = "l4per_clkdm",
2874 .mpu_irqs = dra7xx_timer4_irqs,
2875 .main_clk = "timer4_gfclk_mux",
2876 .prcm = {
2877 .omap4 = {
2878 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
2879 .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
2880 .modulemode = MODULEMODE_SWCTRL,
2881 },
2882 },
2883 };
2885 /* timer5 */
2886 static struct omap_hwmod_irq_info dra7xx_timer5_irqs[] = {
2887 { .irq = 41 + DRA7XX_IRQ_GIC_START },
2888 { .irq = -1 }
2889 };
2891 static struct omap_hwmod dra7xx_timer5_hwmod = {
2892 .name = "timer5",
2893 .class = &dra7xx_timer_hwmod_class,
2894 .clkdm_name = "ipu_clkdm",
2895 .mpu_irqs = dra7xx_timer5_irqs,
2896 .main_clk = "timer5_gfclk_mux",
2897 .prcm = {
2898 .omap4 = {
2899 .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
2900 .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
2901 .modulemode = MODULEMODE_SWCTRL,
2902 },
2903 },
2904 };
2906 /* timer6 */
2907 static struct omap_hwmod_irq_info dra7xx_timer6_irqs[] = {
2908 { .irq = 42 + DRA7XX_IRQ_GIC_START },
2909 { .irq = -1 }
2910 };
2912 static struct omap_hwmod dra7xx_timer6_hwmod = {
2913 .name = "timer6",
2914 .class = &dra7xx_timer_hwmod_class,
2915 .clkdm_name = "ipu_clkdm",
2916 .mpu_irqs = dra7xx_timer6_irqs,
2917 .main_clk = "timer6_gfclk_mux",
2918 .prcm = {
2919 .omap4 = {
2920 .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
2921 .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
2922 .modulemode = MODULEMODE_SWCTRL,
2923 },
2924 },
2925 };
2927 /* timer7 */
2928 static struct omap_hwmod_irq_info dra7xx_timer7_irqs[] = {
2929 { .irq = 43 + DRA7XX_IRQ_GIC_START },
2930 { .irq = -1 }
2931 };
2933 static struct omap_hwmod dra7xx_timer7_hwmod = {
2934 .name = "timer7",
2935 .class = &dra7xx_timer_hwmod_class,
2936 .clkdm_name = "ipu_clkdm",
2937 .mpu_irqs = dra7xx_timer7_irqs,
2938 .main_clk = "timer7_gfclk_mux",
2939 .prcm = {
2940 .omap4 = {
2941 .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
2942 .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
2943 .modulemode = MODULEMODE_SWCTRL,
2944 },
2945 },
2946 };
2948 /* timer8 */
2949 static struct omap_hwmod_irq_info dra7xx_timer8_irqs[] = {
2950 { .irq = 44 + DRA7XX_IRQ_GIC_START },
2951 { .irq = -1 }
2952 };
2954 static struct omap_hwmod dra7xx_timer8_hwmod = {
2955 .name = "timer8",
2956 .class = &dra7xx_timer_hwmod_class,
2957 .clkdm_name = "ipu_clkdm",
2958 .mpu_irqs = dra7xx_timer8_irqs,
2959 .main_clk = "timer8_gfclk_mux",
2960 .prcm = {
2961 .omap4 = {
2962 .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
2963 .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
2964 .modulemode = MODULEMODE_SWCTRL,
2965 },
2966 },
2967 };
2969 /* timer9 */
2970 static struct omap_hwmod_irq_info dra7xx_timer9_irqs[] = {
2971 { .irq = 45 + DRA7XX_IRQ_GIC_START },
2972 { .irq = -1 }
2973 };
2975 static struct omap_hwmod dra7xx_timer9_hwmod = {
2976 .name = "timer9",
2977 .class = &dra7xx_timer_hwmod_class,
2978 .clkdm_name = "l4per_clkdm",
2979 .mpu_irqs = dra7xx_timer9_irqs,
2980 .main_clk = "timer9_gfclk_mux",
2981 .prcm = {
2982 .omap4 = {
2983 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
2984 .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
2985 .modulemode = MODULEMODE_SWCTRL,
2986 },
2987 },
2988 };
2990 /* timer10 */
2991 static struct omap_hwmod_irq_info dra7xx_timer10_irqs[] = {
2992 { .irq = 46 + DRA7XX_IRQ_GIC_START },
2993 { .irq = -1 }
2994 };
2996 static struct omap_hwmod dra7xx_timer10_hwmod = {
2997 .name = "timer10",
2998 .class = &dra7xx_timer_1ms_hwmod_class,
2999 .clkdm_name = "l4per_clkdm",
3000 .mpu_irqs = dra7xx_timer10_irqs,
3001 .main_clk = "timer10_gfclk_mux",
3002 .prcm = {
3003 .omap4 = {
3004 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
3005 .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
3006 .modulemode = MODULEMODE_SWCTRL,
3007 },
3008 },
3009 };
3011 /* timer11 */
3012 static struct omap_hwmod_irq_info dra7xx_timer11_irqs[] = {
3013 { .irq = 47 + DRA7XX_IRQ_GIC_START },
3014 { .irq = -1 }
3015 };
3017 static struct omap_hwmod dra7xx_timer11_hwmod = {
3018 .name = "timer11",
3019 .class = &dra7xx_timer_hwmod_class,
3020 .clkdm_name = "l4per_clkdm",
3021 .mpu_irqs = dra7xx_timer11_irqs,
3022 .main_clk = "timer11_gfclk_mux",
3023 .prcm = {
3024 .omap4 = {
3025 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
3026 .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
3027 .modulemode = MODULEMODE_SWCTRL,
3028 },
3029 },
3030 };
3032 /* timer13 */
3033 static struct omap_hwmod dra7xx_timer13_hwmod = {
3034 .name = "timer13",
3035 .class = &dra7xx_timer_hwmod_class,
3036 .clkdm_name = "l4per3_clkdm",
3037 .main_clk = "timer13_gfclk_mux",
3038 .prcm = {
3039 .omap4 = {
3040 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
3041 .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
3042 .modulemode = MODULEMODE_SWCTRL,
3043 },
3044 },
3045 };
3047 /* timer14 */
3048 static struct omap_hwmod dra7xx_timer14_hwmod = {
3049 .name = "timer14",
3050 .class = &dra7xx_timer_hwmod_class,
3051 .clkdm_name = "l4per3_clkdm",
3052 .main_clk = "timer14_gfclk_mux",
3053 .prcm = {
3054 .omap4 = {
3055 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
3056 .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
3057 .modulemode = MODULEMODE_SWCTRL,
3058 },
3059 },
3060 };
3062 /* timer15 */
3063 static struct omap_hwmod dra7xx_timer15_hwmod = {
3064 .name = "timer15",
3065 .class = &dra7xx_timer_hwmod_class,
3066 .clkdm_name = "l4per3_clkdm",
3067 .main_clk = "timer15_gfclk_mux",
3068 .prcm = {
3069 .omap4 = {
3070 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
3071 .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
3072 .modulemode = MODULEMODE_SWCTRL,
3073 },
3074 },
3075 };
3077 /* timer16 */
3078 static struct omap_hwmod dra7xx_timer16_hwmod = {
3079 .name = "timer16",
3080 .class = &dra7xx_timer_hwmod_class,
3081 .clkdm_name = "l4per3_clkdm",
3082 .main_clk = "timer16_gfclk_mux",
3083 .prcm = {
3084 .omap4 = {
3085 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
3086 .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
3087 .modulemode = MODULEMODE_SWCTRL,
3088 },
3089 },
3090 };
3092 /*
3093 * 'uart' class
3094 *
3095 */
3097 static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
3098 .rev_offs = 0x0050,
3099 .sysc_offs = 0x0054,
3100 .syss_offs = 0x0058,
3101 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3102 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3103 SYSS_HAS_RESET_STATUS),
3104 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3105 SIDLE_SMART_WKUP),
3106 .sysc_fields = &omap_hwmod_sysc_type1,
3107 };
3109 static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
3110 .name = "uart",
3111 .sysc = &dra7xx_uart_sysc,
3112 };
3114 /* uart1 */
3115 static struct omap_hwmod_irq_info dra7xx_uart1_irqs[] = {
3116 { .irq = 72 + DRA7XX_IRQ_GIC_START },
3117 { .irq = -1 }
3118 };
3120 static struct omap_hwmod_dma_info dra7xx_uart1_sdma_reqs[] = {
3121 { .name = "49", .dma_req = 48 + DRA7XX_DMA_REQ_START },
3122 { .name = "50", .dma_req = 49 + DRA7XX_DMA_REQ_START },
3123 { .dma_req = -1 }
3124 };
3126 static struct omap_hwmod dra7xx_uart1_hwmod = {
3127 .name = "uart1",
3128 .class = &dra7xx_uart_hwmod_class,
3129 .clkdm_name = "l4per_clkdm",
3130 .mpu_irqs = dra7xx_uart1_irqs,
3131 .sdma_reqs = dra7xx_uart1_sdma_reqs,
3132 .main_clk = "uart1_gfclk_mux",
3133 .flags = HWMOD_SWSUP_SIDLE_ACT,
3134 .prcm = {
3135 .omap4 = {
3136 .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
3137 .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
3138 .modulemode = MODULEMODE_SWCTRL,
3139 },
3140 },
3141 };
3143 /* uart2 */
3144 static struct omap_hwmod_irq_info dra7xx_uart2_irqs[] = {
3145 { .irq = 73 + DRA7XX_IRQ_GIC_START },
3146 { .irq = -1 }
3147 };
3149 static struct omap_hwmod_dma_info dra7xx_uart2_sdma_reqs[] = {
3150 { .name = "51", .dma_req = 50 + DRA7XX_DMA_REQ_START },
3151 { .name = "52", .dma_req = 51 + DRA7XX_DMA_REQ_START },
3152 { .dma_req = -1 }
3153 };
3155 static struct omap_hwmod dra7xx_uart2_hwmod = {
3156 .name = "uart2",
3157 .class = &dra7xx_uart_hwmod_class,
3158 .clkdm_name = "l4per_clkdm",
3159 .mpu_irqs = dra7xx_uart2_irqs,
3160 .sdma_reqs = dra7xx_uart2_sdma_reqs,
3161 .main_clk = "uart2_gfclk_mux",
3162 .flags = HWMOD_SWSUP_SIDLE_ACT,
3163 .prcm = {
3164 .omap4 = {
3165 .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
3166 .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
3167 .modulemode = MODULEMODE_SWCTRL,
3168 },
3169 },
3170 };
3172 /* uart3 */
3173 static struct omap_hwmod_irq_info dra7xx_uart3_irqs[] = {
3174 { .irq = 74 + DRA7XX_IRQ_GIC_START },
3175 { .irq = -1 }
3176 };
3178 static struct omap_hwmod_dma_info dra7xx_uart3_sdma_reqs[] = {
3179 { .name = "53", .dma_req = 52 + DRA7XX_DMA_REQ_START },
3180 { .name = "54", .dma_req = 53 + DRA7XX_DMA_REQ_START },
3181 { .dma_req = -1 }
3182 };
3184 static struct omap_hwmod dra7xx_uart3_hwmod = {
3185 .name = "uart3",
3186 .class = &dra7xx_uart_hwmod_class,
3187 .clkdm_name = "l4per_clkdm",
3188 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
3189 HWMOD_SWSUP_SIDLE_ACT,
3190 .mpu_irqs = dra7xx_uart3_irqs,
3191 .sdma_reqs = dra7xx_uart3_sdma_reqs,
3192 .main_clk = "uart3_gfclk_mux",
3193 .prcm = {
3194 .omap4 = {
3195 .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
3196 .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
3197 .modulemode = MODULEMODE_SWCTRL,
3198 },
3199 },
3200 };
3202 /* uart4 */
3203 static struct omap_hwmod_irq_info dra7xx_uart4_irqs[] = {
3204 { .irq = 70 + DRA7XX_IRQ_GIC_START },
3205 { .irq = -1 }
3206 };
3208 static struct omap_hwmod_dma_info dra7xx_uart4_sdma_reqs[] = {
3209 { .name = "55", .dma_req = 54 + DRA7XX_DMA_REQ_START },
3210 { .name = "56", .dma_req = 55 + DRA7XX_DMA_REQ_START },
3211 { .dma_req = -1 }
3212 };
3214 static struct omap_hwmod dra7xx_uart4_hwmod = {
3215 .name = "uart4",
3216 .class = &dra7xx_uart_hwmod_class,
3217 .clkdm_name = "l4per_clkdm",
3218 .mpu_irqs = dra7xx_uart4_irqs,
3219 .sdma_reqs = dra7xx_uart4_sdma_reqs,
3220 .main_clk = "uart4_gfclk_mux",
3221 .flags = HWMOD_SWSUP_SIDLE_ACT,
3222 .prcm = {
3223 .omap4 = {
3224 .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
3225 .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
3226 .modulemode = MODULEMODE_SWCTRL,
3227 },
3228 },
3229 };
3231 /* uart5 */
3232 static struct omap_hwmod_irq_info dra7xx_uart5_irqs[] = {
3233 { .irq = 105 + DRA7XX_IRQ_GIC_START },
3234 { .irq = -1 }
3235 };
3237 static struct omap_hwmod_dma_info dra7xx_uart5_sdma_reqs[] = {
3238 { .name = "63", .dma_req = 62 + DRA7XX_DMA_REQ_START },
3239 { .name = "64", .dma_req = 63 + DRA7XX_DMA_REQ_START },
3240 { .dma_req = -1 }
3241 };
3243 static struct omap_hwmod dra7xx_uart5_hwmod = {
3244 .name = "uart5",
3245 .class = &dra7xx_uart_hwmod_class,
3246 .clkdm_name = "l4per_clkdm",
3247 .mpu_irqs = dra7xx_uart5_irqs,
3248 .sdma_reqs = dra7xx_uart5_sdma_reqs,
3249 .main_clk = "uart5_gfclk_mux",
3250 .flags = HWMOD_SWSUP_SIDLE_ACT,
3251 .prcm = {
3252 .omap4 = {
3253 .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
3254 .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
3255 .modulemode = MODULEMODE_SWCTRL,
3256 },
3257 },
3258 };
3260 /* uart6 */
3261 static struct omap_hwmod_irq_info dra7xx_uart6_irqs[] = {
3262 { .irq = 106 + DRA7XX_IRQ_GIC_START },
3263 { .irq = -1 }
3264 };
3266 static struct omap_hwmod_dma_info dra7xx_uart6_sdma_reqs[] = {
3267 { .name = "79", .dma_req = 78 + DRA7XX_DMA_REQ_START },
3268 { .name = "80", .dma_req = 79 + DRA7XX_DMA_REQ_START },
3269 { .dma_req = -1 }
3270 };
3272 static struct omap_hwmod dra7xx_uart6_hwmod = {
3273 .name = "uart6",
3274 .class = &dra7xx_uart_hwmod_class,
3275 .clkdm_name = "ipu_clkdm",
3276 .mpu_irqs = dra7xx_uart6_irqs,
3277 .sdma_reqs = dra7xx_uart6_sdma_reqs,
3278 .main_clk = "uart6_gfclk_mux",
3279 .flags = HWMOD_SWSUP_SIDLE_ACT,
3280 .prcm = {
3281 .omap4 = {
3282 .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
3283 .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
3284 .modulemode = MODULEMODE_SWCTRL,
3285 },
3286 },
3287 };
3289 /* uart7 */
3290 static struct omap_hwmod dra7xx_uart7_hwmod = {
3291 .name = "uart7",
3292 .class = &dra7xx_uart_hwmod_class,
3293 .clkdm_name = "l4per2_clkdm",
3294 .main_clk = "uart7_gfclk_mux",
3295 .flags = HWMOD_SWSUP_SIDLE_ACT,
3296 .prcm = {
3297 .omap4 = {
3298 .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
3299 .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
3300 .modulemode = MODULEMODE_SWCTRL,
3301 },
3302 },
3303 };
3305 /* uart8 */
3306 static struct omap_hwmod dra7xx_uart8_hwmod = {
3307 .name = "uart8",
3308 .class = &dra7xx_uart_hwmod_class,
3309 .clkdm_name = "l4per2_clkdm",
3310 .main_clk = "uart8_gfclk_mux",
3311 .flags = HWMOD_SWSUP_SIDLE_ACT,
3312 .prcm = {
3313 .omap4 = {
3314 .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
3315 .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
3316 .modulemode = MODULEMODE_SWCTRL,
3317 },
3318 },
3319 };
3321 /* uart9 */
3322 static struct omap_hwmod dra7xx_uart9_hwmod = {
3323 .name = "uart9",
3324 .class = &dra7xx_uart_hwmod_class,
3325 .clkdm_name = "l4per2_clkdm",
3326 .main_clk = "uart9_gfclk_mux",
3327 .flags = HWMOD_SWSUP_SIDLE_ACT,
3328 .prcm = {
3329 .omap4 = {
3330 .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
3331 .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
3332 .modulemode = MODULEMODE_SWCTRL,
3333 },
3334 },
3335 };
3337 /* uart10 */
3338 static struct omap_hwmod dra7xx_uart10_hwmod = {
3339 .name = "uart10",
3340 .class = &dra7xx_uart_hwmod_class,
3341 .clkdm_name = "wkupaon_clkdm",
3342 .main_clk = "uart10_gfclk_mux",
3343 .flags = HWMOD_SWSUP_SIDLE_ACT,
3344 .prcm = {
3345 .omap4 = {
3346 .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
3347 .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
3348 .modulemode = MODULEMODE_SWCTRL,
3349 },
3350 },
3351 };
3353 /*
3354 * 'usb_otg_ss' class
3355 *
3356 */
3358 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
3359 .name = "usb_otg_ss",
3360 };
3362 /* usb_otg_ss1 */
3363 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
3364 { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
3365 };
3367 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
3368 .name = "usb_otg_ss1",
3369 .class = &dra7xx_usb_otg_ss_hwmod_class,
3370 .clkdm_name = "l3init_clkdm",
3371 .main_clk = "dpll_core_h13x2_ck",
3372 .prcm = {
3373 .omap4 = {
3374 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
3375 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
3376 .modulemode = MODULEMODE_HWCTRL,
3377 },
3378 },
3379 .opt_clks = usb_otg_ss1_opt_clks,
3380 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
3381 };
3383 /* usb_otg_ss2 */
3384 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
3385 { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
3386 };
3388 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
3389 .name = "usb_otg_ss2",
3390 .class = &dra7xx_usb_otg_ss_hwmod_class,
3391 .clkdm_name = "l3init_clkdm",
3392 .main_clk = "dpll_core_h13x2_ck",
3393 .prcm = {
3394 .omap4 = {
3395 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
3396 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
3397 .modulemode = MODULEMODE_HWCTRL,
3398 },
3399 },
3400 .opt_clks = usb_otg_ss2_opt_clks,
3401 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
3402 };
3404 /* usb_otg_ss3 */
3405 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
3406 .name = "usb_otg_ss3",
3407 .class = &dra7xx_usb_otg_ss_hwmod_class,
3408 .clkdm_name = "l3init_clkdm",
3409 .main_clk = "dpll_core_h13x2_ck",
3410 .prcm = {
3411 .omap4 = {
3412 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
3413 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
3414 .modulemode = MODULEMODE_HWCTRL,
3415 },
3416 },
3417 };
3419 /* usb_otg_ss4 */
3420 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
3421 .name = "usb_otg_ss4",
3422 .class = &dra7xx_usb_otg_ss_hwmod_class,
3423 .clkdm_name = "l3init_clkdm",
3424 .main_clk = "dpll_core_h13x2_ck",
3425 .prcm = {
3426 .omap4 = {
3427 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
3428 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
3429 .modulemode = MODULEMODE_HWCTRL,
3430 },
3431 },
3432 };
3434 /*
3435 * 'vcp' class
3436 *
3437 */
3439 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
3440 .name = "vcp",
3441 };
3443 /* vcp1 */
3444 static struct omap_hwmod dra7xx_vcp1_hwmod = {
3445 .name = "vcp1",
3446 .class = &dra7xx_vcp_hwmod_class,
3447 .clkdm_name = "l3main1_clkdm",
3448 .main_clk = "l3_iclk_div",
3449 .prcm = {
3450 .omap4 = {
3451 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
3452 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
3453 },
3454 },
3455 };
3457 /* vcp2 */
3458 static struct omap_hwmod dra7xx_vcp2_hwmod = {
3459 .name = "vcp2",
3460 .class = &dra7xx_vcp_hwmod_class,
3461 .clkdm_name = "l3main1_clkdm",
3462 .main_clk = "l3_iclk_div",
3463 .prcm = {
3464 .omap4 = {
3465 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
3466 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
3467 },
3468 },
3469 };
3471 /*
3472 * 'vip' class
3473 *
3474 */
3476 static struct omap_hwmod_class_sysconfig dra7xx_vip_sysc = {
3477 .sysc_offs = 0x0010,
3478 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
3479 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3480 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3481 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3482 .sysc_fields = &omap_hwmod_sysc_type2,
3483 };
3485 static struct omap_hwmod_class dra7xx_vip_hwmod_class = {
3486 .name = "vip",
3487 .sysc = &dra7xx_vip_sysc,
3488 };
3490 /* vip1 */
3491 static struct omap_hwmod dra7xx_vip1_hwmod = {
3492 .name = "vip1",
3493 .class = &dra7xx_vip_hwmod_class,
3494 .clkdm_name = "cam_clkdm",
3495 .main_clk = "vip1_gclk_mux",
3496 .prcm = {
3497 .omap4 = {
3498 .clkctrl_offs = DRA7XX_CM_CAM_VIP1_CLKCTRL_OFFSET,
3499 .context_offs = DRA7XX_RM_CAM_VIP1_CONTEXT_OFFSET,
3500 .modulemode = MODULEMODE_HWCTRL,
3501 },
3502 },
3503 };
3505 /* vip2 */
3506 static struct omap_hwmod dra7xx_vip2_hwmod = {
3507 .name = "vip2",
3508 .class = &dra7xx_vip_hwmod_class,
3509 .clkdm_name = "cam_clkdm",
3510 .main_clk = "vip2_gclk_mux",
3511 .prcm = {
3512 .omap4 = {
3513 .clkctrl_offs = DRA7XX_CM_CAM_VIP2_CLKCTRL_OFFSET,
3514 .context_offs = DRA7XX_RM_CAM_VIP2_CONTEXT_OFFSET,
3515 .modulemode = MODULEMODE_HWCTRL,
3516 },
3517 },
3518 };
3520 /* vip3 */
3521 static struct omap_hwmod dra7xx_vip3_hwmod = {
3522 .name = "vip3",
3523 .class = &dra7xx_vip_hwmod_class,
3524 .clkdm_name = "cam_clkdm",
3525 .main_clk = "vip3_gclk_mux",
3526 .prcm = {
3527 .omap4 = {
3528 .clkctrl_offs = DRA7XX_CM_CAM_VIP3_CLKCTRL_OFFSET,
3529 .context_offs = DRA7XX_RM_CAM_VIP3_CONTEXT_OFFSET,
3530 .modulemode = MODULEMODE_HWCTRL,
3531 },
3532 },
3533 };
3535 /*
3536 * 'vpe' class
3537 *
3538 */
3540 static struct omap_hwmod_class_sysconfig dra7xx_vpe_sysc = {
3541 .sysc_offs = 0x0010,
3542 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
3543 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3544 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3545 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3546 .sysc_fields = &omap_hwmod_sysc_type2,
3547 };
3549 static struct omap_hwmod_class dra7xx_vpe_hwmod_class = {
3550 .name = "vpe",
3551 .sysc = &dra7xx_vpe_sysc,
3552 };
3554 /* vpe */
3555 static struct omap_hwmod dra7xx_vpe_hwmod = {
3556 .name = "vpe",
3557 .class = &dra7xx_vpe_hwmod_class,
3558 .clkdm_name = "vpe_clkdm",
3559 .main_clk = "dpll_core_h23x2_ck",
3560 .prcm = {
3561 .omap4 = {
3562 .clkctrl_offs = DRA7XX_CM_VPE_VPE_CLKCTRL_OFFSET,
3563 .context_offs = DRA7XX_RM_VPE_VPE_CONTEXT_OFFSET,
3564 .modulemode = MODULEMODE_HWCTRL,
3565 },
3566 },
3567 };
3569 /*
3570 * 'wd_timer' class
3571 *
3572 */
3574 static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
3575 .rev_offs = 0x0000,
3576 .sysc_offs = 0x0010,
3577 .syss_offs = 0x0014,
3578 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3579 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3580 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3581 SIDLE_SMART_WKUP),
3582 .sysc_fields = &omap_hwmod_sysc_type1,
3583 };
3585 static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
3586 .name = "wd_timer",
3587 .sysc = &dra7xx_wd_timer_sysc,
3588 .pre_shutdown = &omap2_wd_timer_disable,
3589 .reset = &omap2_wd_timer_reset,
3590 };
3592 /* wd_timer2 */
3593 static struct omap_hwmod_irq_info dra7xx_wd_timer2_irqs[] = {
3594 { .irq = 80 + DRA7XX_IRQ_GIC_START },
3595 { .irq = -1 }
3596 };
3598 static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
3599 .name = "wd_timer2",
3600 .class = &dra7xx_wd_timer_hwmod_class,
3601 .clkdm_name = "wkupaon_clkdm",
3602 .mpu_irqs = dra7xx_wd_timer2_irqs,
3603 .main_clk = "sys_32k_ck",
3604 .prcm = {
3605 .omap4 = {
3606 .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
3607 .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
3608 .modulemode = MODULEMODE_SWCTRL,
3609 },
3610 },
3611 };
3614 /*
3615 * Interfaces
3616 */
3618 static struct omap_hwmod_addr_space dra7xx_dmm_addrs[] = {
3619 {
3620 .pa_start = 0x4e000000,
3621 .pa_end = 0x4e0007ff,
3622 .flags = ADDR_TYPE_RT
3623 },
3624 { }
3625 };
3627 /* l3_main_1 -> dmm */
3628 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
3629 .master = &dra7xx_l3_main_1_hwmod,
3630 .slave = &dra7xx_dmm_hwmod,
3631 .clk = "l3_iclk_div",
3632 .addr = dra7xx_dmm_addrs,
3633 .user = OCP_USER_SDMA,
3634 };
3636 /* dmm -> emif_ocp_fw */
3637 static struct omap_hwmod_ocp_if dra7xx_dmm__emif_ocp_fw = {
3638 .master = &dra7xx_dmm_hwmod,
3639 .slave = &dra7xx_emif_ocp_fw_hwmod,
3640 .clk = "l3_iclk_div",
3641 .user = OCP_USER_MPU | OCP_USER_SDMA,
3642 };
3644 /* l4_cfg -> emif_ocp_fw */
3645 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__emif_ocp_fw = {
3646 .master = &dra7xx_l4_cfg_hwmod,
3647 .slave = &dra7xx_emif_ocp_fw_hwmod,
3648 .clk = "l3_iclk_div",
3649 .user = OCP_USER_MPU | OCP_USER_SDMA,
3650 };
3652 /* l3_main_2 -> l3_instr */
3653 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
3654 .master = &dra7xx_l3_main_2_hwmod,
3655 .slave = &dra7xx_l3_instr_hwmod,
3656 .clk = "l3_iclk_div",
3657 .user = OCP_USER_MPU | OCP_USER_SDMA,
3658 };
3660 /* ocp_wp_noc -> l3_instr */
3661 static struct omap_hwmod_ocp_if dra7xx_ocp_wp_noc__l3_instr = {
3662 .master = &dra7xx_ocp_wp_noc_hwmod,
3663 .slave = &dra7xx_l3_instr_hwmod,
3664 .clk = "l3_iclk_div",
3665 .user = OCP_USER_MPU | OCP_USER_SDMA,
3666 };
3668 /* l4_cfg -> l3_main_1 */
3669 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
3670 .master = &dra7xx_l4_cfg_hwmod,
3671 .slave = &dra7xx_l3_main_1_hwmod,
3672 .clk = "l3_iclk_div",
3673 .user = OCP_USER_MPU | OCP_USER_SDMA,
3674 };
3676 static struct omap_hwmod_addr_space dra7xx_l3_main_1_addrs[] = {
3677 {
3678 .pa_start = 0x44000000,
3679 .pa_end = 0x44805fff,
3680 },
3681 { }
3682 };
3684 /* mpu -> l3_main_1 */
3685 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
3686 .master = &dra7xx_mpu_hwmod,
3687 .slave = &dra7xx_l3_main_1_hwmod,
3688 .clk = "l3_iclk_div",
3689 .addr = dra7xx_l3_main_1_addrs,
3690 .user = OCP_USER_MPU,
3691 };
3693 static struct omap_hwmod_addr_space dra7xx_l3_main_2_addrs[] = {
3694 {
3695 .pa_start = 0x45000000,
3696 .pa_end = 0x4500afff,
3697 },
3698 { }
3699 };
3701 /* l3_main_1 -> l3_main_2 */
3702 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
3703 .master = &dra7xx_l3_main_1_hwmod,
3704 .slave = &dra7xx_l3_main_2_hwmod,
3705 .clk = "l3_iclk_div",
3706 .addr = dra7xx_l3_main_2_addrs,
3707 .user = OCP_USER_MPU,
3708 };
3710 /* l4_cfg -> l3_main_2 */
3711 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
3712 .master = &dra7xx_l4_cfg_hwmod,
3713 .slave = &dra7xx_l3_main_2_hwmod,
3714 .clk = "l3_iclk_div",
3715 .user = OCP_USER_MPU | OCP_USER_SDMA,
3716 };
3718 /* l3_main_1 -> l4_cfg */
3719 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
3720 .master = &dra7xx_l3_main_1_hwmod,
3721 .slave = &dra7xx_l4_cfg_hwmod,
3722 .clk = "l3_iclk_div",
3723 .user = OCP_USER_MPU | OCP_USER_SDMA,
3724 };
3726 /* l3_main_1 -> l4_per1 */
3727 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
3728 .master = &dra7xx_l3_main_1_hwmod,
3729 .slave = &dra7xx_l4_per1_hwmod,
3730 .clk = "l3_iclk_div",
3731 .user = OCP_USER_MPU | OCP_USER_SDMA,
3732 };
3734 /* l3_main_1 -> l4_per2 */
3735 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
3736 .master = &dra7xx_l3_main_1_hwmod,
3737 .slave = &dra7xx_l4_per2_hwmod,
3738 .clk = "l3_iclk_div",
3739 .user = OCP_USER_MPU | OCP_USER_SDMA,
3740 };
3742 /* l3_main_1 -> l4_per3 */
3743 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
3744 .master = &dra7xx_l3_main_1_hwmod,
3745 .slave = &dra7xx_l4_per3_hwmod,
3746 .clk = "l3_iclk_div",
3747 .user = OCP_USER_MPU | OCP_USER_SDMA,
3748 };
3750 /* l3_main_1 -> l4_wkup */
3751 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
3752 .master = &dra7xx_l3_main_1_hwmod,
3753 .slave = &dra7xx_l4_wkup_hwmod,
3754 .clk = "wkupaon_iclk_mux",
3755 .user = OCP_USER_MPU | OCP_USER_SDMA,
3756 };
3758 /* mpu -> mpu_private */
3759 static struct omap_hwmod_ocp_if dra7xx_mpu__mpu_private = {
3760 .master = &dra7xx_mpu_hwmod,
3761 .slave = &dra7xx_mpu_private_hwmod,
3762 .clk = "l3_iclk_div",
3763 .user = OCP_USER_MPU | OCP_USER_SDMA,
3764 };
3766 /* l3_main_2 -> ocp_wp_noc */
3767 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__ocp_wp_noc = {
3768 .master = &dra7xx_l3_main_2_hwmod,
3769 .slave = &dra7xx_ocp_wp_noc_hwmod,
3770 .clk = "l3_iclk_div",
3771 .user = OCP_USER_MPU | OCP_USER_SDMA,
3772 };
3774 static struct omap_hwmod_addr_space dra7xx_ocp_wp_noc_addrs[] = {
3775 {
3776 .pa_start = 0x4a102000,
3777 .pa_end = 0x4a10207f,
3778 .flags = ADDR_TYPE_RT
3779 },
3780 { }
3781 };
3783 /* l4_cfg -> ocp_wp_noc */
3784 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp_wp_noc = {
3785 .master = &dra7xx_l4_cfg_hwmod,
3786 .slave = &dra7xx_ocp_wp_noc_hwmod,
3787 .clk = "l3_iclk_div",
3788 .addr = dra7xx_ocp_wp_noc_addrs,
3789 .user = OCP_USER_MPU,
3790 };
3792 /* l4_per2 -> atl */
3793 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
3794 .master = &dra7xx_l4_per2_hwmod,
3795 .slave = &dra7xx_atl_hwmod,
3796 .clk = "l3_iclk_div",
3797 .user = OCP_USER_MPU | OCP_USER_SDMA,
3798 };
3800 static struct omap_hwmod_addr_space dra7xx_bb2d_addrs[] = {
3801 {
3802 .pa_start = 0x59000000,
3803 .pa_end = 0x590007ff,
3804 },
3805 { }
3806 };
3808 /* l3_main_1 -> bb2d */
3809 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
3810 .master = &dra7xx_l3_main_1_hwmod,
3811 .slave = &dra7xx_bb2d_hwmod,
3812 .clk = "l3_iclk_div",
3813 .addr = dra7xx_bb2d_addrs,
3814 .user = OCP_USER_MPU | OCP_USER_SDMA,
3815 };
3817 static struct omap_hwmod_addr_space dra7xx_counter_32k_addrs[] = {
3818 {
3819 .pa_start = 0x4ae04000,
3820 .pa_end = 0x4ae0403f,
3821 .flags = ADDR_TYPE_RT
3822 },
3823 { }
3824 };
3826 /* l4_wkup -> counter_32k */
3827 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
3828 .master = &dra7xx_l4_wkup_hwmod,
3829 .slave = &dra7xx_counter_32k_hwmod,
3830 .clk = "wkupaon_iclk_mux",
3831 .addr = dra7xx_counter_32k_addrs,
3832 .user = OCP_USER_MPU | OCP_USER_SDMA,
3833 };
3835 static struct omap_hwmod_addr_space dra7xx_ctrl_module_wkup_addrs[] = {
3836 {
3837 .name = "avatar_control_wkup_ocpintf",
3838 .pa_start = 0x4ae0c100,
3839 .pa_end = 0x4ae0c8ff,
3840 },
3841 {
3842 .name = "avatar_control_wkup_pad_ocpintf",
3843 .pa_start = 0x4ae0c5a0,
3844 .pa_end = 0x4ae0c61f,
3845 },
3846 { }
3847 };
3849 /* l4_wkup -> ctrl_module_wkup */
3850 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
3851 .master = &dra7xx_l4_wkup_hwmod,
3852 .slave = &dra7xx_ctrl_module_wkup_hwmod,
3853 .clk = "wkupaon_iclk_mux",
3854 .addr = dra7xx_ctrl_module_wkup_addrs,
3855 .user = OCP_USER_MPU | OCP_USER_SDMA,
3856 };
3858 /* l4_wkup -> dcan1 */
3859 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
3860 .master = &dra7xx_l4_wkup_hwmod,
3861 .slave = &dra7xx_dcan1_hwmod,
3862 .clk = "wkupaon_iclk_mux",
3863 .user = OCP_USER_MPU | OCP_USER_SDMA,
3864 };
3866 /* l4_per2 -> dcan2 */
3867 static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
3868 .master = &dra7xx_l4_per2_hwmod,
3869 .slave = &dra7xx_dcan2_hwmod,
3870 .clk = "l3_iclk_div",
3871 .user = OCP_USER_MPU | OCP_USER_SDMA,
3872 };
3874 static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
3875 {
3876 .pa_start = 0x4a056000,
3877 .pa_end = 0x4a056fff,
3878 .flags = ADDR_TYPE_RT
3879 },
3880 { }
3881 };
3883 /* l4_cfg -> dma_system */
3884 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
3885 .master = &dra7xx_l4_cfg_hwmod,
3886 .slave = &dra7xx_dma_system_hwmod,
3887 .clk = "l3_iclk_div",
3888 .addr = dra7xx_dma_system_addrs,
3889 .user = OCP_USER_MPU | OCP_USER_SDMA,
3890 };
3892 static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
3893 {
3894 .name = "family",
3895 .pa_start = 0x58000000,
3896 .pa_end = 0x5800007f,
3897 .flags = ADDR_TYPE_RT
3898 },
3899 {
3900 .name = "pllctrl1",
3901 .pa_start = 0x58004000,
3902 .pa_end = 0x5800433f,
3903 },
3904 {
3905 .name = "pllctrl2",
3906 .pa_start = 0x58005000,
3907 .pa_end = 0x5800533f,
3908 },
3909 };
3911 /* l3_main_1 -> dss */
3912 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
3913 .master = &dra7xx_l3_main_1_hwmod,
3914 .slave = &dra7xx_dss_hwmod,
3915 .clk = "l3_iclk_div",
3916 .addr = dra7xx_dss_addrs,
3917 .user = OCP_USER_MPU | OCP_USER_SDMA,
3918 };
3920 static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = {
3921 {
3922 .name = "dispc",
3923 .pa_start = 0x58001000,
3924 .pa_end = 0x58001fff,
3925 .flags = ADDR_TYPE_RT
3926 },
3927 };
3929 /* l3_main_1 -> dispc */
3930 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
3931 .master = &dra7xx_l3_main_1_hwmod,
3932 .slave = &dra7xx_dss_dispc_hwmod,
3933 .clk = "l3_iclk_div",
3934 .addr = dra7xx_dss_dispc_addrs,
3935 .user = OCP_USER_MPU | OCP_USER_SDMA,
3936 };
3938 static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = {
3939 {
3940 .name = "hdmi_wp",
3941 .pa_start = 0x58040000,
3942 .pa_end = 0x580400ff,
3943 .flags = ADDR_TYPE_RT
3944 },
3945 {
3946 .name = "pllctrl",
3947 .pa_start = 0x58040200,
3948 .pa_end = 0x5804023f,
3949 },
3950 {
3951 .name = "hdmitxphy",
3952 .pa_start = 0x58040300,
3953 .pa_end = 0x5804033f,
3954 },
3955 {
3956 .name = "hdmi_core",
3957 .pa_start = 0x58060000,
3958 .pa_end = 0x58078fff,
3959 },
3960 {
3961 .name = "deshdcp",
3962 .pa_start = 0x58007000,
3963 .pa_end = 0x5800707f,
3964 },
3965 { }
3966 };
3968 /* l3_main_1 -> dispc */
3969 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
3970 .master = &dra7xx_l3_main_1_hwmod,
3971 .slave = &dra7xx_dss_hdmi_hwmod,
3972 .clk = "l3_iclk_div",
3973 .addr = dra7xx_dss_hdmi_addrs,
3974 .user = OCP_USER_MPU | OCP_USER_SDMA,
3975 };
3977 static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = {
3978 {
3979 .pa_start = 0x48078000,
3980 .pa_end = 0x48078fff,
3981 .flags = ADDR_TYPE_RT
3982 },
3983 { }
3984 };
3986 /* l4_per1 -> elm */
3987 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
3988 .master = &dra7xx_l4_per1_hwmod,
3989 .slave = &dra7xx_elm_hwmod,
3990 .clk = "l3_iclk_div",
3991 .addr = dra7xx_elm_addrs,
3992 .user = OCP_USER_MPU | OCP_USER_SDMA,
3993 };
3995 /* emif_ocp_fw -> emif1 */
3996 static struct omap_hwmod_ocp_if dra7xx_emif_ocp_fw__emif1 = {
3997 .master = &dra7xx_emif_ocp_fw_hwmod,
3998 .slave = &dra7xx_emif1_hwmod,
3999 .clk = "dpll_ddr_h11x2_ck",
4000 .user = OCP_USER_MPU | OCP_USER_SDMA,
4001 };
4003 static struct omap_hwmod_addr_space dra7xx_emif1_addrs[] = {
4004 {
4005 .pa_start = 0x4c000000,
4006 .pa_end = 0x4c0003ff,
4007 .flags = ADDR_TYPE_RT
4008 },
4009 { }
4010 };
4012 /* mpu -> emif1 */
4013 static struct omap_hwmod_ocp_if dra7xx_mpu__emif1 = {
4014 .master = &dra7xx_mpu_hwmod,
4015 .slave = &dra7xx_emif1_hwmod,
4016 .clk = "dpll_ddr_h11x2_ck",
4017 .addr = dra7xx_emif1_addrs,
4018 .user = OCP_USER_MPU,
4019 };
4021 /* emif_ocp_fw -> emif2 */
4022 static struct omap_hwmod_ocp_if dra7xx_emif_ocp_fw__emif2 = {
4023 .master = &dra7xx_emif_ocp_fw_hwmod,
4024 .slave = &dra7xx_emif2_hwmod,
4025 .clk = "dpll_ddr_h11x2_ck",
4026 .user = OCP_USER_MPU | OCP_USER_SDMA,
4027 };
4029 static struct omap_hwmod_addr_space dra7xx_emif2_addrs[] = {
4030 {
4031 .pa_start = 0x4d000000,
4032 .pa_end = 0x4d0003ff,
4033 .flags = ADDR_TYPE_RT
4034 },
4035 { }
4036 };
4038 /* mpu -> emif2 */
4039 static struct omap_hwmod_ocp_if dra7xx_mpu__emif2 = {
4040 .master = &dra7xx_mpu_hwmod,
4041 .slave = &dra7xx_emif2_hwmod,
4042 .clk = "dpll_ddr_h11x2_ck",
4043 .addr = dra7xx_emif2_addrs,
4044 .user = OCP_USER_MPU,
4045 };
4047 static struct omap_hwmod_addr_space dra7xx_gpio1_addrs[] = {
4048 {
4049 .pa_start = 0x4ae10000,
4050 .pa_end = 0x4ae101ff,
4051 .flags = ADDR_TYPE_RT
4052 },
4053 { }
4054 };
4056 /* l4_wkup -> gpio1 */
4057 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
4058 .master = &dra7xx_l4_wkup_hwmod,
4059 .slave = &dra7xx_gpio1_hwmod,
4060 .clk = "wkupaon_iclk_mux",
4061 .addr = dra7xx_gpio1_addrs,
4062 .user = OCP_USER_MPU | OCP_USER_SDMA,
4063 };
4065 static struct omap_hwmod_addr_space dra7xx_gpio2_addrs[] = {
4066 {
4067 .pa_start = 0x48055000,
4068 .pa_end = 0x480551ff,
4069 .flags = ADDR_TYPE_RT
4070 },
4071 { }
4072 };
4074 /* l4_per1 -> gpio2 */
4075 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
4076 .master = &dra7xx_l4_per1_hwmod,
4077 .slave = &dra7xx_gpio2_hwmod,
4078 .clk = "l3_iclk_div",
4079 .addr = dra7xx_gpio2_addrs,
4080 .user = OCP_USER_MPU | OCP_USER_SDMA,
4081 };
4083 static struct omap_hwmod_addr_space dra7xx_gpio3_addrs[] = {
4084 {
4085 .pa_start = 0x48057000,
4086 .pa_end = 0x480571ff,
4087 .flags = ADDR_TYPE_RT
4088 },
4089 { }
4090 };
4092 /* l4_per1 -> gpio3 */
4093 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
4094 .master = &dra7xx_l4_per1_hwmod,
4095 .slave = &dra7xx_gpio3_hwmod,
4096 .clk = "l3_iclk_div",
4097 .addr = dra7xx_gpio3_addrs,
4098 .user = OCP_USER_MPU | OCP_USER_SDMA,
4099 };
4101 static struct omap_hwmod_addr_space dra7xx_gpio4_addrs[] = {
4102 {
4103 .pa_start = 0x48059000,
4104 .pa_end = 0x480591ff,
4105 .flags = ADDR_TYPE_RT
4106 },
4107 { }
4108 };
4110 /* l4_per1 -> gpio4 */
4111 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
4112 .master = &dra7xx_l4_per1_hwmod,
4113 .slave = &dra7xx_gpio4_hwmod,
4114 .clk = "l3_iclk_div",
4115 .addr = dra7xx_gpio4_addrs,
4116 .user = OCP_USER_MPU | OCP_USER_SDMA,
4117 };
4119 static struct omap_hwmod_addr_space dra7xx_gpio5_addrs[] = {
4120 {
4121 .pa_start = 0x4805b000,
4122 .pa_end = 0x4805b1ff,
4123 .flags = ADDR_TYPE_RT
4124 },
4125 { }
4126 };
4128 /* l4_per1 -> gpio5 */
4129 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
4130 .master = &dra7xx_l4_per1_hwmod,
4131 .slave = &dra7xx_gpio5_hwmod,
4132 .clk = "l3_iclk_div",
4133 .addr = dra7xx_gpio5_addrs,
4134 .user = OCP_USER_MPU | OCP_USER_SDMA,
4135 };
4137 static struct omap_hwmod_addr_space dra7xx_gpio6_addrs[] = {
4138 {
4139 .pa_start = 0x4805d000,
4140 .pa_end = 0x4805d1ff,
4141 .flags = ADDR_TYPE_RT
4142 },
4143 { }
4144 };
4146 /* l4_per1 -> gpio6 */
4147 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
4148 .master = &dra7xx_l4_per1_hwmod,
4149 .slave = &dra7xx_gpio6_hwmod,
4150 .clk = "l3_iclk_div",
4151 .addr = dra7xx_gpio6_addrs,
4152 .user = OCP_USER_MPU | OCP_USER_SDMA,
4153 };
4155 static struct omap_hwmod_addr_space dra7xx_gpio7_addrs[] = {
4156 {
4157 .pa_start = 0x48051000,
4158 .pa_end = 0x480511ff,
4159 .flags = ADDR_TYPE_RT
4160 },
4161 { }
4162 };
4164 /* l4_per1 -> gpio7 */
4165 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
4166 .master = &dra7xx_l4_per1_hwmod,
4167 .slave = &dra7xx_gpio7_hwmod,
4168 .clk = "l3_iclk_div",
4169 .addr = dra7xx_gpio7_addrs,
4170 .user = OCP_USER_MPU | OCP_USER_SDMA,
4171 };
4173 static struct omap_hwmod_addr_space dra7xx_gpio8_addrs[] = {
4174 {
4175 .pa_start = 0x48053000,
4176 .pa_end = 0x480531ff,
4177 .flags = ADDR_TYPE_RT
4178 },
4179 { }
4180 };
4182 /* l4_per1 -> gpio8 */
4183 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
4184 .master = &dra7xx_l4_per1_hwmod,
4185 .slave = &dra7xx_gpio8_hwmod,
4186 .clk = "l3_iclk_div",
4187 .addr = dra7xx_gpio8_addrs,
4188 .user = OCP_USER_MPU | OCP_USER_SDMA,
4189 };
4191 static struct omap_hwmod_addr_space dra7xx_gpmc_addrs[] = {
4192 {
4193 .pa_start = 0x50000000,
4194 .pa_end = 0x500003ff,
4195 .flags = ADDR_TYPE_RT
4196 },
4197 { }
4198 };
4200 /* l3_main_1 -> gpmc */
4201 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
4202 .master = &dra7xx_l3_main_1_hwmod,
4203 .slave = &dra7xx_gpmc_hwmod,
4204 .clk = "l3_iclk_div",
4205 .addr = dra7xx_gpmc_addrs,
4206 .user = OCP_USER_MPU | OCP_USER_SDMA,
4207 };
4209 static struct omap_hwmod_addr_space dra7xx_gpu_addrs[] = {
4210 {
4211 .name = "klio",
4212 .pa_start = 0x56000000,
4213 .pa_end = 0x56001fff,
4214 },
4215 {
4216 .name = "hydra2",
4217 .pa_start = 0x56004000,
4218 .pa_end = 0x56004fff,
4219 },
4220 {
4221 .name = "klio_0",
4222 .pa_start = 0x56008000,
4223 .pa_end = 0x56009fff,
4224 },
4225 {
4226 .name = "klio_1",
4227 .pa_start = 0x5600c000,
4228 .pa_end = 0x5600dfff,
4229 },
4230 {
4231 .name = "klio_hl",
4232 .pa_start = 0x5600fe00,
4233 .pa_end = 0x5600ffff,
4234 .flags = ADDR_TYPE_RT
4235 },
4236 { }
4237 };
4239 /* l3_main_1 -> gpu */
4240 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpu = {
4241 .master = &dra7xx_l3_main_1_hwmod,
4242 .slave = &dra7xx_gpu_hwmod,
4243 .clk = "gpu_l3_iclk",
4244 .addr = dra7xx_gpu_addrs,
4245 .user = OCP_USER_MPU | OCP_USER_SDMA,
4246 };
4248 static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
4249 {
4250 .pa_start = 0x480b2000,
4251 .pa_end = 0x480b201f,
4252 .flags = ADDR_TYPE_RT
4253 },
4254 { }
4255 };
4257 /* l4_per1 -> hdq1w */
4258 static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
4259 .master = &dra7xx_l4_per1_hwmod,
4260 .slave = &dra7xx_hdq1w_hwmod,
4261 .clk = "l3_iclk_div",
4262 .addr = dra7xx_hdq1w_addrs,
4263 .user = OCP_USER_MPU | OCP_USER_SDMA,
4264 };
4266 static struct omap_hwmod_addr_space dra7xx_i2c1_addrs[] = {
4267 {
4268 .pa_start = 0x48070000,
4269 .pa_end = 0x480700ff,
4270 .flags = ADDR_TYPE_RT
4271 },
4272 { }
4273 };
4275 /* l4_per1 -> i2c1 */
4276 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
4277 .master = &dra7xx_l4_per1_hwmod,
4278 .slave = &dra7xx_i2c1_hwmod,
4279 .clk = "l3_iclk_div",
4280 .addr = dra7xx_i2c1_addrs,
4281 .user = OCP_USER_MPU | OCP_USER_SDMA,
4282 };
4284 static struct omap_hwmod_addr_space dra7xx_i2c2_addrs[] = {
4285 {
4286 .pa_start = 0x48072000,
4287 .pa_end = 0x480720ff,
4288 .flags = ADDR_TYPE_RT
4289 },
4290 { }
4291 };
4293 /* l4_per1 -> i2c2 */
4294 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
4295 .master = &dra7xx_l4_per1_hwmod,
4296 .slave = &dra7xx_i2c2_hwmod,
4297 .clk = "l3_iclk_div",
4298 .addr = dra7xx_i2c2_addrs,
4299 .user = OCP_USER_MPU | OCP_USER_SDMA,
4300 };
4302 static struct omap_hwmod_addr_space dra7xx_i2c3_addrs[] = {
4303 {
4304 .pa_start = 0x48060000,
4305 .pa_end = 0x480600ff,
4306 .flags = ADDR_TYPE_RT
4307 },
4308 { }
4309 };
4311 /* l4_per1 -> i2c3 */
4312 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
4313 .master = &dra7xx_l4_per1_hwmod,
4314 .slave = &dra7xx_i2c3_hwmod,
4315 .clk = "l3_iclk_div",
4316 .addr = dra7xx_i2c3_addrs,
4317 .user = OCP_USER_MPU | OCP_USER_SDMA,
4318 };
4320 static struct omap_hwmod_addr_space dra7xx_i2c4_addrs[] = {
4321 {
4322 .pa_start = 0x4807a000,
4323 .pa_end = 0x4807a0ff,
4324 .flags = ADDR_TYPE_RT
4325 },
4326 { }
4327 };
4329 /* l4_per1 -> i2c4 */
4330 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
4331 .master = &dra7xx_l4_per1_hwmod,
4332 .slave = &dra7xx_i2c4_hwmod,
4333 .clk = "l3_iclk_div",
4334 .addr = dra7xx_i2c4_addrs,
4335 .user = OCP_USER_MPU | OCP_USER_SDMA,
4336 };
4338 static struct omap_hwmod_addr_space dra7xx_i2c5_addrs[] = {
4339 {
4340 .pa_start = 0x4807c000,
4341 .pa_end = 0x4807c0ff,
4342 .flags = ADDR_TYPE_RT
4343 },
4344 { }
4345 };
4347 /* l4_per1 -> i2c5 */
4348 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
4349 .master = &dra7xx_l4_per1_hwmod,
4350 .slave = &dra7xx_i2c5_hwmod,
4351 .clk = "l3_iclk_div",
4352 .addr = dra7xx_i2c5_addrs,
4353 .user = OCP_USER_MPU | OCP_USER_SDMA,
4354 };
4356 static struct omap_hwmod_addr_space dra7xx_mailbox1_addrs[] = {
4357 {
4358 .pa_start = 0x4a0f4000,
4359 .pa_end = 0x4a0f41ff,
4360 .flags = ADDR_TYPE_RT
4361 },
4362 { }
4363 };
4365 /* l4_cfg -> mailbox1 */
4366 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
4367 .master = &dra7xx_l4_cfg_hwmod,
4368 .slave = &dra7xx_mailbox1_hwmod,
4369 .clk = "l3_iclk_div",
4370 .addr = dra7xx_mailbox1_addrs,
4371 .user = OCP_USER_MPU | OCP_USER_SDMA,
4372 };
4374 static struct omap_hwmod_addr_space dra7xx_mailbox2_addrs[] = {
4375 {
4376 .pa_start = 0x4883a000,
4377 .pa_end = 0x4883a1ff,
4378 .flags = ADDR_TYPE_RT
4379 },
4380 { }
4381 };
4383 /* l4_per3 -> mailbox2 */
4384 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
4385 .master = &dra7xx_l4_per3_hwmod,
4386 .slave = &dra7xx_mailbox2_hwmod,
4387 .clk = "l3_iclk_div",
4388 .addr = dra7xx_mailbox2_addrs,
4389 .user = OCP_USER_MPU | OCP_USER_SDMA,
4390 };
4392 static struct omap_hwmod_addr_space dra7xx_mailbox3_addrs[] = {
4393 {
4394 .pa_start = 0x4883c000,
4395 .pa_end = 0x4883c1ff,
4396 .flags = ADDR_TYPE_RT
4397 },
4398 { }
4399 };
4401 /* l4_per3 -> mailbox3 */
4402 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
4403 .master = &dra7xx_l4_per3_hwmod,
4404 .slave = &dra7xx_mailbox3_hwmod,
4405 .clk = "l3_iclk_div",
4406 .addr = dra7xx_mailbox3_addrs,
4407 .user = OCP_USER_MPU | OCP_USER_SDMA,
4408 };
4410 static struct omap_hwmod_addr_space dra7xx_mailbox4_addrs[] = {
4411 {
4412 .pa_start = 0x4883e000,
4413 .pa_end = 0x4883e1ff,
4414 .flags = ADDR_TYPE_RT
4415 },
4416 { }
4417 };
4419 /* l4_per3 -> mailbox4 */
4420 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
4421 .master = &dra7xx_l4_per3_hwmod,
4422 .slave = &dra7xx_mailbox4_hwmod,
4423 .clk = "l3_iclk_div",
4424 .addr = dra7xx_mailbox4_addrs,
4425 .user = OCP_USER_MPU | OCP_USER_SDMA,
4426 };
4428 static struct omap_hwmod_addr_space dra7xx_mailbox5_addrs[] = {
4429 {
4430 .pa_start = 0x48840000,
4431 .pa_end = 0x488401ff,
4432 .flags = ADDR_TYPE_RT
4433 },
4434 { }
4435 };
4437 /* l4_per3 -> mailbox5 */
4438 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
4439 .master = &dra7xx_l4_per3_hwmod,
4440 .slave = &dra7xx_mailbox5_hwmod,
4441 .clk = "l3_iclk_div",
4442 .addr = dra7xx_mailbox5_addrs,
4443 .user = OCP_USER_MPU | OCP_USER_SDMA,
4444 };
4446 static struct omap_hwmod_addr_space dra7xx_mailbox6_addrs[] = {
4447 {
4448 .pa_start = 0x48842000,
4449 .pa_end = 0x488421ff,
4450 .flags = ADDR_TYPE_RT
4451 },
4452 { }
4453 };
4455 /* l4_per3 -> mailbox6 */
4456 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
4457 .master = &dra7xx_l4_per3_hwmod,
4458 .slave = &dra7xx_mailbox6_hwmod,
4459 .clk = "l3_iclk_div",
4460 .addr = dra7xx_mailbox6_addrs,
4461 .user = OCP_USER_MPU | OCP_USER_SDMA,
4462 };
4464 static struct omap_hwmod_addr_space dra7xx_mailbox7_addrs[] = {
4465 {
4466 .pa_start = 0x48844000,
4467 .pa_end = 0x488441ff,
4468 .flags = ADDR_TYPE_RT
4469 },
4470 { }
4471 };
4473 /* l4_per3 -> mailbox7 */
4474 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
4475 .master = &dra7xx_l4_per3_hwmod,
4476 .slave = &dra7xx_mailbox7_hwmod,
4477 .clk = "l3_iclk_div",
4478 .addr = dra7xx_mailbox7_addrs,
4479 .user = OCP_USER_MPU | OCP_USER_SDMA,
4480 };
4482 static struct omap_hwmod_addr_space dra7xx_mailbox8_addrs[] = {
4483 {
4484 .pa_start = 0x48846000,
4485 .pa_end = 0x488461ff,
4486 .flags = ADDR_TYPE_RT
4487 },
4488 { }
4489 };
4491 /* l4_per3 -> mailbox8 */
4492 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
4493 .master = &dra7xx_l4_per3_hwmod,
4494 .slave = &dra7xx_mailbox8_hwmod,
4495 .clk = "l3_iclk_div",
4496 .addr = dra7xx_mailbox8_addrs,
4497 .user = OCP_USER_MPU | OCP_USER_SDMA,
4498 };
4500 static struct omap_hwmod_addr_space dra7xx_mailbox9_addrs[] = {
4501 {
4502 .pa_start = 0x4885e000,
4503 .pa_end = 0x4885e1ff,
4504 .flags = ADDR_TYPE_RT
4505 },
4506 { }
4507 };
4509 /* l4_per3 -> mailbox9 */
4510 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
4511 .master = &dra7xx_l4_per3_hwmod,
4512 .slave = &dra7xx_mailbox9_hwmod,
4513 .clk = "l3_iclk_div",
4514 .addr = dra7xx_mailbox9_addrs,
4515 .user = OCP_USER_MPU | OCP_USER_SDMA,
4516 };
4518 static struct omap_hwmod_addr_space dra7xx_mailbox10_addrs[] = {
4519 {
4520 .pa_start = 0x48860000,
4521 .pa_end = 0x488601ff,
4522 .flags = ADDR_TYPE_RT
4523 },
4524 { }
4525 };
4527 /* l4_per3 -> mailbox10 */
4528 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
4529 .master = &dra7xx_l4_per3_hwmod,
4530 .slave = &dra7xx_mailbox10_hwmod,
4531 .clk = "l3_iclk_div",
4532 .addr = dra7xx_mailbox10_addrs,
4533 .user = OCP_USER_MPU | OCP_USER_SDMA,
4534 };
4536 static struct omap_hwmod_addr_space dra7xx_mailbox11_addrs[] = {
4537 {
4538 .pa_start = 0x48862000,
4539 .pa_end = 0x488621ff,
4540 .flags = ADDR_TYPE_RT
4541 },
4542 { }
4543 };
4545 /* l4_per3 -> mailbox11 */
4546 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
4547 .master = &dra7xx_l4_per3_hwmod,
4548 .slave = &dra7xx_mailbox11_hwmod,
4549 .clk = "l3_iclk_div",
4550 .addr = dra7xx_mailbox11_addrs,
4551 .user = OCP_USER_MPU | OCP_USER_SDMA,
4552 };
4554 static struct omap_hwmod_addr_space dra7xx_mailbox12_addrs[] = {
4555 {
4556 .pa_start = 0x48864000,
4557 .pa_end = 0x488641ff,
4558 .flags = ADDR_TYPE_RT
4559 },
4560 { }
4561 };
4563 /* l4_per3 -> mailbox12 */
4564 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
4565 .master = &dra7xx_l4_per3_hwmod,
4566 .slave = &dra7xx_mailbox12_hwmod,
4567 .clk = "l3_iclk_div",
4568 .addr = dra7xx_mailbox12_addrs,
4569 .user = OCP_USER_MPU | OCP_USER_SDMA,
4570 };
4572 static struct omap_hwmod_addr_space dra7xx_mailbox13_addrs[] = {
4573 {
4574 .pa_start = 0x48802000,
4575 .pa_end = 0x488021ff,
4576 .flags = ADDR_TYPE_RT
4577 },
4578 { }
4579 };
4581 /* l4_per3 -> mailbox13 */
4582 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
4583 .master = &dra7xx_l4_per3_hwmod,
4584 .slave = &dra7xx_mailbox13_hwmod,
4585 .clk = "l3_iclk_div",
4586 .addr = dra7xx_mailbox13_addrs,
4587 .user = OCP_USER_MPU | OCP_USER_SDMA,
4588 };
4590 /* l3_main_1 -> mcasp1 */
4591 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp1 = {
4592 .master = &dra7xx_l3_main_1_hwmod,
4593 .slave = &dra7xx_mcasp1_hwmod,
4594 .clk = "l3_iclk_div",
4595 .user = OCP_USER_MPU | OCP_USER_SDMA,
4596 };
4598 static struct omap_hwmod_addr_space dra7xx_mcasp1_addrs[] = {
4599 {
4600 .pa_start = 0x48460000,
4601 .pa_end = 0x484603ff,
4602 .flags = ADDR_TYPE_RT
4603 },
4604 { }
4605 };
4607 /* l4_per2 -> mcasp1 */
4608 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = {
4609 .master = &dra7xx_l4_per2_hwmod,
4610 .slave = &dra7xx_mcasp1_hwmod,
4611 .clk = "l3_iclk_div",
4612 .addr = dra7xx_mcasp1_addrs,
4613 .user = OCP_USER_MPU,
4614 };
4616 static struct omap_hwmod_addr_space dra7xx_mcasp2_addrs[] = {
4617 {
4618 .pa_start = 0x48464000,
4619 .pa_end = 0x484643ff,
4620 .flags = ADDR_TYPE_RT
4621 },
4622 { }
4623 };
4625 /* l3_main_1 -> mcasp2 */
4626 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp2 = {
4627 .master = &dra7xx_l3_main_1_hwmod,
4628 .slave = &dra7xx_mcasp2_hwmod,
4629 .clk = "l3_iclk_div",
4630 .addr = dra7xx_mcasp2_addrs,
4631 .user = OCP_USER_MPU | OCP_USER_SDMA,
4632 };
4634 static struct omap_hwmod_addr_space dra7xx_mcasp3_addrs[] = {
4635 {
4636 .pa_start = 0x48468000,
4637 .pa_end = 0x484683ff,
4638 .flags = ADDR_TYPE_RT
4639 },
4640 { }
4641 };
4643 /* l3_main_1 -> mcasp3 */
4644 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = {
4645 .master = &dra7xx_l3_main_1_hwmod,
4646 .slave = &dra7xx_mcasp3_hwmod,
4647 .clk = "l3_iclk_div",
4648 .addr = dra7xx_mcasp3_addrs,
4649 .user = OCP_USER_MPU | OCP_USER_SDMA,
4650 };
4652 static struct omap_hwmod_addr_space dra7xx_mcasp4_addrs[] = {
4653 {
4654 .pa_start = 0x4846c000,
4655 .pa_end = 0x4846c3ff,
4656 .flags = ADDR_TYPE_RT
4657 },
4658 { }
4659 };
4661 /* l4_per2 -> mcasp4 */
4662 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp4 = {
4663 .master = &dra7xx_l4_per2_hwmod,
4664 .slave = &dra7xx_mcasp4_hwmod,
4665 .clk = "l3_iclk_div",
4666 .addr = dra7xx_mcasp4_addrs,
4667 .user = OCP_USER_MPU | OCP_USER_SDMA,
4668 };
4670 static struct omap_hwmod_addr_space dra7xx_mcasp5_addrs[] = {
4671 {
4672 .pa_start = 0x48470000,
4673 .pa_end = 0x484703ff,
4674 .flags = ADDR_TYPE_RT
4675 },
4676 { }
4677 };
4679 /* l4_per2 -> mcasp5 */
4680 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp5 = {
4681 .master = &dra7xx_l4_per2_hwmod,
4682 .slave = &dra7xx_mcasp5_hwmod,
4683 .clk = "l3_iclk_div",
4684 .addr = dra7xx_mcasp5_addrs,
4685 .user = OCP_USER_MPU | OCP_USER_SDMA,
4686 };
4688 static struct omap_hwmod_addr_space dra7xx_mcasp6_addrs[] = {
4689 {
4690 .pa_start = 0x48474000,
4691 .pa_end = 0x484743ff,
4692 .flags = ADDR_TYPE_RT
4693 },
4694 { }
4695 };
4697 /* l4_per2 -> mcasp6 */
4698 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = {
4699 .master = &dra7xx_l4_per2_hwmod,
4700 .slave = &dra7xx_mcasp6_hwmod,
4701 .clk = "l3_iclk_div",
4702 .addr = dra7xx_mcasp6_addrs,
4703 .user = OCP_USER_MPU | OCP_USER_SDMA,
4704 };
4706 static struct omap_hwmod_addr_space dra7xx_mcasp7_addrs[] = {
4707 {
4708 .pa_start = 0x48478000,
4709 .pa_end = 0x484783ff,
4710 .flags = ADDR_TYPE_RT
4711 },
4712 { }
4713 };
4715 /* l4_per2 -> mcasp7 */
4716 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = {
4717 .master = &dra7xx_l4_per2_hwmod,
4718 .slave = &dra7xx_mcasp7_hwmod,
4719 .clk = "l3_iclk_div",
4720 .addr = dra7xx_mcasp7_addrs,
4721 .user = OCP_USER_MPU | OCP_USER_SDMA,
4722 };
4724 static struct omap_hwmod_addr_space dra7xx_mcasp8_addrs[] = {
4725 {
4726 .pa_start = 0x4847c000,
4727 .pa_end = 0x4847c3ff,
4728 .flags = ADDR_TYPE_RT
4729 },
4730 { }
4731 };
4733 /* l4_per2 -> mcasp8 */
4734 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = {
4735 .master = &dra7xx_l4_per2_hwmod,
4736 .slave = &dra7xx_mcasp8_hwmod,
4737 .clk = "l3_iclk_div",
4738 .addr = dra7xx_mcasp8_addrs,
4739 .user = OCP_USER_MPU | OCP_USER_SDMA,
4740 };
4742 static struct omap_hwmod_addr_space dra7xx_mcspi1_addrs[] = {
4743 {
4744 .pa_start = 0x48098000,
4745 .pa_end = 0x480981ff,
4746 .flags = ADDR_TYPE_RT
4747 },
4748 { }
4749 };
4751 /* l4_per1 -> mcspi1 */
4752 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
4753 .master = &dra7xx_l4_per1_hwmod,
4754 .slave = &dra7xx_mcspi1_hwmod,
4755 .clk = "l3_iclk_div",
4756 .addr = dra7xx_mcspi1_addrs,
4757 .user = OCP_USER_MPU | OCP_USER_SDMA,
4758 };
4760 static struct omap_hwmod_addr_space dra7xx_mcspi2_addrs[] = {
4761 {
4762 .pa_start = 0x4809a000,
4763 .pa_end = 0x4809a1ff,
4764 .flags = ADDR_TYPE_RT
4765 },
4766 { }
4767 };
4769 /* l4_per1 -> mcspi2 */
4770 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
4771 .master = &dra7xx_l4_per1_hwmod,
4772 .slave = &dra7xx_mcspi2_hwmod,
4773 .clk = "l3_iclk_div",
4774 .addr = dra7xx_mcspi2_addrs,
4775 .user = OCP_USER_MPU | OCP_USER_SDMA,
4776 };
4778 static struct omap_hwmod_addr_space dra7xx_mcspi3_addrs[] = {
4779 {
4780 .pa_start = 0x480b8000,
4781 .pa_end = 0x480b81ff,
4782 .flags = ADDR_TYPE_RT
4783 },
4784 { }
4785 };
4787 /* l4_per1 -> mcspi3 */
4788 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
4789 .master = &dra7xx_l4_per1_hwmod,
4790 .slave = &dra7xx_mcspi3_hwmod,
4791 .clk = "l3_iclk_div",
4792 .addr = dra7xx_mcspi3_addrs,
4793 .user = OCP_USER_MPU | OCP_USER_SDMA,
4794 };
4796 static struct omap_hwmod_addr_space dra7xx_mcspi4_addrs[] = {
4797 {
4798 .pa_start = 0x480ba000,
4799 .pa_end = 0x480ba1ff,
4800 .flags = ADDR_TYPE_RT
4801 },
4802 { }
4803 };
4805 /* l4_per1 -> mcspi4 */
4806 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
4807 .master = &dra7xx_l4_per1_hwmod,
4808 .slave = &dra7xx_mcspi4_hwmod,
4809 .clk = "l3_iclk_div",
4810 .addr = dra7xx_mcspi4_addrs,
4811 .user = OCP_USER_MPU | OCP_USER_SDMA,
4812 };
4814 static struct omap_hwmod_addr_space dra7xx_mmc1_addrs[] = {
4815 {
4816 .pa_start = 0x4809c000,
4817 .pa_end = 0x4809c3ff,
4818 .flags = ADDR_TYPE_RT
4819 },
4820 { }
4821 };
4823 /* l4_per1 -> mmc1 */
4824 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
4825 .master = &dra7xx_l4_per1_hwmod,
4826 .slave = &dra7xx_mmc1_hwmod,
4827 .clk = "l3_iclk_div",
4828 .addr = dra7xx_mmc1_addrs,
4829 .user = OCP_USER_MPU | OCP_USER_SDMA,
4830 };
4832 static struct omap_hwmod_addr_space dra7xx_mmc2_addrs[] = {
4833 {
4834 .pa_start = 0x480b4000,
4835 .pa_end = 0x480b43ff,
4836 .flags = ADDR_TYPE_RT
4837 },
4838 { }
4839 };
4841 /* l4_per1 -> mmc2 */
4842 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
4843 .master = &dra7xx_l4_per1_hwmod,
4844 .slave = &dra7xx_mmc2_hwmod,
4845 .clk = "l3_iclk_div",
4846 .addr = dra7xx_mmc2_addrs,
4847 .user = OCP_USER_MPU | OCP_USER_SDMA,
4848 };
4850 static struct omap_hwmod_addr_space dra7xx_mmc3_addrs[] = {
4851 {
4852 .pa_start = 0x480ad000,
4853 .pa_end = 0x480ad3ff,
4854 .flags = ADDR_TYPE_RT
4855 },
4856 { }
4857 };
4859 /* l4_per1 -> mmc3 */
4860 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
4861 .master = &dra7xx_l4_per1_hwmod,
4862 .slave = &dra7xx_mmc3_hwmod,
4863 .clk = "l3_iclk_div",
4864 .addr = dra7xx_mmc3_addrs,
4865 .user = OCP_USER_MPU | OCP_USER_SDMA,
4866 };
4868 static struct omap_hwmod_addr_space dra7xx_mmc4_addrs[] = {
4869 {
4870 .pa_start = 0x480d1000,
4871 .pa_end = 0x480d13ff,
4872 .flags = ADDR_TYPE_RT
4873 },
4874 { }
4875 };
4877 /* l4_per1 -> mmc4 */
4878 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
4879 .master = &dra7xx_l4_per1_hwmod,
4880 .slave = &dra7xx_mmc4_hwmod,
4881 .clk = "l3_iclk_div",
4882 .addr = dra7xx_mmc4_addrs,
4883 .user = OCP_USER_MPU | OCP_USER_SDMA,
4884 };
4886 static struct omap_hwmod_addr_space dra7xx_mpu_addrs[] = {
4887 {
4888 .pa_start = 0x47000000,
4889 .pa_end = 0x482af27f,
4890 },
4891 { }
4892 };
4894 /* l4_cfg -> mpu */
4895 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
4896 .master = &dra7xx_l4_cfg_hwmod,
4897 .slave = &dra7xx_mpu_hwmod,
4898 .clk = "l3_iclk_div",
4899 .addr = dra7xx_mpu_addrs,
4900 .user = OCP_USER_MPU | OCP_USER_SDMA,
4901 };
4903 /* l4_per3 -> ocmc_ram1 */
4904 static struct omap_hwmod_ocp_if dra7xx_l4_per3__ocmc_ram1 = {
4905 .master = &dra7xx_l4_per3_hwmod,
4906 .slave = &dra7xx_ocmc_ram1_hwmod,
4907 .clk = "l3_iclk_div",
4908 .user = OCP_USER_MPU | OCP_USER_SDMA,
4909 };
4911 /* l4_per3 -> ocmc_ram2 */
4912 static struct omap_hwmod_ocp_if dra7xx_l4_per3__ocmc_ram2 = {
4913 .master = &dra7xx_l4_per3_hwmod,
4914 .slave = &dra7xx_ocmc_ram2_hwmod,
4915 .clk = "l3_iclk_div",
4916 .user = OCP_USER_MPU | OCP_USER_SDMA,
4917 };
4919 /* l4_per3 -> ocmc_ram3 */
4920 static struct omap_hwmod_ocp_if dra7xx_l4_per3__ocmc_ram3 = {
4921 .master = &dra7xx_l4_per3_hwmod,
4922 .slave = &dra7xx_ocmc_ram3_hwmod,
4923 .clk = "l3_iclk_div",
4924 .user = OCP_USER_MPU | OCP_USER_SDMA,
4925 };
4927 /* l3_main_1 -> ocmc_rom */
4928 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__ocmc_rom = {
4929 .master = &dra7xx_l3_main_1_hwmod,
4930 .slave = &dra7xx_ocmc_rom_hwmod,
4931 .clk = "l3_iclk_div",
4932 .user = OCP_USER_MPU | OCP_USER_SDMA,
4933 };
4935 static struct omap_hwmod_addr_space dra7xx_ocp2scp1_addrs[] = {
4936 {
4937 .pa_start = 0x4a080000,
4938 .pa_end = 0x4a08001f,
4939 .flags = ADDR_TYPE_RT
4940 },
4941 { }
4942 };
4944 /* l4_cfg -> ocp2scp1 */
4945 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
4946 .master = &dra7xx_l4_cfg_hwmod,
4947 .slave = &dra7xx_ocp2scp1_hwmod,
4948 .clk = "l4_root_clk_div",
4949 .addr = dra7xx_ocp2scp1_addrs,
4950 .user = OCP_USER_MPU | OCP_USER_SDMA,
4951 };
4953 static struct omap_hwmod_addr_space dra7xx_pruss1_addrs[] = {
4954 {
4955 .name = "u_intc",
4956 .pa_start = 0x4b220000,
4957 .pa_end = 0x4b221fff,
4958 },
4959 {
4960 .name = "u_pru0_ctrl",
4961 .pa_start = 0x4b222000,
4962 .pa_end = 0x4b22203f,
4963 },
4964 {
4965 .name = "u_pru0_debug",
4966 .pa_start = 0x4b222400,
4967 .pa_end = 0x4b2224ff,
4968 },
4969 {
4970 .name = "u_pru1_ctrl",
4971 .pa_start = 0x4b224000,
4972 .pa_end = 0x4b22403f,
4973 },
4974 {
4975 .name = "u_pru1_debug",
4976 .pa_start = 0x4b224400,
4977 .pa_end = 0x4b2244ff,
4978 },
4979 {
4980 .name = "u_cfg",
4981 .pa_start = 0x4b226000,
4982 .pa_end = 0x4b22607f,
4983 },
4984 {
4985 .name = "u_uart",
4986 .pa_start = 0x4b228000,
4987 .pa_end = 0x4b22803f,
4988 },
4989 {
4990 .name = "u_iep",
4991 .pa_start = 0x4b22e000,
4992 .pa_end = 0x4b22e3ff,
4993 },
4994 {
4995 .name = "u_ecap",
4996 .pa_start = 0x4b230000,
4997 .pa_end = 0x4b23007f,
4998 },
4999 {
5000 .name = "u_mii_rt_cfg",
5001 .pa_start = 0x4b232000,
5002 .pa_end = 0x4b23207f,
5003 },
5004 {
5005 .name = "u_mii_mdio",
5006 .pa_start = 0x4b232400,
5007 .pa_end = 0x4b2324ff,
5008 },
5009 { }
5010 };
5012 /* l3_main_1 -> pruss1 */
5013 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pruss1 = {
5014 .master = &dra7xx_l3_main_1_hwmod,
5015 .slave = &dra7xx_pruss1_hwmod,
5016 .clk = "dpll_gmac_h13x2_ck",
5017 .addr = dra7xx_pruss1_addrs,
5018 .user = OCP_USER_MPU | OCP_USER_SDMA,
5019 };
5021 static struct omap_hwmod_addr_space dra7xx_pruss2_addrs[] = {
5022 {
5023 .name = "u_intc",
5024 .pa_start = 0x4b2a0000,
5025 .pa_end = 0x4b2a1fff,
5026 },
5027 {
5028 .name = "u_pru0_ctrl",
5029 .pa_start = 0x4b2a2000,
5030 .pa_end = 0x4b2a203f,
5031 },
5032 {
5033 .name = "u_pru0_debug",
5034 .pa_start = 0x4b2a2400,
5035 .pa_end = 0x4b2a24ff,
5036 },
5037 {
5038 .name = "u_pru1_ctrl",
5039 .pa_start = 0x4b2a4000,
5040 .pa_end = 0x4b2a403f,
5041 },
5042 {
5043 .name = "u_pru1_debug",
5044 .pa_start = 0x4b2a4400,
5045 .pa_end = 0x4b2a44ff,
5046 },
5047 {
5048 .name = "u_cfg",
5049 .pa_start = 0x4b2a6000,
5050 .pa_end = 0x4b2a607f,
5051 },
5052 {
5053 .name = "u_uart",
5054 .pa_start = 0x4b2a8000,
5055 .pa_end = 0x4b2a803f,
5056 },
5057 {
5058 .name = "u_iep",
5059 .pa_start = 0x4b2ae000,
5060 .pa_end = 0x4b2ae3ff,
5061 },
5062 {
5063 .name = "u_ecap",
5064 .pa_start = 0x4b2b0000,
5065 .pa_end = 0x4b2b007f,
5066 },
5067 {
5068 .name = "u_mii_rt_cfg",
5069 .pa_start = 0x4b2b2000,
5070 .pa_end = 0x4b2b207f,
5071 },
5072 {
5073 .name = "u_mii_mdio",
5074 .pa_start = 0x4b2b2400,
5075 .pa_end = 0x4b2b24ff,
5076 },
5077 { }
5078 };
5080 /* l3_main_1 -> pruss2 */
5081 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pruss2 = {
5082 .master = &dra7xx_l3_main_1_hwmod,
5083 .slave = &dra7xx_pruss2_hwmod,
5084 .clk = "dpll_gmac_h13x2_ck",
5085 .addr = dra7xx_pruss2_addrs,
5086 .user = OCP_USER_MPU | OCP_USER_SDMA,
5087 };
5089 /* l4_per2 -> pwmss1 */
5090 static struct omap_hwmod_ocp_if dra7xx_l4_per2__pwmss1 = {
5091 .master = &dra7xx_l4_per2_hwmod,
5092 .slave = &dra7xx_pwmss1_hwmod,
5093 .clk = "l3_iclk_div",
5094 .user = OCP_USER_MPU | OCP_USER_SDMA,
5095 };
5097 /* l4_per2 -> pwmss2 */
5098 static struct omap_hwmod_ocp_if dra7xx_l4_per2__pwmss2 = {
5099 .master = &dra7xx_l4_per2_hwmod,
5100 .slave = &dra7xx_pwmss2_hwmod,
5101 .clk = "l3_iclk_div",
5102 .user = OCP_USER_MPU | OCP_USER_SDMA,
5103 };
5105 /* l4_per2 -> pwmss3 */
5106 static struct omap_hwmod_ocp_if dra7xx_l4_per2__pwmss3 = {
5107 .master = &dra7xx_l4_per2_hwmod,
5108 .slave = &dra7xx_pwmss3_hwmod,
5109 .clk = "l3_iclk_div",
5110 .user = OCP_USER_MPU | OCP_USER_SDMA,
5111 };
5113 static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
5114 {
5115 .pa_start = 0x4b300000,
5116 .pa_end = 0x4b30007f,
5117 .flags = ADDR_TYPE_RT
5118 },
5119 { }
5120 };
5122 /* l3_main_1 -> qspi */
5123 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
5124 .master = &dra7xx_l3_main_1_hwmod,
5125 .slave = &dra7xx_qspi_hwmod,
5126 .clk = "l3_iclk_div",
5127 .addr = dra7xx_qspi_addrs,
5128 .user = OCP_USER_MPU | OCP_USER_SDMA,
5129 };
5131 static struct omap_hwmod_addr_space dra7xx_rtcss_addrs[] = {
5132 {
5133 .pa_start = 0x48838000,
5134 .pa_end = 0x488380ff,
5135 .flags = ADDR_TYPE_RT
5136 },
5137 { }
5138 };
5140 /* l4_per3 -> rtcss */
5141 static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
5142 .master = &dra7xx_l4_per3_hwmod,
5143 .slave = &dra7xx_rtcss_hwmod,
5144 .clk = "l4_root_clk_div",
5145 .addr = dra7xx_rtcss_addrs,
5146 .user = OCP_USER_MPU | OCP_USER_SDMA,
5147 };
5149 static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
5150 {
5151 .name = "ahci",
5152 .pa_start = 0x4a140000,
5153 .pa_end = 0x4a1401ff,
5154 },
5155 {
5156 .name = "sysc",
5157 .pa_start = 0x4a141100,
5158 .pa_end = 0x4a141107,
5159 .flags = ADDR_TYPE_RT
5160 },
5161 { }
5162 };
5164 /* l4_cfg -> sata */
5165 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
5166 .master = &dra7xx_l4_cfg_hwmod,
5167 .slave = &dra7xx_sata_hwmod,
5168 .clk = "l3_iclk_div",
5169 .addr = dra7xx_sata_addrs,
5170 .user = OCP_USER_MPU | OCP_USER_SDMA,
5171 };
5173 static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
5174 {
5175 .pa_start = 0x4a0dd000,
5176 .pa_end = 0x4a0dd07f,
5177 .flags = ADDR_TYPE_RT
5178 },
5179 { }
5180 };
5182 /* l4_cfg -> smartreflex_core */
5183 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
5184 .master = &dra7xx_l4_cfg_hwmod,
5185 .slave = &dra7xx_smartreflex_core_hwmod,
5186 .clk = "l4_root_clk_div",
5187 .addr = dra7xx_smartreflex_core_addrs,
5188 .user = OCP_USER_MPU | OCP_USER_SDMA,
5189 };
5191 static struct omap_hwmod_addr_space dra7xx_smartreflex_dspeve_addrs[] = {
5192 {
5193 .pa_start = 0x4a183000,
5194 .pa_end = 0x4a18307f,
5195 .flags = ADDR_TYPE_RT
5196 },
5197 { }
5198 };
5200 /* l4_cfg -> smartreflex_dspeve */
5201 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_dspeve = {
5202 .master = &dra7xx_l4_cfg_hwmod,
5203 .slave = &dra7xx_smartreflex_dspeve_hwmod,
5204 .clk = "l4_root_clk_div",
5205 .addr = dra7xx_smartreflex_dspeve_addrs,
5206 .user = OCP_USER_MPU | OCP_USER_SDMA,
5207 };
5209 static struct omap_hwmod_addr_space dra7xx_smartreflex_gpu_addrs[] = {
5210 {
5211 .pa_start = 0x4a185000,
5212 .pa_end = 0x4a18507f,
5213 .flags = ADDR_TYPE_RT
5214 },
5215 { }
5216 };
5218 /* l4_cfg -> smartreflex_gpu */
5219 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_gpu = {
5220 .master = &dra7xx_l4_cfg_hwmod,
5221 .slave = &dra7xx_smartreflex_gpu_hwmod,
5222 .clk = "l4_root_clk_div",
5223 .addr = dra7xx_smartreflex_gpu_addrs,
5224 .user = OCP_USER_MPU | OCP_USER_SDMA,
5225 };
5227 static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
5228 {
5229 .pa_start = 0x4a0d9000,
5230 .pa_end = 0x4a0d907f,
5231 .flags = ADDR_TYPE_RT
5232 },
5233 { }
5234 };
5236 /* l4_cfg -> smartreflex_mpu */
5237 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
5238 .master = &dra7xx_l4_cfg_hwmod,
5239 .slave = &dra7xx_smartreflex_mpu_hwmod,
5240 .clk = "l4_root_clk_div",
5241 .addr = dra7xx_smartreflex_mpu_addrs,
5242 .user = OCP_USER_MPU | OCP_USER_SDMA,
5243 };
5245 /* l4_per3 -> spare_cme */
5246 static struct omap_hwmod_ocp_if dra7xx_l4_per3__spare_cme = {
5247 .master = &dra7xx_l4_per3_hwmod,
5248 .slave = &dra7xx_spare_cme_hwmod,
5249 .clk = "l4_root_clk_div",
5250 .user = OCP_USER_MPU | OCP_USER_SDMA,
5251 };
5253 /* l4_per3 -> spare_icm */
5254 static struct omap_hwmod_ocp_if dra7xx_l4_per3__spare_icm = {
5255 .master = &dra7xx_l4_per3_hwmod,
5256 .slave = &dra7xx_spare_icm_hwmod,
5257 .clk = "l4_root_clk_div",
5258 .user = OCP_USER_MPU | OCP_USER_SDMA,
5259 };
5261 /* l3_main_1 -> spare_iva2 */
5262 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__spare_iva2 = {
5263 .master = &dra7xx_l3_main_1_hwmod,
5264 .slave = &dra7xx_spare_iva2_hwmod,
5265 .clk = "l3_iclk_div",
5266 .user = OCP_USER_MPU | OCP_USER_SDMA,
5267 };
5269 /* l4_wkup -> spare_safety1 */
5270 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__spare_safety1 = {
5271 .master = &dra7xx_l4_wkup_hwmod,
5272 .slave = &dra7xx_spare_safety1_hwmod,
5273 .clk = "wkupaon_iclk_mux",
5274 .user = OCP_USER_MPU | OCP_USER_SDMA,
5275 };
5277 /* l4_wkup -> spare_safety2 */
5278 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__spare_safety2 = {
5279 .master = &dra7xx_l4_wkup_hwmod,
5280 .slave = &dra7xx_spare_safety2_hwmod,
5281 .clk = "wkupaon_iclk_mux",
5282 .user = OCP_USER_MPU | OCP_USER_SDMA,
5283 };
5285 /* l4_wkup -> spare_safety3 */
5286 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__spare_safety3 = {
5287 .master = &dra7xx_l4_wkup_hwmod,
5288 .slave = &dra7xx_spare_safety3_hwmod,
5289 .clk = "wkupaon_iclk_mux",
5290 .user = OCP_USER_MPU | OCP_USER_SDMA,
5291 };
5293 /* l4_wkup -> spare_safety4 */
5294 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__spare_safety4 = {
5295 .master = &dra7xx_l4_wkup_hwmod,
5296 .slave = &dra7xx_spare_safety4_hwmod,
5297 .clk = "wkupaon_iclk_mux",
5298 .user = OCP_USER_MPU | OCP_USER_SDMA,
5299 };
5301 /* l4_wkup -> spare_unknown2 */
5302 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__spare_unknown2 = {
5303 .master = &dra7xx_l4_wkup_hwmod,
5304 .slave = &dra7xx_spare_unknown2_hwmod,
5305 .clk = "wkupaon_iclk_mux",
5306 .user = OCP_USER_MPU | OCP_USER_SDMA,
5307 };
5309 /* l4_wkup -> spare_unknown3 */
5310 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__spare_unknown3 = {
5311 .master = &dra7xx_l4_wkup_hwmod,
5312 .slave = &dra7xx_spare_unknown3_hwmod,
5313 .clk = "wkupaon_iclk_mux",
5314 .user = OCP_USER_MPU | OCP_USER_SDMA,
5315 };
5317 /* l4_per2 -> spare_unknown4 */
5318 static struct omap_hwmod_ocp_if dra7xx_l4_per2__spare_unknown4 = {
5319 .master = &dra7xx_l4_per2_hwmod,
5320 .slave = &dra7xx_spare_unknown4_hwmod,
5321 .clk = "l4_root_clk_div",
5322 .user = OCP_USER_MPU | OCP_USER_SDMA,
5323 };
5325 /* l4_per2 -> spare_unknown5 */
5326 static struct omap_hwmod_ocp_if dra7xx_l4_per2__spare_unknown5 = {
5327 .master = &dra7xx_l4_per2_hwmod,
5328 .slave = &dra7xx_spare_unknown5_hwmod,
5329 .clk = "l4_root_clk_div",
5330 .user = OCP_USER_MPU | OCP_USER_SDMA,
5331 };
5333 /* l4_per2 -> spare_unknown6 */
5334 static struct omap_hwmod_ocp_if dra7xx_l4_per2__spare_unknown6 = {
5335 .master = &dra7xx_l4_per2_hwmod,
5336 .slave = &dra7xx_spare_unknown6_hwmod,
5337 .clk = "l4_root_clk_div",
5338 .user = OCP_USER_MPU | OCP_USER_SDMA,
5339 };
5341 /* l4_per3 -> spare_videopll1 */
5342 static struct omap_hwmod_ocp_if dra7xx_l4_per3__spare_videopll1 = {
5343 .master = &dra7xx_l4_per3_hwmod,
5344 .slave = &dra7xx_spare_videopll1_hwmod,
5345 .clk = "l4_root_clk_div",
5346 .user = OCP_USER_MPU | OCP_USER_SDMA,
5347 };
5349 /* l4_per3 -> spare_videopll2 */
5350 static struct omap_hwmod_ocp_if dra7xx_l4_per3__spare_videopll2 = {
5351 .master = &dra7xx_l4_per3_hwmod,
5352 .slave = &dra7xx_spare_videopll2_hwmod,
5353 .clk = "l4_root_clk_div",
5354 .user = OCP_USER_MPU | OCP_USER_SDMA,
5355 };
5357 /* l4_per3 -> spare_videopll3 */
5358 static struct omap_hwmod_ocp_if dra7xx_l4_per3__spare_videopll3 = {
5359 .master = &dra7xx_l4_per3_hwmod,
5360 .slave = &dra7xx_spare_videopll3_hwmod,
5361 .clk = "l4_root_clk_div",
5362 .user = OCP_USER_MPU | OCP_USER_SDMA,
5363 };
5365 /* l4_per3 -> spare_sata2 */
5366 static struct omap_hwmod_ocp_if dra7xx_l4_per3__spare_sata2 = {
5367 .master = &dra7xx_l4_per3_hwmod,
5368 .slave = &dra7xx_spare_sata2_hwmod,
5369 .clk = "l4_root_clk_div",
5370 .user = OCP_USER_MPU | OCP_USER_SDMA,
5371 };
5373 /* l4_cfg -> spare_smartreflex_rtc */
5374 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spare_smartreflex_rtc = {
5375 .master = &dra7xx_l4_cfg_hwmod,
5376 .slave = &dra7xx_spare_smartreflex_rtc_hwmod,
5377 .clk = "l4_root_clk_div",
5378 .user = OCP_USER_MPU | OCP_USER_SDMA,
5379 };
5381 /* l4_cfg -> spare_smartreflex_sdram */
5382 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spare_smartreflex_sdram = {
5383 .master = &dra7xx_l4_cfg_hwmod,
5384 .slave = &dra7xx_spare_smartreflex_sdram_hwmod,
5385 .clk = "l4_root_clk_div",
5386 .user = OCP_USER_MPU | OCP_USER_SDMA,
5387 };
5389 /* l4_cfg -> spare_smartreflex_wkup */
5390 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spare_smartreflex_wkup = {
5391 .master = &dra7xx_l4_cfg_hwmod,
5392 .slave = &dra7xx_spare_smartreflex_wkup_hwmod,
5393 .clk = "l4_root_clk_div",
5394 .user = OCP_USER_MPU | OCP_USER_SDMA,
5395 };
5397 static struct omap_hwmod_addr_space dra7xx_spinlock_addrs[] = {
5398 {
5399 .pa_start = 0x4a0f6000,
5400 .pa_end = 0x4a0f6fff,
5401 .flags = ADDR_TYPE_RT
5402 },
5403 { }
5404 };
5406 /* l4_cfg -> spinlock */
5407 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
5408 .master = &dra7xx_l4_cfg_hwmod,
5409 .slave = &dra7xx_spinlock_hwmod,
5410 .clk = "l3_iclk_div",
5411 .addr = dra7xx_spinlock_addrs,
5412 .user = OCP_USER_MPU | OCP_USER_SDMA,
5413 };
5415 static struct omap_hwmod_addr_space dra7xx_timer1_addrs[] = {
5416 {
5417 .pa_start = 0x4ae18000,
5418 .pa_end = 0x4ae1807f,
5419 .flags = ADDR_TYPE_RT
5420 },
5421 { }
5422 };
5424 /* l4_wkup -> timer1 */
5425 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
5426 .master = &dra7xx_l4_wkup_hwmod,
5427 .slave = &dra7xx_timer1_hwmod,
5428 .clk = "wkupaon_iclk_mux",
5429 .addr = dra7xx_timer1_addrs,
5430 .user = OCP_USER_MPU | OCP_USER_SDMA,
5431 };
5433 static struct omap_hwmod_addr_space dra7xx_timer2_addrs[] = {
5434 {
5435 .pa_start = 0x48032000,
5436 .pa_end = 0x4803207f,
5437 .flags = ADDR_TYPE_RT
5438 },
5439 { }
5440 };
5442 /* l4_per1 -> timer2 */
5443 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
5444 .master = &dra7xx_l4_per1_hwmod,
5445 .slave = &dra7xx_timer2_hwmod,
5446 .clk = "l3_iclk_div",
5447 .addr = dra7xx_timer2_addrs,
5448 .user = OCP_USER_MPU | OCP_USER_SDMA,
5449 };
5451 static struct omap_hwmod_addr_space dra7xx_timer3_addrs[] = {
5452 {
5453 .pa_start = 0x48034000,
5454 .pa_end = 0x4803407f,
5455 .flags = ADDR_TYPE_RT
5456 },
5457 { }
5458 };
5460 /* l4_per1 -> timer3 */
5461 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
5462 .master = &dra7xx_l4_per1_hwmod,
5463 .slave = &dra7xx_timer3_hwmod,
5464 .clk = "l3_iclk_div",
5465 .addr = dra7xx_timer3_addrs,
5466 .user = OCP_USER_MPU | OCP_USER_SDMA,
5467 };
5469 static struct omap_hwmod_addr_space dra7xx_timer4_addrs[] = {
5470 {
5471 .pa_start = 0x48036000,
5472 .pa_end = 0x4803607f,
5473 .flags = ADDR_TYPE_RT
5474 },
5475 { }
5476 };
5478 /* l4_per1 -> timer4 */
5479 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
5480 .master = &dra7xx_l4_per1_hwmod,
5481 .slave = &dra7xx_timer4_hwmod,
5482 .clk = "l3_iclk_div",
5483 .addr = dra7xx_timer4_addrs,
5484 .user = OCP_USER_MPU | OCP_USER_SDMA,
5485 };
5487 static struct omap_hwmod_addr_space dra7xx_timer5_addrs[] = {
5488 {
5489 .pa_start = 0x48820000,
5490 .pa_end = 0x4882007f,
5491 .flags = ADDR_TYPE_RT
5492 },
5493 { }
5494 };
5496 /* l4_per3 -> timer5 */
5497 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
5498 .master = &dra7xx_l4_per3_hwmod,
5499 .slave = &dra7xx_timer5_hwmod,
5500 .clk = "l3_iclk_div",
5501 .addr = dra7xx_timer5_addrs,
5502 .user = OCP_USER_MPU | OCP_USER_SDMA,
5503 };
5505 static struct omap_hwmod_addr_space dra7xx_timer6_addrs[] = {
5506 {
5507 .pa_start = 0x48822000,
5508 .pa_end = 0x4882207f,
5509 .flags = ADDR_TYPE_RT
5510 },
5511 { }
5512 };
5514 /* l4_per3 -> timer6 */
5515 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
5516 .master = &dra7xx_l4_per3_hwmod,
5517 .slave = &dra7xx_timer6_hwmod,
5518 .clk = "l3_iclk_div",
5519 .addr = dra7xx_timer6_addrs,
5520 .user = OCP_USER_MPU | OCP_USER_SDMA,
5521 };
5523 static struct omap_hwmod_addr_space dra7xx_timer7_addrs[] = {
5524 {
5525 .pa_start = 0x48824000,
5526 .pa_end = 0x4882407f,
5527 .flags = ADDR_TYPE_RT
5528 },
5529 { }
5530 };
5532 /* l4_per3 -> timer7 */
5533 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
5534 .master = &dra7xx_l4_per3_hwmod,
5535 .slave = &dra7xx_timer7_hwmod,
5536 .clk = "l3_iclk_div",
5537 .addr = dra7xx_timer7_addrs,
5538 .user = OCP_USER_MPU | OCP_USER_SDMA,
5539 };
5541 static struct omap_hwmod_addr_space dra7xx_timer8_addrs[] = {
5542 {
5543 .pa_start = 0x48826000,
5544 .pa_end = 0x4882607f,
5545 .flags = ADDR_TYPE_RT
5546 },
5547 { }
5548 };
5550 /* l4_per3 -> timer8 */
5551 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
5552 .master = &dra7xx_l4_per3_hwmod,
5553 .slave = &dra7xx_timer8_hwmod,
5554 .clk = "l3_iclk_div",
5555 .addr = dra7xx_timer8_addrs,
5556 .user = OCP_USER_MPU | OCP_USER_SDMA,
5557 };
5559 static struct omap_hwmod_addr_space dra7xx_timer9_addrs[] = {
5560 {
5561 .pa_start = 0x4803e000,
5562 .pa_end = 0x4803e07f,
5563 .flags = ADDR_TYPE_RT
5564 },
5565 { }
5566 };
5568 /* l4_per1 -> timer9 */
5569 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
5570 .master = &dra7xx_l4_per1_hwmod,
5571 .slave = &dra7xx_timer9_hwmod,
5572 .clk = "l3_iclk_div",
5573 .addr = dra7xx_timer9_addrs,
5574 .user = OCP_USER_MPU | OCP_USER_SDMA,
5575 };
5577 static struct omap_hwmod_addr_space dra7xx_timer10_addrs[] = {
5578 {
5579 .pa_start = 0x48086000,
5580 .pa_end = 0x4808607f,
5581 .flags = ADDR_TYPE_RT
5582 },
5583 { }
5584 };
5586 /* l4_per1 -> timer10 */
5587 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
5588 .master = &dra7xx_l4_per1_hwmod,
5589 .slave = &dra7xx_timer10_hwmod,
5590 .clk = "l3_iclk_div",
5591 .addr = dra7xx_timer10_addrs,
5592 .user = OCP_USER_MPU | OCP_USER_SDMA,
5593 };
5595 static struct omap_hwmod_addr_space dra7xx_timer11_addrs[] = {
5596 {
5597 .pa_start = 0x48088000,
5598 .pa_end = 0x4808807f,
5599 .flags = ADDR_TYPE_RT
5600 },
5601 { }
5602 };
5604 /* l4_per1 -> timer11 */
5605 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
5606 .master = &dra7xx_l4_per1_hwmod,
5607 .slave = &dra7xx_timer11_hwmod,
5608 .clk = "l3_iclk_div",
5609 .addr = dra7xx_timer11_addrs,
5610 .user = OCP_USER_MPU | OCP_USER_SDMA,
5611 };
5613 static struct omap_hwmod_addr_space dra7xx_timer13_addrs[] = {
5614 {
5615 .pa_start = 0x48828000,
5616 .pa_end = 0x4882807f,
5617 .flags = ADDR_TYPE_RT
5618 },
5619 { }
5620 };
5622 /* l4_per3 -> timer13 */
5623 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
5624 .master = &dra7xx_l4_per3_hwmod,
5625 .slave = &dra7xx_timer13_hwmod,
5626 .clk = "l3_iclk_div",
5627 .addr = dra7xx_timer13_addrs,
5628 .user = OCP_USER_MPU | OCP_USER_SDMA,
5629 };
5631 static struct omap_hwmod_addr_space dra7xx_timer14_addrs[] = {
5632 {
5633 .pa_start = 0x4882a000,
5634 .pa_end = 0x4882a07f,
5635 .flags = ADDR_TYPE_RT
5636 },
5637 { }
5638 };
5640 /* l4_per3 -> timer14 */
5641 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
5642 .master = &dra7xx_l4_per3_hwmod,
5643 .slave = &dra7xx_timer14_hwmod,
5644 .clk = "l3_iclk_div",
5645 .addr = dra7xx_timer14_addrs,
5646 .user = OCP_USER_MPU | OCP_USER_SDMA,
5647 };
5649 static struct omap_hwmod_addr_space dra7xx_timer15_addrs[] = {
5650 {
5651 .pa_start = 0x4882c000,
5652 .pa_end = 0x4882c07f,
5653 .flags = ADDR_TYPE_RT
5654 },
5655 { }
5656 };
5658 /* l4_per3 -> timer15 */
5659 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
5660 .master = &dra7xx_l4_per3_hwmod,
5661 .slave = &dra7xx_timer15_hwmod,
5662 .clk = "l3_iclk_div",
5663 .addr = dra7xx_timer15_addrs,
5664 .user = OCP_USER_MPU | OCP_USER_SDMA,
5665 };
5667 static struct omap_hwmod_addr_space dra7xx_timer16_addrs[] = {
5668 {
5669 .pa_start = 0x4882e000,
5670 .pa_end = 0x4882e07f,
5671 .flags = ADDR_TYPE_RT
5672 },
5673 { }
5674 };
5676 /* l4_per3 -> timer16 */
5677 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
5678 .master = &dra7xx_l4_per3_hwmod,
5679 .slave = &dra7xx_timer16_hwmod,
5680 .clk = "l3_iclk_div",
5681 .addr = dra7xx_timer16_addrs,
5682 .user = OCP_USER_MPU | OCP_USER_SDMA,
5683 };
5685 static struct omap_hwmod_addr_space dra7xx_uart1_addrs[] = {
5686 {
5687 .pa_start = 0x4806a000,
5688 .pa_end = 0x4806a0ff,
5689 .flags = ADDR_TYPE_RT
5690 },
5691 { }
5692 };
5694 /* l4_per1 -> uart1 */
5695 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
5696 .master = &dra7xx_l4_per1_hwmod,
5697 .slave = &dra7xx_uart1_hwmod,
5698 .clk = "l3_iclk_div",
5699 .addr = dra7xx_uart1_addrs,
5700 .user = OCP_USER_MPU | OCP_USER_SDMA,
5701 };
5703 static struct omap_hwmod_addr_space dra7xx_uart2_addrs[] = {
5704 {
5705 .pa_start = 0x4806c000,
5706 .pa_end = 0x4806c0ff,
5707 .flags = ADDR_TYPE_RT
5708 },
5709 { }
5710 };
5712 /* l4_per1 -> uart2 */
5713 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
5714 .master = &dra7xx_l4_per1_hwmod,
5715 .slave = &dra7xx_uart2_hwmod,
5716 .clk = "l3_iclk_div",
5717 .addr = dra7xx_uart2_addrs,
5718 .user = OCP_USER_MPU | OCP_USER_SDMA,
5719 };
5721 static struct omap_hwmod_addr_space dra7xx_uart3_addrs[] = {
5722 {
5723 .pa_start = 0x48020000,
5724 .pa_end = 0x480200ff,
5725 .flags = ADDR_TYPE_RT
5726 },
5727 { }
5728 };
5730 /* l4_per1 -> uart3 */
5731 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
5732 .master = &dra7xx_l4_per1_hwmod,
5733 .slave = &dra7xx_uart3_hwmod,
5734 .clk = "l3_iclk_div",
5735 .addr = dra7xx_uart3_addrs,
5736 .user = OCP_USER_MPU | OCP_USER_SDMA,
5737 };
5739 static struct omap_hwmod_addr_space dra7xx_uart4_addrs[] = {
5740 {
5741 .pa_start = 0x4806e000,
5742 .pa_end = 0x4806e0ff,
5743 .flags = ADDR_TYPE_RT
5744 },
5745 { }
5746 };
5748 /* l4_per1 -> uart4 */
5749 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
5750 .master = &dra7xx_l4_per1_hwmod,
5751 .slave = &dra7xx_uart4_hwmod,
5752 .clk = "l3_iclk_div",
5753 .addr = dra7xx_uart4_addrs,
5754 .user = OCP_USER_MPU | OCP_USER_SDMA,
5755 };
5757 static struct omap_hwmod_addr_space dra7xx_uart5_addrs[] = {
5758 {
5759 .pa_start = 0x48066000,
5760 .pa_end = 0x480660ff,
5761 .flags = ADDR_TYPE_RT
5762 },
5763 { }
5764 };
5766 /* l4_per1 -> uart5 */
5767 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
5768 .master = &dra7xx_l4_per1_hwmod,
5769 .slave = &dra7xx_uart5_hwmod,
5770 .clk = "l3_iclk_div",
5771 .addr = dra7xx_uart5_addrs,
5772 .user = OCP_USER_MPU | OCP_USER_SDMA,
5773 };
5775 static struct omap_hwmod_addr_space dra7xx_uart6_addrs[] = {
5776 {
5777 .pa_start = 0x48068000,
5778 .pa_end = 0x480680ff,
5779 .flags = ADDR_TYPE_RT
5780 },
5781 { }
5782 };
5784 /* l4_per1 -> uart6 */
5785 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
5786 .master = &dra7xx_l4_per1_hwmod,
5787 .slave = &dra7xx_uart6_hwmod,
5788 .clk = "l3_iclk_div",
5789 .addr = dra7xx_uart6_addrs,
5790 .user = OCP_USER_MPU | OCP_USER_SDMA,
5791 };
5793 static struct omap_hwmod_addr_space dra7xx_uart7_addrs[] = {
5794 {
5795 .pa_start = 0x48420000,
5796 .pa_end = 0x484200ff,
5797 .flags = ADDR_TYPE_RT
5798 },
5799 { }
5800 };
5802 /* l4_per2 -> uart7 */
5803 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
5804 .master = &dra7xx_l4_per2_hwmod,
5805 .slave = &dra7xx_uart7_hwmod,
5806 .clk = "l3_iclk_div",
5807 .addr = dra7xx_uart7_addrs,
5808 .user = OCP_USER_MPU | OCP_USER_SDMA,
5809 };
5811 static struct omap_hwmod_addr_space dra7xx_uart8_addrs[] = {
5812 {
5813 .pa_start = 0x48422000,
5814 .pa_end = 0x484220ff,
5815 .flags = ADDR_TYPE_RT
5816 },
5817 { }
5818 };
5820 /* l4_per2 -> uart8 */
5821 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
5822 .master = &dra7xx_l4_per2_hwmod,
5823 .slave = &dra7xx_uart8_hwmod,
5824 .clk = "l3_iclk_div",
5825 .addr = dra7xx_uart8_addrs,
5826 .user = OCP_USER_MPU | OCP_USER_SDMA,
5827 };
5829 static struct omap_hwmod_addr_space dra7xx_uart9_addrs[] = {
5830 {
5831 .pa_start = 0x48424000,
5832 .pa_end = 0x484240ff,
5833 .flags = ADDR_TYPE_RT
5834 },
5835 { }
5836 };
5838 /* l4_per2 -> uart9 */
5839 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
5840 .master = &dra7xx_l4_per2_hwmod,
5841 .slave = &dra7xx_uart9_hwmod,
5842 .clk = "l3_iclk_div",
5843 .addr = dra7xx_uart9_addrs,
5844 .user = OCP_USER_MPU | OCP_USER_SDMA,
5845 };
5847 static struct omap_hwmod_addr_space dra7xx_uart10_addrs[] = {
5848 {
5849 .pa_start = 0x4ae2b000,
5850 .pa_end = 0x4ae2b0ff,
5851 .flags = ADDR_TYPE_RT
5852 },
5853 { }
5854 };
5856 /* l4_wkup -> uart10 */
5857 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
5858 .master = &dra7xx_l4_wkup_hwmod,
5859 .slave = &dra7xx_uart10_hwmod,
5860 .clk = "wkupaon_iclk_mux",
5861 .addr = dra7xx_uart10_addrs,
5862 .user = OCP_USER_MPU | OCP_USER_SDMA,
5863 };
5865 /* l4_per3 -> usb_otg_ss1 */
5866 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
5867 .master = &dra7xx_l4_per3_hwmod,
5868 .slave = &dra7xx_usb_otg_ss1_hwmod,
5869 .clk = "dpll_core_h13x2_ck",
5870 .user = OCP_USER_MPU | OCP_USER_SDMA,
5871 };
5873 /* l4_per3 -> usb_otg_ss2 */
5874 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
5875 .master = &dra7xx_l4_per3_hwmod,
5876 .slave = &dra7xx_usb_otg_ss2_hwmod,
5877 .clk = "dpll_core_h13x2_ck",
5878 .user = OCP_USER_MPU | OCP_USER_SDMA,
5879 };
5881 /* l4_per3 -> usb_otg_ss3 */
5882 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
5883 .master = &dra7xx_l4_per3_hwmod,
5884 .slave = &dra7xx_usb_otg_ss3_hwmod,
5885 .clk = "dpll_core_h13x2_ck",
5886 .user = OCP_USER_MPU | OCP_USER_SDMA,
5887 };
5889 /* l4_per3 -> usb_otg_ss4 */
5890 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
5891 .master = &dra7xx_l4_per3_hwmod,
5892 .slave = &dra7xx_usb_otg_ss4_hwmod,
5893 .clk = "dpll_core_h13x2_ck",
5894 .user = OCP_USER_MPU | OCP_USER_SDMA,
5895 };
5897 /* l3_main_1 -> vcp1 */
5898 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
5899 .master = &dra7xx_l3_main_1_hwmod,
5900 .slave = &dra7xx_vcp1_hwmod,
5901 .clk = "l3_iclk_div",
5902 .user = OCP_USER_MPU | OCP_USER_SDMA,
5903 };
5905 /* l4_per2 -> vcp1 */
5906 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
5907 .master = &dra7xx_l4_per2_hwmod,
5908 .slave = &dra7xx_vcp1_hwmod,
5909 .clk = "l3_iclk_div",
5910 .user = OCP_USER_MPU | OCP_USER_SDMA,
5911 };
5913 /* l3_main_1 -> vcp2 */
5914 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
5915 .master = &dra7xx_l3_main_1_hwmod,
5916 .slave = &dra7xx_vcp2_hwmod,
5917 .clk = "l3_iclk_div",
5918 .user = OCP_USER_MPU | OCP_USER_SDMA,
5919 };
5921 /* l4_per2 -> vcp2 */
5922 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
5923 .master = &dra7xx_l4_per2_hwmod,
5924 .slave = &dra7xx_vcp2_hwmod,
5925 .clk = "l3_iclk_div",
5926 .user = OCP_USER_MPU | OCP_USER_SDMA,
5927 };
5929 static struct omap_hwmod_addr_space dra7xx_vip1_addrs[] = {
5930 {
5931 .name = "vip_top_level",
5932 .pa_start = 0x48970000,
5933 .pa_end = 0x489701ff,
5934 .flags = ADDR_TYPE_RT
5935 },
5936 {
5937 .name = "vip_slice0_parser",
5938 .pa_start = 0x48975500,
5939 .pa_end = 0x489755ff,
5940 },
5941 {
5942 .name = "vip_slice0_csc",
5943 .pa_start = 0x48975700,
5944 .pa_end = 0x4897571f,
5945 },
5946 {
5947 .name = "vip_slice0_sc",
5948 .pa_start = 0x48975800,
5949 .pa_end = 0x4897587f,
5950 },
5951 {
5952 .name = "vip_slice1_parser",
5953 .pa_start = 0x48975a00,
5954 .pa_end = 0x48975aff,
5955 },
5956 {
5957 .name = "vip_slice1_csc",
5958 .pa_start = 0x48975c00,
5959 .pa_end = 0x48975c1f,
5960 },
5961 {
5962 .name = "vip_slice1_sc",
5963 .pa_start = 0x48975d00,
5964 .pa_end = 0x48975d7f,
5965 },
5966 {
5967 .name = "vip_vpdma",
5968 .pa_start = 0x4897d000,
5969 .pa_end = 0x4897d3ff,
5970 },
5971 { }
5972 };
5974 /* l4_per3 -> vip1 */
5975 static struct omap_hwmod_ocp_if dra7xx_l4_per3__vip1 = {
5976 .master = &dra7xx_l4_per3_hwmod,
5977 .slave = &dra7xx_vip1_hwmod,
5978 .clk = "l3_iclk_div",
5979 .addr = dra7xx_vip1_addrs,
5980 .user = OCP_USER_MPU | OCP_USER_SDMA,
5981 };
5983 static struct omap_hwmod_addr_space dra7xx_vip2_addrs[] = {
5984 {
5985 .name = "vip_top_level",
5986 .pa_start = 0x48990000,
5987 .pa_end = 0x489901ff,
5988 .flags = ADDR_TYPE_RT
5989 },
5990 {
5991 .name = "vip_slice0_parser",
5992 .pa_start = 0x48995500,
5993 .pa_end = 0x489955ff,
5994 },
5995 {
5996 .name = "vip_slice0_csc",
5997 .pa_start = 0x48995700,
5998 .pa_end = 0x4899571f,
5999 },
6000 {
6001 .name = "vip_slice0_sc",
6002 .pa_start = 0x48995800,
6003 .pa_end = 0x4899587f,
6004 },
6005 {
6006 .name = "vip_slice1_parser",
6007 .pa_start = 0x48995a00,
6008 .pa_end = 0x48995aff,
6009 },
6010 {
6011 .name = "vip_slice1_csc",
6012 .pa_start = 0x48995c00,
6013 .pa_end = 0x48995c1f,
6014 },
6015 {
6016 .name = "vip_slice1_sc",
6017 .pa_start = 0x48995d00,
6018 .pa_end = 0x48995d7f,
6019 },
6020 {
6021 .name = "vip_vpdma",
6022 .pa_start = 0x4899d000,
6023 .pa_end = 0x4899d3ff,
6024 },
6025 { }
6026 };
6028 /* l4_per3 -> vip2 */
6029 static struct omap_hwmod_ocp_if dra7xx_l4_per3__vip2 = {
6030 .master = &dra7xx_l4_per3_hwmod,
6031 .slave = &dra7xx_vip2_hwmod,
6032 .clk = "l3_iclk_div",
6033 .addr = dra7xx_vip2_addrs,
6034 .user = OCP_USER_MPU | OCP_USER_SDMA,
6035 };
6037 static struct omap_hwmod_addr_space dra7xx_vip3_addrs[] = {
6038 {
6039 .name = "vip_top_level",
6040 .pa_start = 0x489b0000,
6041 .pa_end = 0x489b01ff,
6042 .flags = ADDR_TYPE_RT
6043 },
6044 {
6045 .name = "vip_slice0_parser",
6046 .pa_start = 0x489b5500,
6047 .pa_end = 0x489b55ff,
6048 },
6049 {
6050 .name = "vip_slice0_csc",
6051 .pa_start = 0x489b5700,
6052 .pa_end = 0x489b571f,
6053 },
6054 {
6055 .name = "vip_slice0_sc",
6056 .pa_start = 0x489b5800,
6057 .pa_end = 0x489b587f,
6058 },
6059 {
6060 .name = "vip_slice1_parser",
6061 .pa_start = 0x489b5a00,
6062 .pa_end = 0x489b5aff,
6063 },
6064 {
6065 .name = "vip_slice1_csc",
6066 .pa_start = 0x489b5c00,
6067 .pa_end = 0x489b5c1f,
6068 },
6069 {
6070 .name = "vip_slice1_sc",
6071 .pa_start = 0x489b5d00,
6072 .pa_end = 0x489b5d7f,
6073 },
6074 {
6075 .name = "vip_vpdma",
6076 .pa_start = 0x489bd000,
6077 .pa_end = 0x489bd3ff,
6078 },
6079 { }
6080 };
6082 /* l4_per3 -> vip3 */
6083 static struct omap_hwmod_ocp_if dra7xx_l4_per3__vip3 = {
6084 .master = &dra7xx_l4_per3_hwmod,
6085 .slave = &dra7xx_vip3_hwmod,
6086 .clk = "l3_iclk_div",
6087 .addr = dra7xx_vip3_addrs,
6088 .user = OCP_USER_MPU | OCP_USER_SDMA,
6089 };
6091 static struct omap_hwmod_addr_space dra7xx_vpe_addrs[] = {
6092 {
6093 .name = "vpe0_vayu_register_inst_0",
6094 .pa_start = 0x489d0000,
6095 .pa_end = 0x489d01ff,
6096 .flags = ADDR_TYPE_RT
6097 },
6098 {
6099 .name = "dss_chr_us_register_inst_0",
6100 .pa_start = 0x489d0300,
6101 .pa_end = 0x489d033f,
6102 },
6103 {
6104 .name = "dss_chr_us_register_inst_1",
6105 .pa_start = 0x489d0400,
6106 .pa_end = 0x489d043f,
6107 },
6108 {
6109 .name = "dss_chr_us_register_inst_2",
6110 .pa_start = 0x489d0500,
6111 .pa_end = 0x489d053f,
6112 },
6113 {
6114 .name = "dss_dei_register_inst_0",
6115 .pa_start = 0x489d0600,
6116 .pa_end = 0x489d063f,
6117 },
6118 {
6119 .name = "dss_sc_m_register_inst_0",
6120 .pa_start = 0x489d0700,
6121 .pa_end = 0x489d077f,
6122 },
6123 {
6124 .name = "dss_csc_register_inst_0",
6125 .pa_start = 0x489d5700,
6126 .pa_end = 0x489d571f,
6127 },
6128 {
6129 .name = "hd_dss_centaurus_vpdma_register_inst_0",
6130 .pa_start = 0x489dd000,
6131 .pa_end = 0x489dd3ff,
6132 },
6133 { }
6134 };
6136 /* l4_per3 -> vpe */
6137 static struct omap_hwmod_ocp_if dra7xx_l4_per3__vpe = {
6138 .master = &dra7xx_l4_per3_hwmod,
6139 .slave = &dra7xx_vpe_hwmod,
6140 .clk = "l3_iclk_div",
6141 .addr = dra7xx_vpe_addrs,
6142 .user = OCP_USER_MPU | OCP_USER_SDMA,
6143 };
6145 static struct omap_hwmod_addr_space dra7xx_wd_timer2_addrs[] = {
6146 {
6147 .pa_start = 0x4ae14000,
6148 .pa_end = 0x4ae1407f,
6149 .flags = ADDR_TYPE_RT
6150 },
6151 { }
6152 };
6154 /* l4_wkup -> wd_timer2 */
6155 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
6156 .master = &dra7xx_l4_wkup_hwmod,
6157 .slave = &dra7xx_wd_timer2_hwmod,
6158 .clk = "wkupaon_iclk_mux",
6159 .addr = dra7xx_wd_timer2_addrs,
6160 .user = OCP_USER_MPU | OCP_USER_SDMA,
6161 };
6163 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
6164 &dra7xx_l3_main_1__dmm,
6165 &dra7xx_dmm__emif_ocp_fw,
6166 &dra7xx_l4_cfg__emif_ocp_fw,
6167 &dra7xx_l3_main_2__l3_instr,
6168 &dra7xx_ocp_wp_noc__l3_instr,
6169 &dra7xx_l4_cfg__l3_main_1,
6170 &dra7xx_mpu__l3_main_1,
6171 &dra7xx_l3_main_1__l3_main_2,
6172 &dra7xx_l4_cfg__l3_main_2,
6173 &dra7xx_l3_main_1__l4_cfg,
6174 &dra7xx_l3_main_1__l4_per1,
6175 &dra7xx_l3_main_1__l4_per2,
6176 &dra7xx_l3_main_1__l4_per3,
6177 &dra7xx_l3_main_1__l4_wkup,
6178 &dra7xx_mpu__mpu_private,
6179 &dra7xx_l3_main_2__ocp_wp_noc,
6180 &dra7xx_l4_cfg__ocp_wp_noc,
6181 &dra7xx_l4_per2__atl,
6182 &dra7xx_l3_main_1__bb2d,
6183 &dra7xx_l4_wkup__counter_32k,
6184 &dra7xx_l4_wkup__ctrl_module_wkup,
6185 &dra7xx_l4_wkup__dcan1,
6186 &dra7xx_l4_per2__dcan2,
6187 &dra7xx_l4_cfg__dma_system,
6188 &dra7xx_l3_main_1__dss,
6189 &dra7xx_l3_main_1__dispc,
6190 &dra7xx_l3_main_1__hdmi,
6191 &dra7xx_l4_per1__elm,
6192 &dra7xx_emif_ocp_fw__emif1,
6193 &dra7xx_mpu__emif1,
6194 &dra7xx_emif_ocp_fw__emif2,
6195 &dra7xx_mpu__emif2,
6196 &dra7xx_l4_wkup__gpio1,
6197 &dra7xx_l4_per1__gpio2,
6198 &dra7xx_l4_per1__gpio3,
6199 &dra7xx_l4_per1__gpio4,
6200 &dra7xx_l4_per1__gpio5,
6201 &dra7xx_l4_per1__gpio6,
6202 &dra7xx_l4_per1__gpio7,
6203 &dra7xx_l4_per1__gpio8,
6204 &dra7xx_l3_main_1__gpmc,
6205 &dra7xx_l3_main_1__gpu,
6206 &dra7xx_l4_per1__hdq1w,
6207 &dra7xx_l4_per1__i2c1,
6208 &dra7xx_l4_per1__i2c2,
6209 &dra7xx_l4_per1__i2c3,
6210 &dra7xx_l4_per1__i2c4,
6211 &dra7xx_l4_per1__i2c5,
6212 &dra7xx_l4_cfg__mailbox1,
6213 &dra7xx_l4_per3__mailbox2,
6214 &dra7xx_l4_per3__mailbox3,
6215 &dra7xx_l4_per3__mailbox4,
6216 &dra7xx_l4_per3__mailbox5,
6217 &dra7xx_l4_per3__mailbox6,
6218 &dra7xx_l4_per3__mailbox7,
6219 &dra7xx_l4_per3__mailbox8,
6220 &dra7xx_l4_per3__mailbox9,
6221 &dra7xx_l4_per3__mailbox10,
6222 &dra7xx_l4_per3__mailbox11,
6223 &dra7xx_l4_per3__mailbox12,
6224 &dra7xx_l4_per3__mailbox13,
6225 &dra7xx_l3_main_1__mcasp1,
6226 &dra7xx_l4_per2__mcasp1,
6227 &dra7xx_l3_main_1__mcasp2,
6228 &dra7xx_l3_main_1__mcasp3,
6229 &dra7xx_l4_per2__mcasp4,
6230 &dra7xx_l4_per2__mcasp5,
6231 &dra7xx_l4_per2__mcasp6,
6232 &dra7xx_l4_per2__mcasp7,
6233 &dra7xx_l4_per2__mcasp8,
6234 &dra7xx_l4_per1__mcspi1,
6235 &dra7xx_l4_per1__mcspi2,
6236 &dra7xx_l4_per1__mcspi3,
6237 &dra7xx_l4_per1__mcspi4,
6238 &dra7xx_l4_per1__mmc1,
6239 &dra7xx_l4_per1__mmc2,
6240 &dra7xx_l4_per1__mmc3,
6241 &dra7xx_l4_per1__mmc4,
6242 &dra7xx_l4_cfg__mpu,
6243 &dra7xx_l4_per3__ocmc_ram1,
6244 &dra7xx_l4_per3__ocmc_ram2,
6245 &dra7xx_l4_per3__ocmc_ram3,
6246 &dra7xx_l3_main_1__ocmc_rom,
6247 &dra7xx_l4_cfg__ocp2scp1,
6248 &dra7xx_l3_main_1__pruss1,
6249 &dra7xx_l3_main_1__pruss2,
6250 &dra7xx_l4_per2__pwmss1,
6251 &dra7xx_l4_per2__pwmss2,
6252 &dra7xx_l4_per2__pwmss3,
6253 &dra7xx_l3_main_1__qspi,
6254 &dra7xx_l4_per3__rtcss,
6255 &dra7xx_l4_cfg__sata,
6256 &dra7xx_l4_cfg__smartreflex_core,
6257 &dra7xx_l4_cfg__smartreflex_dspeve,
6258 &dra7xx_l4_cfg__smartreflex_gpu,
6259 &dra7xx_l4_cfg__smartreflex_mpu,
6260 &dra7xx_l4_per3__spare_cme,
6261 &dra7xx_l4_per3__spare_icm,
6262 &dra7xx_l3_main_1__spare_iva2,
6263 &dra7xx_l4_wkup__spare_safety1,
6264 &dra7xx_l4_wkup__spare_safety2,
6265 &dra7xx_l4_wkup__spare_safety3,
6266 &dra7xx_l4_wkup__spare_safety4,
6267 &dra7xx_l4_wkup__spare_unknown2,
6268 &dra7xx_l4_wkup__spare_unknown3,
6269 &dra7xx_l4_per2__spare_unknown4,
6270 &dra7xx_l4_per2__spare_unknown5,
6271 &dra7xx_l4_per2__spare_unknown6,
6272 &dra7xx_l4_per3__spare_videopll1,
6273 &dra7xx_l4_per3__spare_videopll2,
6274 &dra7xx_l4_per3__spare_videopll3,
6275 &dra7xx_l4_per3__spare_sata2,
6276 &dra7xx_l4_cfg__spare_smartreflex_rtc,
6277 &dra7xx_l4_cfg__spare_smartreflex_sdram,
6278 &dra7xx_l4_cfg__spare_smartreflex_wkup,
6279 &dra7xx_l4_cfg__spinlock,
6280 &dra7xx_l4_wkup__timer1,
6281 &dra7xx_l4_per1__timer2,
6282 &dra7xx_l4_per1__timer3,
6283 &dra7xx_l4_per1__timer4,
6284 &dra7xx_l4_per3__timer5,
6285 &dra7xx_l4_per3__timer6,
6286 &dra7xx_l4_per3__timer7,
6287 &dra7xx_l4_per3__timer8,
6288 &dra7xx_l4_per1__timer9,
6289 &dra7xx_l4_per1__timer10,
6290 &dra7xx_l4_per1__timer11,
6291 &dra7xx_l4_per3__timer13,
6292 &dra7xx_l4_per3__timer14,
6293 &dra7xx_l4_per3__timer15,
6294 &dra7xx_l4_per3__timer16,
6295 &dra7xx_l4_per1__uart1,
6296 &dra7xx_l4_per1__uart2,
6297 &dra7xx_l4_per1__uart3,
6298 &dra7xx_l4_per1__uart4,
6299 &dra7xx_l4_per1__uart5,
6300 &dra7xx_l4_per1__uart6,
6301 &dra7xx_l4_per2__uart7,
6302 &dra7xx_l4_per2__uart8,
6303 &dra7xx_l4_per2__uart9,
6304 &dra7xx_l4_wkup__uart10,
6305 &dra7xx_l4_per3__usb_otg_ss1,
6306 &dra7xx_l4_per3__usb_otg_ss2,
6307 &dra7xx_l4_per3__usb_otg_ss3,
6308 &dra7xx_l4_per3__usb_otg_ss4,
6309 &dra7xx_l3_main_1__vcp1,
6310 &dra7xx_l4_per2__vcp1,
6311 &dra7xx_l3_main_1__vcp2,
6312 &dra7xx_l4_per2__vcp2,
6313 &dra7xx_l4_per3__vip1,
6314 &dra7xx_l4_per3__vip2,
6315 &dra7xx_l4_per3__vip3,
6316 &dra7xx_l4_per3__vpe,
6317 &dra7xx_l4_wkup__wd_timer2,
6318 NULL,
6319 };
6321 int __init dra7xx_hwmod_init(void)
6322 {
6323 omap_hwmod_init();
6324 return omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
6325 }