1 /*
2 * Hardware modules present on the DRA7xx chips
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley
7 * Benoit Cousson
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
20 #include <linux/io.h>
21 #include <linux/platform_data/gpio-omap.h>
22 #include <linux/power/smartreflex.h>
23 #include <linux/i2c-omap.h>
25 #include <linux/omap-dma.h>
26 #include <linux/platform_data/spi-omap2-mcspi.h>
27 #include <linux/platform_data/asoc-ti-mcbsp.h>
28 #include <linux/platform_data/iommu-omap.h>
29 #include <plat/dmtimer.h>
31 #include "omap_hwmod.h"
32 #include "omap_hwmod_common_data.h"
33 #include "cm1_7xx.h"
34 #include "cm2_7xx.h"
35 #include "prm7xx.h"
36 #include "i2c.h"
37 #include "mmc.h"
38 #include "wd_timer.h"
39 #include "soc.h"
41 /* Base offset for all DRA7XX interrupts external to MPUSS */
42 #define DRA7XX_IRQ_GIC_START 32
44 /* Base offset for all DRA7XX dma requests */
45 #define DRA7XX_DMA_REQ_START 1
48 /*
49 * IP blocks
50 */
52 /*
53 * 'dmm' class
54 * instance(s): dmm
55 */
56 static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
57 .name = "dmm",
58 };
60 /* dmm */
61 static struct omap_hwmod dra7xx_dmm_hwmod = {
62 .name = "dmm",
63 .class = &dra7xx_dmm_hwmod_class,
64 .clkdm_name = "emif_clkdm",
65 .prcm = {
66 .omap4 = {
67 .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
68 .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
69 },
70 },
71 };
73 /*
74 * 'emif_ocp_fw' class
75 * instance(s): emif_ocp_fw
76 */
77 static struct omap_hwmod_class dra7xx_emif_ocp_fw_hwmod_class = {
78 .name = "emif_ocp_fw",
79 };
81 /* emif_ocp_fw */
82 static struct omap_hwmod dra7xx_emif_ocp_fw_hwmod = {
83 .name = "emif_ocp_fw",
84 .class = &dra7xx_emif_ocp_fw_hwmod_class,
85 .clkdm_name = "emif_clkdm",
86 .prcm = {
87 .omap4 = {
88 .clkctrl_offs = DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET,
89 .context_offs = DRA7XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET,
90 },
91 },
92 };
94 /*
95 * 'l3' class
96 * instance(s): l3_instr, l3_main_1, l3_main_2
97 */
98 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
99 .name = "l3",
100 };
102 /* l3_instr */
103 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
104 .name = "l3_instr",
105 .class = &dra7xx_l3_hwmod_class,
106 .clkdm_name = "l3instr_clkdm",
107 .prcm = {
108 .omap4 = {
109 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
110 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
111 .modulemode = MODULEMODE_HWCTRL,
112 },
113 },
114 };
116 /* l3_main_1 */
117 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
118 .name = "l3_main_1",
119 .class = &dra7xx_l3_hwmod_class,
120 .clkdm_name = "l3main1_clkdm",
121 .prcm = {
122 .omap4 = {
123 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
124 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
125 },
126 },
127 };
129 /* l3_main_2 */
130 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
131 .name = "l3_main_2",
132 .class = &dra7xx_l3_hwmod_class,
133 .clkdm_name = "l3instr_clkdm",
134 .prcm = {
135 .omap4 = {
136 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
137 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
138 .modulemode = MODULEMODE_HWCTRL,
139 },
140 },
141 };
143 /*
144 * 'l4' class
145 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
146 */
147 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
148 .name = "l4",
149 };
151 /* l4_cfg */
152 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
153 .name = "l4_cfg",
154 .class = &dra7xx_l4_hwmod_class,
155 .clkdm_name = "l4cfg_clkdm",
156 .prcm = {
157 .omap4 = {
158 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
159 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
160 },
161 },
162 };
164 /* l4_per1 */
165 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
166 .name = "l4_per1",
167 .class = &dra7xx_l4_hwmod_class,
168 .clkdm_name = "l4per_clkdm",
169 .prcm = {
170 .omap4 = {
171 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
172 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
173 },
174 },
175 };
177 /* l4_per2 */
178 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
179 .name = "l4_per2",
180 .class = &dra7xx_l4_hwmod_class,
181 .clkdm_name = "l4per2_clkdm",
182 .prcm = {
183 .omap4 = {
184 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
185 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
186 },
187 },
188 };
190 /* l4_per3 */
191 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
192 .name = "l4_per3",
193 .class = &dra7xx_l4_hwmod_class,
194 .clkdm_name = "l4per3_clkdm",
195 .prcm = {
196 .omap4 = {
197 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
198 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
199 },
200 },
201 };
203 /* l4_wkup */
204 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
205 .name = "l4_wkup",
206 .class = &dra7xx_l4_hwmod_class,
207 .clkdm_name = "wkupaon_clkdm",
208 .prcm = {
209 .omap4 = {
210 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
211 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
212 },
213 },
214 };
216 /*
217 * 'atl' class
218 *
219 */
221 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
222 .name = "atl",
223 };
225 /* atl */
226 static struct omap_hwmod dra7xx_atl_hwmod = {
227 .name = "atl",
228 .class = &dra7xx_atl_hwmod_class,
229 .clkdm_name = "atl_clkdm",
230 .main_clk = "atl_gfclk_mux",
231 .lockdep_class = HWMOD_LOCKDEP_SUBCLASS_CLASS1,
232 .prcm = {
233 .omap4 = {
234 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
235 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
236 .modulemode = MODULEMODE_SWCTRL,
237 },
238 },
239 };
241 /*
242 * 'bb2d' class
243 *
244 */
246 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
247 .name = "bb2d",
248 };
250 /* bb2d */
251 static struct omap_hwmod dra7xx_bb2d_hwmod = {
252 .name = "bb2d",
253 .class = &dra7xx_bb2d_hwmod_class,
254 .clkdm_name = "dss_clkdm",
255 .main_clk = "dpll_core_h24x2_ck",
256 .prcm = {
257 .omap4 = {
258 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
259 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
260 .modulemode = MODULEMODE_SWCTRL,
261 },
262 },
263 };
265 /*
266 * 'vpe' class
267 *
268 */
270 static struct omap_hwmod_class_sysconfig dra7xx_vpe_sysc = {
271 .sysc_offs = 0x0010,
272 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
273 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
274 MSTANDBY_FORCE | MSTANDBY_NO |
275 MSTANDBY_SMART),
276 .sysc_fields = &omap_hwmod_sysc_type2,
277 };
279 static struct omap_hwmod_class dra7xx_vpe_hwmod_class = {
280 .name = "vpe",
281 .sysc = &dra7xx_vpe_sysc,
282 };
284 /* vpe */
285 static struct omap_hwmod dra7xx_vpe_hwmod = {
286 .name = "vpe",
287 .class = &dra7xx_vpe_hwmod_class,
288 .clkdm_name = "vpe_clkdm",
289 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
290 .prcm = {
291 .omap4 = {
292 .clkctrl_offs = DRA7XX_CM_VPE_VPE_CLKCTRL_OFFSET,
293 .context_offs = DRA7XX_RM_VPE_VPE_CONTEXT_OFFSET,
294 .modulemode = MODULEMODE_HWCTRL,
295 },
296 },
297 };
299 /*
300 * 'vip' class
301 *
302 */
304 static struct omap_hwmod_class_sysconfig dra7xx_vip_sysc = {
305 .sysc_offs = 0x0010,
306 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
307 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
308 MSTANDBY_FORCE | MSTANDBY_NO |
309 MSTANDBY_SMART),
310 .sysc_fields = &omap_hwmod_sysc_type2,
311 };
313 static struct omap_hwmod_class dra7xx_vip_hwmod_class = {
314 .name = "vip",
315 .sysc = &dra7xx_vip_sysc,
316 };
318 /* vip1 */
319 static struct omap_hwmod dra7xx_vip1_hwmod = {
320 .name = "vip1",
321 .class = &dra7xx_vip_hwmod_class,
322 .clkdm_name = "cam_clkdm",
323 .main_clk = "vip1_gclk_mux",
324 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
325 .prcm = {
326 .omap4 = {
327 .clkctrl_offs = DRA7XX_CM_CAM_VIP1_CLKCTRL_OFFSET,
328 .context_offs = DRA7XX_RM_CAM_VIP1_CONTEXT_OFFSET,
329 .modulemode = MODULEMODE_HWCTRL,
330 },
331 },
332 };
334 /* vip2 */
335 static struct omap_hwmod dra7xx_vip2_hwmod = {
336 .name = "vip2",
337 .class = &dra7xx_vip_hwmod_class,
338 .clkdm_name = "cam_clkdm",
339 .main_clk = "vip2_gclk_mux",
340 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
341 .prcm = {
342 .omap4 = {
343 .clkctrl_offs = DRA7XX_CM_CAM_VIP2_CLKCTRL_OFFSET,
344 .context_offs = DRA7XX_RM_CAM_VIP2_CONTEXT_OFFSET,
345 .modulemode = MODULEMODE_HWCTRL,
346 },
347 },
348 };
350 /* vip3 */
351 static struct omap_hwmod dra7xx_vip3_hwmod = {
352 .name = "vip3",
353 .class = &dra7xx_vip_hwmod_class,
354 .clkdm_name = "cam_clkdm",
355 .main_clk = "vip3_gclk_mux",
356 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
357 .prcm = {
358 .omap4 = {
359 .clkctrl_offs = DRA7XX_CM_CAM_VIP3_CLKCTRL_OFFSET,
360 .context_offs = DRA7XX_RM_CAM_VIP3_CONTEXT_OFFSET,
361 .modulemode = MODULEMODE_HWCTRL,
362 },
363 },
364 };
366 /*
367 * 'cal' class
368 *
369 */
371 static struct omap_hwmod_class_sysconfig dra7xx_cal_sysc = {
372 .sysc_offs = 0x0010,
373 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_RESET_STATUS |
374 SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE),
375 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
376 MSTANDBY_FORCE | MSTANDBY_NO),
377 .sysc_fields = &omap_hwmod_sysc_type2,
378 };
380 static struct omap_hwmod_class dra7xx_cal_hwmod_class = {
381 .name = "cal",
382 .sysc = &dra7xx_cal_sysc,
383 };
385 /* cal */
386 static struct omap_hwmod dra7xx_cal_hwmod = {
387 .name = "cal",
388 .class = &dra7xx_cal_hwmod_class,
389 .clkdm_name = "cam_clkdm",
390 .main_clk = "vip2_gclk_mux",
391 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
392 .prcm = {
393 .omap4 = {
394 .clkctrl_offs = DRA7XX_CM_CAM_VIP2_CLKCTRL_OFFSET,
395 .context_offs = DRA7XX_RM_CAM_VIP2_CONTEXT_OFFSET,
396 .modulemode = MODULEMODE_HWCTRL,
397 },
398 },
399 };
401 /*
402 * 'counter' class
403 *
404 */
406 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
407 .rev_offs = 0x0000,
408 .sysc_offs = 0x0010,
409 .sysc_flags = SYSC_HAS_SIDLEMODE,
410 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
411 SIDLE_SMART_WKUP),
412 .sysc_fields = &omap_hwmod_sysc_type1,
413 };
415 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
416 .name = "counter",
417 .sysc = &dra7xx_counter_sysc,
418 };
420 /* counter_32k */
421 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
422 .name = "counter_32k",
423 .class = &dra7xx_counter_hwmod_class,
424 .clkdm_name = "wkupaon_clkdm",
425 .flags = HWMOD_SWSUP_SIDLE,
426 .main_clk = "wkupaon_iclk_mux",
427 .prcm = {
428 .omap4 = {
429 .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
430 .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
431 },
432 },
433 };
435 /*
436 * 'ctrl_module' class
437 *
438 */
440 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
441 .name = "ctrl_module",
442 };
444 /* ctrl_module_wkup */
445 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
446 .name = "ctrl_module_wkup",
447 .class = &dra7xx_ctrl_module_hwmod_class,
448 .clkdm_name = "wkupaon_clkdm",
449 .prcm = {
450 .omap4 = {
451 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
452 },
453 },
454 };
456 /*
457 * 'gmac' class
458 * cpsw/gmac sub system
459 */
460 static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
461 .rev_offs = 0x0,
462 .sysc_offs = 0x8,
463 .syss_offs = 0x4,
464 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
465 SYSS_HAS_RESET_STATUS),
466 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
467 MSTANDBY_NO),
468 .sysc_fields = &omap_hwmod_sysc_type3,
469 };
471 static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
472 .name = "gmac",
473 .sysc = &dra7xx_gmac_sysc,
474 };
476 static struct omap_hwmod dra7xx_gmac_hwmod = {
477 .name = "gmac",
478 .class = &dra7xx_gmac_hwmod_class,
479 .clkdm_name = "gmac_clkdm",
480 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
481 .main_clk = "dpll_gmac_ck",
482 .mpu_rt_idx = 1,
483 .prcm = {
484 .omap4 = {
485 .clkctrl_offs = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
486 .context_offs = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
487 .modulemode = MODULEMODE_SWCTRL,
488 },
489 },
490 };
492 /*
493 * 'mdio' class
494 */
495 static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
496 .name = "davinci_mdio",
497 };
499 static struct omap_hwmod dra7xx_mdio_hwmod = {
500 .name = "davinci_mdio",
501 .class = &dra7xx_mdio_hwmod_class,
502 .clkdm_name = "gmac_clkdm",
503 .main_clk = "dpll_gmac_ck",
504 };
506 /*
507 * 'dcan' class
508 *
509 */
511 static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
512 .name = "dcan",
513 };
515 /* dcan1 */
516 static struct omap_hwmod dra7xx_dcan1_hwmod = {
517 .name = "dcan1",
518 .class = &dra7xx_dcan_hwmod_class,
519 .clkdm_name = "wkupaon_clkdm",
520 .prcm = {
521 .omap4 = {
522 .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
523 .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
524 .modulemode = MODULEMODE_SWCTRL,
525 },
526 },
527 };
529 /* dcan2 */
530 static struct omap_hwmod dra7xx_dcan2_hwmod = {
531 .name = "dcan2",
532 .class = &dra7xx_dcan_hwmod_class,
533 .clkdm_name = "l4per2_clkdm",
534 .prcm = {
535 .omap4 = {
536 .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
537 .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
538 .modulemode = MODULEMODE_SWCTRL,
539 },
540 },
541 };
543 /* pwmss */
544 static struct omap_hwmod_class_sysconfig dra7xx_epwmss_sysc = {
545 .rev_offs = 0x0,
546 .sysc_offs = 0x4,
547 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_RESET_STATUS,
548 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
549 .sysc_fields = &omap_hwmod_sysc_type2,
550 };
552 struct omap_hwmod_class dra7xx_epwmss_hwmod_class = {
553 .name = "epwmss",
554 .sysc = &dra7xx_epwmss_sysc,
555 };
557 static struct omap_hwmod_class dra7xx_ecap_hwmod_class = {
558 .name = "ecap",
559 };
561 static struct omap_hwmod_class dra7xx_eqep_hwmod_class = {
562 .name = "eqep",
563 };
565 struct omap_hwmod_class dra7xx_ehrpwm_hwmod_class = {
566 .name = "ehrpwm",
567 };
569 /* epwmss0 */
570 struct omap_hwmod dra7xx_epwmss0_hwmod = {
571 .name = "epwmss0",
572 .class = &dra7xx_epwmss_hwmod_class,
573 .clkdm_name = "l4per2_clkdm",
574 .main_clk = "l4_root_clk_div",
575 .prcm = {
576 .omap4 = {
577 .modulemode = MODULEMODE_SWCTRL,
578 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET,
579 .context_offs = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET,
580 },
581 },
582 };
584 /* ecap0 */
585 struct omap_hwmod dra7xx_ecap0_hwmod = {
586 .name = "ecap0",
587 .class = &dra7xx_ecap_hwmod_class,
588 .clkdm_name = "l4per2_clkdm",
589 .main_clk = "l4_root_clk_div",
590 };
592 /* eqep0 */
593 struct omap_hwmod dra7xx_eqep0_hwmod = {
594 .name = "eqep0",
595 .class = &dra7xx_eqep_hwmod_class,
596 .clkdm_name = "l4per2_clkdm",
597 .main_clk = "l4_root_clk_div",
598 };
600 /* ehrpwm0 */
601 struct omap_hwmod dra7xx_ehrpwm0_hwmod = {
602 .name = "ehrpwm0",
603 .class = &dra7xx_ehrpwm_hwmod_class,
604 .clkdm_name = "l4per2_clkdm",
605 .main_clk = "l4_root_clk_div",
606 };
608 /* epwmss1 */
609 struct omap_hwmod dra7xx_epwmss1_hwmod = {
610 .name = "epwmss1",
611 .class = &dra7xx_epwmss_hwmod_class,
612 .clkdm_name = "l4per2_clkdm",
613 .main_clk = "l4_root_clk_div",
614 .prcm = {
615 .omap4 = {
616 .modulemode = MODULEMODE_SWCTRL,
617 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET,
618 .context_offs = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET,
619 },
620 },
621 };
623 /* ecap1 */
624 struct omap_hwmod dra7xx_ecap1_hwmod = {
625 .name = "ecap1",
626 .class = &dra7xx_ecap_hwmod_class,
627 .clkdm_name = "l4per2_clkdm",
628 .main_clk = "l4_root_clk_div",
629 };
631 /* eqep1 */
632 struct omap_hwmod dra7xx_eqep1_hwmod = {
633 .name = "eqep1",
634 .class = &dra7xx_eqep_hwmod_class,
635 .clkdm_name = "l4per2_clkdm",
636 .main_clk = "l4_root_clk_div",
637 };
639 /* ehrpwm1 */
640 struct omap_hwmod dra7xx_ehrpwm1_hwmod = {
641 .name = "ehrpwm1",
642 .class = &dra7xx_ehrpwm_hwmod_class,
643 .clkdm_name = "l4per2_clkdm",
644 .main_clk = "l4_root_clk_div",
645 };
647 /* epwmss2 */
648 struct omap_hwmod dra7xx_epwmss2_hwmod = {
649 .name = "epwmss2",
650 .class = &dra7xx_epwmss_hwmod_class,
651 .clkdm_name = "l4per2_clkdm",
652 .main_clk = "l4_root_clk_div",
653 .prcm = {
654 .omap4 = {
655 .modulemode = MODULEMODE_SWCTRL,
656 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET,
657 .context_offs = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET,
658 },
659 },
660 };
662 /* ecap2 */
663 struct omap_hwmod dra7xx_ecap2_hwmod = {
664 .name = "ecap2",
665 .class = &dra7xx_ecap_hwmod_class,
666 .clkdm_name = "l4per2_clkdm",
667 .main_clk = "l4_root_clk_div",
668 };
670 /* eqep2 */
671 struct omap_hwmod dra7xx_eqep2_hwmod = {
672 .name = "eqep2",
673 .class = &dra7xx_eqep_hwmod_class,
674 .clkdm_name = "l4per2_clkdm",
675 .main_clk = "l4_root_clk_div",
676 };
678 /* ehrpwm2 */
679 struct omap_hwmod dra7xx_ehrpwm2_hwmod = {
680 .name = "ehrpwm2",
681 .class = &dra7xx_ehrpwm_hwmod_class,
682 .clkdm_name = "l4per2_clkdm",
683 .main_clk = "l4_root_clk_div",
684 };
686 /*
687 * 'dma' class
688 *
689 */
691 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
692 .rev_offs = 0x0000,
693 .sysc_offs = 0x002c,
694 .syss_offs = 0x0028,
695 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
696 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
697 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
698 SYSS_HAS_RESET_STATUS),
699 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
700 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
701 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
702 .sysc_fields = &omap_hwmod_sysc_type1,
703 };
705 static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
706 .name = "dma",
707 .sysc = &dra7xx_dma_sysc,
708 };
710 /* dma dev_attr */
711 static struct omap_dma_dev_attr dma_dev_attr = {
712 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
713 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
714 .lch_count = 32,
715 };
717 /* dma_system */
718 static struct omap_hwmod dra7xx_dma_system_hwmod = {
719 .name = "dma_system",
720 .class = &dra7xx_dma_hwmod_class,
721 .clkdm_name = "dma_clkdm",
722 .main_clk = "l3_iclk_div",
723 .prcm = {
724 .omap4 = {
725 .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
726 .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
727 },
728 },
729 .dev_attr = &dma_dev_attr,
730 };
732 /*
733 * 'dsp' class
734 * dsp sub-system
735 */
737 static struct omap_hwmod_class dra7xx_dsp_hwmod_class = {
738 .name = "dsp",
739 };
741 static struct omap_hwmod_rst_info dra7xx_dsp_resets[] = {
742 { .name = "dsp", .rst_shift = 0 },
743 };
745 /* dsp1 processor */
746 static struct omap_hwmod dra7xx_dsp1_hwmod = {
747 .name = "dsp1",
748 .class = &dra7xx_dsp_hwmod_class,
749 .clkdm_name = "dsp1_clkdm",
750 .rst_lines = dra7xx_dsp_resets,
751 .rst_lines_cnt = ARRAY_SIZE(dra7xx_dsp_resets),
752 .main_clk = "dpll_dsp_m2_ck",
753 .prcm = {
754 .omap4 = {
755 .clkctrl_offs = DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET,
756 .rstctrl_offs = DRA7XX_RM_DSP1_RSTCTRL_OFFSET,
757 .context_offs = DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET,
758 },
759 },
760 };
762 /* dsp2 processor */
763 static struct omap_hwmod dra7xx_dsp2_hwmod = {
764 .name = "dsp2",
765 .class = &dra7xx_dsp_hwmod_class,
766 .clkdm_name = "dsp2_clkdm",
767 .rst_lines = dra7xx_dsp_resets,
768 .rst_lines_cnt = ARRAY_SIZE(dra7xx_dsp_resets),
769 .main_clk = "dpll_dsp_m2_ck",
770 .prcm = {
771 .omap4 = {
772 .clkctrl_offs = DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET,
773 .rstctrl_offs = DRA7XX_RM_DSP2_RSTCTRL_OFFSET,
774 .context_offs = DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET,
775 },
776 },
777 };
779 /*
780 * 'dss' class
781 *
782 */
784 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
785 .rev_offs = 0x0000,
786 .syss_offs = 0x0014,
787 .sysc_flags = SYSS_HAS_RESET_STATUS,
788 };
790 static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
791 .name = "dss",
792 .sysc = &dra7xx_dss_sysc,
793 .reset = omap_dss_reset,
794 };
796 /* dss */
797 static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
798 { .dma_req = 75 + DRA7XX_DMA_REQ_START },
799 { .dma_req = -1 }
800 };
802 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
803 { .role = "dss_clk", .clk = "dss_dss_clk" },
804 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
805 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
806 { .role = "video2_clk", .clk = "dss_video2_clk" },
807 { .role = "video1_clk", .clk = "dss_video1_clk" },
808 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
809 };
811 static struct omap_hwmod dra7xx_dss_hwmod = {
812 .name = "dss_core",
813 .class = &dra7xx_dss_hwmod_class,
814 .clkdm_name = "dss_clkdm",
815 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
816 .sdma_reqs = dra7xx_dss_sdma_reqs,
817 .main_clk = "dss_dss_clk",
818 .prcm = {
819 .omap4 = {
820 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
821 .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
822 .modulemode = MODULEMODE_SWCTRL,
823 },
824 },
825 .opt_clks = dss_opt_clks,
826 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
827 };
829 /*
830 * 'dispc' class
831 * display controller
832 */
834 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
835 .rev_offs = 0x0000,
836 .sysc_offs = 0x0010,
837 .syss_offs = 0x0014,
838 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
839 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
840 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
841 SYSS_HAS_RESET_STATUS),
842 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
843 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
844 .sysc_fields = &omap_hwmod_sysc_type1,
845 };
847 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
848 .name = "dispc",
849 .sysc = &dra7xx_dispc_sysc,
850 };
852 /* dss_dispc */
853 /* dss_dispc dev_attr */
854 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
855 .has_framedonetv_irq = 1,
856 .manager_count = 4,
857 };
859 static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
860 .name = "dss_dispc",
861 .class = &dra7xx_dispc_hwmod_class,
862 .clkdm_name = "dss_clkdm",
863 .main_clk = "dss_dss_clk",
864 .prcm = {
865 .omap4 = {
866 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
867 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
868 },
869 },
870 .dev_attr = &dss_dispc_dev_attr,
871 .parent_hwmod = &dra7xx_dss_hwmod,
872 };
874 /*
875 * 'hdmi' class
876 * hdmi controller
877 */
879 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
880 .rev_offs = 0x0000,
881 .sysc_offs = 0x0010,
882 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
883 SYSC_HAS_SOFTRESET),
884 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
885 SIDLE_SMART_WKUP),
886 .sysc_fields = &omap_hwmod_sysc_type2,
887 };
889 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
890 .name = "hdmi",
891 .sysc = &dra7xx_hdmi_sysc,
892 };
894 /* dss_hdmi */
896 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
897 { .role = "sys_clk", .clk = "dss_hdmi_clk" },
898 };
900 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
901 .name = "dss_hdmi",
902 .class = &dra7xx_hdmi_hwmod_class,
903 .clkdm_name = "dss_clkdm",
904 .main_clk = "dss_48mhz_clk",
905 .prcm = {
906 .omap4 = {
907 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
908 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
909 },
910 },
911 .opt_clks = dss_hdmi_opt_clks,
912 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
913 .parent_hwmod = &dra7xx_dss_hwmod,
914 };
916 /* AES (the 'P' (public) device) */
917 static struct omap_hwmod_class_sysconfig dra7xx_aes_sysc = {
918 .rev_offs = 0x0080,
919 .sysc_offs = 0x0084,
920 .syss_offs = 0x0088,
921 .sysc_flags = SYSS_HAS_RESET_STATUS,
922 };
924 static struct omap_hwmod_class dra7xx_aes_hwmod_class = {
925 .name = "aes",
926 .sysc = &dra7xx_aes_sysc,
927 .rev = 2,
928 };
930 /* AES1 */
931 static struct omap_hwmod dra7xx_aes1_hwmod = {
932 .name = "aes1",
933 .class = &dra7xx_aes_hwmod_class,
934 .clkdm_name = "l4sec_clkdm",
935 .main_clk = "l3_iclk_div",
936 .prcm = {
937 .omap4 = {
938 .clkctrl_offs = DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET,
939 .context_offs = DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET,
940 .modulemode = MODULEMODE_HWCTRL,
941 },
942 },
943 };
945 /* AES2 */
946 static struct omap_hwmod dra7xx_aes2_hwmod = {
947 .name = "aes2",
948 .class = &dra7xx_aes_hwmod_class,
949 .clkdm_name = "l4sec_clkdm",
950 .main_clk = "l3_iclk_div",
951 .prcm = {
952 .omap4 = {
953 .clkctrl_offs = DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET,
954 .context_offs = DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET,
955 .modulemode = MODULEMODE_HWCTRL,
956 },
957 },
958 };
960 /* sha0 HIB2 (the 'P' (public) device) */
961 static struct omap_hwmod_class_sysconfig dra7xx_sha0_sysc = {
962 .rev_offs = 0x100,
963 .sysc_offs = 0x110,
964 .syss_offs = 0x114,
965 .sysc_flags = SYSS_HAS_RESET_STATUS,
966 };
968 static struct omap_hwmod_class dra7xx_sha0_hwmod_class = {
969 .name = "sham",
970 .sysc = &dra7xx_sha0_sysc,
971 .rev = 2,
972 };
974 struct omap_hwmod dra7xx_sha0_hwmod = {
975 .name = "sham",
976 .class = &dra7xx_sha0_hwmod_class,
977 .clkdm_name = "l4sec_clkdm",
978 .main_clk = "l3_iclk_div",
979 .prcm = {
980 .omap4 = {
981 .clkctrl_offs = DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
982 .context_offs = DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
983 .modulemode = MODULEMODE_HWCTRL,
984 },
985 },
986 };
988 /*
989 * 'elm' class
990 *
991 */
993 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
994 .rev_offs = 0x0000,
995 .sysc_offs = 0x0010,
996 .syss_offs = 0x0014,
997 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
998 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
999 SYSS_HAS_RESET_STATUS),
1000 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1001 SIDLE_SMART_WKUP),
1002 .sysc_fields = &omap_hwmod_sysc_type1,
1003 };
1005 static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
1006 .name = "elm",
1007 .sysc = &dra7xx_elm_sysc,
1008 };
1010 /* elm */
1012 static struct omap_hwmod dra7xx_elm_hwmod = {
1013 .name = "elm",
1014 .class = &dra7xx_elm_hwmod_class,
1015 .clkdm_name = "l4per_clkdm",
1016 .main_clk = "l3_iclk_div",
1017 .prcm = {
1018 .omap4 = {
1019 .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
1020 .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
1021 },
1022 },
1023 };
1025 /*
1026 * 'gpio' class
1027 *
1028 */
1030 static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
1031 .rev_offs = 0x0000,
1032 .sysc_offs = 0x0010,
1033 .syss_offs = 0x0114,
1034 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1035 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1036 SYSS_HAS_RESET_STATUS),
1037 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1038 SIDLE_SMART_WKUP),
1039 .sysc_fields = &omap_hwmod_sysc_type1,
1040 };
1042 static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
1043 .name = "gpio",
1044 .sysc = &dra7xx_gpio_sysc,
1045 .rev = 2,
1046 };
1048 /* gpio dev_attr */
1049 static struct omap_gpio_dev_attr gpio_dev_attr = {
1050 .bank_width = 32,
1051 .dbck_flag = true,
1052 };
1054 /* gpio1 */
1055 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1056 { .role = "dbclk", .clk = "gpio1_dbclk" },
1057 };
1059 static struct omap_hwmod dra7xx_gpio1_hwmod = {
1060 .name = "gpio1",
1061 .class = &dra7xx_gpio_hwmod_class,
1062 .clkdm_name = "wkupaon_clkdm",
1063 .main_clk = "wkupaon_iclk_mux",
1064 .prcm = {
1065 .omap4 = {
1066 .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
1067 .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
1068 .modulemode = MODULEMODE_HWCTRL,
1069 },
1070 },
1071 .opt_clks = gpio1_opt_clks,
1072 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1073 .dev_attr = &gpio_dev_attr,
1074 };
1076 /* gpio2 */
1077 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1078 { .role = "dbclk", .clk = "gpio2_dbclk" },
1079 };
1081 static struct omap_hwmod dra7xx_gpio2_hwmod = {
1082 .name = "gpio2",
1083 .class = &dra7xx_gpio_hwmod_class,
1084 .clkdm_name = "l4per_clkdm",
1085 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1086 .main_clk = "l3_iclk_div",
1087 .prcm = {
1088 .omap4 = {
1089 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1090 .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1091 .modulemode = MODULEMODE_HWCTRL,
1092 },
1093 },
1094 .opt_clks = gpio2_opt_clks,
1095 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1096 .dev_attr = &gpio_dev_attr,
1097 };
1099 /* gpio3 */
1100 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1101 { .role = "dbclk", .clk = "gpio3_dbclk" },
1102 };
1104 static struct omap_hwmod dra7xx_gpio3_hwmod = {
1105 .name = "gpio3",
1106 .class = &dra7xx_gpio_hwmod_class,
1107 .clkdm_name = "l4per_clkdm",
1108 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1109 .main_clk = "l3_iclk_div",
1110 .prcm = {
1111 .omap4 = {
1112 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1113 .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1114 .modulemode = MODULEMODE_HWCTRL,
1115 },
1116 },
1117 .opt_clks = gpio3_opt_clks,
1118 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1119 .dev_attr = &gpio_dev_attr,
1120 };
1122 /* gpio4 */
1123 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1124 { .role = "dbclk", .clk = "gpio4_dbclk" },
1125 };
1127 static struct omap_hwmod dra7xx_gpio4_hwmod = {
1128 .name = "gpio4",
1129 .class = &dra7xx_gpio_hwmod_class,
1130 .clkdm_name = "l4per_clkdm",
1131 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1132 .main_clk = "l3_iclk_div",
1133 .prcm = {
1134 .omap4 = {
1135 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1136 .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1137 .modulemode = MODULEMODE_HWCTRL,
1138 },
1139 },
1140 .opt_clks = gpio4_opt_clks,
1141 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1142 .dev_attr = &gpio_dev_attr,
1143 };
1145 /* gpio5 */
1146 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1147 { .role = "dbclk", .clk = "gpio5_dbclk" },
1148 };
1150 static struct omap_hwmod dra7xx_gpio5_hwmod = {
1151 .name = "gpio5",
1152 .class = &dra7xx_gpio_hwmod_class,
1153 .clkdm_name = "l4per_clkdm",
1154 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1155 .main_clk = "l3_iclk_div",
1156 .prcm = {
1157 .omap4 = {
1158 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1159 .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1160 .modulemode = MODULEMODE_HWCTRL,
1161 },
1162 },
1163 .opt_clks = gpio5_opt_clks,
1164 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1165 .dev_attr = &gpio_dev_attr,
1166 };
1168 /* gpio6 */
1169 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1170 { .role = "dbclk", .clk = "gpio6_dbclk" },
1171 };
1173 static struct omap_hwmod dra7xx_gpio6_hwmod = {
1174 .name = "gpio6",
1175 .class = &dra7xx_gpio_hwmod_class,
1176 .clkdm_name = "l4per_clkdm",
1177 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1178 .main_clk = "l3_iclk_div",
1179 .prcm = {
1180 .omap4 = {
1181 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1182 .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1183 .modulemode = MODULEMODE_HWCTRL,
1184 },
1185 },
1186 .opt_clks = gpio6_opt_clks,
1187 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1188 .dev_attr = &gpio_dev_attr,
1189 };
1191 /* gpio7 */
1192 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
1193 { .role = "dbclk", .clk = "gpio7_dbclk" },
1194 };
1196 static struct omap_hwmod dra7xx_gpio7_hwmod = {
1197 .name = "gpio7",
1198 .class = &dra7xx_gpio_hwmod_class,
1199 .clkdm_name = "l4per_clkdm",
1200 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1201 .main_clk = "l3_iclk_div",
1202 .prcm = {
1203 .omap4 = {
1204 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
1205 .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
1206 .modulemode = MODULEMODE_HWCTRL,
1207 },
1208 },
1209 .opt_clks = gpio7_opt_clks,
1210 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
1211 .dev_attr = &gpio_dev_attr,
1212 };
1214 /* gpio8 */
1215 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
1216 { .role = "dbclk", .clk = "gpio8_dbclk" },
1217 };
1219 static struct omap_hwmod dra7xx_gpio8_hwmod = {
1220 .name = "gpio8",
1221 .class = &dra7xx_gpio_hwmod_class,
1222 .clkdm_name = "l4per_clkdm",
1223 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1224 .main_clk = "l3_iclk_div",
1225 .prcm = {
1226 .omap4 = {
1227 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
1228 .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
1229 .modulemode = MODULEMODE_HWCTRL,
1230 },
1231 },
1232 .opt_clks = gpio8_opt_clks,
1233 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
1234 .dev_attr = &gpio_dev_attr,
1235 };
1237 /*
1238 * 'gpmc' class
1239 *
1240 */
1242 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
1243 .rev_offs = 0x0000,
1244 .sysc_offs = 0x0010,
1245 .syss_offs = 0x0014,
1246 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1247 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1248 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
1249 .sysc_fields = &omap_hwmod_sysc_type1,
1250 };
1252 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
1253 .name = "gpmc",
1254 .sysc = &dra7xx_gpmc_sysc,
1255 };
1257 /* gpmc */
1259 static struct omap_hwmod dra7xx_gpmc_hwmod = {
1260 .name = "gpmc",
1261 .class = &dra7xx_gpmc_hwmod_class,
1262 .clkdm_name = "l3main1_clkdm",
1263 .main_clk = "l3_iclk_div",
1264 .prcm = {
1265 .omap4 = {
1266 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
1267 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
1268 .modulemode = MODULEMODE_HWCTRL,
1269 },
1270 },
1271 };
1273 /*
1274 * 'hdq1w' class
1275 *
1276 */
1278 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
1279 .rev_offs = 0x0000,
1280 .sysc_offs = 0x0014,
1281 .syss_offs = 0x0018,
1282 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1283 SYSS_HAS_RESET_STATUS),
1284 .sysc_fields = &omap_hwmod_sysc_type1,
1285 };
1287 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
1288 .name = "hdq1w",
1289 .sysc = &dra7xx_hdq1w_sysc,
1290 };
1292 /* hdq1w */
1294 static struct omap_hwmod dra7xx_hdq1w_hwmod = {
1295 .name = "hdq1w",
1296 .class = &dra7xx_hdq1w_hwmod_class,
1297 .clkdm_name = "l4per_clkdm",
1298 .flags = HWMOD_INIT_NO_RESET,
1299 .main_clk = "func_12m_fclk",
1300 .prcm = {
1301 .omap4 = {
1302 .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1303 .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1304 .modulemode = MODULEMODE_SWCTRL,
1305 },
1306 },
1307 };
1309 /*
1310 * 'i2c' class
1311 *
1312 */
1314 static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
1315 .sysc_offs = 0x0010,
1316 .syss_offs = 0x0090,
1317 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1318 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1319 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1320 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1321 SIDLE_SMART_WKUP),
1322 .clockact = CLOCKACT_TEST_ICLK,
1323 .sysc_fields = &omap_hwmod_sysc_type1,
1324 };
1326 static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
1327 .name = "i2c",
1328 .sysc = &dra7xx_i2c_sysc,
1329 .reset = &omap_i2c_reset,
1330 .rev = OMAP_I2C_IP_VERSION_2,
1331 };
1333 /* i2c dev_attr */
1334 static struct omap_i2c_dev_attr i2c_dev_attr = {
1335 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1336 };
1338 /* i2c1 */
1339 static struct omap_hwmod dra7xx_i2c1_hwmod = {
1340 .name = "i2c1",
1341 .class = &dra7xx_i2c_hwmod_class,
1342 .clkdm_name = "l4per_clkdm",
1343 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1344 .main_clk = "func_96m_fclk",
1345 .prcm = {
1346 .omap4 = {
1347 .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1348 .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
1349 .modulemode = MODULEMODE_SWCTRL,
1350 },
1351 },
1352 .dev_attr = &i2c_dev_attr,
1353 };
1355 /* i2c2 */
1356 static struct omap_hwmod dra7xx_i2c2_hwmod = {
1357 .name = "i2c2",
1358 .class = &dra7xx_i2c_hwmod_class,
1359 .clkdm_name = "l4per_clkdm",
1360 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1361 .main_clk = "func_96m_fclk",
1362 .prcm = {
1363 .omap4 = {
1364 .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1365 .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
1366 .modulemode = MODULEMODE_SWCTRL,
1367 },
1368 },
1369 .dev_attr = &i2c_dev_attr,
1370 };
1372 /* i2c3 */
1373 static struct omap_hwmod dra7xx_i2c3_hwmod = {
1374 .name = "i2c3",
1375 .class = &dra7xx_i2c_hwmod_class,
1376 .clkdm_name = "l4per_clkdm",
1377 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1378 .main_clk = "func_96m_fclk",
1379 .prcm = {
1380 .omap4 = {
1381 .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1382 .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
1383 .modulemode = MODULEMODE_SWCTRL,
1384 },
1385 },
1386 .dev_attr = &i2c_dev_attr,
1387 };
1389 /* i2c4 */
1390 static struct omap_hwmod dra7xx_i2c4_hwmod = {
1391 .name = "i2c4",
1392 .class = &dra7xx_i2c_hwmod_class,
1393 .clkdm_name = "l4per_clkdm",
1394 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1395 .main_clk = "func_96m_fclk",
1396 .prcm = {
1397 .omap4 = {
1398 .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1399 .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
1400 .modulemode = MODULEMODE_SWCTRL,
1401 },
1402 },
1403 .dev_attr = &i2c_dev_attr,
1404 };
1406 /* i2c5 */
1407 static struct omap_hwmod dra7xx_i2c5_hwmod = {
1408 .name = "i2c5",
1409 .class = &dra7xx_i2c_hwmod_class,
1410 .clkdm_name = "ipu_clkdm",
1411 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1412 .main_clk = "func_96m_fclk",
1413 .prcm = {
1414 .omap4 = {
1415 .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
1416 .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
1417 .modulemode = MODULEMODE_SWCTRL,
1418 },
1419 },
1420 .dev_attr = &i2c_dev_attr,
1421 };
1423 /*
1424 * 'ipu' class
1425 * imaging processor unit
1426 */
1428 static struct omap_hwmod_class dra7xx_ipu_hwmod_class = {
1429 .name = "ipu",
1430 };
1432 static struct omap_hwmod_rst_info dra7xx_ipu_resets[] = {
1433 { .name = "cpu0", .rst_shift = 0 },
1434 { .name = "cpu1", .rst_shift = 1 },
1435 };
1437 /* ipu1 processor */
1438 static struct omap_hwmod dra7xx_ipu1_hwmod = {
1439 .name = "ipu1",
1440 .class = &dra7xx_ipu_hwmod_class,
1441 .clkdm_name = "ipu1_clkdm",
1442 .rst_lines = dra7xx_ipu_resets,
1443 .rst_lines_cnt = ARRAY_SIZE(dra7xx_ipu_resets),
1444 .main_clk = "ipu1_gfclk_mux",
1445 .prcm = {
1446 .omap4 = {
1447 .clkctrl_offs = DRA7XX_CM_IPU1_IPU1_CLKCTRL_OFFSET,
1448 .rstctrl_offs = DRA7XX_RM_IPU1_RSTCTRL_OFFSET,
1449 .context_offs = DRA7XX_RM_IPU1_IPU1_CONTEXT_OFFSET,
1450 },
1451 },
1452 };
1454 /* ipu2 processor */
1455 static struct omap_hwmod dra7xx_ipu2_hwmod = {
1456 .name = "ipu2",
1457 .class = &dra7xx_ipu_hwmod_class,
1458 .clkdm_name = "ipu2_clkdm",
1459 .rst_lines = dra7xx_ipu_resets,
1460 .rst_lines_cnt = ARRAY_SIZE(dra7xx_ipu_resets),
1461 .main_clk = "dpll_core_h22x2_ck",
1462 .prcm = {
1463 .omap4 = {
1464 .clkctrl_offs = DRA7XX_CM_IPU2_IPU2_CLKCTRL_OFFSET,
1465 .rstctrl_offs = DRA7XX_RM_IPU2_RSTCTRL_OFFSET,
1466 .context_offs = DRA7XX_RM_IPU2_IPU2_CONTEXT_OFFSET,
1467 },
1468 },
1469 };
1471 /*
1472 * 'mailbox' class
1473 *
1474 */
1476 static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
1477 .rev_offs = 0x0000,
1478 .sysc_offs = 0x0010,
1479 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1480 SYSC_HAS_SOFTRESET),
1481 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1482 .sysc_fields = &omap_hwmod_sysc_type2,
1483 };
1485 static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
1486 .name = "mailbox",
1487 .sysc = &dra7xx_mailbox_sysc,
1488 };
1490 /* mailbox1 */
1491 static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1492 .name = "mailbox1",
1493 .class = &dra7xx_mailbox_hwmod_class,
1494 .clkdm_name = "l4cfg_clkdm",
1495 .prcm = {
1496 .omap4 = {
1497 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1498 .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1499 },
1500 },
1501 };
1503 /* mailbox2 */
1504 static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1505 .name = "mailbox2",
1506 .class = &dra7xx_mailbox_hwmod_class,
1507 .clkdm_name = "l4cfg_clkdm",
1508 .prcm = {
1509 .omap4 = {
1510 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1511 .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1512 },
1513 },
1514 };
1516 /* mailbox3 */
1517 static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1518 .name = "mailbox3",
1519 .class = &dra7xx_mailbox_hwmod_class,
1520 .clkdm_name = "l4cfg_clkdm",
1521 .prcm = {
1522 .omap4 = {
1523 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1524 .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1525 },
1526 },
1527 };
1529 /* mailbox4 */
1530 static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1531 .name = "mailbox4",
1532 .class = &dra7xx_mailbox_hwmod_class,
1533 .clkdm_name = "l4cfg_clkdm",
1534 .prcm = {
1535 .omap4 = {
1536 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1537 .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1538 },
1539 },
1540 };
1542 /* mailbox5 */
1543 static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1544 .name = "mailbox5",
1545 .class = &dra7xx_mailbox_hwmod_class,
1546 .clkdm_name = "l4cfg_clkdm",
1547 .prcm = {
1548 .omap4 = {
1549 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1550 .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1551 },
1552 },
1553 };
1555 /* mailbox6 */
1556 static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1557 .name = "mailbox6",
1558 .class = &dra7xx_mailbox_hwmod_class,
1559 .clkdm_name = "l4cfg_clkdm",
1560 .prcm = {
1561 .omap4 = {
1562 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1563 .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1564 },
1565 },
1566 };
1568 /* mailbox7 */
1569 static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1570 .name = "mailbox7",
1571 .class = &dra7xx_mailbox_hwmod_class,
1572 .clkdm_name = "l4cfg_clkdm",
1573 .prcm = {
1574 .omap4 = {
1575 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1576 .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1577 },
1578 },
1579 };
1581 /* mailbox8 */
1582 static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1583 .name = "mailbox8",
1584 .class = &dra7xx_mailbox_hwmod_class,
1585 .clkdm_name = "l4cfg_clkdm",
1586 .prcm = {
1587 .omap4 = {
1588 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1589 .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1590 },
1591 },
1592 };
1594 /* mailbox9 */
1595 static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1596 .name = "mailbox9",
1597 .class = &dra7xx_mailbox_hwmod_class,
1598 .clkdm_name = "l4cfg_clkdm",
1599 .prcm = {
1600 .omap4 = {
1601 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1602 .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1603 },
1604 },
1605 };
1607 /* mailbox10 */
1608 static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1609 .name = "mailbox10",
1610 .class = &dra7xx_mailbox_hwmod_class,
1611 .clkdm_name = "l4cfg_clkdm",
1612 .prcm = {
1613 .omap4 = {
1614 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1615 .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1616 },
1617 },
1618 };
1620 /* mailbox11 */
1621 static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1622 .name = "mailbox11",
1623 .class = &dra7xx_mailbox_hwmod_class,
1624 .clkdm_name = "l4cfg_clkdm",
1625 .prcm = {
1626 .omap4 = {
1627 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1628 .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1629 },
1630 },
1631 };
1633 /* mailbox12 */
1634 static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1635 .name = "mailbox12",
1636 .class = &dra7xx_mailbox_hwmod_class,
1637 .clkdm_name = "l4cfg_clkdm",
1638 .prcm = {
1639 .omap4 = {
1640 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1641 .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1642 },
1643 },
1644 };
1646 /* mailbox13 */
1647 static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1648 .name = "mailbox13",
1649 .class = &dra7xx_mailbox_hwmod_class,
1650 .clkdm_name = "l4cfg_clkdm",
1651 .prcm = {
1652 .omap4 = {
1653 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1654 .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1655 },
1656 },
1657 };
1659 /*
1660 * 'mcspi' class
1661 *
1662 */
1664 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1665 .rev_offs = 0x0000,
1666 .sysc_offs = 0x0010,
1667 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1668 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1669 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1670 SIDLE_SMART_WKUP),
1671 .sysc_fields = &omap_hwmod_sysc_type2,
1672 };
1674 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1675 .name = "mcspi",
1676 .sysc = &dra7xx_mcspi_sysc,
1677 .rev = OMAP4_MCSPI_REV,
1678 };
1680 /* mcspi1 */
1681 /* mcspi1 dev_attr */
1682 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1683 .num_chipselect = 4,
1684 };
1686 static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1687 .name = "mcspi1",
1688 .class = &dra7xx_mcspi_hwmod_class,
1689 .clkdm_name = "l4per_clkdm",
1690 .main_clk = "func_48m_fclk",
1691 .prcm = {
1692 .omap4 = {
1693 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1694 .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1695 .modulemode = MODULEMODE_SWCTRL,
1696 },
1697 },
1698 .dev_attr = &mcspi1_dev_attr,
1699 };
1701 /* mcspi2 */
1702 /* mcspi2 dev_attr */
1703 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1704 .num_chipselect = 2,
1705 };
1707 static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1708 .name = "mcspi2",
1709 .class = &dra7xx_mcspi_hwmod_class,
1710 .clkdm_name = "l4per_clkdm",
1711 .main_clk = "func_48m_fclk",
1712 .prcm = {
1713 .omap4 = {
1714 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1715 .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1716 .modulemode = MODULEMODE_SWCTRL,
1717 },
1718 },
1719 .dev_attr = &mcspi2_dev_attr,
1720 };
1722 /* mcspi3 */
1723 /* mcspi3 dev_attr */
1724 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1725 .num_chipselect = 2,
1726 };
1728 static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1729 .name = "mcspi3",
1730 .class = &dra7xx_mcspi_hwmod_class,
1731 .clkdm_name = "l4per_clkdm",
1732 .main_clk = "func_48m_fclk",
1733 .prcm = {
1734 .omap4 = {
1735 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1736 .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1737 .modulemode = MODULEMODE_SWCTRL,
1738 },
1739 },
1740 .dev_attr = &mcspi3_dev_attr,
1741 };
1743 /* mcspi4 */
1744 /* mcspi4 dev_attr */
1745 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1746 .num_chipselect = 1,
1747 };
1749 static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1750 .name = "mcspi4",
1751 .class = &dra7xx_mcspi_hwmod_class,
1752 .clkdm_name = "l4per_clkdm",
1753 .main_clk = "func_48m_fclk",
1754 .prcm = {
1755 .omap4 = {
1756 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1757 .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1758 .modulemode = MODULEMODE_SWCTRL,
1759 },
1760 },
1761 .dev_attr = &mcspi4_dev_attr,
1762 };
1764 /*
1765 * 'mcasp' class
1766 *
1767 */
1768 static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc = {
1769 .sysc_offs = 0x0004,
1770 .sysc_flags = SYSC_HAS_SIDLEMODE,
1771 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1772 .sysc_fields = &omap_hwmod_sysc_type3,
1773 };
1775 static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
1776 .name = "mcasp",
1777 .sysc = &dra7xx_mcasp_sysc,
1778 };
1780 /* mcasp3 */
1781 static struct omap_hwmod dra7xx_mcasp3_hwmod = {
1782 .name = "mcasp3",
1783 .class = &dra7xx_mcasp_hwmod_class,
1784 .clkdm_name = "l4per2_clkdm",
1785 .main_clk = "mcasp3_ahclkx_mux",
1786 .flags = HWMOD_SWSUP_SIDLE,
1787 .prcm = {
1788 .omap4 = {
1789 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET,
1790 .context_offs = DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET,
1791 .modulemode = MODULEMODE_SWCTRL,
1792 },
1793 },
1794 };
1796 /* mcasp8 */
1797 static struct omap_hwmod dra7xx_mcasp8_hwmod = {
1798 .name = "mcasp8",
1799 .class = &dra7xx_mcasp_hwmod_class,
1800 .clkdm_name = "l4per2_clkdm",
1801 .main_clk = "mcasp8_ahclkx_mux",
1802 .flags = HWMOD_SWSUP_SIDLE_ACT,
1803 .prcm = {
1804 .omap4 = {
1805 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,
1806 .context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
1807 .modulemode = MODULEMODE_SWCTRL,
1808 },
1809 },
1810 };
1812 /*
1813 * 'mmc' class
1814 *
1815 */
1817 static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1818 .rev_offs = 0x0000,
1819 .sysc_offs = 0x0010,
1820 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1821 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1822 SYSC_HAS_SOFTRESET),
1823 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1824 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1825 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1826 .sysc_fields = &omap_hwmod_sysc_type2,
1827 };
1829 static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1830 .name = "mmc",
1831 .sysc = &dra7xx_mmc_sysc,
1832 };
1834 /* mmc1 */
1835 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1836 { .role = "clk32k", .clk = "mmc1_clk32k" },
1837 };
1839 /* mmc1 dev_attr */
1840 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1841 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1842 };
1844 static struct omap_hwmod dra7xx_mmc1_hwmod = {
1845 .name = "mmc1",
1846 .class = &dra7xx_mmc_hwmod_class,
1847 .clkdm_name = "l3init_clkdm",
1848 .main_clk = "mmc1_fclk_div",
1849 .prcm = {
1850 .omap4 = {
1851 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1852 .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1853 .modulemode = MODULEMODE_SWCTRL,
1854 },
1855 },
1856 .opt_clks = mmc1_opt_clks,
1857 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1858 .dev_attr = &mmc1_dev_attr,
1859 };
1861 /* mmc2 */
1862 static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1863 { .role = "clk32k", .clk = "mmc2_clk32k" },
1864 };
1866 static struct omap_hwmod dra7xx_mmc2_hwmod = {
1867 .name = "mmc2",
1868 .class = &dra7xx_mmc_hwmod_class,
1869 .clkdm_name = "l3init_clkdm",
1870 .main_clk = "mmc2_fclk_div",
1871 .prcm = {
1872 .omap4 = {
1873 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1874 .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1875 .modulemode = MODULEMODE_SWCTRL,
1876 },
1877 },
1878 .opt_clks = mmc2_opt_clks,
1879 .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks),
1880 };
1882 /* mmc3 */
1883 static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1884 { .role = "clk32k", .clk = "mmc3_clk32k" },
1885 };
1887 static struct omap_hwmod dra7xx_mmc3_hwmod = {
1888 .name = "mmc3",
1889 .class = &dra7xx_mmc_hwmod_class,
1890 .clkdm_name = "l4per_clkdm",
1891 .main_clk = "mmc3_gfclk_div",
1892 .prcm = {
1893 .omap4 = {
1894 .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1895 .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1896 .modulemode = MODULEMODE_SWCTRL,
1897 },
1898 },
1899 .opt_clks = mmc3_opt_clks,
1900 .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks),
1901 };
1903 /* mmc4 */
1904 static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1905 { .role = "clk32k", .clk = "mmc4_clk32k" },
1906 };
1908 static struct omap_hwmod dra7xx_mmc4_hwmod = {
1909 .name = "mmc4",
1910 .class = &dra7xx_mmc_hwmod_class,
1911 .clkdm_name = "l4per_clkdm",
1912 .main_clk = "mmc4_gfclk_div",
1913 .prcm = {
1914 .omap4 = {
1915 .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1916 .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1917 .modulemode = MODULEMODE_SWCTRL,
1918 },
1919 },
1920 .opt_clks = mmc4_opt_clks,
1921 .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks),
1922 };
1924 /*
1925 * 'mmu' class
1926 * The memory management unit performs virtual to physical address translation
1927 * for its requestors.
1928 */
1930 static struct omap_hwmod_class_sysconfig dra7xx_mmu_sysc = {
1931 .rev_offs = 0x0000,
1932 .sysc_offs = 0x0010,
1933 .syss_offs = 0x0014,
1934 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1935 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1936 SYSS_HAS_RESET_STATUS),
1937 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1938 .sysc_fields = &omap_hwmod_sysc_type1,
1939 };
1941 static struct omap_hwmod_class dra7xx_mmu_hwmod_class = {
1942 .name = "mmu",
1943 .sysc = &dra7xx_mmu_sysc,
1944 };
1946 /* DSP MMUs */
1947 static struct omap_hwmod_rst_info dra7xx_mmu_dsp_resets[] = {
1948 { .name = "mmu_cache", .rst_shift = 1 },
1949 };
1951 /* mmu0 - dsp1 */
1952 static struct omap_hwmod dra7xx_mmu0_dsp1_hwmod = {
1953 .name = "mmu0_dsp1",
1954 .class = &dra7xx_mmu_hwmod_class,
1955 .clkdm_name = "dsp1_clkdm",
1956 .rst_lines = dra7xx_mmu_dsp_resets,
1957 .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_dsp_resets),
1958 .main_clk = "dpll_dsp_m2_ck",
1959 .prcm = {
1960 .omap4 = {
1961 .clkctrl_offs = DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET,
1962 .rstctrl_offs = DRA7XX_RM_DSP1_RSTCTRL_OFFSET,
1963 .context_offs = DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET,
1964 .modulemode = MODULEMODE_HWCTRL,
1965 },
1966 },
1967 };
1969 /* mmu1 - dsp1 */
1970 static struct omap_hwmod dra7xx_mmu1_dsp1_hwmod = {
1971 .name = "mmu1_dsp1",
1972 .class = &dra7xx_mmu_hwmod_class,
1973 .clkdm_name = "dsp1_clkdm",
1974 .rst_lines = dra7xx_mmu_dsp_resets,
1975 .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_dsp_resets),
1976 .main_clk = "dpll_dsp_m2_ck",
1977 .prcm = {
1978 .omap4 = {
1979 .clkctrl_offs = DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET,
1980 .rstctrl_offs = DRA7XX_RM_DSP1_RSTCTRL_OFFSET,
1981 .context_offs = DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET,
1982 .modulemode = MODULEMODE_HWCTRL,
1983 },
1984 },
1985 };
1987 /* mmu0 - dsp2 */
1988 static struct omap_hwmod dra7xx_mmu0_dsp2_hwmod = {
1989 .name = "mmu0_dsp2",
1990 .class = &dra7xx_mmu_hwmod_class,
1991 .clkdm_name = "dsp2_clkdm",
1992 .rst_lines = dra7xx_mmu_dsp_resets,
1993 .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_dsp_resets),
1994 .main_clk = "dpll_dsp_m2_ck",
1995 .prcm = {
1996 .omap4 = {
1997 .clkctrl_offs = DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET,
1998 .rstctrl_offs = DRA7XX_RM_DSP2_RSTCTRL_OFFSET,
1999 .context_offs = DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET,
2000 .modulemode = MODULEMODE_HWCTRL,
2001 },
2002 },
2003 };
2005 /* mmu1 - dsp2 */
2006 static struct omap_hwmod dra7xx_mmu1_dsp2_hwmod = {
2007 .name = "mmu1_dsp2",
2008 .class = &dra7xx_mmu_hwmod_class,
2009 .clkdm_name = "dsp2_clkdm",
2010 .rst_lines = dra7xx_mmu_dsp_resets,
2011 .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_dsp_resets),
2012 .main_clk = "dpll_dsp_m2_ck",
2013 .prcm = {
2014 .omap4 = {
2015 .clkctrl_offs = DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET,
2016 .rstctrl_offs = DRA7XX_RM_DSP2_RSTCTRL_OFFSET,
2017 .context_offs = DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET,
2018 .modulemode = MODULEMODE_HWCTRL,
2019 },
2020 },
2021 };
2023 /* IPU MMUs */
2024 static struct omap_hwmod_rst_info dra7xx_mmu_ipu_resets[] = {
2025 { .name = "mmu_cache", .rst_shift = 2 },
2026 };
2028 /* mmu ipu1 */
2029 static struct omap_hwmod dra7xx_mmu_ipu1_hwmod = {
2030 .name = "mmu_ipu1",
2031 .class = &dra7xx_mmu_hwmod_class,
2032 .clkdm_name = "ipu1_clkdm",
2033 .rst_lines = dra7xx_mmu_ipu_resets,
2034 .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_ipu_resets),
2035 .main_clk = "ipu1_gfclk_mux",
2036 .prcm = {
2037 .omap4 = {
2038 .clkctrl_offs = DRA7XX_CM_IPU1_IPU1_CLKCTRL_OFFSET,
2039 .rstctrl_offs = DRA7XX_RM_IPU1_RSTCTRL_OFFSET,
2040 .context_offs = DRA7XX_RM_IPU1_IPU1_CONTEXT_OFFSET,
2041 .modulemode = MODULEMODE_HWCTRL,
2042 },
2043 },
2044 };
2046 /* mmu ipu2 */
2047 static struct omap_hwmod dra7xx_mmu_ipu2_hwmod = {
2048 .name = "mmu_ipu2",
2049 .class = &dra7xx_mmu_hwmod_class,
2050 .clkdm_name = "ipu2_clkdm",
2051 .rst_lines = dra7xx_mmu_ipu_resets,
2052 .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_ipu_resets),
2053 .main_clk = "dpll_core_h22x2_ck",
2054 .prcm = {
2055 .omap4 = {
2056 .clkctrl_offs = DRA7XX_CM_IPU2_IPU2_CLKCTRL_OFFSET,
2057 .rstctrl_offs = DRA7XX_RM_IPU2_RSTCTRL_OFFSET,
2058 .context_offs = DRA7XX_RM_IPU2_IPU2_CONTEXT_OFFSET,
2059 .modulemode = MODULEMODE_HWCTRL,
2060 },
2061 },
2062 };
2064 /*
2065 * 'mpu' class
2066 *
2067 */
2069 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
2070 .name = "mpu",
2071 };
2073 /* mpu */
2074 static struct omap_hwmod dra7xx_mpu_hwmod = {
2075 .name = "mpu",
2076 .class = &dra7xx_mpu_hwmod_class,
2077 .clkdm_name = "mpu_clkdm",
2078 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2079 .main_clk = "dpll_mpu_m2_ck",
2080 .prcm = {
2081 .omap4 = {
2082 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
2083 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
2084 },
2085 },
2086 };
2088 /*
2089 * 'ocp2scp' class
2090 *
2091 */
2093 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
2094 .rev_offs = 0x0000,
2095 .sysc_offs = 0x0010,
2096 .syss_offs = 0x0014,
2097 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2098 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2099 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2100 SIDLE_SMART_WKUP),
2101 .sysc_fields = &omap_hwmod_sysc_type1,
2102 };
2104 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
2105 .name = "ocp2scp",
2106 .sysc = &dra7xx_ocp2scp_sysc,
2107 };
2109 /* ocp2scp1 */
2110 static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
2111 .name = "ocp2scp1",
2112 .class = &dra7xx_ocp2scp_hwmod_class,
2113 .clkdm_name = "l3init_clkdm",
2114 .main_clk = "l4_root_clk_div",
2115 .prcm = {
2116 .omap4 = {
2117 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
2118 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
2119 .modulemode = MODULEMODE_HWCTRL,
2120 },
2121 },
2122 };
2124 /* ocp2scp3 */
2125 static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
2126 .name = "ocp2scp3",
2127 .class = &dra7xx_ocp2scp_hwmod_class,
2128 .clkdm_name = "l3init_clkdm",
2129 .main_clk = "l4_root_clk_div",
2130 .prcm = {
2131 .omap4 = {
2132 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
2133 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
2134 .modulemode = MODULEMODE_HWCTRL,
2135 },
2136 },
2137 };
2139 /*
2140 * 'PCIE' class
2141 *
2142 */
2144 static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
2145 .name = "pcie",
2146 };
2148 /* pcie1 */
2149 static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = {
2150 { .name = "pcie", .rst_shift = 0 },
2151 };
2153 static struct omap_hwmod dra7xx_pciess1_hwmod = {
2154 .name = "pcie1",
2155 .class = &dra7xx_pciess_hwmod_class,
2156 .clkdm_name = "pcie_clkdm",
2157 .rst_lines = dra7xx_pciess1_resets,
2158 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess1_resets),
2159 .main_clk = "l4_root_clk_div",
2160 .prcm = {
2161 .omap4 = {
2162 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
2163 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
2164 .rstctrl_offs = DRA7XX_RM_L3INIT_RSTCTRL_OFFSET,
2165 .modulemode = MODULEMODE_SWCTRL,
2166 },
2167 },
2168 };
2170 /* pcie2 */
2171 static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = {
2172 { .name = "pcie", .rst_shift = 1 },
2173 };
2175 static struct omap_hwmod dra7xx_pciess2_hwmod = {
2176 .name = "pcie2",
2177 .class = &dra7xx_pciess_hwmod_class,
2178 .clkdm_name = "pcie_clkdm",
2179 .rst_lines = dra7xx_pciess2_resets,
2180 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess2_resets),
2181 .main_clk = "l4_root_clk_div",
2182 .prcm = {
2183 .omap4 = {
2184 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
2185 .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
2186 .rstctrl_offs = DRA7XX_RM_L3INIT_RSTCTRL_OFFSET,
2187 .modulemode = MODULEMODE_SWCTRL,
2188 },
2189 },
2190 };
2192 /*
2193 * 'pru-icss' class
2194 * Programmable Real-Time Unit and Industrial Communication Subsystem
2195 */
2196 static struct omap_hwmod_class dra7xx_pruss_hwmod_class = {
2197 .name = "pruss",
2198 };
2200 /* pru-icss1 */
2201 static struct omap_hwmod dra7xx_pruss1_hwmod = {
2202 .name = "pruss1",
2203 .class = &dra7xx_pruss_hwmod_class,
2204 .clkdm_name = "l4per2_clkdm",
2205 .prcm = {
2206 .omap4 = {
2207 .clkctrl_offs = DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL_OFFSET,
2208 .context_offs = DRA7XX_RM_L4PER2_PRUSS1_CONTEXT_OFFSET,
2209 .modulemode = MODULEMODE_SWCTRL,
2210 },
2211 },
2212 };
2214 /* pru-icss2 */
2215 static struct omap_hwmod dra7xx_pruss2_hwmod = {
2216 .name = "pruss2",
2217 .class = &dra7xx_pruss_hwmod_class,
2218 .clkdm_name = "l4per2_clkdm",
2219 .prcm = {
2220 .omap4 = {
2221 .clkctrl_offs = DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL_OFFSET,
2222 .context_offs = DRA7XX_RM_L4PER2_PRUSS2_CONTEXT_OFFSET,
2223 .modulemode = MODULEMODE_SWCTRL,
2224 },
2225 },
2226 };
2228 /*
2229 * 'qspi' class
2230 *
2231 */
2233 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
2234 .sysc_offs = 0x0010,
2235 .sysc_flags = SYSC_HAS_SIDLEMODE,
2236 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2237 SIDLE_SMART_WKUP),
2238 .sysc_fields = &omap_hwmod_sysc_type2,
2239 };
2241 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
2242 .name = "qspi",
2243 .sysc = &dra7xx_qspi_sysc,
2244 };
2246 /* qspi */
2247 static struct omap_hwmod dra7xx_qspi_hwmod = {
2248 .name = "qspi",
2249 .class = &dra7xx_qspi_hwmod_class,
2250 .clkdm_name = "l4per2_clkdm",
2251 .main_clk = "qspi_gfclk_div",
2252 .prcm = {
2253 .omap4 = {
2254 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
2255 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
2256 .modulemode = MODULEMODE_SWCTRL,
2257 },
2258 },
2259 };
2261 /*
2262 * 'rtcss' class
2263 *
2264 */
2265 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
2266 .sysc_offs = 0x0078,
2267 .sysc_flags = SYSC_HAS_SIDLEMODE,
2268 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2269 SIDLE_SMART_WKUP),
2270 .sysc_fields = &omap_hwmod_sysc_type3,
2271 };
2273 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
2274 .name = "rtcss",
2275 .sysc = &dra7xx_rtcss_sysc,
2276 .reset = &omap_hwmod_rtc_unlock,
2277 };
2279 /* rtcss */
2280 static struct omap_hwmod dra7xx_rtcss_hwmod = {
2281 .name = "rtcss",
2282 .class = &dra7xx_rtcss_hwmod_class,
2283 .clkdm_name = "rtc_clkdm",
2284 .main_clk = "sys_32k_ck",
2285 .prcm = {
2286 .omap4 = {
2287 .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
2288 .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
2289 .modulemode = MODULEMODE_SWCTRL,
2290 },
2291 },
2292 };
2294 /*
2295 * 'sata' class
2296 *
2297 */
2299 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
2300 .sysc_offs = 0x0000,
2301 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
2302 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2303 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2304 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2305 .sysc_fields = &omap_hwmod_sysc_type2,
2306 };
2308 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
2309 .name = "sata",
2310 .sysc = &dra7xx_sata_sysc,
2311 };
2313 /* sata */
2315 static struct omap_hwmod dra7xx_sata_hwmod = {
2316 .name = "sata",
2317 .class = &dra7xx_sata_hwmod_class,
2318 .clkdm_name = "l3init_clkdm",
2319 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2320 .main_clk = "func_48m_fclk",
2321 .mpu_rt_idx = 1,
2322 .prcm = {
2323 .omap4 = {
2324 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
2325 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
2326 .modulemode = MODULEMODE_SWCTRL,
2327 },
2328 },
2329 };
2331 /*
2332 * 'smartreflex' class
2333 *
2334 */
2336 /* The IP is not compliant to type1 / type2 scheme */
2337 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2338 .sidle_shift = 24,
2339 .enwkup_shift = 26,
2340 };
2342 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
2343 .sysc_offs = 0x0038,
2344 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2345 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2346 SIDLE_SMART_WKUP),
2347 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
2348 };
2350 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
2351 .name = "smartreflex",
2352 .sysc = &dra7xx_smartreflex_sysc,
2353 .rev = 2,
2354 };
2356 /* smartreflex_core */
2357 /* smartreflex_core dev_attr */
2358 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2359 .sensor_voltdm_name = "core",
2360 };
2362 static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
2363 .name = "smartreflex_core",
2364 .class = &dra7xx_smartreflex_hwmod_class,
2365 .clkdm_name = "coreaon_clkdm",
2366 .main_clk = "wkupaon_iclk_mux",
2367 .prcm = {
2368 .omap4 = {
2369 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
2370 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
2371 .modulemode = MODULEMODE_SWCTRL,
2372 },
2373 },
2374 .dev_attr = &smartreflex_core_dev_attr,
2375 };
2377 /* smartreflex_mpu */
2378 /* smartreflex_mpu dev_attr */
2379 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2380 .sensor_voltdm_name = "mpu",
2381 };
2383 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
2384 .name = "smartreflex_mpu",
2385 .class = &dra7xx_smartreflex_hwmod_class,
2386 .clkdm_name = "coreaon_clkdm",
2387 .main_clk = "wkupaon_iclk_mux",
2388 .prcm = {
2389 .omap4 = {
2390 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
2391 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
2392 .modulemode = MODULEMODE_SWCTRL,
2393 },
2394 },
2395 .dev_attr = &smartreflex_mpu_dev_attr,
2396 };
2398 /*
2399 * 'spinlock' class
2400 *
2401 */
2403 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
2404 .rev_offs = 0x0000,
2405 .sysc_offs = 0x0010,
2406 .syss_offs = 0x0014,
2407 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2408 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2409 SYSS_HAS_RESET_STATUS),
2410 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2411 .sysc_fields = &omap_hwmod_sysc_type1,
2412 };
2414 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
2415 .name = "spinlock",
2416 .sysc = &dra7xx_spinlock_sysc,
2417 };
2419 /* spinlock */
2420 static struct omap_hwmod dra7xx_spinlock_hwmod = {
2421 .name = "spinlock",
2422 .class = &dra7xx_spinlock_hwmod_class,
2423 .clkdm_name = "l4cfg_clkdm",
2424 .main_clk = "l3_iclk_div",
2425 .prcm = {
2426 .omap4 = {
2427 .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
2428 .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
2429 },
2430 },
2431 };
2433 /*
2434 * 'timer' class
2435 *
2436 * This class contains several variants: ['timer_1ms', 'timer_secure',
2437 * 'timer']
2438 */
2440 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
2441 .rev_offs = 0x0000,
2442 .sysc_offs = 0x0010,
2443 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2444 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2445 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2446 SIDLE_SMART_WKUP),
2447 .sysc_fields = &omap_hwmod_sysc_type2,
2448 };
2450 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
2451 .name = "timer",
2452 .sysc = &dra7xx_timer_1ms_sysc,
2453 };
2455 static struct omap_hwmod_class_sysconfig dra7xx_timer_secure_sysc = {
2456 .rev_offs = 0x0000,
2457 .sysc_offs = 0x0010,
2458 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2459 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2460 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2461 SIDLE_SMART_WKUP),
2462 .sysc_fields = &omap_hwmod_sysc_type2,
2463 };
2465 static struct omap_hwmod_class dra7xx_timer_secure_hwmod_class = {
2466 .name = "timer",
2467 .sysc = &dra7xx_timer_secure_sysc,
2468 };
2470 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
2471 .rev_offs = 0x0000,
2472 .sysc_offs = 0x0010,
2473 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2474 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2475 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2476 SIDLE_SMART_WKUP),
2477 .sysc_fields = &omap_hwmod_sysc_type2,
2478 };
2480 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
2481 .name = "timer",
2482 .sysc = &dra7xx_timer_sysc,
2483 };
2485 /* timer1 */
2486 static struct omap_hwmod dra7xx_timer1_hwmod = {
2487 .name = "timer1",
2488 .class = &dra7xx_timer_1ms_hwmod_class,
2489 .clkdm_name = "wkupaon_clkdm",
2490 .main_clk = "timer1_gfclk_mux",
2491 .prcm = {
2492 .omap4 = {
2493 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
2494 .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
2495 .modulemode = MODULEMODE_SWCTRL,
2496 },
2497 },
2498 };
2500 /* timer2 */
2501 static struct omap_hwmod dra7xx_timer2_hwmod = {
2502 .name = "timer2",
2503 .class = &dra7xx_timer_1ms_hwmod_class,
2504 .clkdm_name = "l4per_clkdm",
2505 .main_clk = "timer2_gfclk_mux",
2506 .prcm = {
2507 .omap4 = {
2508 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
2509 .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
2510 .modulemode = MODULEMODE_SWCTRL,
2511 },
2512 },
2513 };
2515 /* timer3 */
2516 static struct omap_hwmod dra7xx_timer3_hwmod = {
2517 .name = "timer3",
2518 .class = &dra7xx_timer_hwmod_class,
2519 .clkdm_name = "l4per_clkdm",
2520 .main_clk = "timer3_gfclk_mux",
2521 .prcm = {
2522 .omap4 = {
2523 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
2524 .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
2525 .modulemode = MODULEMODE_SWCTRL,
2526 },
2527 },
2528 };
2530 /* timer4 */
2531 static struct omap_hwmod dra7xx_timer4_hwmod = {
2532 .name = "timer4",
2533 .class = &dra7xx_timer_hwmod_class,
2534 .clkdm_name = "l4per_clkdm",
2535 .main_clk = "timer4_gfclk_mux",
2536 .prcm = {
2537 .omap4 = {
2538 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
2539 .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
2540 .modulemode = MODULEMODE_SWCTRL,
2541 },
2542 },
2543 };
2545 /* timer5 */
2546 static struct omap_hwmod dra7xx_timer5_hwmod = {
2547 .name = "timer5",
2548 .class = &dra7xx_timer_hwmod_class,
2549 .clkdm_name = "ipu_clkdm",
2550 .main_clk = "timer5_gfclk_mux",
2551 .prcm = {
2552 .omap4 = {
2553 .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
2554 .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
2555 .modulemode = MODULEMODE_SWCTRL,
2556 },
2557 },
2558 };
2560 /* timer6 */
2561 static struct omap_hwmod dra7xx_timer6_hwmod = {
2562 .name = "timer6",
2563 .class = &dra7xx_timer_hwmod_class,
2564 .clkdm_name = "ipu_clkdm",
2565 .main_clk = "timer6_gfclk_mux",
2566 .prcm = {
2567 .omap4 = {
2568 .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
2569 .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
2570 .modulemode = MODULEMODE_SWCTRL,
2571 },
2572 },
2573 };
2575 /* timer7 */
2576 static struct omap_hwmod dra7xx_timer7_hwmod = {
2577 .name = "timer7",
2578 .class = &dra7xx_timer_hwmod_class,
2579 .clkdm_name = "ipu_clkdm",
2580 .main_clk = "timer7_gfclk_mux",
2581 .prcm = {
2582 .omap4 = {
2583 .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
2584 .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
2585 .modulemode = MODULEMODE_SWCTRL,
2586 },
2587 },
2588 };
2590 /* timer8 */
2591 static struct omap_hwmod dra7xx_timer8_hwmod = {
2592 .name = "timer8",
2593 .class = &dra7xx_timer_hwmod_class,
2594 .clkdm_name = "ipu_clkdm",
2595 .main_clk = "timer8_gfclk_mux",
2596 .prcm = {
2597 .omap4 = {
2598 .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
2599 .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
2600 .modulemode = MODULEMODE_SWCTRL,
2601 },
2602 },
2603 };
2605 /* timer9 */
2606 static struct omap_hwmod dra7xx_timer9_hwmod = {
2607 .name = "timer9",
2608 .class = &dra7xx_timer_hwmod_class,
2609 .clkdm_name = "l4per_clkdm",
2610 .main_clk = "timer9_gfclk_mux",
2611 .prcm = {
2612 .omap4 = {
2613 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
2614 .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
2615 .modulemode = MODULEMODE_SWCTRL,
2616 },
2617 },
2618 };
2620 /* timer10 */
2621 static struct omap_hwmod dra7xx_timer10_hwmod = {
2622 .name = "timer10",
2623 .class = &dra7xx_timer_1ms_hwmod_class,
2624 .clkdm_name = "l4per_clkdm",
2625 .main_clk = "timer10_gfclk_mux",
2626 .prcm = {
2627 .omap4 = {
2628 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
2629 .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
2630 .modulemode = MODULEMODE_SWCTRL,
2631 },
2632 },
2633 };
2635 /* timer11 */
2636 static struct omap_hwmod dra7xx_timer11_hwmod = {
2637 .name = "timer11",
2638 .class = &dra7xx_timer_hwmod_class,
2639 .clkdm_name = "l4per_clkdm",
2640 .main_clk = "timer11_gfclk_mux",
2641 .prcm = {
2642 .omap4 = {
2643 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
2644 .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
2645 .modulemode = MODULEMODE_SWCTRL,
2646 },
2647 },
2648 };
2650 /* timer12 */
2651 static struct omap_hwmod dra7xx_timer12_hwmod = {
2652 .name = "timer12",
2653 .class = &dra7xx_timer_secure_hwmod_class,
2654 .clkdm_name = "wkupaon_clkdm",
2655 .main_clk = "secure_32k_clk_src_ck",
2656 .prcm = {
2657 .omap4 = {
2658 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET,
2659 .context_offs = DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET,
2660 },
2661 },
2662 };
2664 /* timer13 */
2665 static struct omap_hwmod dra7xx_timer13_hwmod = {
2666 .name = "timer13",
2667 .class = &dra7xx_timer_hwmod_class,
2668 .clkdm_name = "l4per3_clkdm",
2669 .main_clk = "timer13_gfclk_mux",
2670 .prcm = {
2671 .omap4 = {
2672 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
2673 .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
2674 .modulemode = MODULEMODE_SWCTRL,
2675 },
2676 },
2677 };
2679 /* timer14 */
2680 static struct omap_hwmod dra7xx_timer14_hwmod = {
2681 .name = "timer14",
2682 .class = &dra7xx_timer_hwmod_class,
2683 .clkdm_name = "l4per3_clkdm",
2684 .main_clk = "timer14_gfclk_mux",
2685 .prcm = {
2686 .omap4 = {
2687 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
2688 .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
2689 .modulemode = MODULEMODE_SWCTRL,
2690 },
2691 },
2692 };
2694 /* timer15 */
2695 static struct omap_hwmod dra7xx_timer15_hwmod = {
2696 .name = "timer15",
2697 .class = &dra7xx_timer_hwmod_class,
2698 .clkdm_name = "l4per3_clkdm",
2699 .main_clk = "timer15_gfclk_mux",
2700 .prcm = {
2701 .omap4 = {
2702 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
2703 .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
2704 .modulemode = MODULEMODE_SWCTRL,
2705 },
2706 },
2707 };
2709 /* timer16 */
2710 static struct omap_hwmod dra7xx_timer16_hwmod = {
2711 .name = "timer16",
2712 .class = &dra7xx_timer_hwmod_class,
2713 .clkdm_name = "l4per3_clkdm",
2714 .main_clk = "timer16_gfclk_mux",
2715 .prcm = {
2716 .omap4 = {
2717 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
2718 .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
2719 .modulemode = MODULEMODE_SWCTRL,
2720 },
2721 },
2722 };
2724 /*
2725 * 'uart' class
2726 *
2727 */
2729 static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
2730 .rev_offs = 0x0050,
2731 .sysc_offs = 0x0054,
2732 .syss_offs = 0x0058,
2733 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2734 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2735 SYSS_HAS_RESET_STATUS),
2736 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2737 SIDLE_SMART_WKUP),
2738 .sysc_fields = &omap_hwmod_sysc_type1,
2739 };
2741 static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
2742 .name = "uart",
2743 .sysc = &dra7xx_uart_sysc,
2744 };
2746 /* uart1 */
2747 static struct omap_hwmod dra7xx_uart1_hwmod = {
2748 .name = "uart1",
2749 .class = &dra7xx_uart_hwmod_class,
2750 .clkdm_name = "l4per_clkdm",
2751 .main_clk = "uart1_gfclk_mux",
2752 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
2753 .prcm = {
2754 .omap4 = {
2755 .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
2756 .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
2757 .modulemode = MODULEMODE_SWCTRL,
2758 },
2759 },
2760 };
2762 /* uart2 */
2763 static struct omap_hwmod dra7xx_uart2_hwmod = {
2764 .name = "uart2",
2765 .class = &dra7xx_uart_hwmod_class,
2766 .clkdm_name = "l4per_clkdm",
2767 .main_clk = "uart2_gfclk_mux",
2768 .flags = HWMOD_SWSUP_SIDLE_ACT,
2769 .prcm = {
2770 .omap4 = {
2771 .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
2772 .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
2773 .modulemode = MODULEMODE_SWCTRL,
2774 },
2775 },
2776 };
2778 /* uart3 */
2779 static struct omap_hwmod dra7xx_uart3_hwmod = {
2780 .name = "uart3",
2781 .class = &dra7xx_uart_hwmod_class,
2782 .clkdm_name = "l4per_clkdm",
2783 .main_clk = "uart3_gfclk_mux",
2784 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART3_FLAGS,
2785 .prcm = {
2786 .omap4 = {
2787 .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
2788 .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
2789 .modulemode = MODULEMODE_SWCTRL,
2790 },
2791 },
2792 };
2794 /* uart4 */
2795 static struct omap_hwmod dra7xx_uart4_hwmod = {
2796 .name = "uart4",
2797 .class = &dra7xx_uart_hwmod_class,
2798 .clkdm_name = "l4per_clkdm",
2799 .main_clk = "uart4_gfclk_mux",
2800 .flags = HWMOD_SWSUP_SIDLE_ACT,
2801 .prcm = {
2802 .omap4 = {
2803 .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
2804 .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
2805 .modulemode = MODULEMODE_SWCTRL,
2806 },
2807 },
2808 };
2810 /* uart5 */
2811 static struct omap_hwmod dra7xx_uart5_hwmod = {
2812 .name = "uart5",
2813 .class = &dra7xx_uart_hwmod_class,
2814 .clkdm_name = "l4per_clkdm",
2815 .main_clk = "uart5_gfclk_mux",
2816 .flags = HWMOD_SWSUP_SIDLE_ACT,
2817 .prcm = {
2818 .omap4 = {
2819 .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
2820 .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
2821 .modulemode = MODULEMODE_SWCTRL,
2822 },
2823 },
2824 };
2826 /* uart6 */
2827 static struct omap_hwmod dra7xx_uart6_hwmod = {
2828 .name = "uart6",
2829 .class = &dra7xx_uart_hwmod_class,
2830 .clkdm_name = "ipu_clkdm",
2831 .main_clk = "uart6_gfclk_mux",
2832 .flags = HWMOD_SWSUP_SIDLE_ACT,
2833 .prcm = {
2834 .omap4 = {
2835 .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
2836 .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
2837 .modulemode = MODULEMODE_SWCTRL,
2838 },
2839 },
2840 };
2842 /* uart7 */
2843 static struct omap_hwmod dra7xx_uart7_hwmod = {
2844 .name = "uart7",
2845 .class = &dra7xx_uart_hwmod_class,
2846 .clkdm_name = "l4per2_clkdm",
2847 .main_clk = "uart7_gfclk_mux",
2848 .flags = HWMOD_SWSUP_SIDLE_ACT,
2849 .prcm = {
2850 .omap4 = {
2851 .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
2852 .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
2853 .modulemode = MODULEMODE_SWCTRL,
2854 },
2855 },
2856 };
2858 /* uart8 */
2859 static struct omap_hwmod dra7xx_uart8_hwmod = {
2860 .name = "uart8",
2861 .class = &dra7xx_uart_hwmod_class,
2862 .clkdm_name = "l4per2_clkdm",
2863 .main_clk = "uart8_gfclk_mux",
2864 .flags = HWMOD_SWSUP_SIDLE_ACT,
2865 .prcm = {
2866 .omap4 = {
2867 .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
2868 .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
2869 .modulemode = MODULEMODE_SWCTRL,
2870 },
2871 },
2872 };
2874 /* uart9 */
2875 static struct omap_hwmod dra7xx_uart9_hwmod = {
2876 .name = "uart9",
2877 .class = &dra7xx_uart_hwmod_class,
2878 .clkdm_name = "l4per2_clkdm",
2879 .main_clk = "uart9_gfclk_mux",
2880 .flags = HWMOD_SWSUP_SIDLE_ACT,
2881 .prcm = {
2882 .omap4 = {
2883 .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
2884 .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
2885 .modulemode = MODULEMODE_SWCTRL,
2886 },
2887 },
2888 };
2890 /* uart10 */
2891 static struct omap_hwmod dra7xx_uart10_hwmod = {
2892 .name = "uart10",
2893 .class = &dra7xx_uart_hwmod_class,
2894 .clkdm_name = "wkupaon_clkdm",
2895 .main_clk = "uart10_gfclk_mux",
2896 .flags = HWMOD_SWSUP_SIDLE_ACT,
2897 .prcm = {
2898 .omap4 = {
2899 .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
2900 .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
2901 .modulemode = MODULEMODE_SWCTRL,
2902 },
2903 },
2904 };
2906 /* DES (the 'P' (public) device) */
2907 static struct omap_hwmod_class_sysconfig dra7xx_des_sysc = {
2908 .rev_offs = 0x0030,
2909 .sysc_offs = 0x0034,
2910 .syss_offs = 0x0038,
2911 .sysc_flags = SYSS_HAS_RESET_STATUS,
2912 };
2914 static struct omap_hwmod_class dra7xx_des_hwmod_class = {
2915 .name = "des",
2916 .sysc = &dra7xx_des_sysc,
2917 };
2919 /* DES */
2920 static struct omap_hwmod dra7xx_des_hwmod = {
2921 .name = "des",
2922 .class = &dra7xx_des_hwmod_class,
2923 .clkdm_name = "l4sec_clkdm",
2924 .main_clk = "l3_iclk_div",
2925 .prcm = {
2926 .omap4 = {
2927 .clkctrl_offs = DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
2928 .context_offs = DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
2929 .modulemode = MODULEMODE_HWCTRL,
2930 },
2931 },
2932 };
2934 /* rng */
2935 static struct omap_hwmod_class_sysconfig dra7xx_rng_sysc = {
2936 .rev_offs = 0x1fe0,
2937 .sysc_offs = 0x1fe4,
2938 .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
2939 .idlemodes = SIDLE_FORCE | SIDLE_NO,
2940 .sysc_fields = &omap_hwmod_sysc_type1,
2941 };
2943 static struct omap_hwmod_class dra7xx_rng_hwmod_class = {
2944 .name = "rng",
2945 .sysc = &dra7xx_rng_sysc,
2946 };
2948 static struct omap_hwmod dra7xx_rng_hwmod = {
2949 .name = "rng",
2950 .class = &dra7xx_rng_hwmod_class,
2951 .flags = HWMOD_SWSUP_SIDLE,
2952 .clkdm_name = "l4sec_clkdm",
2953 .prcm = {
2954 .omap4 = {
2955 .clkctrl_offs = DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET,
2956 .context_offs = DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET,
2957 .modulemode = MODULEMODE_HWCTRL,
2958 },
2959 },
2960 };
2962 /*
2963 * 'usb_otg_ss' class
2964 *
2965 */
2967 static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
2968 .rev_offs = 0x0000,
2969 .sysc_offs = 0x0010,
2970 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
2971 SYSC_HAS_SIDLEMODE),
2972 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2973 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2974 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2975 .sysc_fields = &omap_hwmod_sysc_type2,
2976 };
2978 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
2979 .name = "usb_otg_ss",
2980 .sysc = &dra7xx_usb_otg_ss_sysc,
2981 };
2983 /* usb_otg_ss1 */
2984 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
2985 { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
2986 };
2988 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
2989 .name = "usb_otg_ss1",
2990 .class = &dra7xx_usb_otg_ss_hwmod_class,
2991 .clkdm_name = "l3init_clkdm",
2992 .main_clk = "dpll_core_h13x2_ck",
2993 .prcm = {
2994 .omap4 = {
2995 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
2996 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
2997 .modulemode = MODULEMODE_HWCTRL,
2998 },
2999 },
3000 .opt_clks = usb_otg_ss1_opt_clks,
3001 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
3002 };
3004 /* usb_otg_ss2 */
3005 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
3006 { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
3007 };
3009 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
3010 .name = "usb_otg_ss2",
3011 .class = &dra7xx_usb_otg_ss_hwmod_class,
3012 .clkdm_name = "l3init_clkdm",
3013 .main_clk = "dpll_core_h13x2_ck",
3014 .prcm = {
3015 .omap4 = {
3016 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
3017 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
3018 .modulemode = MODULEMODE_HWCTRL,
3019 },
3020 },
3021 .opt_clks = usb_otg_ss2_opt_clks,
3022 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
3023 };
3025 /* usb_otg_ss3 */
3026 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
3027 .name = "usb_otg_ss3",
3028 .class = &dra7xx_usb_otg_ss_hwmod_class,
3029 .clkdm_name = "l3init_clkdm",
3030 .main_clk = "dpll_core_h13x2_ck",
3031 .prcm = {
3032 .omap4 = {
3033 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
3034 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
3035 .modulemode = MODULEMODE_HWCTRL,
3036 },
3037 },
3038 };
3040 /* usb_otg_ss4 */
3041 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
3042 .name = "usb_otg_ss4",
3043 .class = &dra7xx_usb_otg_ss_hwmod_class,
3044 .clkdm_name = "l3init_clkdm",
3045 .main_clk = "dpll_core_h13x2_ck",
3046 .prcm = {
3047 .omap4 = {
3048 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
3049 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
3050 .modulemode = MODULEMODE_HWCTRL,
3051 },
3052 },
3053 };
3055 /*
3056 * 'vcp' class
3057 *
3058 */
3060 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
3061 .name = "vcp",
3062 };
3064 /* vcp1 */
3065 static struct omap_hwmod dra7xx_vcp1_hwmod = {
3066 .name = "vcp1",
3067 .class = &dra7xx_vcp_hwmod_class,
3068 .clkdm_name = "l3main1_clkdm",
3069 .main_clk = "l3_iclk_div",
3070 .prcm = {
3071 .omap4 = {
3072 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
3073 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
3074 },
3075 },
3076 };
3078 /* vcp2 */
3079 static struct omap_hwmod dra7xx_vcp2_hwmod = {
3080 .name = "vcp2",
3081 .class = &dra7xx_vcp_hwmod_class,
3082 .clkdm_name = "l3main1_clkdm",
3083 .main_clk = "l3_iclk_div",
3084 .prcm = {
3085 .omap4 = {
3086 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
3087 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
3088 },
3089 },
3090 };
3092 /*
3093 * 'wd_timer' class
3094 *
3095 */
3097 static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
3098 .rev_offs = 0x0000,
3099 .sysc_offs = 0x0010,
3100 .syss_offs = 0x0014,
3101 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3102 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3103 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3104 SIDLE_SMART_WKUP),
3105 .sysc_fields = &omap_hwmod_sysc_type1,
3106 };
3108 static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
3109 .name = "wd_timer",
3110 .sysc = &dra7xx_wd_timer_sysc,
3111 .pre_shutdown = &omap2_wd_timer_disable,
3112 .reset = &omap2_wd_timer_reset,
3113 };
3115 /* wd_timer2 */
3116 static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
3117 .name = "wd_timer2",
3118 .class = &dra7xx_wd_timer_hwmod_class,
3119 .clkdm_name = "wkupaon_clkdm",
3120 .main_clk = "sys_32k_ck",
3121 .prcm = {
3122 .omap4 = {
3123 .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
3124 .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
3125 .modulemode = MODULEMODE_SWCTRL,
3126 },
3127 },
3128 };
3131 /*
3132 * Interfaces
3133 */
3135 /* l3_main_2 -> l3_instr */
3136 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
3137 .master = &dra7xx_l3_main_2_hwmod,
3138 .slave = &dra7xx_l3_instr_hwmod,
3139 .clk = "l3_iclk_div",
3140 .user = OCP_USER_MPU | OCP_USER_SDMA,
3141 };
3143 /* l4_cfg -> l3_main_1 */
3144 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
3145 .master = &dra7xx_l4_cfg_hwmod,
3146 .slave = &dra7xx_l3_main_1_hwmod,
3147 .clk = "l3_iclk_div",
3148 .user = OCP_USER_MPU | OCP_USER_SDMA,
3149 };
3151 /*
3152 * Interfaces
3153 */
3155 static struct omap_hwmod_addr_space dra7xx_dmm_addrs[] = {
3156 {
3157 .pa_start = 0x4e000000,
3158 .pa_end = 0x4e0007ff,
3159 .flags = ADDR_TYPE_RT
3160 },
3161 { }
3162 };
3164 /* l3_main_1 -> dmm */
3165 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
3166 .master = &dra7xx_l3_main_1_hwmod,
3167 .slave = &dra7xx_dmm_hwmod,
3168 .clk = "l3_iclk_div",
3169 .addr = dra7xx_dmm_addrs,
3170 .user = OCP_USER_SDMA,
3171 };
3173 /* dmm -> emif_ocp_fw */
3174 static struct omap_hwmod_ocp_if dra7xx_dmm__emif_ocp_fw = {
3175 .master = &dra7xx_dmm_hwmod,
3176 .slave = &dra7xx_emif_ocp_fw_hwmod,
3177 .clk = "l3_iclk_div",
3178 .user = OCP_USER_MPU | OCP_USER_SDMA,
3179 };
3181 /* mpu -> l3_main_1 */
3182 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
3183 .master = &dra7xx_mpu_hwmod,
3184 .slave = &dra7xx_l3_main_1_hwmod,
3185 .clk = "l3_iclk_div",
3186 .user = OCP_USER_MPU,
3187 };
3189 /* l3_main_1 -> l3_main_2 */
3190 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
3191 .master = &dra7xx_l3_main_1_hwmod,
3192 .slave = &dra7xx_l3_main_2_hwmod,
3193 .clk = "l3_iclk_div",
3194 .user = OCP_USER_MPU,
3195 };
3197 /* l4_cfg -> l3_main_2 */
3198 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
3199 .master = &dra7xx_l4_cfg_hwmod,
3200 .slave = &dra7xx_l3_main_2_hwmod,
3201 .clk = "l3_iclk_div",
3202 .user = OCP_USER_MPU | OCP_USER_SDMA,
3203 };
3205 /* l3_main_1 -> l4_cfg */
3206 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
3207 .master = &dra7xx_l3_main_1_hwmod,
3208 .slave = &dra7xx_l4_cfg_hwmod,
3209 .clk = "l3_iclk_div",
3210 .user = OCP_USER_MPU | OCP_USER_SDMA,
3211 };
3213 /* l3_main_1 -> mmu0_dsp1 */
3214 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu0_dsp1 = {
3215 .master = &dra7xx_l3_main_1_hwmod,
3216 .slave = &dra7xx_mmu0_dsp1_hwmod,
3217 .clk = "l3_iclk_div",
3218 .user = OCP_USER_MPU | OCP_USER_SDMA,
3219 };
3221 /* l3_main_1 -> mmu1_dsp1 */
3222 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu1_dsp1 = {
3223 .master = &dra7xx_l3_main_1_hwmod,
3224 .slave = &dra7xx_mmu1_dsp1_hwmod,
3225 .clk = "l3_iclk_div",
3226 .user = OCP_USER_MPU | OCP_USER_SDMA,
3227 };
3229 /* l3_main_1 -> mmu0_dsp2 */
3230 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu0_dsp2 = {
3231 .master = &dra7xx_l3_main_1_hwmod,
3232 .slave = &dra7xx_mmu0_dsp2_hwmod,
3233 .clk = "l3_iclk_div",
3234 .user = OCP_USER_MPU | OCP_USER_SDMA,
3235 };
3237 /* l3_main_1 -> mmu1_dsp2 */
3238 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu1_dsp2 = {
3239 .master = &dra7xx_l3_main_1_hwmod,
3240 .slave = &dra7xx_mmu1_dsp2_hwmod,
3241 .clk = "l3_iclk_div",
3242 .user = OCP_USER_MPU | OCP_USER_SDMA,
3243 };
3245 /* l3_main_1 -> mmu_ipu1 */
3246 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu_ipu1 = {
3247 .master = &dra7xx_l3_main_1_hwmod,
3248 .slave = &dra7xx_mmu_ipu1_hwmod,
3249 .clk = "l3_iclk_div",
3250 .user = OCP_USER_MPU | OCP_USER_SDMA,
3251 };
3253 /* l3_main_1 -> mmu_ipu2 */
3254 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu_ipu2 = {
3255 .master = &dra7xx_l3_main_1_hwmod,
3256 .slave = &dra7xx_mmu_ipu2_hwmod,
3257 .clk = "l3_iclk_div",
3258 .user = OCP_USER_MPU | OCP_USER_SDMA,
3259 };
3261 /* l3_main_1 -> l4_per1 */
3262 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
3263 .master = &dra7xx_l3_main_1_hwmod,
3264 .slave = &dra7xx_l4_per1_hwmod,
3265 .clk = "l3_iclk_div",
3266 .user = OCP_USER_MPU | OCP_USER_SDMA,
3267 };
3269 /* l3_main_1 -> l4_per2 */
3270 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
3271 .master = &dra7xx_l3_main_1_hwmod,
3272 .slave = &dra7xx_l4_per2_hwmod,
3273 .clk = "l3_iclk_div",
3274 .user = OCP_USER_MPU | OCP_USER_SDMA,
3275 };
3277 /* l3_main_1 -> l4_per3 */
3278 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
3279 .master = &dra7xx_l3_main_1_hwmod,
3280 .slave = &dra7xx_l4_per3_hwmod,
3281 .clk = "l3_iclk_div",
3282 .user = OCP_USER_MPU | OCP_USER_SDMA,
3283 };
3285 /* l3_main_1 -> l4_wkup */
3286 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
3287 .master = &dra7xx_l3_main_1_hwmod,
3288 .slave = &dra7xx_l4_wkup_hwmod,
3289 .clk = "wkupaon_iclk_mux",
3290 .user = OCP_USER_MPU | OCP_USER_SDMA,
3291 };
3293 /* l4_per2 -> atl */
3294 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
3295 .master = &dra7xx_l4_per2_hwmod,
3296 .slave = &dra7xx_atl_hwmod,
3297 .clk = "l3_iclk_div",
3298 .user = OCP_USER_MPU | OCP_USER_SDMA,
3299 };
3301 /* l3_main_1 -> bb2d */
3302 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
3303 .master = &dra7xx_l3_main_1_hwmod,
3304 .slave = &dra7xx_bb2d_hwmod,
3305 .clk = "l3_iclk_div",
3306 .user = OCP_USER_MPU | OCP_USER_SDMA,
3307 };
3309 /* l4_wkup -> counter_32k */
3310 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
3311 .master = &dra7xx_l4_wkup_hwmod,
3312 .slave = &dra7xx_counter_32k_hwmod,
3313 .clk = "wkupaon_iclk_mux",
3314 .user = OCP_USER_MPU | OCP_USER_SDMA,
3315 };
3317 /* l4_wkup -> ctrl_module_wkup */
3318 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
3319 .master = &dra7xx_l4_wkup_hwmod,
3320 .slave = &dra7xx_ctrl_module_wkup_hwmod,
3321 .clk = "wkupaon_iclk_mux",
3322 .user = OCP_USER_MPU | OCP_USER_SDMA,
3323 };
3325 static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
3326 .master = &dra7xx_l4_per2_hwmod,
3327 .slave = &dra7xx_gmac_hwmod,
3328 .clk = "dpll_gmac_ck",
3329 .user = OCP_USER_MPU,
3330 };
3332 static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
3333 .master = &dra7xx_gmac_hwmod,
3334 .slave = &dra7xx_mdio_hwmod,
3335 .user = OCP_USER_MPU,
3336 };
3338 /* l4_wkup -> dcan1 */
3339 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
3340 .master = &dra7xx_l4_wkup_hwmod,
3341 .slave = &dra7xx_dcan1_hwmod,
3342 .clk = "wkupaon_iclk_mux",
3343 .user = OCP_USER_MPU | OCP_USER_SDMA,
3344 };
3346 /* l4_per2 -> dcan2 */
3347 static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
3348 .master = &dra7xx_l4_per2_hwmod,
3349 .slave = &dra7xx_dcan2_hwmod,
3350 .clk = "l3_iclk_div",
3351 .user = OCP_USER_MPU | OCP_USER_SDMA,
3352 };
3354 static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
3355 {
3356 .pa_start = 0x4a056000,
3357 .pa_end = 0x4a056fff,
3358 .flags = ADDR_TYPE_RT
3359 },
3360 { }
3361 };
3363 /* l4_cfg -> dma_system */
3364 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
3365 .master = &dra7xx_l4_cfg_hwmod,
3366 .slave = &dra7xx_dma_system_hwmod,
3367 .clk = "l3_iclk_div",
3368 .addr = dra7xx_dma_system_addrs,
3369 .user = OCP_USER_MPU | OCP_USER_SDMA,
3370 };
3372 /* dsp1 -> l3_main_1 */
3373 static struct omap_hwmod_ocp_if dra7xx_dsp1__l3_main_1 = {
3374 .master = &dra7xx_dsp1_hwmod,
3375 .slave = &dra7xx_l3_main_1_hwmod,
3376 .clk = "l3_iclk_div",
3377 .user = OCP_USER_MPU | OCP_USER_SDMA,
3378 };
3380 /* dsp2 -> l3_main_1 */
3381 static struct omap_hwmod_ocp_if dra7xx_dsp2__l3_main_1 = {
3382 .master = &dra7xx_dsp2_hwmod,
3383 .slave = &dra7xx_l3_main_1_hwmod,
3384 .clk = "l3_iclk_div",
3385 .user = OCP_USER_MPU | OCP_USER_SDMA,
3386 };
3388 static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
3389 {
3390 .name = "family",
3391 .pa_start = 0x58000000,
3392 .pa_end = 0x5800007f,
3393 .flags = ADDR_TYPE_RT
3394 },
3395 };
3397 /* l3_main_1 -> dss */
3398 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
3399 .master = &dra7xx_l3_main_1_hwmod,
3400 .slave = &dra7xx_dss_hwmod,
3401 .clk = "l3_iclk_div",
3402 .addr = dra7xx_dss_addrs,
3403 .user = OCP_USER_MPU | OCP_USER_SDMA,
3404 };
3406 static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = {
3407 {
3408 .name = "dispc",
3409 .pa_start = 0x58001000,
3410 .pa_end = 0x58001fff,
3411 .flags = ADDR_TYPE_RT
3412 },
3413 };
3415 /* l3_main_1 -> dispc */
3416 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
3417 .master = &dra7xx_l3_main_1_hwmod,
3418 .slave = &dra7xx_dss_dispc_hwmod,
3419 .clk = "l3_iclk_div",
3420 .addr = dra7xx_dss_dispc_addrs,
3421 .user = OCP_USER_MPU | OCP_USER_SDMA,
3422 };
3424 static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = {
3425 {
3426 .name = "hdmi_wp",
3427 .pa_start = 0x58040000,
3428 .pa_end = 0x580400ff,
3429 .flags = ADDR_TYPE_RT
3430 },
3431 { }
3432 };
3434 /* l3_main_1 -> dispc */
3435 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
3436 .master = &dra7xx_l3_main_1_hwmod,
3437 .slave = &dra7xx_dss_hdmi_hwmod,
3438 .clk = "l3_iclk_div",
3439 .addr = dra7xx_dss_hdmi_addrs,
3440 .user = OCP_USER_MPU | OCP_USER_SDMA,
3441 };
3443 /* l3_main_1 -> aes1 */
3444 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes1 = {
3445 .master = &dra7xx_l3_main_1_hwmod,
3446 .slave = &dra7xx_aes1_hwmod,
3447 .clk = "l3_iclk_div",
3448 .user = OCP_USER_MPU | OCP_USER_SDMA,
3449 };
3451 /* l3_main_1 -> aes2 */
3452 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes2 = {
3453 .master = &dra7xx_l3_main_1_hwmod,
3454 .slave = &dra7xx_aes2_hwmod,
3455 .clk = "l3_iclk_div",
3456 .user = OCP_USER_MPU | OCP_USER_SDMA,
3457 };
3459 /* l3_main_1 -> sha0 */
3460 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__sha0 = {
3461 .master = &dra7xx_l3_main_1_hwmod,
3462 .slave = &dra7xx_sha0_hwmod,
3463 .clk = "l3_iclk_div",
3464 .user = OCP_USER_MPU | OCP_USER_SDMA,
3465 };
3467 /* l4_per2 -> mcasp3 */
3468 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = {
3469 .master = &dra7xx_l4_per2_hwmod,
3470 .slave = &dra7xx_mcasp3_hwmod,
3471 .clk = "l3_iclk_div",
3472 .user = OCP_USER_MPU | OCP_USER_SDMA,
3473 };
3475 /* l4_per2 -> mcasp8 */
3476 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = {
3477 .master = &dra7xx_l4_per2_hwmod,
3478 .slave = &dra7xx_mcasp8_hwmod,
3479 .clk = "l3_iclk_div",
3480 .user = OCP_USER_MPU | OCP_USER_SDMA,
3481 };
3483 static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = {
3484 {
3485 .pa_start = 0x48078000,
3486 .pa_end = 0x48078fff,
3487 .flags = ADDR_TYPE_RT
3488 },
3489 { }
3490 };
3492 /* l4_per1 -> elm */
3493 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
3494 .master = &dra7xx_l4_per1_hwmod,
3495 .slave = &dra7xx_elm_hwmod,
3496 .clk = "l3_iclk_div",
3497 .addr = dra7xx_elm_addrs,
3498 .user = OCP_USER_MPU | OCP_USER_SDMA,
3499 };
3501 /* l4_wkup -> gpio1 */
3502 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
3503 .master = &dra7xx_l4_wkup_hwmod,
3504 .slave = &dra7xx_gpio1_hwmod,
3505 .clk = "wkupaon_iclk_mux",
3506 .user = OCP_USER_MPU | OCP_USER_SDMA,
3507 };
3509 /* l4_per1 -> gpio2 */
3510 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
3511 .master = &dra7xx_l4_per1_hwmod,
3512 .slave = &dra7xx_gpio2_hwmod,
3513 .clk = "l3_iclk_div",
3514 .user = OCP_USER_MPU | OCP_USER_SDMA,
3515 };
3517 /* l4_per1 -> gpio3 */
3518 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
3519 .master = &dra7xx_l4_per1_hwmod,
3520 .slave = &dra7xx_gpio3_hwmod,
3521 .clk = "l3_iclk_div",
3522 .user = OCP_USER_MPU | OCP_USER_SDMA,
3523 };
3525 /* l4_per1 -> gpio4 */
3526 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
3527 .master = &dra7xx_l4_per1_hwmod,
3528 .slave = &dra7xx_gpio4_hwmod,
3529 .clk = "l3_iclk_div",
3530 .user = OCP_USER_MPU | OCP_USER_SDMA,
3531 };
3533 /* l4_per1 -> gpio5 */
3534 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
3535 .master = &dra7xx_l4_per1_hwmod,
3536 .slave = &dra7xx_gpio5_hwmod,
3537 .clk = "l3_iclk_div",
3538 .user = OCP_USER_MPU | OCP_USER_SDMA,
3539 };
3541 /* l4_per1 -> gpio6 */
3542 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
3543 .master = &dra7xx_l4_per1_hwmod,
3544 .slave = &dra7xx_gpio6_hwmod,
3545 .clk = "l3_iclk_div",
3546 .user = OCP_USER_MPU | OCP_USER_SDMA,
3547 };
3549 struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss0 = {
3550 .master = &dra7xx_l4_per2_hwmod,
3551 .slave = &dra7xx_epwmss0_hwmod,
3552 .clk = "l4_root_clk_div",
3553 .user = OCP_USER_MPU,
3554 };
3556 struct omap_hwmod_ocp_if dra7xx_epwmss0__ecap0 = {
3557 .master = &dra7xx_epwmss0_hwmod,
3558 .slave = &dra7xx_ecap0_hwmod,
3559 .clk = "l4_root_clk_div",
3560 .user = OCP_USER_MPU,
3561 };
3563 struct omap_hwmod_ocp_if dra7xx_epwmss0__eqep0 = {
3564 .master = &dra7xx_epwmss0_hwmod,
3565 .slave = &dra7xx_eqep0_hwmod,
3566 .clk = "l4_root_clk_div",
3567 .user = OCP_USER_MPU,
3568 };
3570 struct omap_hwmod_ocp_if dra7xx_epwmss0__ehrpwm0 = {
3571 .master = &dra7xx_epwmss0_hwmod,
3572 .slave = &dra7xx_ehrpwm0_hwmod,
3573 .clk = "l4_root_clk_div",
3574 .user = OCP_USER_MPU,
3575 };
3577 struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss1 = {
3578 .master = &dra7xx_l4_per2_hwmod,
3579 .slave = &dra7xx_epwmss1_hwmod,
3580 .clk = "l4_root_clk_div",
3581 .user = OCP_USER_MPU,
3582 };
3584 struct omap_hwmod_ocp_if dra7xx_epwmss1__ecap1 = {
3585 .master = &dra7xx_epwmss1_hwmod,
3586 .slave = &dra7xx_ecap1_hwmod,
3587 .clk = "l4_root_clk_div",
3588 .user = OCP_USER_MPU,
3589 };
3591 struct omap_hwmod_ocp_if dra7xx_epwmss1__eqep1 = {
3592 .master = &dra7xx_epwmss1_hwmod,
3593 .slave = &dra7xx_eqep1_hwmod,
3594 .clk = "l4_root_clk_div",
3595 .user = OCP_USER_MPU,
3596 };
3598 struct omap_hwmod_ocp_if dra7xx_epwmss1__ehrpwm1 = {
3599 .master = &dra7xx_epwmss1_hwmod,
3600 .slave = &dra7xx_ehrpwm1_hwmod,
3601 .clk = "l4_root_clk_div",
3602 .user = OCP_USER_MPU,
3603 };
3605 struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss2 = {
3606 .master = &dra7xx_l4_per2_hwmod,
3607 .slave = &dra7xx_epwmss2_hwmod,
3608 .clk = "l4_root_clk_div",
3609 .user = OCP_USER_MPU,
3610 };
3612 struct omap_hwmod_ocp_if dra7xx_epwmss2__ecap2 = {
3613 .master = &dra7xx_epwmss2_hwmod,
3614 .slave = &dra7xx_ecap2_hwmod,
3615 .clk = "l4_root_clk_div",
3616 .user = OCP_USER_MPU,
3617 };
3619 struct omap_hwmod_ocp_if dra7xx_epwmss2__eqep2 = {
3620 .master = &dra7xx_epwmss2_hwmod,
3621 .slave = &dra7xx_eqep2_hwmod,
3622 .clk = "l4_root_clk_div",
3623 .user = OCP_USER_MPU,
3624 };
3626 struct omap_hwmod_ocp_if dra7xx_epwmss2__ehrpwm2 = {
3627 .master = &dra7xx_epwmss2_hwmod,
3628 .slave = &dra7xx_ehrpwm2_hwmod,
3629 .clk = "l4_root_clk_div",
3630 .user = OCP_USER_MPU,
3631 };
3633 /* l4_per1 -> gpio7 */
3634 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
3635 .master = &dra7xx_l4_per1_hwmod,
3636 .slave = &dra7xx_gpio7_hwmod,
3637 .clk = "l3_iclk_div",
3638 .user = OCP_USER_MPU | OCP_USER_SDMA,
3639 };
3641 /* l4_per1 -> gpio8 */
3642 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
3643 .master = &dra7xx_l4_per1_hwmod,
3644 .slave = &dra7xx_gpio8_hwmod,
3645 .clk = "l3_iclk_div",
3646 .user = OCP_USER_MPU | OCP_USER_SDMA,
3647 };
3649 static struct omap_hwmod_addr_space dra7xx_gpmc_addrs[] = {
3650 {
3651 .pa_start = 0x50000000,
3652 .pa_end = 0x500003ff,
3653 .flags = ADDR_TYPE_RT
3654 },
3655 { }
3656 };
3658 /* l3_main_1 -> gpmc */
3659 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
3660 .master = &dra7xx_l3_main_1_hwmod,
3661 .slave = &dra7xx_gpmc_hwmod,
3662 .clk = "l3_iclk_div",
3663 .addr = dra7xx_gpmc_addrs,
3664 .user = OCP_USER_MPU | OCP_USER_SDMA,
3665 };
3667 static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
3668 {
3669 .pa_start = 0x480b2000,
3670 .pa_end = 0x480b201f,
3671 .flags = ADDR_TYPE_RT
3672 },
3673 { }
3674 };
3676 /* l4_per1 -> hdq1w */
3677 static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
3678 .master = &dra7xx_l4_per1_hwmod,
3679 .slave = &dra7xx_hdq1w_hwmod,
3680 .clk = "l3_iclk_div",
3681 .addr = dra7xx_hdq1w_addrs,
3682 .user = OCP_USER_MPU | OCP_USER_SDMA,
3683 };
3685 /* l4_per1 -> i2c1 */
3686 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
3687 .master = &dra7xx_l4_per1_hwmod,
3688 .slave = &dra7xx_i2c1_hwmod,
3689 .clk = "l3_iclk_div",
3690 .user = OCP_USER_MPU | OCP_USER_SDMA,
3691 };
3693 /* l4_per1 -> i2c2 */
3694 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
3695 .master = &dra7xx_l4_per1_hwmod,
3696 .slave = &dra7xx_i2c2_hwmod,
3697 .clk = "l3_iclk_div",
3698 .user = OCP_USER_MPU | OCP_USER_SDMA,
3699 };
3701 /* l4_per1 -> i2c3 */
3702 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
3703 .master = &dra7xx_l4_per1_hwmod,
3704 .slave = &dra7xx_i2c3_hwmod,
3705 .clk = "l3_iclk_div",
3706 .user = OCP_USER_MPU | OCP_USER_SDMA,
3707 };
3709 /* l4_per1 -> i2c4 */
3710 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
3711 .master = &dra7xx_l4_per1_hwmod,
3712 .slave = &dra7xx_i2c4_hwmod,
3713 .clk = "l3_iclk_div",
3714 .user = OCP_USER_MPU | OCP_USER_SDMA,
3715 };
3717 /* l4_per1 -> i2c5 */
3718 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
3719 .master = &dra7xx_l4_per1_hwmod,
3720 .slave = &dra7xx_i2c5_hwmod,
3721 .clk = "l3_iclk_div",
3722 .user = OCP_USER_MPU | OCP_USER_SDMA,
3723 };
3725 /* ipu1 -> l3_main_1 */
3726 static struct omap_hwmod_ocp_if dra7xx_ipu1__l3_main_1 = {
3727 .master = &dra7xx_ipu1_hwmod,
3728 .slave = &dra7xx_l3_main_1_hwmod,
3729 .clk = "l3_iclk_div",
3730 .user = OCP_USER_MPU | OCP_USER_SDMA,
3731 };
3733 /* ipu2 -> l3_main_1 */
3734 static struct omap_hwmod_ocp_if dra7xx_ipu2__l3_main_1 = {
3735 .master = &dra7xx_ipu2_hwmod,
3736 .slave = &dra7xx_l3_main_1_hwmod,
3737 .clk = "l3_iclk_div",
3738 .user = OCP_USER_MPU | OCP_USER_SDMA,
3739 };
3741 /* l4_cfg -> mailbox1 */
3742 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
3743 .master = &dra7xx_l4_cfg_hwmod,
3744 .slave = &dra7xx_mailbox1_hwmod,
3745 .clk = "l3_iclk_div",
3746 .user = OCP_USER_MPU | OCP_USER_SDMA,
3747 };
3749 /* l4_per3 -> mailbox2 */
3750 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
3751 .master = &dra7xx_l4_per3_hwmod,
3752 .slave = &dra7xx_mailbox2_hwmod,
3753 .clk = "l3_iclk_div",
3754 .user = OCP_USER_MPU | OCP_USER_SDMA,
3755 };
3757 /* l4_per3 -> mailbox3 */
3758 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
3759 .master = &dra7xx_l4_per3_hwmod,
3760 .slave = &dra7xx_mailbox3_hwmod,
3761 .clk = "l3_iclk_div",
3762 .user = OCP_USER_MPU | OCP_USER_SDMA,
3763 };
3765 /* l4_per3 -> mailbox4 */
3766 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
3767 .master = &dra7xx_l4_per3_hwmod,
3768 .slave = &dra7xx_mailbox4_hwmod,
3769 .clk = "l3_iclk_div",
3770 .user = OCP_USER_MPU | OCP_USER_SDMA,
3771 };
3773 /* l4_per3 -> mailbox5 */
3774 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
3775 .master = &dra7xx_l4_per3_hwmod,
3776 .slave = &dra7xx_mailbox5_hwmod,
3777 .clk = "l3_iclk_div",
3778 .user = OCP_USER_MPU | OCP_USER_SDMA,
3779 };
3781 /* l4_per3 -> mailbox6 */
3782 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
3783 .master = &dra7xx_l4_per3_hwmod,
3784 .slave = &dra7xx_mailbox6_hwmod,
3785 .clk = "l3_iclk_div",
3786 .user = OCP_USER_MPU | OCP_USER_SDMA,
3787 };
3789 /* l4_per3 -> mailbox7 */
3790 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
3791 .master = &dra7xx_l4_per3_hwmod,
3792 .slave = &dra7xx_mailbox7_hwmod,
3793 .clk = "l3_iclk_div",
3794 .user = OCP_USER_MPU | OCP_USER_SDMA,
3795 };
3797 /* l4_per3 -> mailbox8 */
3798 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
3799 .master = &dra7xx_l4_per3_hwmod,
3800 .slave = &dra7xx_mailbox8_hwmod,
3801 .clk = "l3_iclk_div",
3802 .user = OCP_USER_MPU | OCP_USER_SDMA,
3803 };
3805 /* l4_per3 -> mailbox9 */
3806 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
3807 .master = &dra7xx_l4_per3_hwmod,
3808 .slave = &dra7xx_mailbox9_hwmod,
3809 .clk = "l3_iclk_div",
3810 .user = OCP_USER_MPU | OCP_USER_SDMA,
3811 };
3813 /* l4_per3 -> mailbox10 */
3814 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
3815 .master = &dra7xx_l4_per3_hwmod,
3816 .slave = &dra7xx_mailbox10_hwmod,
3817 .clk = "l3_iclk_div",
3818 .user = OCP_USER_MPU | OCP_USER_SDMA,
3819 };
3821 /* l4_per3 -> mailbox11 */
3822 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
3823 .master = &dra7xx_l4_per3_hwmod,
3824 .slave = &dra7xx_mailbox11_hwmod,
3825 .clk = "l3_iclk_div",
3826 .user = OCP_USER_MPU | OCP_USER_SDMA,
3827 };
3829 /* l4_per3 -> mailbox12 */
3830 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
3831 .master = &dra7xx_l4_per3_hwmod,
3832 .slave = &dra7xx_mailbox12_hwmod,
3833 .clk = "l3_iclk_div",
3834 .user = OCP_USER_MPU | OCP_USER_SDMA,
3835 };
3837 /* l4_per3 -> mailbox13 */
3838 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
3839 .master = &dra7xx_l4_per3_hwmod,
3840 .slave = &dra7xx_mailbox13_hwmod,
3841 .clk = "l3_iclk_div",
3842 .user = OCP_USER_MPU | OCP_USER_SDMA,
3843 };
3845 /* l4_per1 -> mcspi1 */
3846 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
3847 .master = &dra7xx_l4_per1_hwmod,
3848 .slave = &dra7xx_mcspi1_hwmod,
3849 .clk = "l3_iclk_div",
3850 .user = OCP_USER_MPU | OCP_USER_SDMA,
3851 };
3853 /* l4_per1 -> mcspi2 */
3854 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
3855 .master = &dra7xx_l4_per1_hwmod,
3856 .slave = &dra7xx_mcspi2_hwmod,
3857 .clk = "l3_iclk_div",
3858 .user = OCP_USER_MPU | OCP_USER_SDMA,
3859 };
3861 /* l4_per1 -> mcspi3 */
3862 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
3863 .master = &dra7xx_l4_per1_hwmod,
3864 .slave = &dra7xx_mcspi3_hwmod,
3865 .clk = "l3_iclk_div",
3866 .user = OCP_USER_MPU | OCP_USER_SDMA,
3867 };
3869 /* l4_per1 -> mcspi4 */
3870 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
3871 .master = &dra7xx_l4_per1_hwmod,
3872 .slave = &dra7xx_mcspi4_hwmod,
3873 .clk = "l3_iclk_div",
3874 .user = OCP_USER_MPU | OCP_USER_SDMA,
3875 };
3877 /* l4_per1 -> mmc1 */
3878 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
3879 .master = &dra7xx_l4_per1_hwmod,
3880 .slave = &dra7xx_mmc1_hwmod,
3881 .clk = "l3_iclk_div",
3882 .user = OCP_USER_MPU | OCP_USER_SDMA,
3883 };
3885 /* l4_per1 -> mmc2 */
3886 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
3887 .master = &dra7xx_l4_per1_hwmod,
3888 .slave = &dra7xx_mmc2_hwmod,
3889 .clk = "l3_iclk_div",
3890 .user = OCP_USER_MPU | OCP_USER_SDMA,
3891 };
3893 /* l4_per1 -> mmc3 */
3894 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
3895 .master = &dra7xx_l4_per1_hwmod,
3896 .slave = &dra7xx_mmc3_hwmod,
3897 .clk = "l3_iclk_div",
3898 .user = OCP_USER_MPU | OCP_USER_SDMA,
3899 };
3901 /* l4_per1 -> mmc4 */
3902 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
3903 .master = &dra7xx_l4_per1_hwmod,
3904 .slave = &dra7xx_mmc4_hwmod,
3905 .clk = "l3_iclk_div",
3906 .user = OCP_USER_MPU | OCP_USER_SDMA,
3907 };
3909 /* l4_cfg -> mpu */
3910 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
3911 .master = &dra7xx_l4_cfg_hwmod,
3912 .slave = &dra7xx_mpu_hwmod,
3913 .clk = "l3_iclk_div",
3914 .user = OCP_USER_MPU | OCP_USER_SDMA,
3915 };
3917 /* l4_cfg -> ocp2scp1 */
3918 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
3919 .master = &dra7xx_l4_cfg_hwmod,
3920 .slave = &dra7xx_ocp2scp1_hwmod,
3921 .clk = "l4_root_clk_div",
3922 .user = OCP_USER_MPU | OCP_USER_SDMA,
3923 };
3925 /* l4_cfg -> ocp2scp3 */
3926 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
3927 .master = &dra7xx_l4_cfg_hwmod,
3928 .slave = &dra7xx_ocp2scp3_hwmod,
3929 .clk = "l4_root_clk_div",
3930 .user = OCP_USER_MPU | OCP_USER_SDMA,
3931 };
3933 /* l3_main_1 -> pcie1 */
3934 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
3935 .master = &dra7xx_l3_main_1_hwmod,
3936 .slave = &dra7xx_pciess1_hwmod,
3937 .clk = "l3_iclk_div",
3938 .user = OCP_USER_MPU | OCP_USER_SDMA,
3939 };
3941 /* l4_cfg -> pcie1 */
3942 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
3943 .master = &dra7xx_l4_cfg_hwmod,
3944 .slave = &dra7xx_pciess1_hwmod,
3945 .clk = "l4_root_clk_div",
3946 .user = OCP_USER_MPU | OCP_USER_SDMA,
3947 };
3949 /* l3_main_1 -> pcie2 */
3950 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
3951 .master = &dra7xx_l3_main_1_hwmod,
3952 .slave = &dra7xx_pciess2_hwmod,
3953 .clk = "l3_iclk_div",
3954 .user = OCP_USER_MPU | OCP_USER_SDMA,
3955 };
3957 /* l4_cfg -> pcie2 */
3958 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
3959 .master = &dra7xx_l4_cfg_hwmod,
3960 .slave = &dra7xx_pciess2_hwmod,
3961 .clk = "l4_root_clk_div",
3962 .user = OCP_USER_MPU | OCP_USER_SDMA,
3963 };
3965 /* l4_cfg -> pruss1 */
3966 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pruss1 = {
3967 .master = &dra7xx_l4_cfg_hwmod,
3968 .slave = &dra7xx_pruss1_hwmod,
3969 .clk = "dpll_gmac_h13x2_ck",
3970 .user = OCP_USER_MPU | OCP_USER_SDMA,
3971 };
3973 /* l4_cfg -> pruss2 */
3974 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pruss2 = {
3975 .master = &dra7xx_l4_cfg_hwmod,
3976 .slave = &dra7xx_pruss2_hwmod,
3977 .clk = "dpll_gmac_h13x2_ck",
3978 .user = OCP_USER_MPU | OCP_USER_SDMA,
3979 };
3981 static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
3982 {
3983 .pa_start = 0x4b300000,
3984 .pa_end = 0x4b30007f,
3985 .flags = ADDR_TYPE_RT
3986 },
3987 { }
3988 };
3990 /* l3_main_1 -> qspi */
3991 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
3992 .master = &dra7xx_l3_main_1_hwmod,
3993 .slave = &dra7xx_qspi_hwmod,
3994 .clk = "l3_iclk_div",
3995 .addr = dra7xx_qspi_addrs,
3996 .user = OCP_USER_MPU | OCP_USER_SDMA,
3997 };
3999 /* l4_per3 -> rtcss */
4000 static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
4001 .master = &dra7xx_l4_per3_hwmod,
4002 .slave = &dra7xx_rtcss_hwmod,
4003 .clk = "l4_root_clk_div",
4004 .user = OCP_USER_MPU | OCP_USER_SDMA,
4005 };
4007 static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
4008 {
4009 .name = "sysc",
4010 .pa_start = 0x4a141100,
4011 .pa_end = 0x4a141107,
4012 .flags = ADDR_TYPE_RT
4013 },
4014 { }
4015 };
4017 /* l4_cfg -> sata */
4018 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
4019 .master = &dra7xx_l4_cfg_hwmod,
4020 .slave = &dra7xx_sata_hwmod,
4021 .clk = "l3_iclk_div",
4022 .addr = dra7xx_sata_addrs,
4023 .user = OCP_USER_MPU | OCP_USER_SDMA,
4024 };
4026 static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
4027 {
4028 .pa_start = 0x4a0dd000,
4029 .pa_end = 0x4a0dd07f,
4030 .flags = ADDR_TYPE_RT
4031 },
4032 { }
4033 };
4035 /* l4_cfg -> smartreflex_core */
4036 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
4037 .master = &dra7xx_l4_cfg_hwmod,
4038 .slave = &dra7xx_smartreflex_core_hwmod,
4039 .clk = "l4_root_clk_div",
4040 .addr = dra7xx_smartreflex_core_addrs,
4041 .user = OCP_USER_MPU | OCP_USER_SDMA,
4042 };
4044 static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
4045 {
4046 .pa_start = 0x4a0d9000,
4047 .pa_end = 0x4a0d907f,
4048 .flags = ADDR_TYPE_RT
4049 },
4050 { }
4051 };
4053 /* l4_cfg -> smartreflex_mpu */
4054 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
4055 .master = &dra7xx_l4_cfg_hwmod,
4056 .slave = &dra7xx_smartreflex_mpu_hwmod,
4057 .clk = "l4_root_clk_div",
4058 .addr = dra7xx_smartreflex_mpu_addrs,
4059 .user = OCP_USER_MPU | OCP_USER_SDMA,
4060 };
4062 static struct omap_hwmod_addr_space dra7xx_spinlock_addrs[] = {
4063 {
4064 .pa_start = 0x4a0f6000,
4065 .pa_end = 0x4a0f6fff,
4066 .flags = ADDR_TYPE_RT
4067 },
4068 { }
4069 };
4071 /* l4_cfg -> spinlock */
4072 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
4073 .master = &dra7xx_l4_cfg_hwmod,
4074 .slave = &dra7xx_spinlock_hwmod,
4075 .clk = "l3_iclk_div",
4076 .addr = dra7xx_spinlock_addrs,
4077 .user = OCP_USER_MPU | OCP_USER_SDMA,
4078 };
4080 /* l4_wkup -> timer1 */
4081 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
4082 .master = &dra7xx_l4_wkup_hwmod,
4083 .slave = &dra7xx_timer1_hwmod,
4084 .clk = "wkupaon_iclk_mux",
4085 .user = OCP_USER_MPU | OCP_USER_SDMA,
4086 };
4088 /* l4_per1 -> timer2 */
4089 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
4090 .master = &dra7xx_l4_per1_hwmod,
4091 .slave = &dra7xx_timer2_hwmod,
4092 .clk = "l3_iclk_div",
4093 .user = OCP_USER_MPU | OCP_USER_SDMA,
4094 };
4096 /* l4_per1 -> timer3 */
4097 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
4098 .master = &dra7xx_l4_per1_hwmod,
4099 .slave = &dra7xx_timer3_hwmod,
4100 .clk = "l3_iclk_div",
4101 .user = OCP_USER_MPU | OCP_USER_SDMA,
4102 };
4104 /* l4_per1 -> timer4 */
4105 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
4106 .master = &dra7xx_l4_per1_hwmod,
4107 .slave = &dra7xx_timer4_hwmod,
4108 .clk = "l3_iclk_div",
4109 .user = OCP_USER_MPU | OCP_USER_SDMA,
4110 };
4112 /* l4_per3 -> timer5 */
4113 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
4114 .master = &dra7xx_l4_per3_hwmod,
4115 .slave = &dra7xx_timer5_hwmod,
4116 .clk = "l3_iclk_div",
4117 .user = OCP_USER_MPU | OCP_USER_SDMA,
4118 };
4120 /* l4_per3 -> timer6 */
4121 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
4122 .master = &dra7xx_l4_per3_hwmod,
4123 .slave = &dra7xx_timer6_hwmod,
4124 .clk = "l3_iclk_div",
4125 .user = OCP_USER_MPU | OCP_USER_SDMA,
4126 };
4128 /* l4_per3 -> timer7 */
4129 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
4130 .master = &dra7xx_l4_per3_hwmod,
4131 .slave = &dra7xx_timer7_hwmod,
4132 .clk = "l3_iclk_div",
4133 .user = OCP_USER_MPU | OCP_USER_SDMA,
4134 };
4136 /* l4_per3 -> timer8 */
4137 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
4138 .master = &dra7xx_l4_per3_hwmod,
4139 .slave = &dra7xx_timer8_hwmod,
4140 .clk = "l3_iclk_div",
4141 .user = OCP_USER_MPU | OCP_USER_SDMA,
4142 };
4144 /* l4_per1 -> timer9 */
4145 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
4146 .master = &dra7xx_l4_per1_hwmod,
4147 .slave = &dra7xx_timer9_hwmod,
4148 .clk = "l3_iclk_div",
4149 .user = OCP_USER_MPU | OCP_USER_SDMA,
4150 };
4152 /* l4_per1 -> timer10 */
4153 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
4154 .master = &dra7xx_l4_per1_hwmod,
4155 .slave = &dra7xx_timer10_hwmod,
4156 .clk = "l3_iclk_div",
4157 .user = OCP_USER_MPU | OCP_USER_SDMA,
4158 };
4160 /* l4_per1 -> timer11 */
4161 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
4162 .master = &dra7xx_l4_per1_hwmod,
4163 .slave = &dra7xx_timer11_hwmod,
4164 .clk = "l3_iclk_div",
4165 .user = OCP_USER_MPU | OCP_USER_SDMA,
4166 };
4168 /* l4_wkup -> timer12 */
4169 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer12 = {
4170 .master = &dra7xx_l4_wkup_hwmod,
4171 .slave = &dra7xx_timer12_hwmod,
4172 .clk = "wkupaon_iclk_mux",
4173 .user = OCP_USER_MPU | OCP_USER_SDMA,
4174 };
4176 /* l4_per3 -> timer13 */
4177 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
4178 .master = &dra7xx_l4_per3_hwmod,
4179 .slave = &dra7xx_timer13_hwmod,
4180 .clk = "l3_iclk_div",
4181 .user = OCP_USER_MPU | OCP_USER_SDMA,
4182 };
4184 /* l4_per3 -> timer14 */
4185 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
4186 .master = &dra7xx_l4_per3_hwmod,
4187 .slave = &dra7xx_timer14_hwmod,
4188 .clk = "l3_iclk_div",
4189 .user = OCP_USER_MPU | OCP_USER_SDMA,
4190 };
4192 /* l4_per3 -> timer15 */
4193 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
4194 .master = &dra7xx_l4_per3_hwmod,
4195 .slave = &dra7xx_timer15_hwmod,
4196 .clk = "l3_iclk_div",
4197 .user = OCP_USER_MPU | OCP_USER_SDMA,
4198 };
4200 /* l4_per3 -> timer16 */
4201 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
4202 .master = &dra7xx_l4_per3_hwmod,
4203 .slave = &dra7xx_timer16_hwmod,
4204 .clk = "l3_iclk_div",
4205 .user = OCP_USER_MPU | OCP_USER_SDMA,
4206 };
4208 /* l4_per1 -> uart1 */
4209 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
4210 .master = &dra7xx_l4_per1_hwmod,
4211 .slave = &dra7xx_uart1_hwmod,
4212 .clk = "l3_iclk_div",
4213 .user = OCP_USER_MPU | OCP_USER_SDMA,
4214 };
4216 /* l4_per1 -> uart2 */
4217 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
4218 .master = &dra7xx_l4_per1_hwmod,
4219 .slave = &dra7xx_uart2_hwmod,
4220 .clk = "l3_iclk_div",
4221 .user = OCP_USER_MPU | OCP_USER_SDMA,
4222 };
4224 /* l4_per1 -> uart3 */
4225 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
4226 .master = &dra7xx_l4_per1_hwmod,
4227 .slave = &dra7xx_uart3_hwmod,
4228 .clk = "l3_iclk_div",
4229 .user = OCP_USER_MPU | OCP_USER_SDMA,
4230 };
4232 /* l4_per1 -> uart4 */
4233 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
4234 .master = &dra7xx_l4_per1_hwmod,
4235 .slave = &dra7xx_uart4_hwmod,
4236 .clk = "l3_iclk_div",
4237 .user = OCP_USER_MPU | OCP_USER_SDMA,
4238 };
4240 /* l4_per1 -> uart5 */
4241 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
4242 .master = &dra7xx_l4_per1_hwmod,
4243 .slave = &dra7xx_uart5_hwmod,
4244 .clk = "l3_iclk_div",
4245 .user = OCP_USER_MPU | OCP_USER_SDMA,
4246 };
4248 /* l4_per1 -> uart6 */
4249 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
4250 .master = &dra7xx_l4_per1_hwmod,
4251 .slave = &dra7xx_uart6_hwmod,
4252 .clk = "l3_iclk_div",
4253 .user = OCP_USER_MPU | OCP_USER_SDMA,
4254 };
4256 /* l4_per2 -> uart7 */
4257 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
4258 .master = &dra7xx_l4_per2_hwmod,
4259 .slave = &dra7xx_uart7_hwmod,
4260 .clk = "l3_iclk_div",
4261 .user = OCP_USER_MPU | OCP_USER_SDMA,
4262 };
4264 /* l4_per2 -> uart8 */
4265 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
4266 .master = &dra7xx_l4_per2_hwmod,
4267 .slave = &dra7xx_uart8_hwmod,
4268 .clk = "l3_iclk_div",
4269 .user = OCP_USER_MPU | OCP_USER_SDMA,
4270 };
4272 /* l4_per2 -> uart9 */
4273 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
4274 .master = &dra7xx_l4_per2_hwmod,
4275 .slave = &dra7xx_uart9_hwmod,
4276 .clk = "l3_iclk_div",
4277 .user = OCP_USER_MPU | OCP_USER_SDMA,
4278 };
4280 /* l4_wkup -> uart10 */
4281 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
4282 .master = &dra7xx_l4_wkup_hwmod,
4283 .slave = &dra7xx_uart10_hwmod,
4284 .clk = "wkupaon_iclk_mux",
4285 .user = OCP_USER_MPU | OCP_USER_SDMA,
4286 };
4288 /* l4_per1 -> des */
4289 static struct omap_hwmod_ocp_if dra7xx_l4_per1__des = {
4290 .master = &dra7xx_l4_per1_hwmod,
4291 .slave = &dra7xx_des_hwmod,
4292 .clk = "l3_iclk_div",
4293 .user = OCP_USER_MPU | OCP_USER_SDMA,
4294 };
4296 /* l4_per1 -> rng */
4297 static struct omap_hwmod_ocp_if dra7xx_l4_per1__rng = {
4298 .master = &dra7xx_l4_per1_hwmod,
4299 .slave = &dra7xx_rng_hwmod,
4300 .user = OCP_USER_MPU,
4301 };
4303 /* l4_per3 -> usb_otg_ss1 */
4304 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
4305 .master = &dra7xx_l4_per3_hwmod,
4306 .slave = &dra7xx_usb_otg_ss1_hwmod,
4307 .clk = "dpll_core_h13x2_ck",
4308 .user = OCP_USER_MPU | OCP_USER_SDMA,
4309 };
4311 /* l4_per3 -> usb_otg_ss2 */
4312 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
4313 .master = &dra7xx_l4_per3_hwmod,
4314 .slave = &dra7xx_usb_otg_ss2_hwmod,
4315 .clk = "dpll_core_h13x2_ck",
4316 .user = OCP_USER_MPU | OCP_USER_SDMA,
4317 };
4319 /* l4_per3 -> usb_otg_ss3 */
4320 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
4321 .master = &dra7xx_l4_per3_hwmod,
4322 .slave = &dra7xx_usb_otg_ss3_hwmod,
4323 .clk = "dpll_core_h13x2_ck",
4324 .user = OCP_USER_MPU | OCP_USER_SDMA,
4325 };
4327 /* l4_per3 -> usb_otg_ss4 */
4328 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
4329 .master = &dra7xx_l4_per3_hwmod,
4330 .slave = &dra7xx_usb_otg_ss4_hwmod,
4331 .clk = "dpll_core_h13x2_ck",
4332 .user = OCP_USER_MPU | OCP_USER_SDMA,
4333 };
4335 /* l3_main_1 -> vcp1 */
4336 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
4337 .master = &dra7xx_l3_main_1_hwmod,
4338 .slave = &dra7xx_vcp1_hwmod,
4339 .clk = "l3_iclk_div",
4340 .user = OCP_USER_MPU | OCP_USER_SDMA,
4341 };
4343 /* l4_per2 -> vcp1 */
4344 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
4345 .master = &dra7xx_l4_per2_hwmod,
4346 .slave = &dra7xx_vcp1_hwmod,
4347 .clk = "l3_iclk_div",
4348 .user = OCP_USER_MPU | OCP_USER_SDMA,
4349 };
4351 /* l3_main_1 -> vcp2 */
4352 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
4353 .master = &dra7xx_l3_main_1_hwmod,
4354 .slave = &dra7xx_vcp2_hwmod,
4355 .clk = "l3_iclk_div",
4356 .user = OCP_USER_MPU | OCP_USER_SDMA,
4357 };
4359 /* l4_per2 -> vcp2 */
4360 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
4361 .master = &dra7xx_l4_per2_hwmod,
4362 .slave = &dra7xx_vcp2_hwmod,
4363 .clk = "l3_iclk_div",
4364 .user = OCP_USER_MPU | OCP_USER_SDMA,
4365 };
4367 /* l4_per3 -> vpe */
4368 static struct omap_hwmod_ocp_if dra7xx_l4_per3__vpe = {
4369 .master = &dra7xx_l4_per3_hwmod,
4370 .slave = &dra7xx_vpe_hwmod,
4371 .clk = "l3_iclk_div",
4372 .user = OCP_USER_MPU | OCP_USER_SDMA,
4373 };
4375 /* l4_per3 -> vip1 */
4376 static struct omap_hwmod_ocp_if dra7xx_l4_per3__vip1 = {
4377 .master = &dra7xx_l4_per3_hwmod,
4378 .slave = &dra7xx_vip1_hwmod,
4379 .clk = "l3_iclk_div",
4380 .user = OCP_USER_MPU | OCP_USER_SDMA,
4381 };
4383 /* l4_per3 -> vip2 */
4384 static struct omap_hwmod_ocp_if dra7xx_l4_per3__vip2 = {
4385 .master = &dra7xx_l4_per3_hwmod,
4386 .slave = &dra7xx_vip2_hwmod,
4387 .clk = "l3_iclk_div",
4388 .user = OCP_USER_MPU | OCP_USER_SDMA,
4389 };
4391 /* l4_per3 -> vip3 */
4392 static struct omap_hwmod_ocp_if dra7xx_l4_per3__vip3 = {
4393 .master = &dra7xx_l4_per3_hwmod,
4394 .slave = &dra7xx_vip3_hwmod,
4395 .clk = "l3_iclk_div",
4396 .user = OCP_USER_MPU | OCP_USER_SDMA,
4397 };
4399 /* l4_per3 -> cal */
4400 static struct omap_hwmod_ocp_if dra7xx_l4_per3__cal = {
4401 .master = &dra7xx_l4_per3_hwmod,
4402 .slave = &dra7xx_cal_hwmod,
4403 .clk = "l3_iclk_div",
4404 .user = OCP_USER_MPU | OCP_USER_SDMA,
4405 };
4407 /* l4_wkup -> wd_timer2 */
4408 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
4409 .master = &dra7xx_l4_wkup_hwmod,
4410 .slave = &dra7xx_wd_timer2_hwmod,
4411 .clk = "wkupaon_iclk_mux",
4412 .user = OCP_USER_MPU | OCP_USER_SDMA,
4413 };
4415 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
4416 &dra7xx_l3_main_1__dmm,
4417 &dra7xx_dmm__emif_ocp_fw,
4418 &dra7xx_l3_main_2__l3_instr,
4419 &dra7xx_l4_cfg__l3_main_1,
4420 &dra7xx_mpu__l3_main_1,
4421 &dra7xx_l3_main_1__l3_main_2,
4422 &dra7xx_l4_cfg__l3_main_2,
4423 &dra7xx_l3_main_1__l4_cfg,
4424 &dra7xx_l3_main_1__l4_per1,
4425 &dra7xx_l3_main_1__l4_per2,
4426 &dra7xx_l3_main_1__l4_per3,
4427 &dra7xx_l3_main_1__l4_wkup,
4428 &dra7xx_l4_per2__atl,
4429 &dra7xx_l3_main_1__bb2d,
4430 &dra7xx_l4_wkup__counter_32k,
4431 &dra7xx_l4_wkup__ctrl_module_wkup,
4432 &dra7xx_l4_wkup__dcan1,
4433 &dra7xx_l4_per2__dcan2,
4434 &dra7xx_l4_per2__cpgmac0,
4435 &dra7xx_gmac__mdio,
4436 &dra7xx_l4_cfg__dma_system,
4437 &dra7xx_l3_main_1__dss,
4438 &dra7xx_l3_main_1__dispc,
4439 &dra7xx_dsp1__l3_main_1,
4440 &dra7xx_l3_main_1__hdmi,
4441 &dra7xx_l3_main_1__aes1,
4442 &dra7xx_l3_main_1__aes2,
4443 &dra7xx_l3_main_1__sha0,
4444 &dra7xx_l4_per2__mcasp3,
4445 &dra7xx_l4_per2__mcasp8,
4446 &dra7xx_l4_per1__elm,
4447 &dra7xx_l4_wkup__gpio1,
4448 &dra7xx_l4_per1__gpio2,
4449 &dra7xx_l4_per1__gpio3,
4450 &dra7xx_l4_per1__gpio4,
4451 &dra7xx_l4_per1__gpio5,
4452 &dra7xx_l4_per1__gpio6,
4453 &dra7xx_l4_per1__gpio7,
4454 &dra7xx_l4_per1__gpio8,
4455 &dra7xx_l3_main_1__gpmc,
4456 &dra7xx_l4_per1__hdq1w,
4457 &dra7xx_l4_per1__i2c1,
4458 &dra7xx_l4_per1__i2c2,
4459 &dra7xx_l4_per1__i2c3,
4460 &dra7xx_l4_per1__i2c4,
4461 &dra7xx_l4_per1__i2c5,
4462 &dra7xx_ipu1__l3_main_1,
4463 &dra7xx_ipu2__l3_main_1,
4464 &dra7xx_l4_cfg__mailbox1,
4465 &dra7xx_l4_per3__mailbox2,
4466 &dra7xx_l4_per3__mailbox3,
4467 &dra7xx_l4_per3__mailbox4,
4468 &dra7xx_l4_per3__mailbox5,
4469 &dra7xx_l4_per3__mailbox6,
4470 &dra7xx_l4_per3__mailbox7,
4471 &dra7xx_l4_per3__mailbox8,
4472 &dra7xx_l4_per3__mailbox9,
4473 &dra7xx_l4_per3__mailbox10,
4474 &dra7xx_l4_per3__mailbox11,
4475 &dra7xx_l4_per3__mailbox12,
4476 &dra7xx_l4_per3__mailbox13,
4477 &dra7xx_l4_per1__mcspi1,
4478 &dra7xx_l4_per1__mcspi2,
4479 &dra7xx_l4_per1__mcspi3,
4480 &dra7xx_l4_per1__mcspi4,
4481 &dra7xx_l4_per1__mmc1,
4482 &dra7xx_l4_per1__mmc2,
4483 &dra7xx_l4_per1__mmc3,
4484 &dra7xx_l4_per1__mmc4,
4485 &dra7xx_l3_main_1__mmu0_dsp1,
4486 &dra7xx_l3_main_1__mmu1_dsp1,
4487 &dra7xx_l3_main_1__mmu_ipu1,
4488 &dra7xx_l3_main_1__mmu_ipu2,
4489 &dra7xx_l4_cfg__mpu,
4490 &dra7xx_l4_cfg__ocp2scp1,
4491 &dra7xx_l4_cfg__ocp2scp3,
4492 &dra7xx_l3_main_1__pciess1,
4493 &dra7xx_l4_cfg__pciess1,
4494 &dra7xx_l3_main_1__pciess2,
4495 &dra7xx_l4_cfg__pciess2,
4496 &dra7xx_l4_cfg__pruss1, /* AM57xx only */
4497 &dra7xx_l4_cfg__pruss2, /* AM57xx only */
4498 &dra7xx_l3_main_1__qspi,
4499 &dra7xx_l4_per3__rtcss,
4500 &dra7xx_l4_cfg__sata,
4501 &dra7xx_l4_cfg__smartreflex_core,
4502 &dra7xx_l4_cfg__smartreflex_mpu,
4503 &dra7xx_l4_cfg__spinlock,
4504 &dra7xx_l4_wkup__timer1,
4505 &dra7xx_l4_per1__timer2,
4506 &dra7xx_l4_per1__timer3,
4507 &dra7xx_l4_per1__timer4,
4508 &dra7xx_l4_per3__timer5,
4509 &dra7xx_l4_per3__timer6,
4510 &dra7xx_l4_per3__timer7,
4511 &dra7xx_l4_per3__timer8,
4512 &dra7xx_l4_per1__timer9,
4513 &dra7xx_l4_per1__timer10,
4514 &dra7xx_l4_per1__timer11,
4515 &dra7xx_l4_wkup__timer12,
4516 &dra7xx_l4_per3__timer13,
4517 &dra7xx_l4_per3__timer14,
4518 &dra7xx_l4_per3__timer15,
4519 &dra7xx_l4_per3__timer16,
4520 &dra7xx_l4_per1__uart1,
4521 &dra7xx_l4_per1__uart2,
4522 &dra7xx_l4_per1__uart3,
4523 &dra7xx_l4_per1__uart4,
4524 &dra7xx_l4_per1__uart5,
4525 &dra7xx_l4_per1__uart6,
4526 &dra7xx_l4_per2__uart7,
4527 &dra7xx_l4_per2__uart8,
4528 &dra7xx_l4_per2__uart9,
4529 &dra7xx_l4_wkup__uart10,
4530 &dra7xx_l4_per1__des,
4531 &dra7xx_l4_per1__rng,
4532 &dra7xx_l4_per3__usb_otg_ss1,
4533 &dra7xx_l4_per3__usb_otg_ss2,
4534 &dra7xx_l4_per3__usb_otg_ss3,
4535 &dra7xx_l3_main_1__vcp1,
4536 &dra7xx_l4_per2__vcp1,
4537 &dra7xx_l3_main_1__vcp2,
4538 &dra7xx_l4_per2__vcp2,
4539 &dra7xx_l4_per3__vpe,
4540 &dra7xx_l4_per3__vip1,
4541 &dra7xx_l4_wkup__wd_timer2,
4542 &dra7xx_l4_per2__epwmss0,
4543 &dra7xx_epwmss0__ecap0,
4544 &dra7xx_epwmss0__eqep0,
4545 &dra7xx_epwmss0__ehrpwm0,
4546 &dra7xx_l4_per2__epwmss1,
4547 &dra7xx_epwmss1__ecap1,
4548 &dra7xx_epwmss1__eqep1,
4549 &dra7xx_epwmss1__ehrpwm1,
4550 &dra7xx_l4_per2__epwmss2,
4551 &dra7xx_epwmss2__ecap2,
4552 &dra7xx_epwmss2__eqep2,
4553 &dra7xx_epwmss2__ehrpwm2,
4554 NULL,
4555 };
4557 static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
4558 &dra7xx_l4_per3__usb_otg_ss4,
4559 &dra7xx_l3_main_1__mmu0_dsp2,
4560 &dra7xx_l3_main_1__mmu1_dsp2,
4561 &dra7xx_dsp2__l3_main_1,
4562 &dra7xx_l4_per3__vip2,
4563 &dra7xx_l4_per3__vip3,
4564 NULL,
4565 };
4567 static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
4568 &dra7xx_l4_per3__cal,
4569 NULL,
4570 };
4572 int __init dra7xx_hwmod_init(void)
4573 {
4574 int ret;
4576 omap_hwmod_init();
4577 ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
4579 if (!ret && soc_is_dra74x())
4580 return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
4581 else if (!ret && soc_is_dra72x())
4582 return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
4584 return ret;
4585 }