1 /*
2 * Hardware modules present on the DRA7xx chips
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley
7 * Benoit Cousson
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
20 #include <linux/io.h>
21 #include <linux/platform_data/gpio-omap.h>
22 #include <linux/power/smartreflex.h>
23 #include <linux/i2c-omap.h>
25 #include <linux/omap-dma.h>
26 #include <linux/platform_data/spi-omap2-mcspi.h>
27 #include <linux/platform_data/asoc-ti-mcbsp.h>
28 #include <linux/platform_data/iommu-omap.h>
29 #include <plat/dmtimer.h>
31 #include "omap_hwmod.h"
32 #include "omap_hwmod_common_data.h"
33 #include "cm1_7xx.h"
34 #include "cm2_7xx.h"
35 #include "prm7xx.h"
36 #include "i2c.h"
37 #include "mmc.h"
38 #include "wd_timer.h"
39 #include "soc.h"
41 /* Base offset for all DRA7XX interrupts external to MPUSS */
42 #define DRA7XX_IRQ_GIC_START 32
44 /* Base offset for all DRA7XX dma requests */
45 #define DRA7XX_DMA_REQ_START 1
48 /*
49 * IP blocks
50 */
52 /*
53 * 'dmm' class
54 * instance(s): dmm
55 */
56 static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
57 .name = "dmm",
58 };
60 /* dmm */
61 static struct omap_hwmod dra7xx_dmm_hwmod = {
62 .name = "dmm",
63 .class = &dra7xx_dmm_hwmod_class,
64 .clkdm_name = "emif_clkdm",
65 .prcm = {
66 .omap4 = {
67 .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
68 .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
69 },
70 },
71 };
73 /*
74 * 'emif_ocp_fw' class
75 * instance(s): emif_ocp_fw
76 */
77 static struct omap_hwmod_class dra7xx_emif_ocp_fw_hwmod_class = {
78 .name = "emif_ocp_fw",
79 };
81 /* emif_ocp_fw */
82 static struct omap_hwmod dra7xx_emif_ocp_fw_hwmod = {
83 .name = "emif_ocp_fw",
84 .class = &dra7xx_emif_ocp_fw_hwmod_class,
85 .clkdm_name = "emif_clkdm",
86 .prcm = {
87 .omap4 = {
88 .clkctrl_offs = DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET,
89 .context_offs = DRA7XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET,
90 },
91 },
92 };
94 /*
95 * 'l3' class
96 * instance(s): l3_instr, l3_main_1, l3_main_2
97 */
98 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
99 .name = "l3",
100 };
102 /* l3_instr */
103 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
104 .name = "l3_instr",
105 .class = &dra7xx_l3_hwmod_class,
106 .clkdm_name = "l3instr_clkdm",
107 .prcm = {
108 .omap4 = {
109 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
110 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
111 .modulemode = MODULEMODE_HWCTRL,
112 },
113 },
114 };
116 /* l3_main_1 */
117 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
118 .name = "l3_main_1",
119 .class = &dra7xx_l3_hwmod_class,
120 .clkdm_name = "l3main1_clkdm",
121 .prcm = {
122 .omap4 = {
123 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
124 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
125 },
126 },
127 };
129 /* l3_main_2 */
130 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
131 .name = "l3_main_2",
132 .class = &dra7xx_l3_hwmod_class,
133 .clkdm_name = "l3instr_clkdm",
134 .prcm = {
135 .omap4 = {
136 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
137 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
138 .modulemode = MODULEMODE_HWCTRL,
139 },
140 },
141 };
143 /*
144 * 'l4' class
145 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
146 */
147 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
148 .name = "l4",
149 };
151 /* l4_cfg */
152 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
153 .name = "l4_cfg",
154 .class = &dra7xx_l4_hwmod_class,
155 .clkdm_name = "l4cfg_clkdm",
156 .prcm = {
157 .omap4 = {
158 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
159 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
160 },
161 },
162 };
164 /* l4_per1 */
165 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
166 .name = "l4_per1",
167 .class = &dra7xx_l4_hwmod_class,
168 .clkdm_name = "l4per_clkdm",
169 .prcm = {
170 .omap4 = {
171 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
172 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
173 },
174 },
175 };
177 /* l4_per2 */
178 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
179 .name = "l4_per2",
180 .class = &dra7xx_l4_hwmod_class,
181 .clkdm_name = "l4per2_clkdm",
182 .prcm = {
183 .omap4 = {
184 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
185 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
186 },
187 },
188 };
190 /* l4_per3 */
191 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
192 .name = "l4_per3",
193 .class = &dra7xx_l4_hwmod_class,
194 .clkdm_name = "l4per3_clkdm",
195 .prcm = {
196 .omap4 = {
197 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
198 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
199 },
200 },
201 };
203 /* l4_wkup */
204 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
205 .name = "l4_wkup",
206 .class = &dra7xx_l4_hwmod_class,
207 .clkdm_name = "wkupaon_clkdm",
208 .prcm = {
209 .omap4 = {
210 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
211 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
212 },
213 },
214 };
216 /*
217 * 'atl' class
218 *
219 */
221 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
222 .name = "atl",
223 };
225 /* atl */
226 static struct omap_hwmod dra7xx_atl_hwmod = {
227 .name = "atl",
228 .class = &dra7xx_atl_hwmod_class,
229 .clkdm_name = "atl_clkdm",
230 .main_clk = "atl_gfclk_mux",
231 .lockdep_class = HWMOD_LOCKDEP_SUBCLASS_CLASS1,
232 .prcm = {
233 .omap4 = {
234 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
235 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
236 .modulemode = MODULEMODE_SWCTRL,
237 },
238 },
239 };
241 /*
242 * 'bb2d' class
243 *
244 */
246 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
247 .name = "bb2d",
248 };
250 /* bb2d */
251 static struct omap_hwmod dra7xx_bb2d_hwmod = {
252 .name = "bb2d",
253 .class = &dra7xx_bb2d_hwmod_class,
254 .clkdm_name = "dss_clkdm",
255 .main_clk = "dpll_core_h24x2_ck",
256 .prcm = {
257 .omap4 = {
258 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
259 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
260 .modulemode = MODULEMODE_SWCTRL,
261 },
262 },
263 };
265 /*
266 * 'vpe' class
267 *
268 */
270 static struct omap_hwmod_class_sysconfig dra7xx_vpe_sysc = {
271 .sysc_offs = 0x0010,
272 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
273 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
274 MSTANDBY_FORCE | MSTANDBY_NO |
275 MSTANDBY_SMART),
276 .sysc_fields = &omap_hwmod_sysc_type2,
277 };
279 static struct omap_hwmod_class dra7xx_vpe_hwmod_class = {
280 .name = "vpe",
281 .sysc = &dra7xx_vpe_sysc,
282 };
284 /* vpe */
285 static struct omap_hwmod dra7xx_vpe_hwmod = {
286 .name = "vpe",
287 .class = &dra7xx_vpe_hwmod_class,
288 .clkdm_name = "vpe_clkdm",
289 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
290 .prcm = {
291 .omap4 = {
292 .clkctrl_offs = DRA7XX_CM_VPE_VPE_CLKCTRL_OFFSET,
293 .context_offs = DRA7XX_RM_VPE_VPE_CONTEXT_OFFSET,
294 .modulemode = MODULEMODE_HWCTRL,
295 },
296 },
297 };
299 /*
300 * 'vip' class
301 *
302 */
304 static struct omap_hwmod_class_sysconfig dra7xx_vip_sysc = {
305 .sysc_offs = 0x0010,
306 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
307 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
308 MSTANDBY_FORCE | MSTANDBY_NO |
309 MSTANDBY_SMART),
310 .sysc_fields = &omap_hwmod_sysc_type2,
311 };
313 static struct omap_hwmod_class dra7xx_vip_hwmod_class = {
314 .name = "vip",
315 .sysc = &dra7xx_vip_sysc,
316 };
318 /* vip1 */
319 static struct omap_hwmod dra7xx_vip1_hwmod = {
320 .name = "vip1",
321 .class = &dra7xx_vip_hwmod_class,
322 .clkdm_name = "cam_clkdm",
323 .main_clk = "vip1_gclk_mux",
324 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
325 .prcm = {
326 .omap4 = {
327 .clkctrl_offs = DRA7XX_CM_CAM_VIP1_CLKCTRL_OFFSET,
328 .context_offs = DRA7XX_RM_CAM_VIP1_CONTEXT_OFFSET,
329 .modulemode = MODULEMODE_HWCTRL,
330 },
331 },
332 };
334 /* vip2 */
335 static struct omap_hwmod dra7xx_vip2_hwmod = {
336 .name = "vip2",
337 .class = &dra7xx_vip_hwmod_class,
338 .clkdm_name = "cam_clkdm",
339 .main_clk = "vip2_gclk_mux",
340 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
341 .prcm = {
342 .omap4 = {
343 .clkctrl_offs = DRA7XX_CM_CAM_VIP2_CLKCTRL_OFFSET,
344 .context_offs = DRA7XX_RM_CAM_VIP2_CONTEXT_OFFSET,
345 .modulemode = MODULEMODE_HWCTRL,
346 },
347 },
348 };
350 /* vip3 */
351 static struct omap_hwmod dra7xx_vip3_hwmod = {
352 .name = "vip3",
353 .class = &dra7xx_vip_hwmod_class,
354 .clkdm_name = "cam_clkdm",
355 .main_clk = "vip3_gclk_mux",
356 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
357 .prcm = {
358 .omap4 = {
359 .clkctrl_offs = DRA7XX_CM_CAM_VIP3_CLKCTRL_OFFSET,
360 .context_offs = DRA7XX_RM_CAM_VIP3_CONTEXT_OFFSET,
361 .modulemode = MODULEMODE_HWCTRL,
362 },
363 },
364 };
366 /*
367 * 'cal' class
368 *
369 */
371 static struct omap_hwmod_class_sysconfig dra7xx_cal_sysc = {
372 .sysc_offs = 0x0010,
373 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_RESET_STATUS |
374 SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE),
375 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
376 MSTANDBY_FORCE | MSTANDBY_NO),
377 .sysc_fields = &omap_hwmod_sysc_type2,
378 };
380 static struct omap_hwmod_class dra7xx_cal_hwmod_class = {
381 .name = "cal",
382 .sysc = &dra7xx_cal_sysc,
383 };
385 /* cal */
386 static struct omap_hwmod dra7xx_cal_hwmod = {
387 .name = "cal",
388 .class = &dra7xx_cal_hwmod_class,
389 .clkdm_name = "cam_clkdm",
390 .main_clk = "vip2_gclk_mux",
391 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
392 .prcm = {
393 .omap4 = {
394 .clkctrl_offs = DRA7XX_CM_CAM_VIP2_CLKCTRL_OFFSET,
395 .context_offs = DRA7XX_RM_CAM_VIP2_CONTEXT_OFFSET,
396 .modulemode = MODULEMODE_HWCTRL,
397 },
398 },
399 };
401 /*
402 * 'counter' class
403 *
404 */
406 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
407 .rev_offs = 0x0000,
408 .sysc_offs = 0x0010,
409 .sysc_flags = SYSC_HAS_SIDLEMODE,
410 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
411 SIDLE_SMART_WKUP),
412 .sysc_fields = &omap_hwmod_sysc_type1,
413 };
415 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
416 .name = "counter",
417 .sysc = &dra7xx_counter_sysc,
418 };
420 /* counter_32k */
421 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
422 .name = "counter_32k",
423 .class = &dra7xx_counter_hwmod_class,
424 .clkdm_name = "wkupaon_clkdm",
425 .flags = HWMOD_SWSUP_SIDLE,
426 .main_clk = "wkupaon_iclk_mux",
427 .prcm = {
428 .omap4 = {
429 .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
430 .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
431 },
432 },
433 };
435 /*
436 * 'ctrl_module' class
437 *
438 */
440 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
441 .name = "ctrl_module",
442 };
444 /* ctrl_module_wkup */
445 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
446 .name = "ctrl_module_wkup",
447 .class = &dra7xx_ctrl_module_hwmod_class,
448 .clkdm_name = "wkupaon_clkdm",
449 .prcm = {
450 .omap4 = {
451 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
452 },
453 },
454 };
456 /*
457 * 'gmac' class
458 * cpsw/gmac sub system
459 */
460 static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
461 .rev_offs = 0x0,
462 .sysc_offs = 0x8,
463 .syss_offs = 0x4,
464 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
465 SYSS_HAS_RESET_STATUS),
466 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
467 MSTANDBY_NO),
468 .sysc_fields = &omap_hwmod_sysc_type3,
469 };
471 static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
472 .name = "gmac",
473 .sysc = &dra7xx_gmac_sysc,
474 };
476 static struct omap_hwmod dra7xx_gmac_hwmod = {
477 .name = "gmac",
478 .class = &dra7xx_gmac_hwmod_class,
479 .clkdm_name = "gmac_clkdm",
480 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
481 .main_clk = "dpll_gmac_ck",
482 .mpu_rt_idx = 1,
483 .prcm = {
484 .omap4 = {
485 .clkctrl_offs = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
486 .context_offs = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
487 .modulemode = MODULEMODE_SWCTRL,
488 },
489 },
490 };
492 /*
493 * 'mdio' class
494 */
495 static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
496 .name = "davinci_mdio",
497 };
499 static struct omap_hwmod dra7xx_mdio_hwmod = {
500 .name = "davinci_mdio",
501 .class = &dra7xx_mdio_hwmod_class,
502 .clkdm_name = "gmac_clkdm",
503 .main_clk = "dpll_gmac_ck",
504 };
506 /*
507 * 'dcan' class
508 *
509 */
511 static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
512 .name = "dcan",
513 };
515 /* dcan1 */
516 static struct omap_hwmod dra7xx_dcan1_hwmod = {
517 .name = "dcan1",
518 .class = &dra7xx_dcan_hwmod_class,
519 .clkdm_name = "wkupaon_clkdm",
520 .prcm = {
521 .omap4 = {
522 .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
523 .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
524 .modulemode = MODULEMODE_SWCTRL,
525 },
526 },
527 };
529 /* dcan2 */
530 static struct omap_hwmod dra7xx_dcan2_hwmod = {
531 .name = "dcan2",
532 .class = &dra7xx_dcan_hwmod_class,
533 .clkdm_name = "l4per2_clkdm",
534 .prcm = {
535 .omap4 = {
536 .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
537 .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
538 .modulemode = MODULEMODE_SWCTRL,
539 },
540 },
541 };
543 /* pwmss */
544 static struct omap_hwmod_class_sysconfig dra7xx_epwmss_sysc = {
545 .rev_offs = 0x0,
546 .sysc_offs = 0x4,
547 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_RESET_STATUS,
548 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
549 .sysc_fields = &omap_hwmod_sysc_type2,
550 };
552 struct omap_hwmod_class dra7xx_epwmss_hwmod_class = {
553 .name = "epwmss",
554 .sysc = &dra7xx_epwmss_sysc,
555 };
557 static struct omap_hwmod_class dra7xx_ecap_hwmod_class = {
558 .name = "ecap",
559 };
561 static struct omap_hwmod_class dra7xx_eqep_hwmod_class = {
562 .name = "eqep",
563 };
565 struct omap_hwmod_class dra7xx_ehrpwm_hwmod_class = {
566 .name = "ehrpwm",
567 };
569 /* epwmss0 */
570 struct omap_hwmod dra7xx_epwmss0_hwmod = {
571 .name = "epwmss0",
572 .class = &dra7xx_epwmss_hwmod_class,
573 .clkdm_name = "l4per2_clkdm",
574 .main_clk = "l4_root_clk_div",
575 .prcm = {
576 .omap4 = {
577 .modulemode = MODULEMODE_SWCTRL,
578 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET,
579 .context_offs = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET,
580 },
581 },
582 };
584 /* ecap0 */
585 struct omap_hwmod dra7xx_ecap0_hwmod = {
586 .name = "ecap0",
587 .class = &dra7xx_ecap_hwmod_class,
588 .clkdm_name = "l4per2_clkdm",
589 .main_clk = "l4_root_clk_div",
590 };
592 /* eqep0 */
593 struct omap_hwmod dra7xx_eqep0_hwmod = {
594 .name = "eqep0",
595 .class = &dra7xx_eqep_hwmod_class,
596 .clkdm_name = "l4per2_clkdm",
597 .main_clk = "l4_root_clk_div",
598 };
600 /* ehrpwm0 */
601 struct omap_hwmod dra7xx_ehrpwm0_hwmod = {
602 .name = "ehrpwm0",
603 .class = &dra7xx_ehrpwm_hwmod_class,
604 .clkdm_name = "l4per2_clkdm",
605 .main_clk = "l4_root_clk_div",
606 };
608 /* epwmss1 */
609 struct omap_hwmod dra7xx_epwmss1_hwmod = {
610 .name = "epwmss1",
611 .class = &dra7xx_epwmss_hwmod_class,
612 .clkdm_name = "l4per2_clkdm",
613 .main_clk = "l4_root_clk_div",
614 .prcm = {
615 .omap4 = {
616 .modulemode = MODULEMODE_SWCTRL,
617 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET,
618 .context_offs = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET,
619 },
620 },
621 };
623 /* ecap1 */
624 struct omap_hwmod dra7xx_ecap1_hwmod = {
625 .name = "ecap1",
626 .class = &dra7xx_ecap_hwmod_class,
627 .clkdm_name = "l4per2_clkdm",
628 .main_clk = "l4_root_clk_div",
629 };
631 /* eqep1 */
632 struct omap_hwmod dra7xx_eqep1_hwmod = {
633 .name = "eqep1",
634 .class = &dra7xx_eqep_hwmod_class,
635 .clkdm_name = "l4per2_clkdm",
636 .main_clk = "l4_root_clk_div",
637 };
639 /* ehrpwm1 */
640 struct omap_hwmod dra7xx_ehrpwm1_hwmod = {
641 .name = "ehrpwm1",
642 .class = &dra7xx_ehrpwm_hwmod_class,
643 .clkdm_name = "l4per2_clkdm",
644 .main_clk = "l4_root_clk_div",
645 };
647 /* epwmss2 */
648 struct omap_hwmod dra7xx_epwmss2_hwmod = {
649 .name = "epwmss2",
650 .class = &dra7xx_epwmss_hwmod_class,
651 .clkdm_name = "l4per2_clkdm",
652 .main_clk = "l4_root_clk_div",
653 .prcm = {
654 .omap4 = {
655 .modulemode = MODULEMODE_SWCTRL,
656 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET,
657 .context_offs = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET,
658 },
659 },
660 };
662 /* ecap2 */
663 struct omap_hwmod dra7xx_ecap2_hwmod = {
664 .name = "ecap2",
665 .class = &dra7xx_ecap_hwmod_class,
666 .clkdm_name = "l4per2_clkdm",
667 .main_clk = "l4_root_clk_div",
668 };
670 /* eqep2 */
671 struct omap_hwmod dra7xx_eqep2_hwmod = {
672 .name = "eqep2",
673 .class = &dra7xx_eqep_hwmod_class,
674 .clkdm_name = "l4per2_clkdm",
675 .main_clk = "l4_root_clk_div",
676 };
678 /* ehrpwm2 */
679 struct omap_hwmod dra7xx_ehrpwm2_hwmod = {
680 .name = "ehrpwm2",
681 .class = &dra7xx_ehrpwm_hwmod_class,
682 .clkdm_name = "l4per2_clkdm",
683 .main_clk = "l4_root_clk_div",
684 };
686 /*
687 * 'dma' class
688 *
689 */
691 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
692 .rev_offs = 0x0000,
693 .sysc_offs = 0x002c,
694 .syss_offs = 0x0028,
695 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
696 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
697 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
698 SYSS_HAS_RESET_STATUS),
699 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
700 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
701 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
702 .sysc_fields = &omap_hwmod_sysc_type1,
703 };
705 static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
706 .name = "dma",
707 .sysc = &dra7xx_dma_sysc,
708 };
710 /* dma dev_attr */
711 static struct omap_dma_dev_attr dma_dev_attr = {
712 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
713 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
714 .lch_count = 32,
715 };
717 /* dma_system */
718 static struct omap_hwmod dra7xx_dma_system_hwmod = {
719 .name = "dma_system",
720 .class = &dra7xx_dma_hwmod_class,
721 .clkdm_name = "dma_clkdm",
722 .main_clk = "l3_iclk_div",
723 .prcm = {
724 .omap4 = {
725 .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
726 .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
727 },
728 },
729 .dev_attr = &dma_dev_attr,
730 };
732 /* tpcc */
733 static struct omap_hwmod_class dra7xx_tpcc_hwmod_class = {
734 .name = "tpcc",
735 };
737 struct omap_hwmod dra7xx_tpcc_hwmod = {
738 .name = "tpcc",
739 .class = &dra7xx_tpcc_hwmod_class,
740 .clkdm_name = "l3main1_clkdm",
741 .main_clk = "l3_iclk_div",
742 .prcm = {
743 .omap4 = {
744 .modulemode = MODULEMODE_SWCTRL,
745 },
746 },
747 };
749 /* 'tptc' class */
750 static struct omap_hwmod_class dra7xx_tptc_hwmod_class = {
751 .name = "tptc",
752 };
754 /* tptc0 */
755 struct omap_hwmod dra7xx_tptc0_hwmod = {
756 .name = "tptc0",
757 .class = &dra7xx_tptc_hwmod_class,
758 .clkdm_name = "l3main1_clkdm",
759 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
760 HWMOD_NEEDS_REIDLE,
761 .main_clk = "l3_iclk_div",
762 .prcm = {
763 .omap4 = {
764 .modulemode = MODULEMODE_SWCTRL,
765 },
766 },
767 };
769 /* tptc1 */
770 struct omap_hwmod dra7xx_tptc1_hwmod = {
771 .name = "tptc1",
772 .class = &dra7xx_tptc_hwmod_class,
773 .clkdm_name = "l3main1_clkdm",
774 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
775 HWMOD_NEEDS_REIDLE,
776 .main_clk = "l3_iclk_div",
777 .prcm = {
778 .omap4 = {
779 .modulemode = MODULEMODE_SWCTRL,
780 },
781 },
782 };
784 /* tptc2 */
785 struct omap_hwmod dra7xx_tptc2_hwmod = {
786 .name = "tptc2",
787 .class = &dra7xx_tptc_hwmod_class,
788 .clkdm_name = "l3main1_clkdm",
789 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
790 HWMOD_NEEDS_REIDLE,
791 .main_clk = "l3_iclk_div",
792 .prcm = {
793 .omap4 = {
794 .modulemode = MODULEMODE_SWCTRL,
795 },
796 },
797 };
799 /*
800 * 'dsp' class
801 * dsp sub-system
802 */
804 static struct omap_hwmod_class dra7xx_dsp_hwmod_class = {
805 .name = "dsp",
806 };
808 static struct omap_hwmod_rst_info dra7xx_dsp_resets[] = {
809 { .name = "dsp", .rst_shift = 0 },
810 };
812 /* dsp1 processor */
813 static struct omap_hwmod dra7xx_dsp1_hwmod = {
814 .name = "dsp1",
815 .class = &dra7xx_dsp_hwmod_class,
816 .clkdm_name = "dsp1_clkdm",
817 .rst_lines = dra7xx_dsp_resets,
818 .rst_lines_cnt = ARRAY_SIZE(dra7xx_dsp_resets),
819 .main_clk = "dpll_dsp_m2_ck",
820 .prcm = {
821 .omap4 = {
822 .clkctrl_offs = DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET,
823 .rstctrl_offs = DRA7XX_RM_DSP1_RSTCTRL_OFFSET,
824 .context_offs = DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET,
825 },
826 },
827 };
829 /* dsp2 processor */
830 static struct omap_hwmod dra7xx_dsp2_hwmod = {
831 .name = "dsp2",
832 .class = &dra7xx_dsp_hwmod_class,
833 .clkdm_name = "dsp2_clkdm",
834 .rst_lines = dra7xx_dsp_resets,
835 .rst_lines_cnt = ARRAY_SIZE(dra7xx_dsp_resets),
836 .main_clk = "dpll_dsp_m2_ck",
837 .prcm = {
838 .omap4 = {
839 .clkctrl_offs = DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET,
840 .rstctrl_offs = DRA7XX_RM_DSP2_RSTCTRL_OFFSET,
841 .context_offs = DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET,
842 },
843 },
844 };
846 /*
847 * 'dss' class
848 *
849 */
851 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
852 .rev_offs = 0x0000,
853 .syss_offs = 0x0014,
854 .sysc_flags = SYSS_HAS_RESET_STATUS,
855 };
857 static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
858 .name = "dss",
859 .sysc = &dra7xx_dss_sysc,
860 .reset = omap_dss_reset,
861 };
863 /* dss */
864 static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
865 { .dma_req = 75 + DRA7XX_DMA_REQ_START },
866 { .dma_req = -1 }
867 };
869 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
870 { .role = "dss_clk", .clk = "dss_dss_clk" },
871 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
872 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
873 { .role = "video2_clk", .clk = "dss_video2_clk" },
874 { .role = "video1_clk", .clk = "dss_video1_clk" },
875 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
876 };
878 static struct omap_hwmod dra7xx_dss_hwmod = {
879 .name = "dss_core",
880 .class = &dra7xx_dss_hwmod_class,
881 .clkdm_name = "dss_clkdm",
882 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
883 .sdma_reqs = dra7xx_dss_sdma_reqs,
884 .main_clk = "dss_dss_clk",
885 .prcm = {
886 .omap4 = {
887 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
888 .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
889 .modulemode = MODULEMODE_SWCTRL,
890 },
891 },
892 .opt_clks = dss_opt_clks,
893 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
894 };
896 /*
897 * 'dispc' class
898 * display controller
899 */
901 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
902 .rev_offs = 0x0000,
903 .sysc_offs = 0x0010,
904 .syss_offs = 0x0014,
905 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
906 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
907 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
908 SYSS_HAS_RESET_STATUS),
909 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
910 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
911 .sysc_fields = &omap_hwmod_sysc_type1,
912 };
914 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
915 .name = "dispc",
916 .sysc = &dra7xx_dispc_sysc,
917 };
919 /* dss_dispc */
920 /* dss_dispc dev_attr */
921 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
922 .has_framedonetv_irq = 1,
923 .manager_count = 4,
924 };
926 static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
927 .name = "dss_dispc",
928 .class = &dra7xx_dispc_hwmod_class,
929 .clkdm_name = "dss_clkdm",
930 .main_clk = "dss_dss_clk",
931 .prcm = {
932 .omap4 = {
933 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
934 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
935 },
936 },
937 .dev_attr = &dss_dispc_dev_attr,
938 .parent_hwmod = &dra7xx_dss_hwmod,
939 };
941 /*
942 * 'hdmi' class
943 * hdmi controller
944 */
946 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
947 .rev_offs = 0x0000,
948 .sysc_offs = 0x0010,
949 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
950 SYSC_HAS_SOFTRESET),
951 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
952 SIDLE_SMART_WKUP),
953 .sysc_fields = &omap_hwmod_sysc_type2,
954 };
956 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
957 .name = "hdmi",
958 .sysc = &dra7xx_hdmi_sysc,
959 };
961 /* dss_hdmi */
963 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
964 { .role = "sys_clk", .clk = "dss_hdmi_clk" },
965 };
967 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
968 .name = "dss_hdmi",
969 .class = &dra7xx_hdmi_hwmod_class,
970 .clkdm_name = "dss_clkdm",
971 .main_clk = "dss_48mhz_clk",
972 .prcm = {
973 .omap4 = {
974 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
975 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
976 },
977 },
978 .opt_clks = dss_hdmi_opt_clks,
979 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
980 .parent_hwmod = &dra7xx_dss_hwmod,
981 };
983 /* AES (the 'P' (public) device) */
984 static struct omap_hwmod_class_sysconfig dra7xx_aes_sysc = {
985 .rev_offs = 0x0080,
986 .sysc_offs = 0x0084,
987 .syss_offs = 0x0088,
988 .sysc_flags = SYSS_HAS_RESET_STATUS,
989 };
991 static struct omap_hwmod_class dra7xx_aes_hwmod_class = {
992 .name = "aes",
993 .sysc = &dra7xx_aes_sysc,
994 .rev = 2,
995 };
997 /* AES1 */
998 static struct omap_hwmod dra7xx_aes1_hwmod = {
999 .name = "aes1",
1000 .class = &dra7xx_aes_hwmod_class,
1001 .clkdm_name = "l4sec_clkdm",
1002 .main_clk = "l3_iclk_div",
1003 .prcm = {
1004 .omap4 = {
1005 .clkctrl_offs = DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET,
1006 .context_offs = DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET,
1007 .modulemode = MODULEMODE_HWCTRL,
1008 },
1009 },
1010 };
1012 /* AES2 */
1013 static struct omap_hwmod dra7xx_aes2_hwmod = {
1014 .name = "aes2",
1015 .class = &dra7xx_aes_hwmod_class,
1016 .clkdm_name = "l4sec_clkdm",
1017 .main_clk = "l3_iclk_div",
1018 .prcm = {
1019 .omap4 = {
1020 .clkctrl_offs = DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET,
1021 .context_offs = DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET,
1022 .modulemode = MODULEMODE_HWCTRL,
1023 },
1024 },
1025 };
1027 /* sha0 HIB2 (the 'P' (public) device) */
1028 static struct omap_hwmod_class_sysconfig dra7xx_sha0_sysc = {
1029 .rev_offs = 0x100,
1030 .sysc_offs = 0x110,
1031 .syss_offs = 0x114,
1032 .sysc_flags = SYSS_HAS_RESET_STATUS,
1033 };
1035 static struct omap_hwmod_class dra7xx_sha0_hwmod_class = {
1036 .name = "sham",
1037 .sysc = &dra7xx_sha0_sysc,
1038 .rev = 2,
1039 };
1041 struct omap_hwmod dra7xx_sha0_hwmod = {
1042 .name = "sham",
1043 .class = &dra7xx_sha0_hwmod_class,
1044 .clkdm_name = "l4sec_clkdm",
1045 .main_clk = "l3_iclk_div",
1046 .prcm = {
1047 .omap4 = {
1048 .clkctrl_offs = DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
1049 .context_offs = DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
1050 .modulemode = MODULEMODE_HWCTRL,
1051 },
1052 },
1053 };
1055 /*
1056 * 'elm' class
1057 *
1058 */
1060 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
1061 .rev_offs = 0x0000,
1062 .sysc_offs = 0x0010,
1063 .syss_offs = 0x0014,
1064 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1065 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1066 SYSS_HAS_RESET_STATUS),
1067 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1068 SIDLE_SMART_WKUP),
1069 .sysc_fields = &omap_hwmod_sysc_type1,
1070 };
1072 static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
1073 .name = "elm",
1074 .sysc = &dra7xx_elm_sysc,
1075 };
1077 /* elm */
1079 static struct omap_hwmod dra7xx_elm_hwmod = {
1080 .name = "elm",
1081 .class = &dra7xx_elm_hwmod_class,
1082 .clkdm_name = "l4per_clkdm",
1083 .main_clk = "l3_iclk_div",
1084 .prcm = {
1085 .omap4 = {
1086 .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
1087 .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
1088 },
1089 },
1090 };
1092 /*
1093 * 'gpio' class
1094 *
1095 */
1097 static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
1098 .rev_offs = 0x0000,
1099 .sysc_offs = 0x0010,
1100 .syss_offs = 0x0114,
1101 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1102 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1103 SYSS_HAS_RESET_STATUS),
1104 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1105 SIDLE_SMART_WKUP),
1106 .sysc_fields = &omap_hwmod_sysc_type1,
1107 };
1109 static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
1110 .name = "gpio",
1111 .sysc = &dra7xx_gpio_sysc,
1112 .rev = 2,
1113 };
1115 /* gpio dev_attr */
1116 static struct omap_gpio_dev_attr gpio_dev_attr = {
1117 .bank_width = 32,
1118 .dbck_flag = true,
1119 };
1121 /* gpio1 */
1122 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1123 { .role = "dbclk", .clk = "gpio1_dbclk" },
1124 };
1126 static struct omap_hwmod dra7xx_gpio1_hwmod = {
1127 .name = "gpio1",
1128 .class = &dra7xx_gpio_hwmod_class,
1129 .clkdm_name = "wkupaon_clkdm",
1130 .main_clk = "wkupaon_iclk_mux",
1131 .prcm = {
1132 .omap4 = {
1133 .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
1134 .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
1135 .modulemode = MODULEMODE_HWCTRL,
1136 },
1137 },
1138 .opt_clks = gpio1_opt_clks,
1139 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1140 .dev_attr = &gpio_dev_attr,
1141 };
1143 /* gpio2 */
1144 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1145 { .role = "dbclk", .clk = "gpio2_dbclk" },
1146 };
1148 static struct omap_hwmod dra7xx_gpio2_hwmod = {
1149 .name = "gpio2",
1150 .class = &dra7xx_gpio_hwmod_class,
1151 .clkdm_name = "l4per_clkdm",
1152 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1153 .main_clk = "l3_iclk_div",
1154 .prcm = {
1155 .omap4 = {
1156 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1157 .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1158 .modulemode = MODULEMODE_HWCTRL,
1159 },
1160 },
1161 .opt_clks = gpio2_opt_clks,
1162 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1163 .dev_attr = &gpio_dev_attr,
1164 };
1166 /* gpio3 */
1167 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1168 { .role = "dbclk", .clk = "gpio3_dbclk" },
1169 };
1171 static struct omap_hwmod dra7xx_gpio3_hwmod = {
1172 .name = "gpio3",
1173 .class = &dra7xx_gpio_hwmod_class,
1174 .clkdm_name = "l4per_clkdm",
1175 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1176 .main_clk = "l3_iclk_div",
1177 .prcm = {
1178 .omap4 = {
1179 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1180 .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1181 .modulemode = MODULEMODE_HWCTRL,
1182 },
1183 },
1184 .opt_clks = gpio3_opt_clks,
1185 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1186 .dev_attr = &gpio_dev_attr,
1187 };
1189 /* gpio4 */
1190 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1191 { .role = "dbclk", .clk = "gpio4_dbclk" },
1192 };
1194 static struct omap_hwmod dra7xx_gpio4_hwmod = {
1195 .name = "gpio4",
1196 .class = &dra7xx_gpio_hwmod_class,
1197 .clkdm_name = "l4per_clkdm",
1198 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1199 .main_clk = "l3_iclk_div",
1200 .prcm = {
1201 .omap4 = {
1202 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1203 .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1204 .modulemode = MODULEMODE_HWCTRL,
1205 },
1206 },
1207 .opt_clks = gpio4_opt_clks,
1208 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1209 .dev_attr = &gpio_dev_attr,
1210 };
1212 /* gpio5 */
1213 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1214 { .role = "dbclk", .clk = "gpio5_dbclk" },
1215 };
1217 static struct omap_hwmod dra7xx_gpio5_hwmod = {
1218 .name = "gpio5",
1219 .class = &dra7xx_gpio_hwmod_class,
1220 .clkdm_name = "l4per_clkdm",
1221 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1222 .main_clk = "l3_iclk_div",
1223 .prcm = {
1224 .omap4 = {
1225 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1226 .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1227 .modulemode = MODULEMODE_HWCTRL,
1228 },
1229 },
1230 .opt_clks = gpio5_opt_clks,
1231 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1232 .dev_attr = &gpio_dev_attr,
1233 };
1235 /* gpio6 */
1236 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1237 { .role = "dbclk", .clk = "gpio6_dbclk" },
1238 };
1240 static struct omap_hwmod dra7xx_gpio6_hwmod = {
1241 .name = "gpio6",
1242 .class = &dra7xx_gpio_hwmod_class,
1243 .clkdm_name = "l4per_clkdm",
1244 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1245 .main_clk = "l3_iclk_div",
1246 .prcm = {
1247 .omap4 = {
1248 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1249 .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1250 .modulemode = MODULEMODE_HWCTRL,
1251 },
1252 },
1253 .opt_clks = gpio6_opt_clks,
1254 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1255 .dev_attr = &gpio_dev_attr,
1256 };
1258 /* gpio7 */
1259 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
1260 { .role = "dbclk", .clk = "gpio7_dbclk" },
1261 };
1263 static struct omap_hwmod dra7xx_gpio7_hwmod = {
1264 .name = "gpio7",
1265 .class = &dra7xx_gpio_hwmod_class,
1266 .clkdm_name = "l4per_clkdm",
1267 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1268 .main_clk = "l3_iclk_div",
1269 .prcm = {
1270 .omap4 = {
1271 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
1272 .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
1273 .modulemode = MODULEMODE_HWCTRL,
1274 },
1275 },
1276 .opt_clks = gpio7_opt_clks,
1277 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
1278 .dev_attr = &gpio_dev_attr,
1279 };
1281 /* gpio8 */
1282 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
1283 { .role = "dbclk", .clk = "gpio8_dbclk" },
1284 };
1286 static struct omap_hwmod dra7xx_gpio8_hwmod = {
1287 .name = "gpio8",
1288 .class = &dra7xx_gpio_hwmod_class,
1289 .clkdm_name = "l4per_clkdm",
1290 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1291 .main_clk = "l3_iclk_div",
1292 .prcm = {
1293 .omap4 = {
1294 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
1295 .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
1296 .modulemode = MODULEMODE_HWCTRL,
1297 },
1298 },
1299 .opt_clks = gpio8_opt_clks,
1300 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
1301 .dev_attr = &gpio_dev_attr,
1302 };
1304 /*
1305 * 'gpmc' class
1306 *
1307 */
1309 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
1310 .rev_offs = 0x0000,
1311 .sysc_offs = 0x0010,
1312 .syss_offs = 0x0014,
1313 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1314 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1315 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
1316 .sysc_fields = &omap_hwmod_sysc_type1,
1317 };
1319 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
1320 .name = "gpmc",
1321 .sysc = &dra7xx_gpmc_sysc,
1322 };
1324 /* gpmc */
1326 static struct omap_hwmod dra7xx_gpmc_hwmod = {
1327 .name = "gpmc",
1328 .class = &dra7xx_gpmc_hwmod_class,
1329 .clkdm_name = "l3main1_clkdm",
1330 .main_clk = "l3_iclk_div",
1331 .prcm = {
1332 .omap4 = {
1333 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
1334 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
1335 .modulemode = MODULEMODE_HWCTRL,
1336 },
1337 },
1338 };
1340 /*
1341 * 'gpu' class
1342 * 2d/3d graphics accelerator
1343 */
1345 static struct omap_hwmod_class_sysconfig dra7xx_gpu_sysc = {
1346 .rev_offs = 0x0000,
1347 .sysc_offs = 0x0010,
1348 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1349 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1350 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1351 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1352 .sysc_fields = &omap_hwmod_sysc_type2,
1353 };
1355 static struct omap_hwmod_class dra7xx_gpu_hwmod_class = {
1356 .name = "gpu",
1357 .sysc = &dra7xx_gpu_sysc,
1358 };
1360 static struct omap_hwmod dra7xx_gpu_hwmod = {
1361 .name = "gpu",
1362 .class = &dra7xx_gpu_hwmod_class,
1363 .clkdm_name = "gpu_clkdm",
1364 .main_clk = "gpu_core_gclk_mux",
1365 .prcm = {
1366 .omap4 = {
1367 .clkctrl_offs = DRA7XX_CM_GPU_GPU_CLKCTRL_OFFSET,
1368 .context_offs = DRA7XX_RM_GPU_GPU_CONTEXT_OFFSET,
1369 .modulemode = MODULEMODE_SWCTRL,
1370 },
1371 },
1372 };
1374 /*
1375 * 'hdq1w' class
1376 *
1377 */
1379 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
1380 .rev_offs = 0x0000,
1381 .sysc_offs = 0x0014,
1382 .syss_offs = 0x0018,
1383 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1384 SYSS_HAS_RESET_STATUS),
1385 .sysc_fields = &omap_hwmod_sysc_type1,
1386 };
1388 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
1389 .name = "hdq1w",
1390 .sysc = &dra7xx_hdq1w_sysc,
1391 };
1393 /* hdq1w */
1395 static struct omap_hwmod dra7xx_hdq1w_hwmod = {
1396 .name = "hdq1w",
1397 .class = &dra7xx_hdq1w_hwmod_class,
1398 .clkdm_name = "l4per_clkdm",
1399 .flags = HWMOD_INIT_NO_RESET,
1400 .main_clk = "func_12m_fclk",
1401 .prcm = {
1402 .omap4 = {
1403 .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1404 .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1405 .modulemode = MODULEMODE_SWCTRL,
1406 },
1407 },
1408 };
1410 /*
1411 * 'i2c' class
1412 *
1413 */
1415 static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
1416 .sysc_offs = 0x0010,
1417 .syss_offs = 0x0090,
1418 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1419 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1420 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1421 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1422 SIDLE_SMART_WKUP),
1423 .clockact = CLOCKACT_TEST_ICLK,
1424 .sysc_fields = &omap_hwmod_sysc_type1,
1425 };
1427 static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
1428 .name = "i2c",
1429 .sysc = &dra7xx_i2c_sysc,
1430 .reset = &omap_i2c_reset,
1431 .rev = OMAP_I2C_IP_VERSION_2,
1432 };
1434 /* i2c dev_attr */
1435 static struct omap_i2c_dev_attr i2c_dev_attr = {
1436 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1437 };
1439 /* i2c1 */
1440 static struct omap_hwmod dra7xx_i2c1_hwmod = {
1441 .name = "i2c1",
1442 .class = &dra7xx_i2c_hwmod_class,
1443 .clkdm_name = "l4per_clkdm",
1444 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1445 .main_clk = "func_96m_fclk",
1446 .prcm = {
1447 .omap4 = {
1448 .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1449 .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
1450 .modulemode = MODULEMODE_SWCTRL,
1451 },
1452 },
1453 .dev_attr = &i2c_dev_attr,
1454 };
1456 /* i2c2 */
1457 static struct omap_hwmod dra7xx_i2c2_hwmod = {
1458 .name = "i2c2",
1459 .class = &dra7xx_i2c_hwmod_class,
1460 .clkdm_name = "l4per_clkdm",
1461 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1462 .main_clk = "func_96m_fclk",
1463 .prcm = {
1464 .omap4 = {
1465 .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1466 .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
1467 .modulemode = MODULEMODE_SWCTRL,
1468 },
1469 },
1470 .dev_attr = &i2c_dev_attr,
1471 };
1473 /* i2c3 */
1474 static struct omap_hwmod dra7xx_i2c3_hwmod = {
1475 .name = "i2c3",
1476 .class = &dra7xx_i2c_hwmod_class,
1477 .clkdm_name = "l4per_clkdm",
1478 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1479 .main_clk = "func_96m_fclk",
1480 .prcm = {
1481 .omap4 = {
1482 .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1483 .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
1484 .modulemode = MODULEMODE_SWCTRL,
1485 },
1486 },
1487 .dev_attr = &i2c_dev_attr,
1488 };
1490 /* i2c4 */
1491 static struct omap_hwmod dra7xx_i2c4_hwmod = {
1492 .name = "i2c4",
1493 .class = &dra7xx_i2c_hwmod_class,
1494 .clkdm_name = "l4per_clkdm",
1495 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1496 .main_clk = "func_96m_fclk",
1497 .prcm = {
1498 .omap4 = {
1499 .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1500 .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
1501 .modulemode = MODULEMODE_SWCTRL,
1502 },
1503 },
1504 .dev_attr = &i2c_dev_attr,
1505 };
1507 /* i2c5 */
1508 static struct omap_hwmod dra7xx_i2c5_hwmod = {
1509 .name = "i2c5",
1510 .class = &dra7xx_i2c_hwmod_class,
1511 .clkdm_name = "ipu_clkdm",
1512 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1513 .main_clk = "func_96m_fclk",
1514 .prcm = {
1515 .omap4 = {
1516 .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
1517 .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
1518 .modulemode = MODULEMODE_SWCTRL,
1519 },
1520 },
1521 .dev_attr = &i2c_dev_attr,
1522 };
1524 /*
1525 * 'ipu' class
1526 * imaging processor unit
1527 */
1529 static struct omap_hwmod_class dra7xx_ipu_hwmod_class = {
1530 .name = "ipu",
1531 };
1533 static struct omap_hwmod_rst_info dra7xx_ipu_resets[] = {
1534 { .name = "cpu0", .rst_shift = 0 },
1535 { .name = "cpu1", .rst_shift = 1 },
1536 };
1538 /* ipu1 processor */
1539 static struct omap_hwmod dra7xx_ipu1_hwmod = {
1540 .name = "ipu1",
1541 .class = &dra7xx_ipu_hwmod_class,
1542 .clkdm_name = "ipu1_clkdm",
1543 .rst_lines = dra7xx_ipu_resets,
1544 .rst_lines_cnt = ARRAY_SIZE(dra7xx_ipu_resets),
1545 .main_clk = "ipu1_gfclk_mux",
1546 .prcm = {
1547 .omap4 = {
1548 .clkctrl_offs = DRA7XX_CM_IPU1_IPU1_CLKCTRL_OFFSET,
1549 .rstctrl_offs = DRA7XX_RM_IPU1_RSTCTRL_OFFSET,
1550 .context_offs = DRA7XX_RM_IPU1_IPU1_CONTEXT_OFFSET,
1551 },
1552 },
1553 };
1555 /* ipu2 processor */
1556 static struct omap_hwmod dra7xx_ipu2_hwmod = {
1557 .name = "ipu2",
1558 .class = &dra7xx_ipu_hwmod_class,
1559 .clkdm_name = "ipu2_clkdm",
1560 .rst_lines = dra7xx_ipu_resets,
1561 .rst_lines_cnt = ARRAY_SIZE(dra7xx_ipu_resets),
1562 .main_clk = "dpll_core_h22x2_ck",
1563 .prcm = {
1564 .omap4 = {
1565 .clkctrl_offs = DRA7XX_CM_IPU2_IPU2_CLKCTRL_OFFSET,
1566 .rstctrl_offs = DRA7XX_RM_IPU2_RSTCTRL_OFFSET,
1567 .context_offs = DRA7XX_RM_IPU2_IPU2_CONTEXT_OFFSET,
1568 },
1569 },
1570 };
1572 /*
1573 * 'mailbox' class
1574 *
1575 */
1577 static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
1578 .rev_offs = 0x0000,
1579 .sysc_offs = 0x0010,
1580 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1581 SYSC_HAS_SOFTRESET),
1582 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1583 .sysc_fields = &omap_hwmod_sysc_type2,
1584 };
1586 static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
1587 .name = "mailbox",
1588 .sysc = &dra7xx_mailbox_sysc,
1589 };
1591 /* mailbox1 */
1592 static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1593 .name = "mailbox1",
1594 .class = &dra7xx_mailbox_hwmod_class,
1595 .clkdm_name = "l4cfg_clkdm",
1596 .prcm = {
1597 .omap4 = {
1598 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1599 .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1600 },
1601 },
1602 };
1604 /* mailbox2 */
1605 static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1606 .name = "mailbox2",
1607 .class = &dra7xx_mailbox_hwmod_class,
1608 .clkdm_name = "l4cfg_clkdm",
1609 .prcm = {
1610 .omap4 = {
1611 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1612 .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1613 },
1614 },
1615 };
1617 /* mailbox3 */
1618 static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1619 .name = "mailbox3",
1620 .class = &dra7xx_mailbox_hwmod_class,
1621 .clkdm_name = "l4cfg_clkdm",
1622 .prcm = {
1623 .omap4 = {
1624 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1625 .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1626 },
1627 },
1628 };
1630 /* mailbox4 */
1631 static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1632 .name = "mailbox4",
1633 .class = &dra7xx_mailbox_hwmod_class,
1634 .clkdm_name = "l4cfg_clkdm",
1635 .prcm = {
1636 .omap4 = {
1637 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1638 .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1639 },
1640 },
1641 };
1643 /* mailbox5 */
1644 static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1645 .name = "mailbox5",
1646 .class = &dra7xx_mailbox_hwmod_class,
1647 .clkdm_name = "l4cfg_clkdm",
1648 .prcm = {
1649 .omap4 = {
1650 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1651 .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1652 },
1653 },
1654 };
1656 /* mailbox6 */
1657 static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1658 .name = "mailbox6",
1659 .class = &dra7xx_mailbox_hwmod_class,
1660 .clkdm_name = "l4cfg_clkdm",
1661 .prcm = {
1662 .omap4 = {
1663 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1664 .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1665 },
1666 },
1667 };
1669 /* mailbox7 */
1670 static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1671 .name = "mailbox7",
1672 .class = &dra7xx_mailbox_hwmod_class,
1673 .clkdm_name = "l4cfg_clkdm",
1674 .prcm = {
1675 .omap4 = {
1676 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1677 .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1678 },
1679 },
1680 };
1682 /* mailbox8 */
1683 static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1684 .name = "mailbox8",
1685 .class = &dra7xx_mailbox_hwmod_class,
1686 .clkdm_name = "l4cfg_clkdm",
1687 .prcm = {
1688 .omap4 = {
1689 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1690 .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1691 },
1692 },
1693 };
1695 /* mailbox9 */
1696 static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1697 .name = "mailbox9",
1698 .class = &dra7xx_mailbox_hwmod_class,
1699 .clkdm_name = "l4cfg_clkdm",
1700 .prcm = {
1701 .omap4 = {
1702 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1703 .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1704 },
1705 },
1706 };
1708 /* mailbox10 */
1709 static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1710 .name = "mailbox10",
1711 .class = &dra7xx_mailbox_hwmod_class,
1712 .clkdm_name = "l4cfg_clkdm",
1713 .prcm = {
1714 .omap4 = {
1715 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1716 .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1717 },
1718 },
1719 };
1721 /* mailbox11 */
1722 static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1723 .name = "mailbox11",
1724 .class = &dra7xx_mailbox_hwmod_class,
1725 .clkdm_name = "l4cfg_clkdm",
1726 .prcm = {
1727 .omap4 = {
1728 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1729 .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1730 },
1731 },
1732 };
1734 /* mailbox12 */
1735 static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1736 .name = "mailbox12",
1737 .class = &dra7xx_mailbox_hwmod_class,
1738 .clkdm_name = "l4cfg_clkdm",
1739 .prcm = {
1740 .omap4 = {
1741 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1742 .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1743 },
1744 },
1745 };
1747 /* mailbox13 */
1748 static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1749 .name = "mailbox13",
1750 .class = &dra7xx_mailbox_hwmod_class,
1751 .clkdm_name = "l4cfg_clkdm",
1752 .prcm = {
1753 .omap4 = {
1754 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1755 .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1756 },
1757 },
1758 };
1760 /*
1761 * 'mcspi' class
1762 *
1763 */
1765 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1766 .rev_offs = 0x0000,
1767 .sysc_offs = 0x0010,
1768 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1769 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1770 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1771 SIDLE_SMART_WKUP),
1772 .sysc_fields = &omap_hwmod_sysc_type2,
1773 };
1775 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1776 .name = "mcspi",
1777 .sysc = &dra7xx_mcspi_sysc,
1778 .rev = OMAP4_MCSPI_REV,
1779 };
1781 /* mcspi1 */
1782 /* mcspi1 dev_attr */
1783 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1784 .num_chipselect = 4,
1785 };
1787 static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1788 .name = "mcspi1",
1789 .class = &dra7xx_mcspi_hwmod_class,
1790 .clkdm_name = "l4per_clkdm",
1791 .main_clk = "func_48m_fclk",
1792 .prcm = {
1793 .omap4 = {
1794 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1795 .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1796 .modulemode = MODULEMODE_SWCTRL,
1797 },
1798 },
1799 .dev_attr = &mcspi1_dev_attr,
1800 };
1802 /* mcspi2 */
1803 /* mcspi2 dev_attr */
1804 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1805 .num_chipselect = 2,
1806 };
1808 static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1809 .name = "mcspi2",
1810 .class = &dra7xx_mcspi_hwmod_class,
1811 .clkdm_name = "l4per_clkdm",
1812 .main_clk = "func_48m_fclk",
1813 .prcm = {
1814 .omap4 = {
1815 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1816 .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1817 .modulemode = MODULEMODE_SWCTRL,
1818 },
1819 },
1820 .dev_attr = &mcspi2_dev_attr,
1821 };
1823 /* mcspi3 */
1824 /* mcspi3 dev_attr */
1825 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1826 .num_chipselect = 2,
1827 };
1829 static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1830 .name = "mcspi3",
1831 .class = &dra7xx_mcspi_hwmod_class,
1832 .clkdm_name = "l4per_clkdm",
1833 .main_clk = "func_48m_fclk",
1834 .prcm = {
1835 .omap4 = {
1836 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1837 .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1838 .modulemode = MODULEMODE_SWCTRL,
1839 },
1840 },
1841 .dev_attr = &mcspi3_dev_attr,
1842 };
1844 /* mcspi4 */
1845 /* mcspi4 dev_attr */
1846 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1847 .num_chipselect = 1,
1848 };
1850 static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1851 .name = "mcspi4",
1852 .class = &dra7xx_mcspi_hwmod_class,
1853 .clkdm_name = "l4per_clkdm",
1854 .main_clk = "func_48m_fclk",
1855 .prcm = {
1856 .omap4 = {
1857 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1858 .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1859 .modulemode = MODULEMODE_SWCTRL,
1860 },
1861 },
1862 .dev_attr = &mcspi4_dev_attr,
1863 };
1865 /*
1866 * 'mcasp' class
1867 *
1868 */
1869 static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc = {
1870 .sysc_offs = 0x0004,
1871 .sysc_flags = SYSC_HAS_SIDLEMODE,
1872 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1873 .sysc_fields = &omap_hwmod_sysc_type3,
1874 };
1876 static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
1877 .name = "mcasp",
1878 .sysc = &dra7xx_mcasp_sysc,
1879 };
1881 /* mcasp2 */
1882 static struct omap_hwmod dra7xx_mcasp2_hwmod = {
1883 .name = "mcasp2",
1884 .class = &dra7xx_mcasp_hwmod_class,
1885 .clkdm_name = "l4per2_clkdm",
1886 .main_clk = "mcasp2_ahclkx_mux",
1887 .flags = HWMOD_SWSUP_SIDLE_ACT,
1888 .prcm = {
1889 .omap4 = {
1890 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,
1891 .context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
1892 .modulemode = MODULEMODE_SWCTRL,
1893 },
1894 },
1895 };
1897 /* mcasp3 */
1898 static struct omap_hwmod dra7xx_mcasp3_hwmod = {
1899 .name = "mcasp3",
1900 .class = &dra7xx_mcasp_hwmod_class,
1901 .clkdm_name = "l4per2_clkdm",
1902 .main_clk = "mcasp3_ahclkx_mux",
1903 .flags = HWMOD_SWSUP_SIDLE,
1904 .prcm = {
1905 .omap4 = {
1906 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET,
1907 .context_offs = DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET,
1908 .modulemode = MODULEMODE_SWCTRL,
1909 },
1910 },
1911 };
1913 /* mcasp6 */
1914 static struct omap_hwmod dra7xx_mcasp6_hwmod = {
1915 .name = "mcasp6",
1916 .class = &dra7xx_mcasp_hwmod_class,
1917 .clkdm_name = "l4per2_clkdm",
1918 .main_clk = "mcasp6_ahclkx_mux",
1919 .flags = HWMOD_SWSUP_SIDLE_ACT,
1920 .prcm = {
1921 .omap4 = {
1922 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,
1923 .context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
1924 .modulemode = MODULEMODE_SWCTRL,
1925 },
1926 },
1927 };
1929 /* mcasp7 */
1930 static struct omap_hwmod dra7xx_mcasp7_hwmod = {
1931 .name = "mcasp7",
1932 .class = &dra7xx_mcasp_hwmod_class,
1933 .clkdm_name = "l4per2_clkdm",
1934 .main_clk = "mcasp7_ahclkx_mux",
1935 .flags = HWMOD_SWSUP_SIDLE_ACT,
1936 .prcm = {
1937 .omap4 = {
1938 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET,
1939 .context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,
1940 .modulemode = MODULEMODE_SWCTRL,
1941 },
1942 },
1943 };
1945 /* mcasp8 */
1946 static struct omap_hwmod dra7xx_mcasp8_hwmod = {
1947 .name = "mcasp8",
1948 .class = &dra7xx_mcasp_hwmod_class,
1949 .clkdm_name = "l4per2_clkdm",
1950 .main_clk = "mcasp8_ahclkx_mux",
1951 .flags = HWMOD_SWSUP_SIDLE_ACT,
1952 .prcm = {
1953 .omap4 = {
1954 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,
1955 .context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
1956 .modulemode = MODULEMODE_SWCTRL,
1957 },
1958 },
1959 };
1961 /*
1962 * 'mmc' class
1963 *
1964 */
1966 static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1967 .rev_offs = 0x0000,
1968 .sysc_offs = 0x0010,
1969 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1970 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1971 SYSC_HAS_SOFTRESET),
1972 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1973 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1974 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1975 .sysc_fields = &omap_hwmod_sysc_type2,
1976 };
1978 static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1979 .name = "mmc",
1980 .sysc = &dra7xx_mmc_sysc,
1981 };
1983 /* mmc1 */
1984 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1985 { .role = "clk32k", .clk = "mmc1_clk32k" },
1986 };
1988 /* mmc1 dev_attr */
1989 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1990 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1991 };
1993 static struct omap_hwmod dra7xx_mmc1_hwmod = {
1994 .name = "mmc1",
1995 .class = &dra7xx_mmc_hwmod_class,
1996 .clkdm_name = "l3init_clkdm",
1997 .main_clk = "mmc1_fclk_div",
1998 .prcm = {
1999 .omap4 = {
2000 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2001 .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2002 .modulemode = MODULEMODE_SWCTRL,
2003 },
2004 },
2005 .opt_clks = mmc1_opt_clks,
2006 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
2007 .dev_attr = &mmc1_dev_attr,
2008 };
2010 /* mmc2 */
2011 static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
2012 { .role = "clk32k", .clk = "mmc2_clk32k" },
2013 };
2015 static struct omap_hwmod dra7xx_mmc2_hwmod = {
2016 .name = "mmc2",
2017 .class = &dra7xx_mmc_hwmod_class,
2018 .clkdm_name = "l3init_clkdm",
2019 .main_clk = "mmc2_fclk_div",
2020 .prcm = {
2021 .omap4 = {
2022 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2023 .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2024 .modulemode = MODULEMODE_SWCTRL,
2025 },
2026 },
2027 .opt_clks = mmc2_opt_clks,
2028 .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks),
2029 };
2031 /* mmc3 */
2032 static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
2033 { .role = "clk32k", .clk = "mmc3_clk32k" },
2034 };
2036 static struct omap_hwmod dra7xx_mmc3_hwmod = {
2037 .name = "mmc3",
2038 .class = &dra7xx_mmc_hwmod_class,
2039 .clkdm_name = "l4per_clkdm",
2040 .main_clk = "mmc3_gfclk_div",
2041 .prcm = {
2042 .omap4 = {
2043 .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
2044 .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
2045 .modulemode = MODULEMODE_SWCTRL,
2046 },
2047 },
2048 .opt_clks = mmc3_opt_clks,
2049 .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks),
2050 };
2052 /* mmc4 */
2053 static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
2054 { .role = "clk32k", .clk = "mmc4_clk32k" },
2055 };
2057 static struct omap_hwmod dra7xx_mmc4_hwmod = {
2058 .name = "mmc4",
2059 .class = &dra7xx_mmc_hwmod_class,
2060 .clkdm_name = "l4per_clkdm",
2061 .main_clk = "mmc4_gfclk_div",
2062 .prcm = {
2063 .omap4 = {
2064 .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
2065 .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
2066 .modulemode = MODULEMODE_SWCTRL,
2067 },
2068 },
2069 .opt_clks = mmc4_opt_clks,
2070 .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks),
2071 };
2073 /*
2074 * 'mmu' class
2075 * The memory management unit performs virtual to physical address translation
2076 * for its requestors.
2077 */
2079 static struct omap_hwmod_class_sysconfig dra7xx_mmu_sysc = {
2080 .rev_offs = 0x0000,
2081 .sysc_offs = 0x0010,
2082 .syss_offs = 0x0014,
2083 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2084 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2085 SYSS_HAS_RESET_STATUS),
2086 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2087 .sysc_fields = &omap_hwmod_sysc_type1,
2088 };
2090 static struct omap_hwmod_class dra7xx_mmu_hwmod_class = {
2091 .name = "mmu",
2092 .sysc = &dra7xx_mmu_sysc,
2093 };
2095 /* DSP MMUs */
2096 static struct omap_hwmod_rst_info dra7xx_mmu_dsp_resets[] = {
2097 { .name = "mmu_cache", .rst_shift = 1 },
2098 };
2100 /* mmu0 - dsp1 */
2101 static struct omap_hwmod dra7xx_mmu0_dsp1_hwmod = {
2102 .name = "mmu0_dsp1",
2103 .class = &dra7xx_mmu_hwmod_class,
2104 .clkdm_name = "dsp1_clkdm",
2105 .rst_lines = dra7xx_mmu_dsp_resets,
2106 .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_dsp_resets),
2107 .main_clk = "dpll_dsp_m2_ck",
2108 .prcm = {
2109 .omap4 = {
2110 .clkctrl_offs = DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET,
2111 .rstctrl_offs = DRA7XX_RM_DSP1_RSTCTRL_OFFSET,
2112 .context_offs = DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET,
2113 .modulemode = MODULEMODE_HWCTRL,
2114 },
2115 },
2116 };
2118 /* mmu1 - dsp1 */
2119 static struct omap_hwmod dra7xx_mmu1_dsp1_hwmod = {
2120 .name = "mmu1_dsp1",
2121 .class = &dra7xx_mmu_hwmod_class,
2122 .clkdm_name = "dsp1_clkdm",
2123 .rst_lines = dra7xx_mmu_dsp_resets,
2124 .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_dsp_resets),
2125 .main_clk = "dpll_dsp_m2_ck",
2126 .prcm = {
2127 .omap4 = {
2128 .clkctrl_offs = DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET,
2129 .rstctrl_offs = DRA7XX_RM_DSP1_RSTCTRL_OFFSET,
2130 .context_offs = DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET,
2131 .modulemode = MODULEMODE_HWCTRL,
2132 },
2133 },
2134 };
2136 /* mmu0 - dsp2 */
2137 static struct omap_hwmod dra7xx_mmu0_dsp2_hwmod = {
2138 .name = "mmu0_dsp2",
2139 .class = &dra7xx_mmu_hwmod_class,
2140 .clkdm_name = "dsp2_clkdm",
2141 .rst_lines = dra7xx_mmu_dsp_resets,
2142 .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_dsp_resets),
2143 .main_clk = "dpll_dsp_m2_ck",
2144 .prcm = {
2145 .omap4 = {
2146 .clkctrl_offs = DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET,
2147 .rstctrl_offs = DRA7XX_RM_DSP2_RSTCTRL_OFFSET,
2148 .context_offs = DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET,
2149 .modulemode = MODULEMODE_HWCTRL,
2150 },
2151 },
2152 };
2154 /* mmu1 - dsp2 */
2155 static struct omap_hwmod dra7xx_mmu1_dsp2_hwmod = {
2156 .name = "mmu1_dsp2",
2157 .class = &dra7xx_mmu_hwmod_class,
2158 .clkdm_name = "dsp2_clkdm",
2159 .rst_lines = dra7xx_mmu_dsp_resets,
2160 .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_dsp_resets),
2161 .main_clk = "dpll_dsp_m2_ck",
2162 .prcm = {
2163 .omap4 = {
2164 .clkctrl_offs = DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET,
2165 .rstctrl_offs = DRA7XX_RM_DSP2_RSTCTRL_OFFSET,
2166 .context_offs = DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET,
2167 .modulemode = MODULEMODE_HWCTRL,
2168 },
2169 },
2170 };
2172 /* IPU MMUs */
2173 static struct omap_hwmod_rst_info dra7xx_mmu_ipu_resets[] = {
2174 { .name = "mmu_cache", .rst_shift = 2 },
2175 };
2177 /* mmu ipu1 */
2178 static struct omap_hwmod dra7xx_mmu_ipu1_hwmod = {
2179 .name = "mmu_ipu1",
2180 .class = &dra7xx_mmu_hwmod_class,
2181 .clkdm_name = "ipu1_clkdm",
2182 .rst_lines = dra7xx_mmu_ipu_resets,
2183 .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_ipu_resets),
2184 .main_clk = "ipu1_gfclk_mux",
2185 .prcm = {
2186 .omap4 = {
2187 .clkctrl_offs = DRA7XX_CM_IPU1_IPU1_CLKCTRL_OFFSET,
2188 .rstctrl_offs = DRA7XX_RM_IPU1_RSTCTRL_OFFSET,
2189 .context_offs = DRA7XX_RM_IPU1_IPU1_CONTEXT_OFFSET,
2190 .modulemode = MODULEMODE_HWCTRL,
2191 },
2192 },
2193 };
2195 /* mmu ipu2 */
2196 static struct omap_hwmod dra7xx_mmu_ipu2_hwmod = {
2197 .name = "mmu_ipu2",
2198 .class = &dra7xx_mmu_hwmod_class,
2199 .clkdm_name = "ipu2_clkdm",
2200 .rst_lines = dra7xx_mmu_ipu_resets,
2201 .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_ipu_resets),
2202 .main_clk = "dpll_core_h22x2_ck",
2203 .prcm = {
2204 .omap4 = {
2205 .clkctrl_offs = DRA7XX_CM_IPU2_IPU2_CLKCTRL_OFFSET,
2206 .rstctrl_offs = DRA7XX_RM_IPU2_RSTCTRL_OFFSET,
2207 .context_offs = DRA7XX_RM_IPU2_IPU2_CONTEXT_OFFSET,
2208 .modulemode = MODULEMODE_HWCTRL,
2209 },
2210 },
2211 };
2213 /*
2214 * 'mpu' class
2215 *
2216 */
2218 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
2219 .name = "mpu",
2220 };
2222 /* mpu */
2223 static struct omap_hwmod dra7xx_mpu_hwmod = {
2224 .name = "mpu",
2225 .class = &dra7xx_mpu_hwmod_class,
2226 .clkdm_name = "mpu_clkdm",
2227 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2228 .main_clk = "dpll_mpu_m2_ck",
2229 .prcm = {
2230 .omap4 = {
2231 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
2232 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
2233 },
2234 },
2235 };
2237 /*
2238 * 'ocp2scp' class
2239 *
2240 */
2242 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
2243 .rev_offs = 0x0000,
2244 .sysc_offs = 0x0010,
2245 .syss_offs = 0x0014,
2246 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2247 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2248 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2249 SIDLE_SMART_WKUP),
2250 .sysc_fields = &omap_hwmod_sysc_type1,
2251 };
2253 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
2254 .name = "ocp2scp",
2255 .sysc = &dra7xx_ocp2scp_sysc,
2256 };
2258 /* ocp2scp1 */
2259 static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
2260 .name = "ocp2scp1",
2261 .class = &dra7xx_ocp2scp_hwmod_class,
2262 .clkdm_name = "l3init_clkdm",
2263 .main_clk = "l4_root_clk_div",
2264 .prcm = {
2265 .omap4 = {
2266 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
2267 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
2268 .modulemode = MODULEMODE_HWCTRL,
2269 },
2270 },
2271 };
2273 /* ocp2scp3 */
2274 static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
2275 .name = "ocp2scp3",
2276 .class = &dra7xx_ocp2scp_hwmod_class,
2277 .clkdm_name = "l3init_clkdm",
2278 .main_clk = "l4_root_clk_div",
2279 .prcm = {
2280 .omap4 = {
2281 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
2282 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
2283 .modulemode = MODULEMODE_HWCTRL,
2284 },
2285 },
2286 };
2288 /*
2289 * 'PCIE' class
2290 *
2291 */
2293 static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
2294 .name = "pcie",
2295 };
2297 /* pcie1 */
2298 static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = {
2299 { .name = "pcie", .rst_shift = 0 },
2300 };
2302 static struct omap_hwmod dra7xx_pciess1_hwmod = {
2303 .name = "pcie1",
2304 .class = &dra7xx_pciess_hwmod_class,
2305 .clkdm_name = "pcie_clkdm",
2306 .rst_lines = dra7xx_pciess1_resets,
2307 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess1_resets),
2308 .main_clk = "l4_root_clk_div",
2309 .prcm = {
2310 .omap4 = {
2311 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
2312 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
2313 .rstctrl_offs = DRA7XX_RM_L3INIT_RSTCTRL_OFFSET,
2314 .modulemode = MODULEMODE_SWCTRL,
2315 },
2316 },
2317 };
2319 /* pcie2 */
2320 static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = {
2321 { .name = "pcie", .rst_shift = 1 },
2322 };
2324 static struct omap_hwmod dra7xx_pciess2_hwmod = {
2325 .name = "pcie2",
2326 .class = &dra7xx_pciess_hwmod_class,
2327 .clkdm_name = "pcie_clkdm",
2328 .rst_lines = dra7xx_pciess2_resets,
2329 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess2_resets),
2330 .main_clk = "l4_root_clk_div",
2331 .prcm = {
2332 .omap4 = {
2333 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
2334 .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
2335 .rstctrl_offs = DRA7XX_RM_L3INIT_RSTCTRL_OFFSET,
2336 .modulemode = MODULEMODE_SWCTRL,
2337 },
2338 },
2339 };
2341 /*
2342 * 'pru-icss' class
2343 * Programmable Real-Time Unit and Industrial Communication Subsystem
2344 */
2345 static struct omap_hwmod_class dra7xx_pruss_hwmod_class = {
2346 .name = "pruss",
2347 };
2349 /* pru-icss1 */
2350 static struct omap_hwmod dra7xx_pruss1_hwmod = {
2351 .name = "pruss1",
2352 .class = &dra7xx_pruss_hwmod_class,
2353 .clkdm_name = "l4per2_clkdm",
2354 .prcm = {
2355 .omap4 = {
2356 .clkctrl_offs = DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL_OFFSET,
2357 .context_offs = DRA7XX_RM_L4PER2_PRUSS1_CONTEXT_OFFSET,
2358 .modulemode = MODULEMODE_SWCTRL,
2359 },
2360 },
2361 };
2363 /* pru-icss2 */
2364 static struct omap_hwmod dra7xx_pruss2_hwmod = {
2365 .name = "pruss2",
2366 .class = &dra7xx_pruss_hwmod_class,
2367 .clkdm_name = "l4per2_clkdm",
2368 .prcm = {
2369 .omap4 = {
2370 .clkctrl_offs = DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL_OFFSET,
2371 .context_offs = DRA7XX_RM_L4PER2_PRUSS2_CONTEXT_OFFSET,
2372 .modulemode = MODULEMODE_SWCTRL,
2373 },
2374 },
2375 };
2377 /*
2378 * 'qspi' class
2379 *
2380 */
2382 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
2383 .sysc_offs = 0x0010,
2384 .sysc_flags = SYSC_HAS_SIDLEMODE,
2385 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2386 SIDLE_SMART_WKUP),
2387 .sysc_fields = &omap_hwmod_sysc_type2,
2388 };
2390 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
2391 .name = "qspi",
2392 .sysc = &dra7xx_qspi_sysc,
2393 };
2395 /* qspi */
2396 static struct omap_hwmod dra7xx_qspi_hwmod = {
2397 .name = "qspi",
2398 .class = &dra7xx_qspi_hwmod_class,
2399 .clkdm_name = "l4per2_clkdm",
2400 .main_clk = "qspi_gfclk_div",
2401 .prcm = {
2402 .omap4 = {
2403 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
2404 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
2405 .modulemode = MODULEMODE_SWCTRL,
2406 },
2407 },
2408 };
2410 /*
2411 * 'rtcss' class
2412 *
2413 */
2414 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
2415 .sysc_offs = 0x0078,
2416 .sysc_flags = SYSC_HAS_SIDLEMODE,
2417 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2418 SIDLE_SMART_WKUP),
2419 .sysc_fields = &omap_hwmod_sysc_type3,
2420 };
2422 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
2423 .name = "rtcss",
2424 .sysc = &dra7xx_rtcss_sysc,
2425 .reset = &omap_hwmod_rtc_unlock,
2426 };
2428 /* rtcss */
2429 static struct omap_hwmod dra7xx_rtcss_hwmod = {
2430 .name = "rtcss",
2431 .class = &dra7xx_rtcss_hwmod_class,
2432 .clkdm_name = "rtc_clkdm",
2433 .main_clk = "sys_32k_ck",
2434 .prcm = {
2435 .omap4 = {
2436 .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
2437 .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
2438 .modulemode = MODULEMODE_SWCTRL,
2439 },
2440 },
2441 };
2443 /*
2444 * 'sata' class
2445 *
2446 */
2448 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
2449 .sysc_offs = 0x0000,
2450 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
2451 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2452 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2453 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2454 .sysc_fields = &omap_hwmod_sysc_type2,
2455 };
2457 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
2458 .name = "sata",
2459 .sysc = &dra7xx_sata_sysc,
2460 };
2462 /* sata */
2464 static struct omap_hwmod dra7xx_sata_hwmod = {
2465 .name = "sata",
2466 .class = &dra7xx_sata_hwmod_class,
2467 .clkdm_name = "l3init_clkdm",
2468 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2469 .main_clk = "func_48m_fclk",
2470 .mpu_rt_idx = 1,
2471 .prcm = {
2472 .omap4 = {
2473 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
2474 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
2475 .modulemode = MODULEMODE_SWCTRL,
2476 },
2477 },
2478 };
2480 /*
2481 * 'smartreflex' class
2482 *
2483 */
2485 /* The IP is not compliant to type1 / type2 scheme */
2486 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2487 .sidle_shift = 24,
2488 .enwkup_shift = 26,
2489 };
2491 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
2492 .sysc_offs = 0x0038,
2493 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2494 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2495 SIDLE_SMART_WKUP),
2496 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
2497 };
2499 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
2500 .name = "smartreflex",
2501 .sysc = &dra7xx_smartreflex_sysc,
2502 .rev = 2,
2503 };
2505 /* smartreflex_core */
2506 /* smartreflex_core dev_attr */
2507 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2508 .sensor_voltdm_name = "core",
2509 };
2511 static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
2512 .name = "smartreflex_core",
2513 .class = &dra7xx_smartreflex_hwmod_class,
2514 .clkdm_name = "coreaon_clkdm",
2515 .main_clk = "wkupaon_iclk_mux",
2516 .prcm = {
2517 .omap4 = {
2518 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
2519 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
2520 .modulemode = MODULEMODE_SWCTRL,
2521 },
2522 },
2523 .dev_attr = &smartreflex_core_dev_attr,
2524 };
2526 /* smartreflex_mpu */
2527 /* smartreflex_mpu dev_attr */
2528 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2529 .sensor_voltdm_name = "mpu",
2530 };
2532 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
2533 .name = "smartreflex_mpu",
2534 .class = &dra7xx_smartreflex_hwmod_class,
2535 .clkdm_name = "coreaon_clkdm",
2536 .main_clk = "wkupaon_iclk_mux",
2537 .prcm = {
2538 .omap4 = {
2539 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
2540 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
2541 .modulemode = MODULEMODE_SWCTRL,
2542 },
2543 },
2544 .dev_attr = &smartreflex_mpu_dev_attr,
2545 };
2547 /*
2548 * 'spinlock' class
2549 *
2550 */
2552 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
2553 .rev_offs = 0x0000,
2554 .sysc_offs = 0x0010,
2555 .syss_offs = 0x0014,
2556 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2557 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2558 SYSS_HAS_RESET_STATUS),
2559 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2560 .sysc_fields = &omap_hwmod_sysc_type1,
2561 };
2563 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
2564 .name = "spinlock",
2565 .sysc = &dra7xx_spinlock_sysc,
2566 };
2568 /* spinlock */
2569 static struct omap_hwmod dra7xx_spinlock_hwmod = {
2570 .name = "spinlock",
2571 .class = &dra7xx_spinlock_hwmod_class,
2572 .clkdm_name = "l4cfg_clkdm",
2573 .main_clk = "l3_iclk_div",
2574 .prcm = {
2575 .omap4 = {
2576 .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
2577 .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
2578 },
2579 },
2580 };
2582 /*
2583 * 'timer' class
2584 *
2585 * This class contains several variants: ['timer_1ms', 'timer_secure',
2586 * 'timer']
2587 */
2589 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
2590 .rev_offs = 0x0000,
2591 .sysc_offs = 0x0010,
2592 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2593 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2594 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2595 SIDLE_SMART_WKUP),
2596 .sysc_fields = &omap_hwmod_sysc_type2,
2597 };
2599 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
2600 .name = "timer",
2601 .sysc = &dra7xx_timer_1ms_sysc,
2602 };
2604 static struct omap_hwmod_class_sysconfig dra7xx_timer_secure_sysc = {
2605 .rev_offs = 0x0000,
2606 .sysc_offs = 0x0010,
2607 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2608 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2609 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2610 SIDLE_SMART_WKUP),
2611 .sysc_fields = &omap_hwmod_sysc_type2,
2612 };
2614 static struct omap_hwmod_class dra7xx_timer_secure_hwmod_class = {
2615 .name = "timer",
2616 .sysc = &dra7xx_timer_secure_sysc,
2617 };
2619 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
2620 .rev_offs = 0x0000,
2621 .sysc_offs = 0x0010,
2622 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2623 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2624 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2625 SIDLE_SMART_WKUP),
2626 .sysc_fields = &omap_hwmod_sysc_type2,
2627 };
2629 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
2630 .name = "timer",
2631 .sysc = &dra7xx_timer_sysc,
2632 };
2634 /* timer1 */
2635 static struct omap_hwmod dra7xx_timer1_hwmod = {
2636 .name = "timer1",
2637 .class = &dra7xx_timer_1ms_hwmod_class,
2638 .clkdm_name = "wkupaon_clkdm",
2639 .main_clk = "timer1_gfclk_mux",
2640 .prcm = {
2641 .omap4 = {
2642 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
2643 .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
2644 .modulemode = MODULEMODE_SWCTRL,
2645 },
2646 },
2647 };
2649 /* timer2 */
2650 static struct omap_hwmod dra7xx_timer2_hwmod = {
2651 .name = "timer2",
2652 .class = &dra7xx_timer_1ms_hwmod_class,
2653 .clkdm_name = "l4per_clkdm",
2654 .main_clk = "timer2_gfclk_mux",
2655 .prcm = {
2656 .omap4 = {
2657 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
2658 .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
2659 .modulemode = MODULEMODE_SWCTRL,
2660 },
2661 },
2662 };
2664 /* timer3 */
2665 static struct omap_hwmod dra7xx_timer3_hwmod = {
2666 .name = "timer3",
2667 .class = &dra7xx_timer_hwmod_class,
2668 .clkdm_name = "l4per_clkdm",
2669 .main_clk = "timer3_gfclk_mux",
2670 .prcm = {
2671 .omap4 = {
2672 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
2673 .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
2674 .modulemode = MODULEMODE_SWCTRL,
2675 },
2676 },
2677 };
2679 /* timer4 */
2680 static struct omap_hwmod dra7xx_timer4_hwmod = {
2681 .name = "timer4",
2682 .class = &dra7xx_timer_hwmod_class,
2683 .clkdm_name = "l4per_clkdm",
2684 .main_clk = "timer4_gfclk_mux",
2685 .prcm = {
2686 .omap4 = {
2687 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
2688 .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
2689 .modulemode = MODULEMODE_SWCTRL,
2690 },
2691 },
2692 };
2694 /* timer5 */
2695 static struct omap_hwmod dra7xx_timer5_hwmod = {
2696 .name = "timer5",
2697 .class = &dra7xx_timer_hwmod_class,
2698 .clkdm_name = "ipu_clkdm",
2699 .main_clk = "timer5_gfclk_mux",
2700 .prcm = {
2701 .omap4 = {
2702 .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
2703 .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
2704 .modulemode = MODULEMODE_SWCTRL,
2705 },
2706 },
2707 };
2709 /* timer6 */
2710 static struct omap_hwmod dra7xx_timer6_hwmod = {
2711 .name = "timer6",
2712 .class = &dra7xx_timer_hwmod_class,
2713 .clkdm_name = "ipu_clkdm",
2714 .main_clk = "timer6_gfclk_mux",
2715 .prcm = {
2716 .omap4 = {
2717 .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
2718 .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
2719 .modulemode = MODULEMODE_SWCTRL,
2720 },
2721 },
2722 };
2724 /* timer7 */
2725 static struct omap_hwmod dra7xx_timer7_hwmod = {
2726 .name = "timer7",
2727 .class = &dra7xx_timer_hwmod_class,
2728 .clkdm_name = "ipu_clkdm",
2729 .main_clk = "timer7_gfclk_mux",
2730 .prcm = {
2731 .omap4 = {
2732 .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
2733 .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
2734 .modulemode = MODULEMODE_SWCTRL,
2735 },
2736 },
2737 };
2739 /* timer8 */
2740 static struct omap_hwmod dra7xx_timer8_hwmod = {
2741 .name = "timer8",
2742 .class = &dra7xx_timer_hwmod_class,
2743 .clkdm_name = "ipu_clkdm",
2744 .main_clk = "timer8_gfclk_mux",
2745 .prcm = {
2746 .omap4 = {
2747 .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
2748 .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
2749 .modulemode = MODULEMODE_SWCTRL,
2750 },
2751 },
2752 };
2754 /* timer9 */
2755 static struct omap_hwmod dra7xx_timer9_hwmod = {
2756 .name = "timer9",
2757 .class = &dra7xx_timer_hwmod_class,
2758 .clkdm_name = "l4per_clkdm",
2759 .main_clk = "timer9_gfclk_mux",
2760 .prcm = {
2761 .omap4 = {
2762 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
2763 .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
2764 .modulemode = MODULEMODE_SWCTRL,
2765 },
2766 },
2767 };
2769 /* timer10 */
2770 static struct omap_hwmod dra7xx_timer10_hwmod = {
2771 .name = "timer10",
2772 .class = &dra7xx_timer_1ms_hwmod_class,
2773 .clkdm_name = "l4per_clkdm",
2774 .main_clk = "timer10_gfclk_mux",
2775 .prcm = {
2776 .omap4 = {
2777 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
2778 .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
2779 .modulemode = MODULEMODE_SWCTRL,
2780 },
2781 },
2782 };
2784 /* timer11 */
2785 static struct omap_hwmod dra7xx_timer11_hwmod = {
2786 .name = "timer11",
2787 .class = &dra7xx_timer_hwmod_class,
2788 .clkdm_name = "l4per_clkdm",
2789 .main_clk = "timer11_gfclk_mux",
2790 .prcm = {
2791 .omap4 = {
2792 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
2793 .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
2794 .modulemode = MODULEMODE_SWCTRL,
2795 },
2796 },
2797 };
2799 /* timer12 */
2800 static struct omap_hwmod dra7xx_timer12_hwmod = {
2801 .name = "timer12",
2802 .class = &dra7xx_timer_secure_hwmod_class,
2803 .clkdm_name = "wkupaon_clkdm",
2804 .main_clk = "secure_32k_clk_src_ck",
2805 .prcm = {
2806 .omap4 = {
2807 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET,
2808 .context_offs = DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET,
2809 },
2810 },
2811 };
2813 /* timer13 */
2814 static struct omap_hwmod dra7xx_timer13_hwmod = {
2815 .name = "timer13",
2816 .class = &dra7xx_timer_hwmod_class,
2817 .clkdm_name = "l4per3_clkdm",
2818 .main_clk = "timer13_gfclk_mux",
2819 .prcm = {
2820 .omap4 = {
2821 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
2822 .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
2823 .modulemode = MODULEMODE_SWCTRL,
2824 },
2825 },
2826 };
2828 /* timer14 */
2829 static struct omap_hwmod dra7xx_timer14_hwmod = {
2830 .name = "timer14",
2831 .class = &dra7xx_timer_hwmod_class,
2832 .clkdm_name = "l4per3_clkdm",
2833 .main_clk = "timer14_gfclk_mux",
2834 .prcm = {
2835 .omap4 = {
2836 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
2837 .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
2838 .modulemode = MODULEMODE_SWCTRL,
2839 },
2840 },
2841 };
2843 /* timer15 */
2844 static struct omap_hwmod dra7xx_timer15_hwmod = {
2845 .name = "timer15",
2846 .class = &dra7xx_timer_hwmod_class,
2847 .clkdm_name = "l4per3_clkdm",
2848 .main_clk = "timer15_gfclk_mux",
2849 .prcm = {
2850 .omap4 = {
2851 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
2852 .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
2853 .modulemode = MODULEMODE_SWCTRL,
2854 },
2855 },
2856 };
2858 /* timer16 */
2859 static struct omap_hwmod dra7xx_timer16_hwmod = {
2860 .name = "timer16",
2861 .class = &dra7xx_timer_hwmod_class,
2862 .clkdm_name = "l4per3_clkdm",
2863 .main_clk = "timer16_gfclk_mux",
2864 .prcm = {
2865 .omap4 = {
2866 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
2867 .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
2868 .modulemode = MODULEMODE_SWCTRL,
2869 },
2870 },
2871 };
2873 /*
2874 * 'uart' class
2875 *
2876 */
2878 static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
2879 .rev_offs = 0x0050,
2880 .sysc_offs = 0x0054,
2881 .syss_offs = 0x0058,
2882 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2883 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2884 SYSS_HAS_RESET_STATUS),
2885 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2886 SIDLE_SMART_WKUP),
2887 .sysc_fields = &omap_hwmod_sysc_type1,
2888 };
2890 static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
2891 .name = "uart",
2892 .sysc = &dra7xx_uart_sysc,
2893 };
2895 /* uart1 */
2896 static struct omap_hwmod dra7xx_uart1_hwmod = {
2897 .name = "uart1",
2898 .class = &dra7xx_uart_hwmod_class,
2899 .clkdm_name = "l4per_clkdm",
2900 .main_clk = "uart1_gfclk_mux",
2901 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
2902 .prcm = {
2903 .omap4 = {
2904 .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
2905 .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
2906 .modulemode = MODULEMODE_SWCTRL,
2907 },
2908 },
2909 };
2911 /* uart2 */
2912 static struct omap_hwmod dra7xx_uart2_hwmod = {
2913 .name = "uart2",
2914 .class = &dra7xx_uart_hwmod_class,
2915 .clkdm_name = "l4per_clkdm",
2916 .main_clk = "uart2_gfclk_mux",
2917 .flags = HWMOD_SWSUP_SIDLE_ACT,
2918 .prcm = {
2919 .omap4 = {
2920 .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
2921 .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
2922 .modulemode = MODULEMODE_SWCTRL,
2923 },
2924 },
2925 };
2927 /* uart3 */
2928 static struct omap_hwmod dra7xx_uart3_hwmod = {
2929 .name = "uart3",
2930 .class = &dra7xx_uart_hwmod_class,
2931 .clkdm_name = "l4per_clkdm",
2932 .main_clk = "uart3_gfclk_mux",
2933 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART3_FLAGS,
2934 .prcm = {
2935 .omap4 = {
2936 .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
2937 .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
2938 .modulemode = MODULEMODE_SWCTRL,
2939 },
2940 },
2941 };
2943 /* uart4 */
2944 static struct omap_hwmod dra7xx_uart4_hwmod = {
2945 .name = "uart4",
2946 .class = &dra7xx_uart_hwmod_class,
2947 .clkdm_name = "l4per_clkdm",
2948 .main_clk = "uart4_gfclk_mux",
2949 .flags = HWMOD_SWSUP_SIDLE_ACT,
2950 .prcm = {
2951 .omap4 = {
2952 .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
2953 .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
2954 .modulemode = MODULEMODE_SWCTRL,
2955 },
2956 },
2957 };
2959 /* uart5 */
2960 static struct omap_hwmod dra7xx_uart5_hwmod = {
2961 .name = "uart5",
2962 .class = &dra7xx_uart_hwmod_class,
2963 .clkdm_name = "l4per_clkdm",
2964 .main_clk = "uart5_gfclk_mux",
2965 .flags = HWMOD_SWSUP_SIDLE_ACT,
2966 .prcm = {
2967 .omap4 = {
2968 .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
2969 .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
2970 .modulemode = MODULEMODE_SWCTRL,
2971 },
2972 },
2973 };
2975 /* uart6 */
2976 static struct omap_hwmod dra7xx_uart6_hwmod = {
2977 .name = "uart6",
2978 .class = &dra7xx_uart_hwmod_class,
2979 .clkdm_name = "ipu_clkdm",
2980 .main_clk = "uart6_gfclk_mux",
2981 .flags = HWMOD_SWSUP_SIDLE_ACT,
2982 .prcm = {
2983 .omap4 = {
2984 .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
2985 .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
2986 .modulemode = MODULEMODE_SWCTRL,
2987 },
2988 },
2989 };
2991 /* uart7 */
2992 static struct omap_hwmod dra7xx_uart7_hwmod = {
2993 .name = "uart7",
2994 .class = &dra7xx_uart_hwmod_class,
2995 .clkdm_name = "l4per2_clkdm",
2996 .main_clk = "uart7_gfclk_mux",
2997 .flags = HWMOD_SWSUP_SIDLE_ACT,
2998 .prcm = {
2999 .omap4 = {
3000 .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
3001 .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
3002 .modulemode = MODULEMODE_SWCTRL,
3003 },
3004 },
3005 };
3007 /* uart8 */
3008 static struct omap_hwmod dra7xx_uart8_hwmod = {
3009 .name = "uart8",
3010 .class = &dra7xx_uart_hwmod_class,
3011 .clkdm_name = "l4per2_clkdm",
3012 .main_clk = "uart8_gfclk_mux",
3013 .flags = HWMOD_SWSUP_SIDLE_ACT,
3014 .prcm = {
3015 .omap4 = {
3016 .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
3017 .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
3018 .modulemode = MODULEMODE_SWCTRL,
3019 },
3020 },
3021 };
3023 /* uart9 */
3024 static struct omap_hwmod dra7xx_uart9_hwmod = {
3025 .name = "uart9",
3026 .class = &dra7xx_uart_hwmod_class,
3027 .clkdm_name = "l4per2_clkdm",
3028 .main_clk = "uart9_gfclk_mux",
3029 .flags = HWMOD_SWSUP_SIDLE_ACT,
3030 .prcm = {
3031 .omap4 = {
3032 .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
3033 .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
3034 .modulemode = MODULEMODE_SWCTRL,
3035 },
3036 },
3037 };
3039 /* uart10 */
3040 static struct omap_hwmod dra7xx_uart10_hwmod = {
3041 .name = "uart10",
3042 .class = &dra7xx_uart_hwmod_class,
3043 .clkdm_name = "wkupaon_clkdm",
3044 .main_clk = "uart10_gfclk_mux",
3045 .flags = HWMOD_SWSUP_SIDLE_ACT,
3046 .prcm = {
3047 .omap4 = {
3048 .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
3049 .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
3050 .modulemode = MODULEMODE_SWCTRL,
3051 },
3052 },
3053 };
3055 /* DES (the 'P' (public) device) */
3056 static struct omap_hwmod_class_sysconfig dra7xx_des_sysc = {
3057 .rev_offs = 0x0030,
3058 .sysc_offs = 0x0034,
3059 .syss_offs = 0x0038,
3060 .sysc_flags = SYSS_HAS_RESET_STATUS,
3061 };
3063 static struct omap_hwmod_class dra7xx_des_hwmod_class = {
3064 .name = "des",
3065 .sysc = &dra7xx_des_sysc,
3066 };
3068 /* DES */
3069 static struct omap_hwmod dra7xx_des_hwmod = {
3070 .name = "des",
3071 .class = &dra7xx_des_hwmod_class,
3072 .clkdm_name = "l4sec_clkdm",
3073 .main_clk = "l3_iclk_div",
3074 .prcm = {
3075 .omap4 = {
3076 .clkctrl_offs = DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
3077 .context_offs = DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
3078 .modulemode = MODULEMODE_HWCTRL,
3079 },
3080 },
3081 };
3083 /* rng */
3084 static struct omap_hwmod_class_sysconfig dra7xx_rng_sysc = {
3085 .rev_offs = 0x1fe0,
3086 .sysc_offs = 0x1fe4,
3087 .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
3088 .idlemodes = SIDLE_FORCE | SIDLE_NO,
3089 .sysc_fields = &omap_hwmod_sysc_type1,
3090 };
3092 static struct omap_hwmod_class dra7xx_rng_hwmod_class = {
3093 .name = "rng",
3094 .sysc = &dra7xx_rng_sysc,
3095 };
3097 static struct omap_hwmod dra7xx_rng_hwmod = {
3098 .name = "rng",
3099 .class = &dra7xx_rng_hwmod_class,
3100 .flags = HWMOD_SWSUP_SIDLE,
3101 .clkdm_name = "l4sec_clkdm",
3102 .prcm = {
3103 .omap4 = {
3104 .clkctrl_offs = DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET,
3105 .context_offs = DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET,
3106 .modulemode = MODULEMODE_HWCTRL,
3107 },
3108 },
3109 };
3111 /*
3112 * 'usb_otg_ss' class
3113 *
3114 */
3116 static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
3117 .rev_offs = 0x0000,
3118 .sysc_offs = 0x0010,
3119 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
3120 SYSC_HAS_SIDLEMODE),
3121 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3122 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3123 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3124 .sysc_fields = &omap_hwmod_sysc_type2,
3125 };
3127 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
3128 .name = "usb_otg_ss",
3129 .sysc = &dra7xx_usb_otg_ss_sysc,
3130 };
3132 /* usb_otg_ss1 */
3133 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
3134 { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
3135 };
3137 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
3138 .name = "usb_otg_ss1",
3139 .class = &dra7xx_usb_otg_ss_hwmod_class,
3140 .clkdm_name = "l3init_clkdm",
3141 .main_clk = "dpll_core_h13x2_ck",
3142 .prcm = {
3143 .omap4 = {
3144 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
3145 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
3146 .modulemode = MODULEMODE_HWCTRL,
3147 },
3148 },
3149 .opt_clks = usb_otg_ss1_opt_clks,
3150 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
3151 };
3153 /* usb_otg_ss2 */
3154 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
3155 { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
3156 };
3158 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
3159 .name = "usb_otg_ss2",
3160 .class = &dra7xx_usb_otg_ss_hwmod_class,
3161 .clkdm_name = "l3init_clkdm",
3162 .main_clk = "dpll_core_h13x2_ck",
3163 .prcm = {
3164 .omap4 = {
3165 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
3166 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
3167 .modulemode = MODULEMODE_HWCTRL,
3168 },
3169 },
3170 .opt_clks = usb_otg_ss2_opt_clks,
3171 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
3172 };
3174 /* usb_otg_ss3 */
3175 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
3176 .name = "usb_otg_ss3",
3177 .class = &dra7xx_usb_otg_ss_hwmod_class,
3178 .clkdm_name = "l3init_clkdm",
3179 .main_clk = "dpll_core_h13x2_ck",
3180 .prcm = {
3181 .omap4 = {
3182 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
3183 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
3184 .modulemode = MODULEMODE_HWCTRL,
3185 },
3186 },
3187 };
3189 /* usb_otg_ss4 */
3190 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
3191 .name = "usb_otg_ss4",
3192 .class = &dra7xx_usb_otg_ss_hwmod_class,
3193 .clkdm_name = "l3init_clkdm",
3194 .main_clk = "dpll_core_h13x2_ck",
3195 .prcm = {
3196 .omap4 = {
3197 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
3198 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
3199 .modulemode = MODULEMODE_HWCTRL,
3200 },
3201 },
3202 };
3204 /*
3205 * 'vcp' class
3206 *
3207 */
3209 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
3210 .name = "vcp",
3211 };
3213 /* vcp1 */
3214 static struct omap_hwmod dra7xx_vcp1_hwmod = {
3215 .name = "vcp1",
3216 .class = &dra7xx_vcp_hwmod_class,
3217 .clkdm_name = "l3main1_clkdm",
3218 .main_clk = "l3_iclk_div",
3219 .prcm = {
3220 .omap4 = {
3221 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
3222 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
3223 },
3224 },
3225 };
3227 /* vcp2 */
3228 static struct omap_hwmod dra7xx_vcp2_hwmod = {
3229 .name = "vcp2",
3230 .class = &dra7xx_vcp_hwmod_class,
3231 .clkdm_name = "l3main1_clkdm",
3232 .main_clk = "l3_iclk_div",
3233 .prcm = {
3234 .omap4 = {
3235 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
3236 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
3237 },
3238 },
3239 };
3241 /*
3242 * 'wd_timer' class
3243 *
3244 */
3246 static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
3247 .rev_offs = 0x0000,
3248 .sysc_offs = 0x0010,
3249 .syss_offs = 0x0014,
3250 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3251 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3252 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3253 SIDLE_SMART_WKUP),
3254 .sysc_fields = &omap_hwmod_sysc_type1,
3255 };
3257 static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
3258 .name = "wd_timer",
3259 .sysc = &dra7xx_wd_timer_sysc,
3260 .pre_shutdown = &omap2_wd_timer_disable,
3261 .reset = &omap2_wd_timer_reset,
3262 };
3264 /* wd_timer2 */
3265 static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
3266 .name = "wd_timer2",
3267 .class = &dra7xx_wd_timer_hwmod_class,
3268 .clkdm_name = "wkupaon_clkdm",
3269 .main_clk = "sys_32k_ck",
3270 .prcm = {
3271 .omap4 = {
3272 .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
3273 .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
3274 .modulemode = MODULEMODE_SWCTRL,
3275 },
3276 },
3277 };
3280 /*
3281 * Interfaces
3282 */
3284 /* l3_main_2 -> l3_instr */
3285 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
3286 .master = &dra7xx_l3_main_2_hwmod,
3287 .slave = &dra7xx_l3_instr_hwmod,
3288 .clk = "l3_iclk_div",
3289 .user = OCP_USER_MPU | OCP_USER_SDMA,
3290 };
3292 /* l4_cfg -> l3_main_1 */
3293 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
3294 .master = &dra7xx_l4_cfg_hwmod,
3295 .slave = &dra7xx_l3_main_1_hwmod,
3296 .clk = "l3_iclk_div",
3297 .user = OCP_USER_MPU | OCP_USER_SDMA,
3298 };
3300 /*
3301 * Interfaces
3302 */
3304 static struct omap_hwmod_addr_space dra7xx_dmm_addrs[] = {
3305 {
3306 .pa_start = 0x4e000000,
3307 .pa_end = 0x4e0007ff,
3308 .flags = ADDR_TYPE_RT
3309 },
3310 { }
3311 };
3313 /* l3_main_1 -> dmm */
3314 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
3315 .master = &dra7xx_l3_main_1_hwmod,
3316 .slave = &dra7xx_dmm_hwmod,
3317 .clk = "l3_iclk_div",
3318 .addr = dra7xx_dmm_addrs,
3319 .user = OCP_USER_SDMA,
3320 };
3322 /* dmm -> emif_ocp_fw */
3323 static struct omap_hwmod_ocp_if dra7xx_dmm__emif_ocp_fw = {
3324 .master = &dra7xx_dmm_hwmod,
3325 .slave = &dra7xx_emif_ocp_fw_hwmod,
3326 .clk = "l3_iclk_div",
3327 .user = OCP_USER_MPU | OCP_USER_SDMA,
3328 };
3330 /* mpu -> l3_main_1 */
3331 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
3332 .master = &dra7xx_mpu_hwmod,
3333 .slave = &dra7xx_l3_main_1_hwmod,
3334 .clk = "l3_iclk_div",
3335 .user = OCP_USER_MPU,
3336 };
3338 /* l3_main_1 -> l3_main_2 */
3339 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
3340 .master = &dra7xx_l3_main_1_hwmod,
3341 .slave = &dra7xx_l3_main_2_hwmod,
3342 .clk = "l3_iclk_div",
3343 .user = OCP_USER_MPU,
3344 };
3346 /* l4_cfg -> l3_main_2 */
3347 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
3348 .master = &dra7xx_l4_cfg_hwmod,
3349 .slave = &dra7xx_l3_main_2_hwmod,
3350 .clk = "l3_iclk_div",
3351 .user = OCP_USER_MPU | OCP_USER_SDMA,
3352 };
3354 /* l3_main_1 -> l4_cfg */
3355 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
3356 .master = &dra7xx_l3_main_1_hwmod,
3357 .slave = &dra7xx_l4_cfg_hwmod,
3358 .clk = "l3_iclk_div",
3359 .user = OCP_USER_MPU | OCP_USER_SDMA,
3360 };
3362 /* l3_main_1 -> mmu0_dsp1 */
3363 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu0_dsp1 = {
3364 .master = &dra7xx_l3_main_1_hwmod,
3365 .slave = &dra7xx_mmu0_dsp1_hwmod,
3366 .clk = "l3_iclk_div",
3367 .user = OCP_USER_MPU | OCP_USER_SDMA,
3368 };
3370 /* l3_main_1 -> mmu1_dsp1 */
3371 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu1_dsp1 = {
3372 .master = &dra7xx_l3_main_1_hwmod,
3373 .slave = &dra7xx_mmu1_dsp1_hwmod,
3374 .clk = "l3_iclk_div",
3375 .user = OCP_USER_MPU | OCP_USER_SDMA,
3376 };
3378 /* l3_main_1 -> mmu0_dsp2 */
3379 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu0_dsp2 = {
3380 .master = &dra7xx_l3_main_1_hwmod,
3381 .slave = &dra7xx_mmu0_dsp2_hwmod,
3382 .clk = "l3_iclk_div",
3383 .user = OCP_USER_MPU | OCP_USER_SDMA,
3384 };
3386 /* l3_main_1 -> mmu1_dsp2 */
3387 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu1_dsp2 = {
3388 .master = &dra7xx_l3_main_1_hwmod,
3389 .slave = &dra7xx_mmu1_dsp2_hwmod,
3390 .clk = "l3_iclk_div",
3391 .user = OCP_USER_MPU | OCP_USER_SDMA,
3392 };
3394 /* l3_main_1 -> mmu_ipu1 */
3395 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu_ipu1 = {
3396 .master = &dra7xx_l3_main_1_hwmod,
3397 .slave = &dra7xx_mmu_ipu1_hwmod,
3398 .clk = "l3_iclk_div",
3399 .user = OCP_USER_MPU | OCP_USER_SDMA,
3400 };
3402 /* l3_main_1 -> mmu_ipu2 */
3403 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu_ipu2 = {
3404 .master = &dra7xx_l3_main_1_hwmod,
3405 .slave = &dra7xx_mmu_ipu2_hwmod,
3406 .clk = "l3_iclk_div",
3407 .user = OCP_USER_MPU | OCP_USER_SDMA,
3408 };
3410 /* l3_main_1 -> l4_per1 */
3411 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
3412 .master = &dra7xx_l3_main_1_hwmod,
3413 .slave = &dra7xx_l4_per1_hwmod,
3414 .clk = "l3_iclk_div",
3415 .user = OCP_USER_MPU | OCP_USER_SDMA,
3416 };
3418 /* l3_main_1 -> l4_per2 */
3419 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
3420 .master = &dra7xx_l3_main_1_hwmod,
3421 .slave = &dra7xx_l4_per2_hwmod,
3422 .clk = "l3_iclk_div",
3423 .user = OCP_USER_MPU | OCP_USER_SDMA,
3424 };
3426 /* l3_main_1 -> l4_per3 */
3427 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
3428 .master = &dra7xx_l3_main_1_hwmod,
3429 .slave = &dra7xx_l4_per3_hwmod,
3430 .clk = "l3_iclk_div",
3431 .user = OCP_USER_MPU | OCP_USER_SDMA,
3432 };
3434 /* l3_main_1 -> l4_wkup */
3435 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
3436 .master = &dra7xx_l3_main_1_hwmod,
3437 .slave = &dra7xx_l4_wkup_hwmod,
3438 .clk = "wkupaon_iclk_mux",
3439 .user = OCP_USER_MPU | OCP_USER_SDMA,
3440 };
3442 /* l4_per2 -> atl */
3443 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
3444 .master = &dra7xx_l4_per2_hwmod,
3445 .slave = &dra7xx_atl_hwmod,
3446 .clk = "l3_iclk_div",
3447 .user = OCP_USER_MPU | OCP_USER_SDMA,
3448 };
3450 /* l3_main_1 -> bb2d */
3451 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
3452 .master = &dra7xx_l3_main_1_hwmod,
3453 .slave = &dra7xx_bb2d_hwmod,
3454 .clk = "l3_iclk_div",
3455 .user = OCP_USER_MPU | OCP_USER_SDMA,
3456 };
3458 /* l4_wkup -> counter_32k */
3459 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
3460 .master = &dra7xx_l4_wkup_hwmod,
3461 .slave = &dra7xx_counter_32k_hwmod,
3462 .clk = "wkupaon_iclk_mux",
3463 .user = OCP_USER_MPU | OCP_USER_SDMA,
3464 };
3466 /* l4_wkup -> ctrl_module_wkup */
3467 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
3468 .master = &dra7xx_l4_wkup_hwmod,
3469 .slave = &dra7xx_ctrl_module_wkup_hwmod,
3470 .clk = "wkupaon_iclk_mux",
3471 .user = OCP_USER_MPU | OCP_USER_SDMA,
3472 };
3474 static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
3475 .master = &dra7xx_l4_per2_hwmod,
3476 .slave = &dra7xx_gmac_hwmod,
3477 .clk = "dpll_gmac_ck",
3478 .user = OCP_USER_MPU,
3479 };
3481 static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
3482 .master = &dra7xx_gmac_hwmod,
3483 .slave = &dra7xx_mdio_hwmod,
3484 .user = OCP_USER_MPU,
3485 };
3487 /* l4_wkup -> dcan1 */
3488 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
3489 .master = &dra7xx_l4_wkup_hwmod,
3490 .slave = &dra7xx_dcan1_hwmod,
3491 .clk = "wkupaon_iclk_mux",
3492 .user = OCP_USER_MPU | OCP_USER_SDMA,
3493 };
3495 /* l4_per2 -> dcan2 */
3496 static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
3497 .master = &dra7xx_l4_per2_hwmod,
3498 .slave = &dra7xx_dcan2_hwmod,
3499 .clk = "l3_iclk_div",
3500 .user = OCP_USER_MPU | OCP_USER_SDMA,
3501 };
3503 static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
3504 {
3505 .pa_start = 0x4a056000,
3506 .pa_end = 0x4a056fff,
3507 .flags = ADDR_TYPE_RT
3508 },
3509 { }
3510 };
3512 /* l4_cfg -> dma_system */
3513 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
3514 .master = &dra7xx_l4_cfg_hwmod,
3515 .slave = &dra7xx_dma_system_hwmod,
3516 .clk = "l3_iclk_div",
3517 .addr = dra7xx_dma_system_addrs,
3518 .user = OCP_USER_MPU | OCP_USER_SDMA,
3519 };
3522 /* l4_cfg -> tpcc */
3523 struct omap_hwmod_ocp_if dra7xx_l4_cfg__tpcc = {
3524 .master = &dra7xx_l4_cfg_hwmod,
3525 .slave = &dra7xx_tpcc_hwmod,
3526 .clk = "l3_iclk_div",
3527 .user = OCP_USER_MPU,
3528 };
3530 /* l4_cfg -> tptc0 */
3531 static struct omap_hwmod_addr_space dra7xx_tptc0_addr_space[] = {
3532 {
3533 .pa_start = 0x43400000,
3534 .pa_end = 0x43400212,
3535 .flags = ADDR_TYPE_RT,
3536 },
3537 { }
3538 };
3540 struct omap_hwmod_ocp_if dra7xx_l4_cfg__tptc0 = {
3541 .master = &dra7xx_l4_cfg_hwmod,
3542 .slave = &dra7xx_tptc0_hwmod,
3543 .clk = "l3_iclk_div",
3544 .addr = dra7xx_tptc0_addr_space,
3545 .user = OCP_USER_MPU,
3546 };
3548 /* l4_cfg -> tptc1 */
3549 static struct omap_hwmod_addr_space dra7xx_tptc1_addr_space[] = {
3550 {
3551 .pa_start = 0x43500000,
3552 .pa_end = 0x43500212,
3553 .flags = ADDR_TYPE_RT,
3554 },
3555 { }
3556 };
3558 struct omap_hwmod_ocp_if dra7xx_l4_cfg__tptc1 = {
3559 .master = &dra7xx_l4_cfg_hwmod,
3560 .slave = &dra7xx_tptc1_hwmod,
3561 .clk = "l3_iclk_div",
3562 .addr = dra7xx_tptc1_addr_space,
3563 .user = OCP_USER_MPU,
3564 };
3566 /* dsp1 -> l3_main_1 */
3567 static struct omap_hwmod_ocp_if dra7xx_dsp1__l3_main_1 = {
3568 .master = &dra7xx_dsp1_hwmod,
3569 .slave = &dra7xx_l3_main_1_hwmod,
3570 .clk = "l3_iclk_div",
3571 .user = OCP_USER_MPU | OCP_USER_SDMA,
3572 };
3574 /* dsp2 -> l3_main_1 */
3575 static struct omap_hwmod_ocp_if dra7xx_dsp2__l3_main_1 = {
3576 .master = &dra7xx_dsp2_hwmod,
3577 .slave = &dra7xx_l3_main_1_hwmod,
3578 .clk = "l3_iclk_div",
3579 .user = OCP_USER_MPU | OCP_USER_SDMA,
3580 };
3582 static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
3583 {
3584 .name = "family",
3585 .pa_start = 0x58000000,
3586 .pa_end = 0x5800007f,
3587 .flags = ADDR_TYPE_RT
3588 },
3589 };
3591 /* l3_main_1 -> dss */
3592 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
3593 .master = &dra7xx_l3_main_1_hwmod,
3594 .slave = &dra7xx_dss_hwmod,
3595 .clk = "l3_iclk_div",
3596 .addr = dra7xx_dss_addrs,
3597 .user = OCP_USER_MPU | OCP_USER_SDMA,
3598 };
3600 static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = {
3601 {
3602 .name = "dispc",
3603 .pa_start = 0x58001000,
3604 .pa_end = 0x58001fff,
3605 .flags = ADDR_TYPE_RT
3606 },
3607 };
3609 /* l3_main_1 -> dispc */
3610 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
3611 .master = &dra7xx_l3_main_1_hwmod,
3612 .slave = &dra7xx_dss_dispc_hwmod,
3613 .clk = "l3_iclk_div",
3614 .addr = dra7xx_dss_dispc_addrs,
3615 .user = OCP_USER_MPU | OCP_USER_SDMA,
3616 };
3618 static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = {
3619 {
3620 .name = "hdmi_wp",
3621 .pa_start = 0x58040000,
3622 .pa_end = 0x580400ff,
3623 .flags = ADDR_TYPE_RT
3624 },
3625 { }
3626 };
3628 /* l3_main_1 -> dispc */
3629 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
3630 .master = &dra7xx_l3_main_1_hwmod,
3631 .slave = &dra7xx_dss_hdmi_hwmod,
3632 .clk = "l3_iclk_div",
3633 .addr = dra7xx_dss_hdmi_addrs,
3634 .user = OCP_USER_MPU | OCP_USER_SDMA,
3635 };
3637 /* l3_main_1 -> aes1 */
3638 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes1 = {
3639 .master = &dra7xx_l3_main_1_hwmod,
3640 .slave = &dra7xx_aes1_hwmod,
3641 .clk = "l3_iclk_div",
3642 .user = OCP_USER_MPU | OCP_USER_SDMA,
3643 };
3645 /* l3_main_1 -> aes2 */
3646 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes2 = {
3647 .master = &dra7xx_l3_main_1_hwmod,
3648 .slave = &dra7xx_aes2_hwmod,
3649 .clk = "l3_iclk_div",
3650 .user = OCP_USER_MPU | OCP_USER_SDMA,
3651 };
3653 /* l3_main_1 -> sha0 */
3654 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__sha0 = {
3655 .master = &dra7xx_l3_main_1_hwmod,
3656 .slave = &dra7xx_sha0_hwmod,
3657 .clk = "l3_iclk_div",
3658 .user = OCP_USER_MPU | OCP_USER_SDMA,
3659 };
3661 /* l4_per2 -> mcasp2 */
3662 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp2 = {
3663 .master = &dra7xx_l4_per2_hwmod,
3664 .slave = &dra7xx_mcasp2_hwmod,
3665 .clk = "l3_iclk_div",
3666 .user = OCP_USER_MPU,
3667 };
3669 /* l4_per2 -> mcasp3 */
3670 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = {
3671 .master = &dra7xx_l4_per2_hwmod,
3672 .slave = &dra7xx_mcasp3_hwmod,
3673 .clk = "l3_iclk_div",
3674 .user = OCP_USER_MPU | OCP_USER_SDMA,
3675 };
3677 /* l4_per2 -> mcasp6 */
3678 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = {
3679 .master = &dra7xx_l4_per2_hwmod,
3680 .slave = &dra7xx_mcasp6_hwmod,
3681 .clk = "l3_iclk_div",
3682 .user = OCP_USER_MPU | OCP_USER_SDMA,
3683 };
3685 /* l4_per2 -> mcasp7 */
3686 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = {
3687 .master = &dra7xx_l4_per2_hwmod,
3688 .slave = &dra7xx_mcasp7_hwmod,
3689 .clk = "l3_iclk_div",
3690 .user = OCP_USER_MPU | OCP_USER_SDMA,
3691 };
3693 /* l4_per2 -> mcasp8 */
3694 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = {
3695 .master = &dra7xx_l4_per2_hwmod,
3696 .slave = &dra7xx_mcasp8_hwmod,
3697 .clk = "l3_iclk_div",
3698 .user = OCP_USER_MPU | OCP_USER_SDMA,
3699 };
3701 static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = {
3702 {
3703 .pa_start = 0x48078000,
3704 .pa_end = 0x48078fff,
3705 .flags = ADDR_TYPE_RT
3706 },
3707 { }
3708 };
3710 /* l4_per1 -> elm */
3711 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
3712 .master = &dra7xx_l4_per1_hwmod,
3713 .slave = &dra7xx_elm_hwmod,
3714 .clk = "l3_iclk_div",
3715 .addr = dra7xx_elm_addrs,
3716 .user = OCP_USER_MPU | OCP_USER_SDMA,
3717 };
3719 /* l4_wkup -> gpio1 */
3720 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
3721 .master = &dra7xx_l4_wkup_hwmod,
3722 .slave = &dra7xx_gpio1_hwmod,
3723 .clk = "wkupaon_iclk_mux",
3724 .user = OCP_USER_MPU | OCP_USER_SDMA,
3725 };
3727 /* l4_per1 -> gpio2 */
3728 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
3729 .master = &dra7xx_l4_per1_hwmod,
3730 .slave = &dra7xx_gpio2_hwmod,
3731 .clk = "l3_iclk_div",
3732 .user = OCP_USER_MPU | OCP_USER_SDMA,
3733 };
3735 /* l4_per1 -> gpio3 */
3736 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
3737 .master = &dra7xx_l4_per1_hwmod,
3738 .slave = &dra7xx_gpio3_hwmod,
3739 .clk = "l3_iclk_div",
3740 .user = OCP_USER_MPU | OCP_USER_SDMA,
3741 };
3743 /* l4_per1 -> gpio4 */
3744 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
3745 .master = &dra7xx_l4_per1_hwmod,
3746 .slave = &dra7xx_gpio4_hwmod,
3747 .clk = "l3_iclk_div",
3748 .user = OCP_USER_MPU | OCP_USER_SDMA,
3749 };
3751 /* l4_per1 -> gpio5 */
3752 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
3753 .master = &dra7xx_l4_per1_hwmod,
3754 .slave = &dra7xx_gpio5_hwmod,
3755 .clk = "l3_iclk_div",
3756 .user = OCP_USER_MPU | OCP_USER_SDMA,
3757 };
3759 /* l4_per1 -> gpio6 */
3760 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
3761 .master = &dra7xx_l4_per1_hwmod,
3762 .slave = &dra7xx_gpio6_hwmod,
3763 .clk = "l3_iclk_div",
3764 .user = OCP_USER_MPU | OCP_USER_SDMA,
3765 };
3767 struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss0 = {
3768 .master = &dra7xx_l4_per2_hwmod,
3769 .slave = &dra7xx_epwmss0_hwmod,
3770 .clk = "l4_root_clk_div",
3771 .user = OCP_USER_MPU,
3772 };
3774 struct omap_hwmod_ocp_if dra7xx_epwmss0__ecap0 = {
3775 .master = &dra7xx_epwmss0_hwmod,
3776 .slave = &dra7xx_ecap0_hwmod,
3777 .clk = "l4_root_clk_div",
3778 .user = OCP_USER_MPU,
3779 };
3781 struct omap_hwmod_ocp_if dra7xx_epwmss0__eqep0 = {
3782 .master = &dra7xx_epwmss0_hwmod,
3783 .slave = &dra7xx_eqep0_hwmod,
3784 .clk = "l4_root_clk_div",
3785 .user = OCP_USER_MPU,
3786 };
3788 struct omap_hwmod_ocp_if dra7xx_epwmss0__ehrpwm0 = {
3789 .master = &dra7xx_epwmss0_hwmod,
3790 .slave = &dra7xx_ehrpwm0_hwmod,
3791 .clk = "l4_root_clk_div",
3792 .user = OCP_USER_MPU,
3793 };
3795 struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss1 = {
3796 .master = &dra7xx_l4_per2_hwmod,
3797 .slave = &dra7xx_epwmss1_hwmod,
3798 .clk = "l4_root_clk_div",
3799 .user = OCP_USER_MPU,
3800 };
3802 struct omap_hwmod_ocp_if dra7xx_epwmss1__ecap1 = {
3803 .master = &dra7xx_epwmss1_hwmod,
3804 .slave = &dra7xx_ecap1_hwmod,
3805 .clk = "l4_root_clk_div",
3806 .user = OCP_USER_MPU,
3807 };
3809 struct omap_hwmod_ocp_if dra7xx_epwmss1__eqep1 = {
3810 .master = &dra7xx_epwmss1_hwmod,
3811 .slave = &dra7xx_eqep1_hwmod,
3812 .clk = "l4_root_clk_div",
3813 .user = OCP_USER_MPU,
3814 };
3816 struct omap_hwmod_ocp_if dra7xx_epwmss1__ehrpwm1 = {
3817 .master = &dra7xx_epwmss1_hwmod,
3818 .slave = &dra7xx_ehrpwm1_hwmod,
3819 .clk = "l4_root_clk_div",
3820 .user = OCP_USER_MPU,
3821 };
3823 struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss2 = {
3824 .master = &dra7xx_l4_per2_hwmod,
3825 .slave = &dra7xx_epwmss2_hwmod,
3826 .clk = "l4_root_clk_div",
3827 .user = OCP_USER_MPU,
3828 };
3830 struct omap_hwmod_ocp_if dra7xx_epwmss2__ecap2 = {
3831 .master = &dra7xx_epwmss2_hwmod,
3832 .slave = &dra7xx_ecap2_hwmod,
3833 .clk = "l4_root_clk_div",
3834 .user = OCP_USER_MPU,
3835 };
3837 struct omap_hwmod_ocp_if dra7xx_epwmss2__eqep2 = {
3838 .master = &dra7xx_epwmss2_hwmod,
3839 .slave = &dra7xx_eqep2_hwmod,
3840 .clk = "l4_root_clk_div",
3841 .user = OCP_USER_MPU,
3842 };
3844 struct omap_hwmod_ocp_if dra7xx_epwmss2__ehrpwm2 = {
3845 .master = &dra7xx_epwmss2_hwmod,
3846 .slave = &dra7xx_ehrpwm2_hwmod,
3847 .clk = "l4_root_clk_div",
3848 .user = OCP_USER_MPU,
3849 };
3851 /* l4_per1 -> gpio7 */
3852 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
3853 .master = &dra7xx_l4_per1_hwmod,
3854 .slave = &dra7xx_gpio7_hwmod,
3855 .clk = "l3_iclk_div",
3856 .user = OCP_USER_MPU | OCP_USER_SDMA,
3857 };
3859 /* l4_per1 -> gpio8 */
3860 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
3861 .master = &dra7xx_l4_per1_hwmod,
3862 .slave = &dra7xx_gpio8_hwmod,
3863 .clk = "l3_iclk_div",
3864 .user = OCP_USER_MPU | OCP_USER_SDMA,
3865 };
3867 static struct omap_hwmod_addr_space dra7xx_gpmc_addrs[] = {
3868 {
3869 .pa_start = 0x50000000,
3870 .pa_end = 0x500003ff,
3871 .flags = ADDR_TYPE_RT
3872 },
3873 { }
3874 };
3876 /* l3_main_1 -> gpmc */
3877 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
3878 .master = &dra7xx_l3_main_1_hwmod,
3879 .slave = &dra7xx_gpmc_hwmod,
3880 .clk = "l3_iclk_div",
3881 .addr = dra7xx_gpmc_addrs,
3882 .user = OCP_USER_MPU | OCP_USER_SDMA,
3883 };
3885 static struct omap_hwmod_addr_space dra7xx_gpu_addrs[] = {
3886 {
3887 .name = "klio",
3888 .pa_start = 0x56000000,
3889 .pa_end = 0x56001fff,
3890 },
3891 {
3892 .name = "hydra2",
3893 .pa_start = 0x56004000,
3894 .pa_end = 0x56004fff,
3895 },
3896 {
3897 .name = "klio_0",
3898 .pa_start = 0x56008000,
3899 .pa_end = 0x56009fff,
3900 },
3901 {
3902 .name = "klio_1",
3903 .pa_start = 0x5600c000,
3904 .pa_end = 0x5600dfff,
3905 },
3906 {
3907 .name = "klio_hl",
3908 .pa_start = 0x5600fe00,
3909 .pa_end = 0x5600ffff,
3910 .flags = ADDR_TYPE_RT
3911 },
3912 { }
3913 };
3915 /* l3_main_1 -> gpu */
3916 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpu = {
3917 .master = &dra7xx_l3_main_1_hwmod,
3918 .slave = &dra7xx_gpu_hwmod,
3919 .clk = "l3_iclk_div",
3920 .addr = dra7xx_gpu_addrs,
3921 .user = OCP_USER_MPU | OCP_USER_SDMA,
3922 };
3924 static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
3925 {
3926 .pa_start = 0x480b2000,
3927 .pa_end = 0x480b201f,
3928 .flags = ADDR_TYPE_RT
3929 },
3930 { }
3931 };
3933 /* l4_per1 -> hdq1w */
3934 static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
3935 .master = &dra7xx_l4_per1_hwmod,
3936 .slave = &dra7xx_hdq1w_hwmod,
3937 .clk = "l3_iclk_div",
3938 .addr = dra7xx_hdq1w_addrs,
3939 .user = OCP_USER_MPU | OCP_USER_SDMA,
3940 };
3942 /* l4_per1 -> i2c1 */
3943 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
3944 .master = &dra7xx_l4_per1_hwmod,
3945 .slave = &dra7xx_i2c1_hwmod,
3946 .clk = "l3_iclk_div",
3947 .user = OCP_USER_MPU | OCP_USER_SDMA,
3948 };
3950 /* l4_per1 -> i2c2 */
3951 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
3952 .master = &dra7xx_l4_per1_hwmod,
3953 .slave = &dra7xx_i2c2_hwmod,
3954 .clk = "l3_iclk_div",
3955 .user = OCP_USER_MPU | OCP_USER_SDMA,
3956 };
3958 /* l4_per1 -> i2c3 */
3959 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
3960 .master = &dra7xx_l4_per1_hwmod,
3961 .slave = &dra7xx_i2c3_hwmod,
3962 .clk = "l3_iclk_div",
3963 .user = OCP_USER_MPU | OCP_USER_SDMA,
3964 };
3966 /* l4_per1 -> i2c4 */
3967 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
3968 .master = &dra7xx_l4_per1_hwmod,
3969 .slave = &dra7xx_i2c4_hwmod,
3970 .clk = "l3_iclk_div",
3971 .user = OCP_USER_MPU | OCP_USER_SDMA,
3972 };
3974 /* l4_per1 -> i2c5 */
3975 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
3976 .master = &dra7xx_l4_per1_hwmod,
3977 .slave = &dra7xx_i2c5_hwmod,
3978 .clk = "l3_iclk_div",
3979 .user = OCP_USER_MPU | OCP_USER_SDMA,
3980 };
3982 /* ipu1 -> l3_main_1 */
3983 static struct omap_hwmod_ocp_if dra7xx_ipu1__l3_main_1 = {
3984 .master = &dra7xx_ipu1_hwmod,
3985 .slave = &dra7xx_l3_main_1_hwmod,
3986 .clk = "l3_iclk_div",
3987 .user = OCP_USER_MPU | OCP_USER_SDMA,
3988 };
3990 /* ipu2 -> l3_main_1 */
3991 static struct omap_hwmod_ocp_if dra7xx_ipu2__l3_main_1 = {
3992 .master = &dra7xx_ipu2_hwmod,
3993 .slave = &dra7xx_l3_main_1_hwmod,
3994 .clk = "l3_iclk_div",
3995 .user = OCP_USER_MPU | OCP_USER_SDMA,
3996 };
3998 /* l4_cfg -> mailbox1 */
3999 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
4000 .master = &dra7xx_l4_cfg_hwmod,
4001 .slave = &dra7xx_mailbox1_hwmod,
4002 .clk = "l3_iclk_div",
4003 .user = OCP_USER_MPU | OCP_USER_SDMA,
4004 };
4006 /* l4_per3 -> mailbox2 */
4007 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
4008 .master = &dra7xx_l4_per3_hwmod,
4009 .slave = &dra7xx_mailbox2_hwmod,
4010 .clk = "l3_iclk_div",
4011 .user = OCP_USER_MPU | OCP_USER_SDMA,
4012 };
4014 /* l4_per3 -> mailbox3 */
4015 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
4016 .master = &dra7xx_l4_per3_hwmod,
4017 .slave = &dra7xx_mailbox3_hwmod,
4018 .clk = "l3_iclk_div",
4019 .user = OCP_USER_MPU | OCP_USER_SDMA,
4020 };
4022 /* l4_per3 -> mailbox4 */
4023 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
4024 .master = &dra7xx_l4_per3_hwmod,
4025 .slave = &dra7xx_mailbox4_hwmod,
4026 .clk = "l3_iclk_div",
4027 .user = OCP_USER_MPU | OCP_USER_SDMA,
4028 };
4030 /* l4_per3 -> mailbox5 */
4031 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
4032 .master = &dra7xx_l4_per3_hwmod,
4033 .slave = &dra7xx_mailbox5_hwmod,
4034 .clk = "l3_iclk_div",
4035 .user = OCP_USER_MPU | OCP_USER_SDMA,
4036 };
4038 /* l4_per3 -> mailbox6 */
4039 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
4040 .master = &dra7xx_l4_per3_hwmod,
4041 .slave = &dra7xx_mailbox6_hwmod,
4042 .clk = "l3_iclk_div",
4043 .user = OCP_USER_MPU | OCP_USER_SDMA,
4044 };
4046 /* l4_per3 -> mailbox7 */
4047 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
4048 .master = &dra7xx_l4_per3_hwmod,
4049 .slave = &dra7xx_mailbox7_hwmod,
4050 .clk = "l3_iclk_div",
4051 .user = OCP_USER_MPU | OCP_USER_SDMA,
4052 };
4054 /* l4_per3 -> mailbox8 */
4055 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
4056 .master = &dra7xx_l4_per3_hwmod,
4057 .slave = &dra7xx_mailbox8_hwmod,
4058 .clk = "l3_iclk_div",
4059 .user = OCP_USER_MPU | OCP_USER_SDMA,
4060 };
4062 /* l4_per3 -> mailbox9 */
4063 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
4064 .master = &dra7xx_l4_per3_hwmod,
4065 .slave = &dra7xx_mailbox9_hwmod,
4066 .clk = "l3_iclk_div",
4067 .user = OCP_USER_MPU | OCP_USER_SDMA,
4068 };
4070 /* l4_per3 -> mailbox10 */
4071 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
4072 .master = &dra7xx_l4_per3_hwmod,
4073 .slave = &dra7xx_mailbox10_hwmod,
4074 .clk = "l3_iclk_div",
4075 .user = OCP_USER_MPU | OCP_USER_SDMA,
4076 };
4078 /* l4_per3 -> mailbox11 */
4079 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
4080 .master = &dra7xx_l4_per3_hwmod,
4081 .slave = &dra7xx_mailbox11_hwmod,
4082 .clk = "l3_iclk_div",
4083 .user = OCP_USER_MPU | OCP_USER_SDMA,
4084 };
4086 /* l4_per3 -> mailbox12 */
4087 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
4088 .master = &dra7xx_l4_per3_hwmod,
4089 .slave = &dra7xx_mailbox12_hwmod,
4090 .clk = "l3_iclk_div",
4091 .user = OCP_USER_MPU | OCP_USER_SDMA,
4092 };
4094 /* l4_per3 -> mailbox13 */
4095 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
4096 .master = &dra7xx_l4_per3_hwmod,
4097 .slave = &dra7xx_mailbox13_hwmod,
4098 .clk = "l3_iclk_div",
4099 .user = OCP_USER_MPU | OCP_USER_SDMA,
4100 };
4102 /* l4_per1 -> mcspi1 */
4103 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
4104 .master = &dra7xx_l4_per1_hwmod,
4105 .slave = &dra7xx_mcspi1_hwmod,
4106 .clk = "l3_iclk_div",
4107 .user = OCP_USER_MPU | OCP_USER_SDMA,
4108 };
4110 /* l4_per1 -> mcspi2 */
4111 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
4112 .master = &dra7xx_l4_per1_hwmod,
4113 .slave = &dra7xx_mcspi2_hwmod,
4114 .clk = "l3_iclk_div",
4115 .user = OCP_USER_MPU | OCP_USER_SDMA,
4116 };
4118 /* l4_per1 -> mcspi3 */
4119 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
4120 .master = &dra7xx_l4_per1_hwmod,
4121 .slave = &dra7xx_mcspi3_hwmod,
4122 .clk = "l3_iclk_div",
4123 .user = OCP_USER_MPU | OCP_USER_SDMA,
4124 };
4126 /* l4_per1 -> mcspi4 */
4127 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
4128 .master = &dra7xx_l4_per1_hwmod,
4129 .slave = &dra7xx_mcspi4_hwmod,
4130 .clk = "l3_iclk_div",
4131 .user = OCP_USER_MPU | OCP_USER_SDMA,
4132 };
4134 /* l4_per1 -> mmc1 */
4135 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
4136 .master = &dra7xx_l4_per1_hwmod,
4137 .slave = &dra7xx_mmc1_hwmod,
4138 .clk = "l3_iclk_div",
4139 .user = OCP_USER_MPU | OCP_USER_SDMA,
4140 };
4142 /* l4_per1 -> mmc2 */
4143 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
4144 .master = &dra7xx_l4_per1_hwmod,
4145 .slave = &dra7xx_mmc2_hwmod,
4146 .clk = "l3_iclk_div",
4147 .user = OCP_USER_MPU | OCP_USER_SDMA,
4148 };
4150 /* l4_per1 -> mmc3 */
4151 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
4152 .master = &dra7xx_l4_per1_hwmod,
4153 .slave = &dra7xx_mmc3_hwmod,
4154 .clk = "l3_iclk_div",
4155 .user = OCP_USER_MPU | OCP_USER_SDMA,
4156 };
4158 /* l4_per1 -> mmc4 */
4159 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
4160 .master = &dra7xx_l4_per1_hwmod,
4161 .slave = &dra7xx_mmc4_hwmod,
4162 .clk = "l3_iclk_div",
4163 .user = OCP_USER_MPU | OCP_USER_SDMA,
4164 };
4166 /* l4_cfg -> mpu */
4167 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
4168 .master = &dra7xx_l4_cfg_hwmod,
4169 .slave = &dra7xx_mpu_hwmod,
4170 .clk = "l3_iclk_div",
4171 .user = OCP_USER_MPU | OCP_USER_SDMA,
4172 };
4174 /* l4_cfg -> ocp2scp1 */
4175 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
4176 .master = &dra7xx_l4_cfg_hwmod,
4177 .slave = &dra7xx_ocp2scp1_hwmod,
4178 .clk = "l4_root_clk_div",
4179 .user = OCP_USER_MPU | OCP_USER_SDMA,
4180 };
4182 /* l4_cfg -> ocp2scp3 */
4183 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
4184 .master = &dra7xx_l4_cfg_hwmod,
4185 .slave = &dra7xx_ocp2scp3_hwmod,
4186 .clk = "l4_root_clk_div",
4187 .user = OCP_USER_MPU | OCP_USER_SDMA,
4188 };
4190 /* l3_main_1 -> pcie1 */
4191 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
4192 .master = &dra7xx_l3_main_1_hwmod,
4193 .slave = &dra7xx_pciess1_hwmod,
4194 .clk = "l3_iclk_div",
4195 .user = OCP_USER_MPU | OCP_USER_SDMA,
4196 };
4198 /* l4_cfg -> pcie1 */
4199 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
4200 .master = &dra7xx_l4_cfg_hwmod,
4201 .slave = &dra7xx_pciess1_hwmod,
4202 .clk = "l4_root_clk_div",
4203 .user = OCP_USER_MPU | OCP_USER_SDMA,
4204 };
4206 /* l3_main_1 -> pcie2 */
4207 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
4208 .master = &dra7xx_l3_main_1_hwmod,
4209 .slave = &dra7xx_pciess2_hwmod,
4210 .clk = "l3_iclk_div",
4211 .user = OCP_USER_MPU | OCP_USER_SDMA,
4212 };
4214 /* l4_cfg -> pcie2 */
4215 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
4216 .master = &dra7xx_l4_cfg_hwmod,
4217 .slave = &dra7xx_pciess2_hwmod,
4218 .clk = "l4_root_clk_div",
4219 .user = OCP_USER_MPU | OCP_USER_SDMA,
4220 };
4222 /* l4_cfg -> pruss1 */
4223 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pruss1 = {
4224 .master = &dra7xx_l4_cfg_hwmod,
4225 .slave = &dra7xx_pruss1_hwmod,
4226 .clk = "dpll_gmac_h13x2_ck",
4227 .user = OCP_USER_MPU | OCP_USER_SDMA,
4228 };
4230 /* l4_cfg -> pruss2 */
4231 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pruss2 = {
4232 .master = &dra7xx_l4_cfg_hwmod,
4233 .slave = &dra7xx_pruss2_hwmod,
4234 .clk = "dpll_gmac_h13x2_ck",
4235 .user = OCP_USER_MPU | OCP_USER_SDMA,
4236 };
4238 static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
4239 {
4240 .pa_start = 0x4b300000,
4241 .pa_end = 0x4b30007f,
4242 .flags = ADDR_TYPE_RT
4243 },
4244 { }
4245 };
4247 /* l3_main_1 -> qspi */
4248 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
4249 .master = &dra7xx_l3_main_1_hwmod,
4250 .slave = &dra7xx_qspi_hwmod,
4251 .clk = "l3_iclk_div",
4252 .addr = dra7xx_qspi_addrs,
4253 .user = OCP_USER_MPU | OCP_USER_SDMA,
4254 };
4256 /* l4_per3 -> rtcss */
4257 static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
4258 .master = &dra7xx_l4_per3_hwmod,
4259 .slave = &dra7xx_rtcss_hwmod,
4260 .clk = "l4_root_clk_div",
4261 .user = OCP_USER_MPU | OCP_USER_SDMA,
4262 };
4264 static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
4265 {
4266 .name = "sysc",
4267 .pa_start = 0x4a141100,
4268 .pa_end = 0x4a141107,
4269 .flags = ADDR_TYPE_RT
4270 },
4271 { }
4272 };
4274 /* l4_cfg -> sata */
4275 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
4276 .master = &dra7xx_l4_cfg_hwmod,
4277 .slave = &dra7xx_sata_hwmod,
4278 .clk = "l3_iclk_div",
4279 .addr = dra7xx_sata_addrs,
4280 .user = OCP_USER_MPU | OCP_USER_SDMA,
4281 };
4283 static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
4284 {
4285 .pa_start = 0x4a0dd000,
4286 .pa_end = 0x4a0dd07f,
4287 .flags = ADDR_TYPE_RT
4288 },
4289 { }
4290 };
4292 /* l4_cfg -> smartreflex_core */
4293 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
4294 .master = &dra7xx_l4_cfg_hwmod,
4295 .slave = &dra7xx_smartreflex_core_hwmod,
4296 .clk = "l4_root_clk_div",
4297 .addr = dra7xx_smartreflex_core_addrs,
4298 .user = OCP_USER_MPU | OCP_USER_SDMA,
4299 };
4301 static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
4302 {
4303 .pa_start = 0x4a0d9000,
4304 .pa_end = 0x4a0d907f,
4305 .flags = ADDR_TYPE_RT
4306 },
4307 { }
4308 };
4310 /* l4_cfg -> smartreflex_mpu */
4311 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
4312 .master = &dra7xx_l4_cfg_hwmod,
4313 .slave = &dra7xx_smartreflex_mpu_hwmod,
4314 .clk = "l4_root_clk_div",
4315 .addr = dra7xx_smartreflex_mpu_addrs,
4316 .user = OCP_USER_MPU | OCP_USER_SDMA,
4317 };
4319 static struct omap_hwmod_addr_space dra7xx_spinlock_addrs[] = {
4320 {
4321 .pa_start = 0x4a0f6000,
4322 .pa_end = 0x4a0f6fff,
4323 .flags = ADDR_TYPE_RT
4324 },
4325 { }
4326 };
4328 /* l4_cfg -> spinlock */
4329 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
4330 .master = &dra7xx_l4_cfg_hwmod,
4331 .slave = &dra7xx_spinlock_hwmod,
4332 .clk = "l3_iclk_div",
4333 .addr = dra7xx_spinlock_addrs,
4334 .user = OCP_USER_MPU | OCP_USER_SDMA,
4335 };
4337 /* l4_wkup -> timer1 */
4338 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
4339 .master = &dra7xx_l4_wkup_hwmod,
4340 .slave = &dra7xx_timer1_hwmod,
4341 .clk = "wkupaon_iclk_mux",
4342 .user = OCP_USER_MPU | OCP_USER_SDMA,
4343 };
4345 /* l4_per1 -> timer2 */
4346 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
4347 .master = &dra7xx_l4_per1_hwmod,
4348 .slave = &dra7xx_timer2_hwmod,
4349 .clk = "l3_iclk_div",
4350 .user = OCP_USER_MPU | OCP_USER_SDMA,
4351 };
4353 /* l4_per1 -> timer3 */
4354 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
4355 .master = &dra7xx_l4_per1_hwmod,
4356 .slave = &dra7xx_timer3_hwmod,
4357 .clk = "l3_iclk_div",
4358 .user = OCP_USER_MPU | OCP_USER_SDMA,
4359 };
4361 /* l4_per1 -> timer4 */
4362 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
4363 .master = &dra7xx_l4_per1_hwmod,
4364 .slave = &dra7xx_timer4_hwmod,
4365 .clk = "l3_iclk_div",
4366 .user = OCP_USER_MPU | OCP_USER_SDMA,
4367 };
4369 /* l4_per3 -> timer5 */
4370 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
4371 .master = &dra7xx_l4_per3_hwmod,
4372 .slave = &dra7xx_timer5_hwmod,
4373 .clk = "l3_iclk_div",
4374 .user = OCP_USER_MPU | OCP_USER_SDMA,
4375 };
4377 /* l4_per3 -> timer6 */
4378 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
4379 .master = &dra7xx_l4_per3_hwmod,
4380 .slave = &dra7xx_timer6_hwmod,
4381 .clk = "l3_iclk_div",
4382 .user = OCP_USER_MPU | OCP_USER_SDMA,
4383 };
4385 /* l4_per3 -> timer7 */
4386 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
4387 .master = &dra7xx_l4_per3_hwmod,
4388 .slave = &dra7xx_timer7_hwmod,
4389 .clk = "l3_iclk_div",
4390 .user = OCP_USER_MPU | OCP_USER_SDMA,
4391 };
4393 /* l4_per3 -> timer8 */
4394 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
4395 .master = &dra7xx_l4_per3_hwmod,
4396 .slave = &dra7xx_timer8_hwmod,
4397 .clk = "l3_iclk_div",
4398 .user = OCP_USER_MPU | OCP_USER_SDMA,
4399 };
4401 /* l4_per1 -> timer9 */
4402 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
4403 .master = &dra7xx_l4_per1_hwmod,
4404 .slave = &dra7xx_timer9_hwmod,
4405 .clk = "l3_iclk_div",
4406 .user = OCP_USER_MPU | OCP_USER_SDMA,
4407 };
4409 /* l4_per1 -> timer10 */
4410 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
4411 .master = &dra7xx_l4_per1_hwmod,
4412 .slave = &dra7xx_timer10_hwmod,
4413 .clk = "l3_iclk_div",
4414 .user = OCP_USER_MPU | OCP_USER_SDMA,
4415 };
4417 /* l4_per1 -> timer11 */
4418 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
4419 .master = &dra7xx_l4_per1_hwmod,
4420 .slave = &dra7xx_timer11_hwmod,
4421 .clk = "l3_iclk_div",
4422 .user = OCP_USER_MPU | OCP_USER_SDMA,
4423 };
4425 /* l4_wkup -> timer12 */
4426 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer12 = {
4427 .master = &dra7xx_l4_wkup_hwmod,
4428 .slave = &dra7xx_timer12_hwmod,
4429 .clk = "wkupaon_iclk_mux",
4430 .user = OCP_USER_MPU | OCP_USER_SDMA,
4431 };
4433 /* l4_per3 -> timer13 */
4434 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
4435 .master = &dra7xx_l4_per3_hwmod,
4436 .slave = &dra7xx_timer13_hwmod,
4437 .clk = "l3_iclk_div",
4438 .user = OCP_USER_MPU | OCP_USER_SDMA,
4439 };
4441 /* l4_per3 -> timer14 */
4442 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
4443 .master = &dra7xx_l4_per3_hwmod,
4444 .slave = &dra7xx_timer14_hwmod,
4445 .clk = "l3_iclk_div",
4446 .user = OCP_USER_MPU | OCP_USER_SDMA,
4447 };
4449 /* l4_per3 -> timer15 */
4450 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
4451 .master = &dra7xx_l4_per3_hwmod,
4452 .slave = &dra7xx_timer15_hwmod,
4453 .clk = "l3_iclk_div",
4454 .user = OCP_USER_MPU | OCP_USER_SDMA,
4455 };
4457 /* l4_per3 -> timer16 */
4458 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
4459 .master = &dra7xx_l4_per3_hwmod,
4460 .slave = &dra7xx_timer16_hwmod,
4461 .clk = "l3_iclk_div",
4462 .user = OCP_USER_MPU | OCP_USER_SDMA,
4463 };
4465 /* l4_per1 -> uart1 */
4466 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
4467 .master = &dra7xx_l4_per1_hwmod,
4468 .slave = &dra7xx_uart1_hwmod,
4469 .clk = "l3_iclk_div",
4470 .user = OCP_USER_MPU | OCP_USER_SDMA,
4471 };
4473 /* l4_per1 -> uart2 */
4474 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
4475 .master = &dra7xx_l4_per1_hwmod,
4476 .slave = &dra7xx_uart2_hwmod,
4477 .clk = "l3_iclk_div",
4478 .user = OCP_USER_MPU | OCP_USER_SDMA,
4479 };
4481 /* l4_per1 -> uart3 */
4482 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
4483 .master = &dra7xx_l4_per1_hwmod,
4484 .slave = &dra7xx_uart3_hwmod,
4485 .clk = "l3_iclk_div",
4486 .user = OCP_USER_MPU | OCP_USER_SDMA,
4487 };
4489 /* l4_per1 -> uart4 */
4490 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
4491 .master = &dra7xx_l4_per1_hwmod,
4492 .slave = &dra7xx_uart4_hwmod,
4493 .clk = "l3_iclk_div",
4494 .user = OCP_USER_MPU | OCP_USER_SDMA,
4495 };
4497 /* l4_per1 -> uart5 */
4498 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
4499 .master = &dra7xx_l4_per1_hwmod,
4500 .slave = &dra7xx_uart5_hwmod,
4501 .clk = "l3_iclk_div",
4502 .user = OCP_USER_MPU | OCP_USER_SDMA,
4503 };
4505 /* l4_per1 -> uart6 */
4506 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
4507 .master = &dra7xx_l4_per1_hwmod,
4508 .slave = &dra7xx_uart6_hwmod,
4509 .clk = "l3_iclk_div",
4510 .user = OCP_USER_MPU | OCP_USER_SDMA,
4511 };
4513 /* l4_per2 -> uart7 */
4514 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
4515 .master = &dra7xx_l4_per2_hwmod,
4516 .slave = &dra7xx_uart7_hwmod,
4517 .clk = "l3_iclk_div",
4518 .user = OCP_USER_MPU | OCP_USER_SDMA,
4519 };
4521 /* l4_per2 -> uart8 */
4522 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
4523 .master = &dra7xx_l4_per2_hwmod,
4524 .slave = &dra7xx_uart8_hwmod,
4525 .clk = "l3_iclk_div",
4526 .user = OCP_USER_MPU | OCP_USER_SDMA,
4527 };
4529 /* l4_per2 -> uart9 */
4530 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
4531 .master = &dra7xx_l4_per2_hwmod,
4532 .slave = &dra7xx_uart9_hwmod,
4533 .clk = "l3_iclk_div",
4534 .user = OCP_USER_MPU | OCP_USER_SDMA,
4535 };
4537 /* l4_wkup -> uart10 */
4538 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
4539 .master = &dra7xx_l4_wkup_hwmod,
4540 .slave = &dra7xx_uart10_hwmod,
4541 .clk = "wkupaon_iclk_mux",
4542 .user = OCP_USER_MPU | OCP_USER_SDMA,
4543 };
4545 /* l4_per1 -> des */
4546 static struct omap_hwmod_ocp_if dra7xx_l4_per1__des = {
4547 .master = &dra7xx_l4_per1_hwmod,
4548 .slave = &dra7xx_des_hwmod,
4549 .clk = "l3_iclk_div",
4550 .user = OCP_USER_MPU | OCP_USER_SDMA,
4551 };
4553 /* l4_per1 -> rng */
4554 static struct omap_hwmod_ocp_if dra7xx_l4_per1__rng = {
4555 .master = &dra7xx_l4_per1_hwmod,
4556 .slave = &dra7xx_rng_hwmod,
4557 .user = OCP_USER_MPU,
4558 };
4560 /* l4_per3 -> usb_otg_ss1 */
4561 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
4562 .master = &dra7xx_l4_per3_hwmod,
4563 .slave = &dra7xx_usb_otg_ss1_hwmod,
4564 .clk = "dpll_core_h13x2_ck",
4565 .user = OCP_USER_MPU | OCP_USER_SDMA,
4566 };
4568 /* l4_per3 -> usb_otg_ss2 */
4569 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
4570 .master = &dra7xx_l4_per3_hwmod,
4571 .slave = &dra7xx_usb_otg_ss2_hwmod,
4572 .clk = "dpll_core_h13x2_ck",
4573 .user = OCP_USER_MPU | OCP_USER_SDMA,
4574 };
4576 /* l4_per3 -> usb_otg_ss3 */
4577 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
4578 .master = &dra7xx_l4_per3_hwmod,
4579 .slave = &dra7xx_usb_otg_ss3_hwmod,
4580 .clk = "dpll_core_h13x2_ck",
4581 .user = OCP_USER_MPU | OCP_USER_SDMA,
4582 };
4584 /* l4_per3 -> usb_otg_ss4 */
4585 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
4586 .master = &dra7xx_l4_per3_hwmod,
4587 .slave = &dra7xx_usb_otg_ss4_hwmod,
4588 .clk = "dpll_core_h13x2_ck",
4589 .user = OCP_USER_MPU | OCP_USER_SDMA,
4590 };
4592 /* l3_main_1 -> vcp1 */
4593 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
4594 .master = &dra7xx_l3_main_1_hwmod,
4595 .slave = &dra7xx_vcp1_hwmod,
4596 .clk = "l3_iclk_div",
4597 .user = OCP_USER_MPU | OCP_USER_SDMA,
4598 };
4600 /* l4_per2 -> vcp1 */
4601 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
4602 .master = &dra7xx_l4_per2_hwmod,
4603 .slave = &dra7xx_vcp1_hwmod,
4604 .clk = "l3_iclk_div",
4605 .user = OCP_USER_MPU | OCP_USER_SDMA,
4606 };
4608 /* l3_main_1 -> vcp2 */
4609 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
4610 .master = &dra7xx_l3_main_1_hwmod,
4611 .slave = &dra7xx_vcp2_hwmod,
4612 .clk = "l3_iclk_div",
4613 .user = OCP_USER_MPU | OCP_USER_SDMA,
4614 };
4616 /* l4_per2 -> vcp2 */
4617 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
4618 .master = &dra7xx_l4_per2_hwmod,
4619 .slave = &dra7xx_vcp2_hwmod,
4620 .clk = "l3_iclk_div",
4621 .user = OCP_USER_MPU | OCP_USER_SDMA,
4622 };
4624 /* l4_per3 -> vpe */
4625 static struct omap_hwmod_ocp_if dra7xx_l4_per3__vpe = {
4626 .master = &dra7xx_l4_per3_hwmod,
4627 .slave = &dra7xx_vpe_hwmod,
4628 .clk = "l3_iclk_div",
4629 .user = OCP_USER_MPU | OCP_USER_SDMA,
4630 };
4632 /* l4_per3 -> vip1 */
4633 static struct omap_hwmod_ocp_if dra7xx_l4_per3__vip1 = {
4634 .master = &dra7xx_l4_per3_hwmod,
4635 .slave = &dra7xx_vip1_hwmod,
4636 .clk = "l3_iclk_div",
4637 .user = OCP_USER_MPU | OCP_USER_SDMA,
4638 };
4640 /* l4_per3 -> vip2 */
4641 static struct omap_hwmod_ocp_if dra7xx_l4_per3__vip2 = {
4642 .master = &dra7xx_l4_per3_hwmod,
4643 .slave = &dra7xx_vip2_hwmod,
4644 .clk = "l3_iclk_div",
4645 .user = OCP_USER_MPU | OCP_USER_SDMA,
4646 };
4648 /* l4_per3 -> vip3 */
4649 static struct omap_hwmod_ocp_if dra7xx_l4_per3__vip3 = {
4650 .master = &dra7xx_l4_per3_hwmod,
4651 .slave = &dra7xx_vip3_hwmod,
4652 .clk = "l3_iclk_div",
4653 .user = OCP_USER_MPU | OCP_USER_SDMA,
4654 };
4656 /* l4_per3 -> cal */
4657 static struct omap_hwmod_ocp_if dra7xx_l4_per3__cal = {
4658 .master = &dra7xx_l4_per3_hwmod,
4659 .slave = &dra7xx_cal_hwmod,
4660 .clk = "l3_iclk_div",
4661 .user = OCP_USER_MPU | OCP_USER_SDMA,
4662 };
4664 /* l4_wkup -> wd_timer2 */
4665 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
4666 .master = &dra7xx_l4_wkup_hwmod,
4667 .slave = &dra7xx_wd_timer2_hwmod,
4668 .clk = "wkupaon_iclk_mux",
4669 .user = OCP_USER_MPU | OCP_USER_SDMA,
4670 };
4672 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
4673 &dra7xx_l3_main_1__dmm,
4674 &dra7xx_dmm__emif_ocp_fw,
4675 &dra7xx_l3_main_2__l3_instr,
4676 &dra7xx_l4_cfg__l3_main_1,
4677 &dra7xx_mpu__l3_main_1,
4678 &dra7xx_l3_main_1__l3_main_2,
4679 &dra7xx_l4_cfg__l3_main_2,
4680 &dra7xx_l3_main_1__l4_cfg,
4681 &dra7xx_l3_main_1__l4_per1,
4682 &dra7xx_l3_main_1__l4_per2,
4683 &dra7xx_l3_main_1__l4_per3,
4684 &dra7xx_l3_main_1__l4_wkup,
4685 &dra7xx_l4_per2__atl,
4686 &dra7xx_l3_main_1__bb2d,
4687 &dra7xx_l4_wkup__counter_32k,
4688 &dra7xx_l4_wkup__ctrl_module_wkup,
4689 &dra7xx_l4_wkup__dcan1,
4690 &dra7xx_l4_per2__dcan2,
4691 &dra7xx_l4_per2__cpgmac0,
4692 &dra7xx_gmac__mdio,
4693 &dra7xx_l4_cfg__dma_system,
4694 &dra7xx_l4_cfg__tpcc,
4695 &dra7xx_l4_cfg__tptc0,
4696 &dra7xx_l4_cfg__tptc1,
4697 &dra7xx_l3_main_1__dss,
4698 &dra7xx_l3_main_1__dispc,
4699 &dra7xx_dsp1__l3_main_1,
4700 &dra7xx_l3_main_1__hdmi,
4701 &dra7xx_l3_main_1__aes1,
4702 &dra7xx_l3_main_1__aes2,
4703 &dra7xx_l3_main_1__sha0,
4704 &dra7xx_l4_per2__mcasp2,
4705 &dra7xx_l4_per2__mcasp3,
4706 &dra7xx_l4_per2__mcasp6,
4707 &dra7xx_l4_per2__mcasp7,
4708 &dra7xx_l4_per2__mcasp8,
4709 &dra7xx_l4_per1__elm,
4710 &dra7xx_l4_wkup__gpio1,
4711 &dra7xx_l4_per1__gpio2,
4712 &dra7xx_l4_per1__gpio3,
4713 &dra7xx_l4_per1__gpio4,
4714 &dra7xx_l4_per1__gpio5,
4715 &dra7xx_l4_per1__gpio6,
4716 &dra7xx_l4_per1__gpio7,
4717 &dra7xx_l4_per1__gpio8,
4718 &dra7xx_l3_main_1__gpmc,
4719 &dra7xx_l3_main_1__gpu,
4720 &dra7xx_l4_per1__hdq1w,
4721 &dra7xx_l4_per1__i2c1,
4722 &dra7xx_l4_per1__i2c2,
4723 &dra7xx_l4_per1__i2c3,
4724 &dra7xx_l4_per1__i2c4,
4725 &dra7xx_l4_per1__i2c5,
4726 &dra7xx_ipu1__l3_main_1,
4727 &dra7xx_ipu2__l3_main_1,
4728 &dra7xx_l4_cfg__mailbox1,
4729 &dra7xx_l4_per3__mailbox2,
4730 &dra7xx_l4_per3__mailbox3,
4731 &dra7xx_l4_per3__mailbox4,
4732 &dra7xx_l4_per3__mailbox5,
4733 &dra7xx_l4_per3__mailbox6,
4734 &dra7xx_l4_per3__mailbox7,
4735 &dra7xx_l4_per3__mailbox8,
4736 &dra7xx_l4_per3__mailbox9,
4737 &dra7xx_l4_per3__mailbox10,
4738 &dra7xx_l4_per3__mailbox11,
4739 &dra7xx_l4_per3__mailbox12,
4740 &dra7xx_l4_per3__mailbox13,
4741 &dra7xx_l4_per1__mcspi1,
4742 &dra7xx_l4_per1__mcspi2,
4743 &dra7xx_l4_per1__mcspi3,
4744 &dra7xx_l4_per1__mcspi4,
4745 &dra7xx_l4_per1__mmc1,
4746 &dra7xx_l4_per1__mmc2,
4747 &dra7xx_l4_per1__mmc3,
4748 &dra7xx_l4_per1__mmc4,
4749 &dra7xx_l3_main_1__mmu0_dsp1,
4750 &dra7xx_l3_main_1__mmu1_dsp1,
4751 &dra7xx_l3_main_1__mmu_ipu1,
4752 &dra7xx_l3_main_1__mmu_ipu2,
4753 &dra7xx_l4_cfg__mpu,
4754 &dra7xx_l4_cfg__ocp2scp1,
4755 &dra7xx_l4_cfg__ocp2scp3,
4756 &dra7xx_l3_main_1__pciess1,
4757 &dra7xx_l4_cfg__pciess1,
4758 &dra7xx_l3_main_1__pciess2,
4759 &dra7xx_l4_cfg__pciess2,
4760 &dra7xx_l4_cfg__pruss1, /* AM57xx only */
4761 &dra7xx_l4_cfg__pruss2, /* AM57xx only */
4762 &dra7xx_l3_main_1__qspi,
4763 &dra7xx_l4_per3__rtcss,
4764 &dra7xx_l4_cfg__sata,
4765 &dra7xx_l4_cfg__smartreflex_core,
4766 &dra7xx_l4_cfg__smartreflex_mpu,
4767 &dra7xx_l4_cfg__spinlock,
4768 &dra7xx_l4_wkup__timer1,
4769 &dra7xx_l4_per1__timer2,
4770 &dra7xx_l4_per1__timer3,
4771 &dra7xx_l4_per1__timer4,
4772 &dra7xx_l4_per3__timer5,
4773 &dra7xx_l4_per3__timer6,
4774 &dra7xx_l4_per3__timer7,
4775 &dra7xx_l4_per3__timer8,
4776 &dra7xx_l4_per1__timer9,
4777 &dra7xx_l4_per1__timer10,
4778 &dra7xx_l4_per1__timer11,
4779 &dra7xx_l4_per3__timer13,
4780 &dra7xx_l4_per3__timer14,
4781 &dra7xx_l4_per3__timer15,
4782 &dra7xx_l4_per3__timer16,
4783 &dra7xx_l4_per1__uart1,
4784 &dra7xx_l4_per1__uart2,
4785 &dra7xx_l4_per1__uart3,
4786 &dra7xx_l4_per1__uart4,
4787 &dra7xx_l4_per1__uart5,
4788 &dra7xx_l4_per1__uart6,
4789 &dra7xx_l4_per2__uart7,
4790 &dra7xx_l4_per2__uart8,
4791 &dra7xx_l4_per2__uart9,
4792 &dra7xx_l4_wkup__uart10,
4793 &dra7xx_l4_per1__des,
4794 &dra7xx_l4_per1__rng,
4795 &dra7xx_l4_per3__usb_otg_ss1,
4796 &dra7xx_l4_per3__usb_otg_ss2,
4797 &dra7xx_l4_per3__usb_otg_ss3,
4798 &dra7xx_l3_main_1__vcp1,
4799 &dra7xx_l4_per2__vcp1,
4800 &dra7xx_l3_main_1__vcp2,
4801 &dra7xx_l4_per2__vcp2,
4802 &dra7xx_l4_per3__vpe,
4803 &dra7xx_l4_per3__vip1,
4804 &dra7xx_l4_wkup__wd_timer2,
4805 &dra7xx_l4_per2__epwmss0,
4806 &dra7xx_epwmss0__ecap0,
4807 &dra7xx_epwmss0__eqep0,
4808 &dra7xx_epwmss0__ehrpwm0,
4809 &dra7xx_l4_per2__epwmss1,
4810 &dra7xx_epwmss1__ecap1,
4811 &dra7xx_epwmss1__eqep1,
4812 &dra7xx_epwmss1__ehrpwm1,
4813 &dra7xx_l4_per2__epwmss2,
4814 &dra7xx_epwmss2__ecap2,
4815 &dra7xx_epwmss2__eqep2,
4816 &dra7xx_epwmss2__ehrpwm2,
4817 NULL,
4818 };
4820 static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
4821 &dra7xx_l4_per3__usb_otg_ss4,
4822 &dra7xx_l3_main_1__mmu0_dsp2,
4823 &dra7xx_l3_main_1__mmu1_dsp2,
4824 &dra7xx_dsp2__l3_main_1,
4825 &dra7xx_l4_per3__vip2,
4826 &dra7xx_l4_per3__vip3,
4827 NULL,
4828 };
4830 static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
4831 &dra7xx_l4_per3__cal,
4832 NULL,
4833 };
4835 static struct omap_hwmod_ocp_if *dra7xx_gp_hwmod_ocp_ifs[] __initdata = {
4836 &dra7xx_l4_wkup__timer12,
4837 NULL,
4838 };
4840 int __init dra7xx_hwmod_init(void)
4841 {
4842 int ret;
4844 omap_hwmod_init();
4846 if (OMAP2_DEVICE_TYPE_GP != omap_type()) {
4847 /* AES, DES, SHAM and RNG HWAs are shared between secure and public
4848 worlds for a HS/EMU device. In this case the module clocks are
4849 already enabled and should not be touched by the kernel driver.
4850 */
4851 dra7xx_aes_hwmod_class.sysc = NULL;
4852 dra7xx_aes_hwmod_class.rev = 0;
4853 dra7xx_aes1_hwmod.prcm.omap4.modulemode = 0;
4854 dra7xx_aes2_hwmod.prcm.omap4.modulemode = 0;
4856 dra7xx_des_hwmod_class.sysc = NULL;
4857 dra7xx_des_hwmod_class.rev = 0;
4858 dra7xx_des_hwmod.prcm.omap4.modulemode = 0;
4860 dra7xx_sha0_hwmod_class.sysc = NULL;
4861 dra7xx_sha0_hwmod_class.rev = 0;
4862 dra7xx_sha0_hwmod.prcm.omap4.modulemode = 0;
4864 dra7xx_rng_hwmod_class.sysc = NULL;
4865 dra7xx_rng_hwmod_class.rev = 0;
4866 dra7xx_rng_hwmod.prcm.omap4.modulemode = 0;
4867 }
4869 ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
4871 if (!ret && OMAP2_DEVICE_TYPE_GP == omap_type())
4872 ret = omap_hwmod_register_links(dra7xx_gp_hwmod_ocp_ifs);
4874 if (!ret && soc_is_dra74x())
4875 return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
4876 else if (!ret && soc_is_dra72x())
4877 return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
4879 return ret;
4880 }