1 /*
2 * DRA7xx Power domains framework
3 *
4 * Copyright (C) 2009-2011 Texas Instruments, Inc.
5 * Copyright (C) 2009-2011 Nokia Corporation
6 *
7 * Abhijit Pagare (abhijitpagare@ti.com)
8 * Benoit Cousson (b-cousson@ti.com)
9 * Paul Walmsley (paul@pwsan.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 */
22 #include <linux/kernel.h>
23 #include <linux/init.h>
25 #include "powerdomain.h"
27 #include "prcm-common.h"
28 #include "prcm44xx.h"
29 #include "prm-regbits-7xx.h"
30 #include "prm7xx.h"
31 #include "prcm_mpu7xx.h"
33 /* iva_7xx_pwrdm: IVA-HD power domain */
34 static struct powerdomain iva_7xx_pwrdm = {
35 .name = "iva_pwrdm",
36 .voltdm = { .name = "avatar" },
37 .prcm_offs = DRA7XX_PRM_IVA_INST,
38 .prcm_partition = DRA7XX_PRM_PARTITION,
39 .pwrsts = PWRSTS_OFF_RET_ON,
40 .pwrsts_logic_ret = PWRSTS_OFF,
41 .banks = 4,
42 .pwrsts_mem_ret = {
43 [0] = PWRSTS_OFF_RET, /* hwa_mem */
44 [1] = PWRSTS_OFF_RET, /* sl2_mem */
45 [2] = PWRSTS_OFF_RET, /* tcm1_mem */
46 [3] = PWRSTS_OFF_RET, /* tcm2_mem */
47 },
48 .pwrsts_mem_on = {
49 [0] = PWRSTS_OFF_RET, /* hwa_mem */
50 [1] = PWRSTS_OFF_RET, /* sl2_mem */
51 [2] = PWRSTS_OFF_RET, /* tcm1_mem */
52 [3] = PWRSTS_OFF_RET, /* tcm2_mem */
53 },
54 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
55 };
57 /* rtc_7xx_pwrdm: */
58 static struct powerdomain rtc_7xx_pwrdm = {
59 .name = "rtc_pwrdm",
60 .voltdm = { .name = "avatar" },
61 .prcm_offs = DRA7XX_PRM_RTC_INST,
62 .prcm_partition = DRA7XX_PRM_PARTITION,
63 .pwrsts = PWRSTS_ON,
64 };
66 /* custefuse_7xx_pwrdm: Customer efuse controller power domain */
67 static struct powerdomain custefuse_7xx_pwrdm = {
68 .name = "custefuse_pwrdm",
69 .voltdm = { .name = "avatar" },
70 .prcm_offs = DRA7XX_PRM_CUSTEFUSE_INST,
71 .prcm_partition = DRA7XX_PRM_PARTITION,
72 .pwrsts = PWRSTS_OFF_ON,
73 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
74 };
76 /* ipu_7xx_pwrdm: Audio back end power domain */
77 static struct powerdomain ipu_7xx_pwrdm = {
78 .name = "ipu_pwrdm",
79 .voltdm = { .name = "avatar" },
80 .prcm_offs = DRA7XX_PRM_IPU_INST,
81 .prcm_partition = DRA7XX_PRM_PARTITION,
82 .pwrsts = PWRSTS_OFF_RET_ON,
83 .pwrsts_logic_ret = PWRSTS_OFF,
84 .banks = 2,
85 .pwrsts_mem_ret = {
86 [0] = PWRSTS_OFF_RET, /* aessmem */
87 [1] = PWRSTS_OFF_RET, /* periphmem */
88 },
89 .pwrsts_mem_on = {
90 [0] = PWRSTS_OFF_RET, /* aessmem */
91 [1] = PWRSTS_OFF_RET, /* periphmem */
92 },
93 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
94 };
96 /* dss_7xx_pwrdm: Display subsystem power domain */
97 static struct powerdomain dss_7xx_pwrdm = {
98 .name = "dss_pwrdm",
99 .voltdm = { .name = "avatar" },
100 .prcm_offs = DRA7XX_PRM_DSS_INST,
101 .prcm_partition = DRA7XX_PRM_PARTITION,
102 .pwrsts = PWRSTS_OFF_RET_ON,
103 .pwrsts_logic_ret = PWRSTS_OFF,
104 .banks = 1,
105 .pwrsts_mem_ret = {
106 [0] = PWRSTS_OFF_RET, /* dss_mem */
107 },
108 .pwrsts_mem_on = {
109 [0] = PWRSTS_OFF_RET, /* dss_mem */
110 },
111 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
112 };
114 /* l4per_7xx_pwrdm: Target peripherals power domain */
115 static struct powerdomain l4per_7xx_pwrdm = {
116 .name = "l4per_pwrdm",
117 .voltdm = { .name = "avatar" },
118 .prcm_offs = DRA7XX_PRM_L4PER_INST,
119 .prcm_partition = DRA7XX_PRM_PARTITION,
120 .pwrsts = PWRSTS_RET_ON,
121 .pwrsts_logic_ret = PWRSTS_OFF_RET,
122 .banks = 2,
123 .pwrsts_mem_ret = {
124 [0] = PWRSTS_OFF_RET, /* nonretained_bank */
125 [1] = PWRSTS_OFF_RET, /* retained_bank */
126 },
127 .pwrsts_mem_on = {
128 [0] = PWRSTS_OFF_RET, /* nonretained_bank */
129 [1] = PWRSTS_OFF_RET, /* retained_bank */
130 },
131 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
132 };
134 /* gpu_7xx_pwrdm: 3D accelerator power domain */
135 static struct powerdomain gpu_7xx_pwrdm = {
136 .name = "gpu_pwrdm",
137 .voltdm = { .name = "avatar" },
138 .prcm_offs = DRA7XX_PRM_GPU_INST,
139 .prcm_partition = DRA7XX_PRM_PARTITION,
140 .pwrsts = PWRSTS_OFF_ON,
141 .banks = 1,
142 .pwrsts_mem_ret = {
143 [0] = PWRSTS_OFF_RET, /* gpu_mem */
144 },
145 .pwrsts_mem_on = {
146 [0] = PWRSTS_OFF_RET, /* gpu_mem */
147 },
148 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
149 };
151 /* wkupaon_7xx_pwrdm: Wake-up power domain */
152 static struct powerdomain wkupaon_7xx_pwrdm = {
153 .name = "wkupaon_pwrdm",
154 .voltdm = { .name = "avatar" },
155 .prcm_offs = DRA7XX_PRM_WKUPAON_INST,
156 .prcm_partition = DRA7XX_PRM_PARTITION,
157 .pwrsts = PWRSTS_ON,
158 .banks = 1,
159 .pwrsts_mem_ret = {
160 },
161 .pwrsts_mem_on = {
162 [0] = PWRSTS_ON, /* wkup_bank */
163 },
164 };
166 /* core_7xx_pwrdm: CORE power domain */
167 static struct powerdomain core_7xx_pwrdm = {
168 .name = "core_pwrdm",
169 .voltdm = { .name = "avatar" },
170 .prcm_offs = DRA7XX_PRM_CORE_INST,
171 .prcm_partition = DRA7XX_PRM_PARTITION,
172 .pwrsts = PWRSTS_RET_ON,
173 .pwrsts_logic_ret = PWRSTS_OFF_RET,
174 .banks = 5,
175 .pwrsts_mem_ret = {
176 [0] = PWRSTS_OFF_RET, /* core_nret_bank */
177 [1] = PWRSTS_OFF_RET, /* core_ocmram */
178 [2] = PWRSTS_OFF_RET, /* core_other_bank */
179 [3] = PWRSTS_OFF_RET, /* ipu_l2ram */
180 [4] = PWRSTS_OFF_RET, /* ipu_unicache */
181 },
182 .pwrsts_mem_on = {
183 [0] = PWRSTS_OFF_RET, /* core_nret_bank */
184 [1] = PWRSTS_OFF_RET, /* core_ocmram */
185 [2] = PWRSTS_OFF_RET, /* core_other_bank */
186 [3] = PWRSTS_OFF_RET, /* ipu_l2ram */
187 [4] = PWRSTS_OFF_RET, /* ipu_unicache */
188 },
189 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
190 };
192 /* coreaon_7xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */
193 static struct powerdomain coreaon_7xx_pwrdm = {
194 .name = "coreaon_pwrdm",
195 .voltdm = { .name = "avatar" },
196 .prcm_offs = DRA7XX_PRM_COREAON_INST,
197 .prcm_partition = DRA7XX_PRM_PARTITION,
198 .pwrsts = PWRSTS_ON,
199 };
201 /* cpu0_7xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
202 static struct powerdomain cpu0_7xx_pwrdm = {
203 .name = "cpu0_pwrdm",
204 .voltdm = { .name = "mpu" },
205 .prcm_offs = DRA7XX_MPU_PRCM_PRM_C0_INST,
206 .prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
207 .pwrsts = PWRSTS_OFF_RET_ON,
208 .pwrsts_logic_ret = PWRSTS_OFF_RET,
209 .banks = 1,
210 .pwrsts_mem_ret = {
211 [0] = PWRSTS_OFF_RET, /* cpu0_l1 */
212 },
213 .pwrsts_mem_on = {
214 [0] = PWRSTS_ON, /* cpu0_l1 */
215 },
216 };
218 /* cpu1_7xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
219 static struct powerdomain cpu1_7xx_pwrdm = {
220 .name = "cpu1_pwrdm",
221 .voltdm = { .name = "mpu" },
222 .prcm_offs = DRA7XX_MPU_PRCM_PRM_C1_INST,
223 .prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
224 .pwrsts = PWRSTS_OFF_RET_ON,
225 .pwrsts_logic_ret = PWRSTS_OFF_RET,
226 .banks = 1,
227 .pwrsts_mem_ret = {
228 [0] = PWRSTS_OFF_RET, /* cpu1_l1 */
229 },
230 .pwrsts_mem_on = {
231 [0] = PWRSTS_ON, /* cpu1_l1 */
232 },
233 };
235 /* vpe_7xx_pwrdm: */
236 static struct powerdomain vpe_7xx_pwrdm = {
237 .name = "vpe_pwrdm",
238 .voltdm = { .name = "avatar" },
239 .prcm_offs = DRA7XX_PRM_VPE_INST,
240 .prcm_partition = DRA7XX_PRM_PARTITION,
241 .pwrsts = PWRSTS_OFF_RET_ON,
242 .pwrsts_logic_ret = PWRSTS_OFF_RET,
243 .banks = 1,
244 .pwrsts_mem_ret = {
245 [0] = PWRSTS_OFF_RET, /* vpe_bank */
246 },
247 .pwrsts_mem_on = {
248 [0] = PWRSTS_OFF_RET, /* vpe_bank */
249 },
250 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
251 };
253 /* mpu_7xx_pwrdm: Modena processor and the Neon coprocessor power domain */
254 static struct powerdomain mpu_7xx_pwrdm = {
255 .name = "mpu_pwrdm",
256 .voltdm = { .name = "avatar" },
257 .prcm_offs = DRA7XX_PRM_MPU_INST,
258 .prcm_partition = DRA7XX_PRM_PARTITION,
259 .pwrsts = PWRSTS_RET_ON,
260 .pwrsts_logic_ret = PWRSTS_OFF_RET,
261 .banks = 2,
262 .pwrsts_mem_ret = {
263 [0] = PWRSTS_OFF_RET, /* mpu_l2 */
264 [1] = PWRSTS_RET, /* mpu_ram */
265 },
266 .pwrsts_mem_on = {
267 [0] = PWRSTS_OFF_RET, /* mpu_l2 */
268 [1] = PWRSTS_OFF_RET, /* mpu_ram */
269 },
270 };
272 /* l3init_7xx_pwrdm: L3 initators pheripherals power domain */
273 static struct powerdomain l3init_7xx_pwrdm = {
274 .name = "l3init_pwrdm",
275 .voltdm = { .name = "avatar" },
276 .prcm_offs = DRA7XX_PRM_L3INIT_INST,
277 .prcm_partition = DRA7XX_PRM_PARTITION,
278 .pwrsts = PWRSTS_RET_ON,
279 .pwrsts_logic_ret = PWRSTS_OFF_RET,
280 .banks = 3,
281 .pwrsts_mem_ret = {
282 [0] = PWRSTS_OFF_RET, /* gmac_bank */
283 [1] = PWRSTS_OFF_RET, /* l3init_bank1 */
284 [2] = PWRSTS_OFF_RET, /* l3init_bank2 */
285 },
286 .pwrsts_mem_on = {
287 [0] = PWRSTS_OFF_RET, /* gmac_bank */
288 [1] = PWRSTS_OFF_RET, /* l3init_bank1 */
289 [2] = PWRSTS_OFF_RET, /* l3init_bank2 */
290 },
291 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
292 };
294 /* eve3_7xx_pwrdm: */
295 static struct powerdomain eve3_7xx_pwrdm = {
296 .name = "eve3_pwrdm",
297 .voltdm = { .name = "avatar" },
298 .prcm_offs = DRA7XX_PRM_EVE3_INST,
299 .prcm_partition = DRA7XX_PRM_PARTITION,
300 .pwrsts = PWRSTS_OFF_ON,
301 .banks = 1,
302 .pwrsts_mem_ret = {
303 [0] = PWRSTS_OFF_RET, /* eve3_bank */
304 },
305 .pwrsts_mem_on = {
306 [0] = PWRSTS_OFF_RET, /* eve3_bank */
307 },
308 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
309 };
311 /* emu_7xx_pwrdm: Emulation power domain */
312 static struct powerdomain emu_7xx_pwrdm = {
313 .name = "emu_pwrdm",
314 .voltdm = { .name = "avatar" },
315 .prcm_offs = DRA7XX_PRM_EMU_INST,
316 .prcm_partition = DRA7XX_PRM_PARTITION,
317 .pwrsts = PWRSTS_OFF_ON,
318 .banks = 1,
319 .pwrsts_mem_ret = {
320 [0] = PWRSTS_OFF_RET, /* emu_bank */
321 },
322 .pwrsts_mem_on = {
323 [0] = PWRSTS_OFF_RET, /* emu_bank */
324 },
325 };
327 /* dsp2_7xx_pwrdm: */
328 static struct powerdomain dsp2_7xx_pwrdm = {
329 .name = "dsp2_pwrdm",
330 .voltdm = { .name = "avatar" },
331 .prcm_offs = DRA7XX_PRM_DSP2_INST,
332 .prcm_partition = DRA7XX_PRM_PARTITION,
333 .pwrsts = PWRSTS_OFF_ON,
334 .banks = 3,
335 .pwrsts_mem_ret = {
336 [0] = PWRSTS_OFF_RET, /* dsp2_edma */
337 [1] = PWRSTS_OFF_RET, /* dsp2_l1 */
338 [2] = PWRSTS_OFF_RET, /* dsp2_l2 */
339 },
340 .pwrsts_mem_on = {
341 [0] = PWRSTS_OFF_RET, /* dsp2_edma */
342 [1] = PWRSTS_OFF_RET, /* dsp2_l1 */
343 [2] = PWRSTS_OFF_RET, /* dsp2_l2 */
344 },
345 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
346 };
348 /* dsp1_7xx_pwrdm: Tesla processor power domain */
349 static struct powerdomain dsp1_7xx_pwrdm = {
350 .name = "dsp1_pwrdm",
351 .voltdm = { .name = "avatar" },
352 .prcm_offs = DRA7XX_PRM_DSP1_INST,
353 .prcm_partition = DRA7XX_PRM_PARTITION,
354 .pwrsts = PWRSTS_OFF_ON,
355 .banks = 3,
356 .pwrsts_mem_ret = {
357 [0] = PWRSTS_OFF_RET, /* dsp1_edma */
358 [1] = PWRSTS_OFF_RET, /* dsp1_l1 */
359 [2] = PWRSTS_OFF_RET, /* dsp1_l2 */
360 },
361 .pwrsts_mem_on = {
362 [0] = PWRSTS_OFF_RET, /* dsp1_edma */
363 [1] = PWRSTS_OFF_RET, /* dsp1_l1 */
364 [2] = PWRSTS_OFF_RET, /* dsp1_l2 */
365 },
366 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
367 };
369 /* cam_7xx_pwrdm: Camera subsystem power domain */
370 static struct powerdomain cam_7xx_pwrdm = {
371 .name = "cam_pwrdm",
372 .voltdm = { .name = "avatar" },
373 .prcm_offs = DRA7XX_PRM_CAM_INST,
374 .prcm_partition = DRA7XX_PRM_PARTITION,
375 .pwrsts = PWRSTS_OFF_ON,
376 .banks = 1,
377 .pwrsts_mem_ret = {
378 [0] = PWRSTS_OFF_RET, /* vip_bank */
379 },
380 .pwrsts_mem_on = {
381 [0] = PWRSTS_OFF_RET, /* vip_bank */
382 },
383 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
384 };
386 /* eve4_7xx_pwrdm: */
387 static struct powerdomain eve4_7xx_pwrdm = {
388 .name = "eve4_pwrdm",
389 .voltdm = { .name = "avatar" },
390 .prcm_offs = DRA7XX_PRM_EVE4_INST,
391 .prcm_partition = DRA7XX_PRM_PARTITION,
392 .pwrsts = PWRSTS_OFF_ON,
393 .banks = 1,
394 .pwrsts_mem_ret = {
395 [0] = PWRSTS_OFF_RET, /* eve4_bank */
396 },
397 .pwrsts_mem_on = {
398 [0] = PWRSTS_OFF_RET, /* eve4_bank */
399 },
400 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
401 };
403 /* eve2_7xx_pwrdm: */
404 static struct powerdomain eve2_7xx_pwrdm = {
405 .name = "eve2_pwrdm",
406 .voltdm = { .name = "avatar" },
407 .prcm_offs = DRA7XX_PRM_EVE2_INST,
408 .prcm_partition = DRA7XX_PRM_PARTITION,
409 .pwrsts = PWRSTS_OFF_ON,
410 .banks = 1,
411 .pwrsts_mem_ret = {
412 [0] = PWRSTS_OFF_RET, /* eve2_bank */
413 },
414 .pwrsts_mem_on = {
415 [0] = PWRSTS_OFF_RET, /* eve2_bank */
416 },
417 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
418 };
420 /* eve1_7xx_pwrdm: */
421 static struct powerdomain eve1_7xx_pwrdm = {
422 .name = "eve1_pwrdm",
423 .voltdm = { .name = "avatar" },
424 .prcm_offs = DRA7XX_PRM_EVE1_INST,
425 .prcm_partition = DRA7XX_PRM_PARTITION,
426 .pwrsts = PWRSTS_OFF_ON,
427 .banks = 1,
428 .pwrsts_mem_ret = {
429 [0] = PWRSTS_OFF_RET, /* eve1_bank */
430 },
431 .pwrsts_mem_on = {
432 [0] = PWRSTS_OFF_RET, /* eve1_bank */
433 },
434 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
435 };
437 /*
438 * The following power domains are not under SW control
439 *
440 * mpuaon
441 * mmaon
442 */
444 /* As powerdomains are added or removed above, this list must also be changed */
445 static struct powerdomain *powerdomains_dra7xx[] __initdata = {
446 &iva_7xx_pwrdm,
447 &rtc_7xx_pwrdm,
448 &custefuse_7xx_pwrdm,
449 &ipu_7xx_pwrdm,
450 &dss_7xx_pwrdm,
451 &l4per_7xx_pwrdm,
452 &gpu_7xx_pwrdm,
453 &wkupaon_7xx_pwrdm,
454 &core_7xx_pwrdm,
455 &coreaon_7xx_pwrdm,
456 &cpu0_7xx_pwrdm,
457 &cpu1_7xx_pwrdm,
458 &vpe_7xx_pwrdm,
459 &mpu_7xx_pwrdm,
460 &l3init_7xx_pwrdm,
461 &eve3_7xx_pwrdm,
462 &emu_7xx_pwrdm,
463 &dsp2_7xx_pwrdm,
464 &dsp1_7xx_pwrdm,
465 &cam_7xx_pwrdm,
466 &eve4_7xx_pwrdm,
467 &eve2_7xx_pwrdm,
468 &eve1_7xx_pwrdm,
469 NULL
470 };
472 void __init dra7xx_powerdomains_init(void)
473 {
474 pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
475 pwrdm_register_pwrdms(powerdomains_dra7xx);
476 pwrdm_complete_init();
477 }