OMAP: cdm data: Use sw sleep/wkup instead of hw_auto for dss

[android-sdk/kernel-video.git] / arch / arm / mach-omap2 / prm-regbits-7xx.h

/*
 * DRA7xx Power Management register bits
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
 *
 * Paul Walmsley (paul@pwsan.com)
 * Rajendra Nayak (rnayak@ti.com)
 * Benoit Cousson (b-cousson@ti.com)
 *
 * This file is automatically generated from the OMAP hardware databases.
 * We respectfully ask that any modifications to this file be coordinated
 * with the public linux-omap@vger.kernel.org mailing list and the
 * authors above to ensure that the autogeneration scripts are kept
 * up-to-date with the file contents.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_7XX_H
#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_7XX_H

/*
 * Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_DSPEVE_SETUP, PRM_SLDO_GPU_SETUP,
 * PRM_SLDO_IVA_SETUP, PRM_SLDO_MPU_SETUP
 */
#define DRA7XX_ABBOFF_ACT_SHIFT                                 1
#define DRA7XX_ABBOFF_ACT_WIDTH                                 0x1
#define DRA7XX_ABBOFF_ACT_MASK                                  (1 << 1)

/*
 * Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_DSPEVE_SETUP, PRM_SLDO_GPU_SETUP,
 * PRM_SLDO_IVA_SETUP, PRM_SLDO_MPU_SETUP
 */
#define DRA7XX_ABBOFF_SLEEP_SHIFT                               2
#define DRA7XX_ABBOFF_SLEEP_WIDTH                               0x1
#define DRA7XX_ABBOFF_SLEEP_MASK                                (1 << 2)

/*
 * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
 * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
 * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2
 */
#define DRA7XX_ABB_DSPEVE_DONE_EN_SHIFT                         29
#define DRA7XX_ABB_DSPEVE_DONE_EN_WIDTH                         0x1
#define DRA7XX_ABB_DSPEVE_DONE_EN_MASK                          (1 << 29)

/* Renamed from ABB_DSPEVE_DONE_EN Used by PRM_IRQENABLE_MPU */
#define DRA7XX_ABB_DSPEVE_DONE_EN_30_30_SHIFT                   30
#define DRA7XX_ABB_DSPEVE_DONE_EN_30_30_WIDTH                   0x1
#define DRA7XX_ABB_DSPEVE_DONE_EN_30_30_MASK                    (1 << 30)

/*
 * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
 * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
 * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
 */
#define DRA7XX_ABB_DSPEVE_DONE_ST_SHIFT                         29
#define DRA7XX_ABB_DSPEVE_DONE_ST_WIDTH                         0x1
#define DRA7XX_ABB_DSPEVE_DONE_ST_MASK                          (1 << 29)

/*
 * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
 * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
 * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2
 */
#define DRA7XX_ABB_GPU_DONE_EN_SHIFT                            28
#define DRA7XX_ABB_GPU_DONE_EN_WIDTH                            0x1
#define DRA7XX_ABB_GPU_DONE_EN_MASK                             (1 << 28)

/* Renamed from ABB_GPU_DONE_EN Used by PRM_IRQENABLE_MPU */
#define DRA7XX_ABB_GPU_DONE_EN_PRM_IRQENABLE_MPU_SHIFT          29
#define DRA7XX_ABB_GPU_DONE_EN_PRM_IRQENABLE_MPU_WIDTH          0x1
#define DRA7XX_ABB_GPU_DONE_EN_PRM_IRQENABLE_MPU_MASK           (1 << 29)

/*
 * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
 * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
 * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
 */
#define DRA7XX_ABB_GPU_DONE_ST_SHIFT                            28
#define DRA7XX_ABB_GPU_DONE_ST_WIDTH                            0x1
#define DRA7XX_ABB_GPU_DONE_ST_MASK                             (1 << 28)

/*
 * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
 * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
 * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2
 */
#define DRA7XX_ABB_IVA_DONE_EN_SHIFT                            30
#define DRA7XX_ABB_IVA_DONE_EN_WIDTH                            0x1
#define DRA7XX_ABB_IVA_DONE_EN_MASK                             (1 << 30)

/* Renamed from ABB_IVA_DONE_EN Used by PRM_IRQENABLE_MPU */
#define DRA7XX_ABB_IVA_DONE_EN_PRM_IRQENABLE_MPU_SHIFT          31
#define DRA7XX_ABB_IVA_DONE_EN_PRM_IRQENABLE_MPU_WIDTH          0x1
#define DRA7XX_ABB_IVA_DONE_EN_PRM_IRQENABLE_MPU_MASK           (1 << 31)

/*
 * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
 * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
 * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
 */
#define DRA7XX_ABB_IVA_DONE_ST_SHIFT                            30
#define DRA7XX_ABB_IVA_DONE_ST_WIDTH                            0x1
#define DRA7XX_ABB_IVA_DONE_ST_MASK                             (1 << 30)

/*
 * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
 * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
 * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2
 */
#define DRA7XX_ABB_MPU_DONE_EN_SHIFT                            31
#define DRA7XX_ABB_MPU_DONE_EN_WIDTH                            0x1
#define DRA7XX_ABB_MPU_DONE_EN_MASK                             (1 << 31)

/* Renamed from ABB_MPU_DONE_EN Used by PRM_IRQENABLE_MPU_2 */
#define DRA7XX_ABB_MPU_DONE_EN_7_7_SHIFT                        7
#define DRA7XX_ABB_MPU_DONE_EN_7_7_WIDTH                        0x1
#define DRA7XX_ABB_MPU_DONE_EN_7_7_MASK                         (1 << 7)

/*
 * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
 * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
 * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2
 */
#define DRA7XX_ABB_MPU_DONE_ST_SHIFT                            31
#define DRA7XX_ABB_MPU_DONE_ST_WIDTH                            0x1
#define DRA7XX_ABB_MPU_DONE_ST_MASK                             (1 << 31)

/* Renamed from ABB_MPU_DONE_ST Used by PRM_IRQSTATUS_MPU_2 */
#define DRA7XX_ABB_MPU_DONE_ST_7_7_SHIFT                        7
#define DRA7XX_ABB_MPU_DONE_ST_7_7_WIDTH                        0x1
#define DRA7XX_ABB_MPU_DONE_ST_7_7_MASK                         (1 << 7)

/*
 * Used by PRM_ABBLDO_DSPEVE_SETUP, PRM_ABBLDO_GPU_SETUP, PRM_ABBLDO_IVA_SETUP,
 * PRM_ABBLDO_MPU_SETUP
 */
#define DRA7XX_ACTIVE_FBB_SEL_SHIFT                             2
#define DRA7XX_ACTIVE_FBB_SEL_WIDTH                             0x1
#define DRA7XX_ACTIVE_FBB_SEL_MASK                              (1 << 2)

/* Used by PM_IPU_PWRSTCTRL */
#define DRA7XX_AESSMEM_ONSTATE_SHIFT                            16
#define DRA7XX_AESSMEM_ONSTATE_WIDTH                            0x2
#define DRA7XX_AESSMEM_ONSTATE_MASK                             (0x3 << 16)

/* Used by PM_IPU_PWRSTCTRL */
#define DRA7XX_AESSMEM_RETSTATE_SHIFT                           8
#define DRA7XX_AESSMEM_RETSTATE_WIDTH                           0x1
#define DRA7XX_AESSMEM_RETSTATE_MASK                            (1 << 8)

/* Used by PM_IPU_PWRSTST */
#define DRA7XX_AESSMEM_STATEST_SHIFT                            4
#define DRA7XX_AESSMEM_STATEST_WIDTH                            0x2
#define DRA7XX_AESSMEM_STATEST_MASK                             (0x3 << 4)

/*
 * Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_DSPEVE_SETUP, PRM_SLDO_GPU_SETUP,
 * PRM_SLDO_IVA_SETUP, PRM_SLDO_MPU_SETUP
 */
#define DRA7XX_AIPOFF_SHIFT                                     8
#define DRA7XX_AIPOFF_WIDTH                                     0x1
#define DRA7XX_AIPOFF_MASK                                      (1 << 8)

/* Used by PRM_VOLTCTRL */
#define DRA7XX_AUTO_CTRL_VDD_CORE_L_SHIFT                       0
#define DRA7XX_AUTO_CTRL_VDD_CORE_L_WIDTH                       0x2
#define DRA7XX_AUTO_CTRL_VDD_CORE_L_MASK                        (0x3 << 0)

/* Used by PRM_VOLTCTRL */
#define DRA7XX_AUTO_CTRL_VDD_MM_L_SHIFT                         4
#define DRA7XX_AUTO_CTRL_VDD_MM_L_WIDTH                         0x2
#define DRA7XX_AUTO_CTRL_VDD_MM_L_MASK                          (0x3 << 4)

/* Used by PRM_VOLTCTRL */
#define DRA7XX_AUTO_CTRL_VDD_MPU_L_SHIFT                        2
#define DRA7XX_AUTO_CTRL_VDD_MPU_L_WIDTH                        0x2
#define DRA7XX_AUTO_CTRL_VDD_MPU_L_MASK                         (0x3 << 2)

/* Used by PRM_RSTST */
#define DRA7XX_C2C_RST_SHIFT                                    10
#define DRA7XX_C2C_RST_WIDTH                                    0x1
#define DRA7XX_C2C_RST_MASK                                     (1 << 10)

/* Used by PRM_CLKREQCTRL */
#define DRA7XX_CLKREQ_COND_SHIFT                                0
#define DRA7XX_CLKREQ_COND_WIDTH                                0x3
#define DRA7XX_CLKREQ_COND_MASK                                 (0x7 << 0)

/* Used by PM_CORE_PWRSTCTRL */
#define DRA7XX_CORE_OCMRAM_ONSTATE_SHIFT                        18
#define DRA7XX_CORE_OCMRAM_ONSTATE_WIDTH                        0x2
#define DRA7XX_CORE_OCMRAM_ONSTATE_MASK                         (0x3 << 18)

/* Used by PM_CORE_PWRSTCTRL */
#define DRA7XX_CORE_OCMRAM_RETSTATE_SHIFT                       9
#define DRA7XX_CORE_OCMRAM_RETSTATE_WIDTH                       0x1
#define DRA7XX_CORE_OCMRAM_RETSTATE_MASK                        (1 << 9)

/* Used by PM_CORE_PWRSTST */
#define DRA7XX_CORE_OCMRAM_STATEST_SHIFT                        6
#define DRA7XX_CORE_OCMRAM_STATEST_WIDTH                        0x2
#define DRA7XX_CORE_OCMRAM_STATEST_MASK                         (0x3 << 6)

/* Used by PM_CORE_PWRSTCTRL */
#define DRA7XX_CORE_OTHER_BANK_ONSTATE_SHIFT                    16
#define DRA7XX_CORE_OTHER_BANK_ONSTATE_WIDTH                    0x2
#define DRA7XX_CORE_OTHER_BANK_ONSTATE_MASK                     (0x3 << 16)

/* Used by PM_CORE_PWRSTCTRL */
#define DRA7XX_CORE_OTHER_BANK_RETSTATE_SHIFT                   8
#define DRA7XX_CORE_OTHER_BANK_RETSTATE_WIDTH                   0x1
#define DRA7XX_CORE_OTHER_BANK_RETSTATE_MASK                    (1 << 8)

/* Used by PM_CORE_PWRSTST */
#define DRA7XX_CORE_OTHER_BANK_STATEST_SHIFT                    4
#define DRA7XX_CORE_OTHER_BANK_STATEST_WIDTH                    0x2
#define DRA7XX_CORE_OTHER_BANK_STATEST_MASK                     (0x3 << 4)

/* Used by REVISION_PRM */
#define DRA7XX_CUSTOM_SHIFT                                     6
#define DRA7XX_CUSTOM_WIDTH                                     0x2
#define DRA7XX_CUSTOM_MASK                                      (0x3 << 6)

/* Used by PRM_DEVICE_OFF_CTRL */
#define DRA7XX_DEVICE_OFF_ENABLE_SHIFT                          0
#define DRA7XX_DEVICE_OFF_ENABLE_WIDTH                          0x1
#define DRA7XX_DEVICE_OFF_ENABLE_MASK                           (1 << 0)

/*
 * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
 * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
 * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2, PRM_IRQENABLE_MPU
 */
#define DRA7XX_DPLL_ABE_RECAL_EN_SHIFT                          4
#define DRA7XX_DPLL_ABE_RECAL_EN_WIDTH                          0x1
#define DRA7XX_DPLL_ABE_RECAL_EN_MASK                           (1 << 4)

/*
 * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
 * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
 * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
 */
#define DRA7XX_DPLL_ABE_RECAL_ST_SHIFT                          4
#define DRA7XX_DPLL_ABE_RECAL_ST_WIDTH                          0x1
#define DRA7XX_DPLL_ABE_RECAL_ST_MASK                           (1 << 4)

/*
 * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
 * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
 * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2, PRM_IRQENABLE_MPU
 */
#define DRA7XX_DPLL_CORE_RECAL_EN_SHIFT                         0
#define DRA7XX_DPLL_CORE_RECAL_EN_WIDTH                         0x1
#define DRA7XX_DPLL_CORE_RECAL_EN_MASK                          (1 << 0)

/*
 * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
 * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
 * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
 */
#define DRA7XX_DPLL_CORE_RECAL_ST_SHIFT                         0
#define DRA7XX_DPLL_CORE_RECAL_ST_WIDTH                         0x1
#define DRA7XX_DPLL_CORE_RECAL_ST_MASK                          (1 << 0)

/*
 * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
 * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
 * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2, PRM_IRQENABLE_MPU
 */
#define DRA7XX_DPLL_DDR_RECAL_EN_SHIFT                          7
#define DRA7XX_DPLL_DDR_RECAL_EN_WIDTH                          0x1
#define DRA7XX_DPLL_DDR_RECAL_EN_MASK                           (1 << 7)

/*
 * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
 * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
 * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
 */
#define DRA7XX_DPLL_DDR_RECAL_ST_SHIFT                          7
#define DRA7XX_DPLL_DDR_RECAL_ST_WIDTH                          0x1
#define DRA7XX_DPLL_DDR_RECAL_ST_MASK                           (1 << 7)

/*
 * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
 * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
 * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2
 */
#define DRA7XX_DPLL_DSP_RECAL_EN_SHIFT                          11
#define DRA7XX_DPLL_DSP_RECAL_EN_WIDTH                          0x1
#define DRA7XX_DPLL_DSP_RECAL_EN_MASK                           (1 << 11)

/* Renamed from DPLL_DSP_RECAL_EN Used by PRM_IRQENABLE_MPU */
#define DRA7XX_DPLL_DSP_RECAL_EN_PRM_IRQENABLE_MPU_SHIFT        10
#define DRA7XX_DPLL_DSP_RECAL_EN_PRM_IRQENABLE_MPU_WIDTH        0x1
#define DRA7XX_DPLL_DSP_RECAL_EN_PRM_IRQENABLE_MPU_MASK         (1 << 10)

/*
 * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
 * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
 * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
 */
#define DRA7XX_DPLL_DSP_RECAL_ST_SHIFT                          11
#define DRA7XX_DPLL_DSP_RECAL_ST_WIDTH                          0x1
#define DRA7XX_DPLL_DSP_RECAL_ST_MASK                           (1 << 11)

/*
 * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
 * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
 * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2
 */
#define DRA7XX_DPLL_EVE_RECAL_EN_SHIFT                          12
#define DRA7XX_DPLL_EVE_RECAL_EN_WIDTH                          0x1
#define DRA7XX_DPLL_EVE_RECAL_EN_MASK                           (1 << 12)

/* Renamed from DPLL_EVE_RECAL_EN Used by PRM_IRQENABLE_MPU */
#define DRA7XX_DPLL_EVE_RECAL_EN_PRM_IRQENABLE_MPU_SHIFT        11
#define DRA7XX_DPLL_EVE_RECAL_EN_PRM_IRQENABLE_MPU_WIDTH        0x1
#define DRA7XX_DPLL_EVE_RECAL_EN_PRM_IRQENABLE_MPU_MASK         (1 << 11)

/*
 * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
 * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
 * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
 */
#define DRA7XX_DPLL_EVE_RECAL_ST_SHIFT                          12
#define DRA7XX_DPLL_EVE_RECAL_ST_WIDTH                          0x1
#define DRA7XX_DPLL_EVE_RECAL_ST_MASK                           (1 << 12)

/*
 * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
 * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
 * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2, PRM_IRQENABLE_MPU
 */
#define DRA7XX_DPLL_GMAC_RECAL_EN_SHIFT                         5
#define DRA7XX_DPLL_GMAC_RECAL_EN_WIDTH                         0x1
#define DRA7XX_DPLL_GMAC_RECAL_EN_MASK                          (1 << 5)

/*
 * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
 * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
 * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
 */
#define DRA7XX_DPLL_GMAC_RECAL_ST_SHIFT                         5
#define DRA7XX_DPLL_GMAC_RECAL_ST_WIDTH                         0x1
#define DRA7XX_DPLL_GMAC_RECAL_ST_MASK                          (1 << 5)

/*
 * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
 * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
 * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2, PRM_IRQENABLE_MPU
 */
#define DRA7XX_DPLL_GPU_RECAL_EN_SHIFT                          6
#define DRA7XX_DPLL_GPU_RECAL_EN_WIDTH                          0x1
#define DRA7XX_DPLL_GPU_RECAL_EN_MASK                           (1 << 6)

/*
 * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
 * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
 * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
 */
#define DRA7XX_DPLL_GPU_RECAL_ST_SHIFT                          6
#define DRA7XX_DPLL_GPU_RECAL_ST_WIDTH                          0x1
#define DRA7XX_DPLL_GPU_RECAL_ST_MASK                           (1 << 6)

/*
 * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
 * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
 * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2, PRM_IRQENABLE_MPU
 */
#define DRA7XX_DPLL_IVA_RECAL_EN_SHIFT                          2
#define DRA7XX_DPLL_IVA_RECAL_EN_WIDTH                          0x1
#define DRA7XX_DPLL_IVA_RECAL_EN_MASK                           (1 << 2)

/*
 * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
 * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
 * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
 */
#define DRA7XX_DPLL_IVA_RECAL_ST_SHIFT                          2
#define DRA7XX_DPLL_IVA_RECAL_ST_WIDTH                          0x1
#define DRA7XX_DPLL_IVA_RECAL_ST_MASK                           (1 << 2)

/*
 * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
 * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
 * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2, PRM_IRQENABLE_MPU
 */
#define DRA7XX_DPLL_MPU_RECAL_EN_SHIFT                          1
#define DRA7XX_DPLL_MPU_RECAL_EN_WIDTH                          0x1
#define DRA7XX_DPLL_MPU_RECAL_EN_MASK                           (1 << 1)

/*
 * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
 * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
 * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
 */
#define DRA7XX_DPLL_MPU_RECAL_ST_SHIFT                          1
#define DRA7XX_DPLL_MPU_RECAL_ST_WIDTH                          0x1
#define DRA7XX_DPLL_MPU_RECAL_ST_MASK                           (1 << 1)

/*
 * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
 * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
 * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2, PRM_IRQENABLE_MPU
 */
#define DRA7XX_DPLL_PER_RECAL_EN_SHIFT                          3
#define DRA7XX_DPLL_PER_RECAL_EN_WIDTH                          0x1
#define DRA7XX_DPLL_PER_RECAL_EN_MASK                           (1 << 3)

/*
 * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
 * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
 * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
 */
#define DRA7XX_DPLL_PER_RECAL_ST_SHIFT                          3
#define DRA7XX_DPLL_PER_RECAL_ST_WIDTH                          0x1
#define DRA7XX_DPLL_PER_RECAL_ST_MASK                           (1 << 3)

/* Used by PRM_IRQENABLE_DSP1 */
#define DRA7XX_DPLL_USB_RECAL_EN_SHIFT                          13
#define DRA7XX_DPLL_USB_RECAL_EN_WIDTH                          0x1
#define DRA7XX_DPLL_USB_RECAL_EN_MASK                           (1 << 13)

/* Used by PM_DSP1_PWRSTCTRL */
#define DRA7XX_DSP1_EDMA_ONSTATE_SHIFT                          20
#define DRA7XX_DSP1_EDMA_ONSTATE_WIDTH                          0x2
#define DRA7XX_DSP1_EDMA_ONSTATE_MASK                           (0x3 << 20)

/* Used by PM_DSP1_PWRSTST */
#define DRA7XX_DSP1_EDMA_STATEST_SHIFT                          8
#define DRA7XX_DSP1_EDMA_STATEST_WIDTH                          0x2
#define DRA7XX_DSP1_EDMA_STATEST_MASK                           (0x3 << 8)

/* Used by PM_DSP1_PWRSTCTRL */
#define DRA7XX_DSP1_L1_ONSTATE_SHIFT                            16
#define DRA7XX_DSP1_L1_ONSTATE_WIDTH                            0x2
#define DRA7XX_DSP1_L1_ONSTATE_MASK                             (0x3 << 16)

/* Used by PM_DSP1_PWRSTST */
#define DRA7XX_DSP1_L1_STATEST_SHIFT                            4
#define DRA7XX_DSP1_L1_STATEST_WIDTH                            0x2
#define DRA7XX_DSP1_L1_STATEST_MASK                             (0x3 << 4)

/* Used by PM_DSP1_PWRSTCTRL */
#define DRA7XX_DSP1_L2_ONSTATE_SHIFT                            18
#define DRA7XX_DSP1_L2_ONSTATE_WIDTH                            0x2
#define DRA7XX_DSP1_L2_ONSTATE_MASK                             (0x3 << 18)

/* Used by PM_DSP1_PWRSTST */
#define DRA7XX_DSP1_L2_STATEST_SHIFT                            6
#define DRA7XX_DSP1_L2_STATEST_WIDTH                            0x2
#define DRA7XX_DSP1_L2_STATEST_MASK                             (0x3 << 6)

/* Used by PM_DSP2_PWRSTCTRL */
#define DRA7XX_DSP2_EDMA_ONSTATE_SHIFT                          20
#define DRA7XX_DSP2_EDMA_ONSTATE_WIDTH                          0x2
#define DRA7XX_DSP2_EDMA_ONSTATE_MASK                           (0x3 << 20)

/* Used by PM_DSP2_PWRSTST */
#define DRA7XX_DSP2_EDMA_STATEST_SHIFT                          8
#define DRA7XX_DSP2_EDMA_STATEST_WIDTH                          0x2
#define DRA7XX_DSP2_EDMA_STATEST_MASK                           (0x3 << 8)

/* Used by PM_DSP2_PWRSTCTRL */
#define DRA7XX_DSP2_L1_ONSTATE_SHIFT                            16
#define DRA7XX_DSP2_L1_ONSTATE_WIDTH                            0x2
#define DRA7XX_DSP2_L1_ONSTATE_MASK                             (0x3 << 16)

/* Used by PM_DSP2_PWRSTST */
#define DRA7XX_DSP2_L1_STATEST_SHIFT                            4
#define DRA7XX_DSP2_L1_STATEST_WIDTH                            0x2
#define DRA7XX_DSP2_L1_STATEST_MASK                             (0x3 << 4)

/* Used by PM_DSP2_PWRSTCTRL */
#define DRA7XX_DSP2_L2_ONSTATE_SHIFT                            18
#define DRA7XX_DSP2_L2_ONSTATE_WIDTH                            0x2
#define DRA7XX_DSP2_L2_ONSTATE_MASK                             (0x3 << 18)

/* Used by PM_DSP2_PWRSTST */
#define DRA7XX_DSP2_L2_STATEST_SHIFT                            6
#define DRA7XX_DSP2_L2_STATEST_WIDTH                            0x2
#define DRA7XX_DSP2_L2_STATEST_MASK                             (0x3 << 6)

/* Used by PM_DSS_PWRSTCTRL */
#define DRA7XX_DSS_MEM_ONSTATE_SHIFT                            16
#define DRA7XX_DSS_MEM_ONSTATE_WIDTH                            0x2
#define DRA7XX_DSS_MEM_ONSTATE_MASK                             (0x3 << 16)

/* Used by PM_DSS_PWRSTCTRL */
#define DRA7XX_DSS_MEM_RETSTATE_SHIFT                           8
#define DRA7XX_DSS_MEM_RETSTATE_WIDTH                           0x1
#define DRA7XX_DSS_MEM_RETSTATE_MASK                            (1 << 8)

/* Used by PM_DSS_PWRSTST */
#define DRA7XX_DSS_MEM_STATEST_SHIFT                            4
#define DRA7XX_DSS_MEM_STATEST_WIDTH                            0x2
#define DRA7XX_DSS_MEM_STATEST_MASK                             (0x3 << 4)

/* Used by PRM_DEVICE_OFF_CTRL */
#define DRA7XX_EMIF1_OFFWKUP_DISABLE_SHIFT                      8
#define DRA7XX_EMIF1_OFFWKUP_DISABLE_WIDTH                      0x1
#define DRA7XX_EMIF1_OFFWKUP_DISABLE_MASK                       (1 << 8)

/* Used by PRM_DEVICE_OFF_CTRL */
#define DRA7XX_EMIF2_OFFWKUP_DISABLE_SHIFT                      9
#define DRA7XX_EMIF2_OFFWKUP_DISABLE_WIDTH                      0x1
#define DRA7XX_EMIF2_OFFWKUP_DISABLE_MASK                       (1 << 9)

/* Used by PM_EMU_PWRSTCTRL */
#define DRA7XX_EMU_BANK_ONSTATE_SHIFT                           16
#define DRA7XX_EMU_BANK_ONSTATE_WIDTH                           0x2
#define DRA7XX_EMU_BANK_ONSTATE_MASK                            (0x3 << 16)

/* Used by PM_EMU_PWRSTST */
#define DRA7XX_EMU_BANK_STATEST_SHIFT                           4
#define DRA7XX_EMU_BANK_STATEST_WIDTH                           0x2
#define DRA7XX_EMU_BANK_STATEST_MASK                            (0x3 << 4)

/*
 * Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_DSPEVE_SETUP, PRM_SLDO_GPU_SETUP,
 * PRM_SLDO_IVA_SETUP, PRM_SLDO_MPU_SETUP, PRM_SRAM_WKUP_SETUP
 */
#define DRA7XX_ENABLE_RTA_SHIFT                                 0
#define DRA7XX_ENABLE_RTA_WIDTH                                 0x1
#define DRA7XX_ENABLE_RTA_MASK                                  (1 << 0)

/*
 * Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_DSPEVE_SETUP, PRM_SLDO_GPU_SETUP,
 * PRM_SLDO_IVA_SETUP, PRM_SLDO_MPU_SETUP
 */
#define DRA7XX_ENFUNC1_SHIFT                                    3
#define DRA7XX_ENFUNC1_WIDTH                                    0x1
#define DRA7XX_ENFUNC1_MASK                                     (1 << 3)

/*
 * Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_DSPEVE_SETUP, PRM_SLDO_GPU_SETUP,
 * PRM_SLDO_IVA_SETUP, PRM_SLDO_MPU_SETUP
 */
#define DRA7XX_ENFUNC2_SHIFT                                    4
#define DRA7XX_ENFUNC2_WIDTH                                    0x1
#define DRA7XX_ENFUNC2_MASK                                     (1 << 4)

/*
 * Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_DSPEVE_SETUP, PRM_SLDO_GPU_SETUP,
 * PRM_SLDO_IVA_SETUP, PRM_SLDO_MPU_SETUP
 */
#define DRA7XX_ENFUNC3_SHIFT                                    5
#define DRA7XX_ENFUNC3_WIDTH                                    0x1
#define DRA7XX_ENFUNC3_MASK                                     (1 << 5)

/*
 * Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_DSPEVE_SETUP, PRM_SLDO_GPU_SETUP,
 * PRM_SLDO_IVA_SETUP, PRM_SLDO_MPU_SETUP
 */
#define DRA7XX_ENFUNC4_SHIFT                                    6
#define DRA7XX_ENFUNC4_WIDTH                                    0x1
#define DRA7XX_ENFUNC4_MASK                                     (1 << 6)

/*
 * Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_DSPEVE_SETUP, PRM_SLDO_GPU_SETUP,
 * PRM_SLDO_IVA_SETUP, PRM_SLDO_MPU_SETUP
 */
#define DRA7XX_ENFUNC5_SHIFT                                    7
#define DRA7XX_ENFUNC5_WIDTH                                    0x1
#define DRA7XX_ENFUNC5_MASK                                     (1 << 7)

/* Used by PM_EVE1_PWRSTCTRL */
#define DRA7XX_EVE1_BANK_ONSTATE_SHIFT                          16
#define DRA7XX_EVE1_BANK_ONSTATE_WIDTH                          0x2
#define DRA7XX_EVE1_BANK_ONSTATE_MASK                           (0x3 << 16)

/* Used by PM_EVE1_PWRSTST */
#define DRA7XX_EVE1_BANK_STATEST_SHIFT                          4
#define DRA7XX_EVE1_BANK_STATEST_WIDTH                          0x2
#define DRA7XX_EVE1_BANK_STATEST_MASK                           (0x3 << 4)

/* Used by PM_EVE2_PWRSTCTRL */
#define DRA7XX_EVE2_BANK_ONSTATE_SHIFT                          16
#define DRA7XX_EVE2_BANK_ONSTATE_WIDTH                          0x2
#define DRA7XX_EVE2_BANK_ONSTATE_MASK                           (0x3 << 16)

/* Used by PM_EVE2_PWRSTST */
#define DRA7XX_EVE2_BANK_STATEST_SHIFT                          4
#define DRA7XX_EVE2_BANK_STATEST_WIDTH                          0x2
#define DRA7XX_EVE2_BANK_STATEST_MASK                           (0x3 << 4)

/* Used by PM_EVE3_PWRSTCTRL */
#define DRA7XX_EVE3_BANK_ONSTATE_SHIFT                          16
#define DRA7XX_EVE3_BANK_ONSTATE_WIDTH                          0x2
#define DRA7XX_EVE3_BANK_ONSTATE_MASK                           (0x3 << 16)

/* Used by PM_EVE3_PWRSTST */
#define DRA7XX_EVE3_BANK_STATEST_SHIFT                          4
#define DRA7XX_EVE3_BANK_STATEST_WIDTH                          0x2
#define DRA7XX_EVE3_BANK_STATEST_MASK                           (0x3 << 4)

/* Used by PM_EVE4_PWRSTCTRL */
#define DRA7XX_EVE4_BANK_ONSTATE_SHIFT                          16
#define DRA7XX_EVE4_BANK_ONSTATE_WIDTH                          0x2
#define DRA7XX_EVE4_BANK_ONSTATE_MASK                           (0x3 << 16)

/* Used by PM_EVE4_PWRSTST */
#define DRA7XX_EVE4_BANK_STATEST_SHIFT                          4
#define DRA7XX_EVE4_BANK_STATEST_WIDTH                          0x2
#define DRA7XX_EVE4_BANK_STATEST_MASK                           (0x3 << 4)

/* Used by PRM_RSTST */
#define DRA7XX_EXTERNAL_WARM_RST_SHIFT                          5
#define DRA7XX_EXTERNAL_WARM_RST_WIDTH                          0x1
#define DRA7XX_EXTERNAL_WARM_RST_MASK                           (1 << 5)

/*
 * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
 * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
 * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2
 */
#define DRA7XX_FORCEWKUP_EN_SHIFT                               10
#define DRA7XX_FORCEWKUP_EN_WIDTH                               0x1
#define DRA7XX_FORCEWKUP_EN_MASK                                (1 << 10)

/*
 * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
 * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
 * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2
 */
#define DRA7XX_FORCEWKUP_ST_SHIFT                               10
#define DRA7XX_FORCEWKUP_ST_WIDTH                               0x1
#define DRA7XX_FORCEWKUP_ST_MASK                                (1 << 10)

/* Used by REVISION_PRM */
#define DRA7XX_FUNC_SHIFT                                       16
#define DRA7XX_FUNC_WIDTH                                       0xc
#define DRA7XX_FUNC_MASK                                        (0xfff << 16)

/* Used by PRM_RSTST */
#define DRA7XX_GLOBAL_COLD_RST_SHIFT                            0
#define DRA7XX_GLOBAL_COLD_RST_WIDTH                            0x1
#define DRA7XX_GLOBAL_COLD_RST_MASK                             (1 << 0)

/* Used by PRM_RSTST */
#define DRA7XX_GLOBAL_WARM_SW_RST_SHIFT                         1
#define DRA7XX_GLOBAL_WARM_SW_RST_WIDTH                         0x1
#define DRA7XX_GLOBAL_WARM_SW_RST_MASK                          (1 << 1)

/* Used by PRM_IO_PMCTRL */
#define DRA7XX_GLOBAL_WUEN_SHIFT                                16
#define DRA7XX_GLOBAL_WUEN_WIDTH                                0x1
#define DRA7XX_GLOBAL_WUEN_MASK                                 (1 << 16)

/* Used by PM_L3INIT_PWRSTCTRL */
#define DRA7XX_GMAC_BANK_ONSTATE_SHIFT                          18
#define DRA7XX_GMAC_BANK_ONSTATE_WIDTH                          0x2
#define DRA7XX_GMAC_BANK_ONSTATE_MASK                           (0x3 << 18)

/* Used by PM_L3INIT_PWRSTCTRL */
#define DRA7XX_GMAC_BANK_RETSTATE_SHIFT                         10
#define DRA7XX_GMAC_BANK_RETSTATE_WIDTH                         0x1
#define DRA7XX_GMAC_BANK_RETSTATE_MASK                          (1 << 10)

/* Used by PM_GPU_PWRSTCTRL */
#define DRA7XX_GPU_MEM_ONSTATE_SHIFT                            16
#define DRA7XX_GPU_MEM_ONSTATE_WIDTH                            0x2
#define DRA7XX_GPU_MEM_ONSTATE_MASK                             (0x3 << 16)

/* Used by PM_GPU_PWRSTST */
#define DRA7XX_GPU_MEM_STATEST_SHIFT                            4
#define DRA7XX_GPU_MEM_STATEST_WIDTH                            0x2
#define DRA7XX_GPU_MEM_STATEST_MASK                             (0x3 << 4)

/* Used by PRM_PSCON_COUNT */
#define DRA7XX_HG_PONOUT_2_PGOODIN_TIME_SHIFT                   16
#define DRA7XX_HG_PONOUT_2_PGOODIN_TIME_WIDTH                   0x8
#define DRA7XX_HG_PONOUT_2_PGOODIN_TIME_MASK                    (0xff << 16)

/* Used by PM_IVA_PWRSTCTRL */
#define DRA7XX_HWA_MEM_ONSTATE_SHIFT                            16
#define DRA7XX_HWA_MEM_ONSTATE_WIDTH                            0x2
#define DRA7XX_HWA_MEM_ONSTATE_MASK                             (0x3 << 16)

/* Used by PM_IVA_PWRSTCTRL */
#define DRA7XX_HWA_MEM_RETSTATE_SHIFT                           8
#define DRA7XX_HWA_MEM_RETSTATE_WIDTH                           0x1
#define DRA7XX_HWA_MEM_RETSTATE_MASK                            (1 << 8)

/* Used by PM_IVA_PWRSTST */
#define DRA7XX_HWA_MEM_STATEST_SHIFT                            4
#define DRA7XX_HWA_MEM_STATEST_WIDTH                            0x2
#define DRA7XX_HWA_MEM_STATEST_MASK                             (0x3 << 4)

/* Used by PRM_RSTST */
#define DRA7XX_ICEPICK_RST_SHIFT                                9
#define DRA7XX_ICEPICK_RST_WIDTH                                0x1
#define DRA7XX_ICEPICK_RST_MASK                                 (1 << 9)

/*
 * Used by PM_CAM_PWRSTST, PM_CORE_PWRSTST, PM_CUSTEFUSE_PWRSTST,
 * PM_DSP1_PWRSTST, PM_DSP2_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST,
 * PM_EVE1_PWRSTST, PM_EVE2_PWRSTST, PM_EVE3_PWRSTST, PM_EVE4_PWRSTST,
 * PM_GPU_PWRSTST, PM_IPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST,
 * PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_VPE_PWRSTST, PRM_VOLTST_MM,
 * PRM_VOLTST_MPU
 */
#define DRA7XX_INTRANSITION_SHIFT                               20
#define DRA7XX_INTRANSITION_WIDTH                               0x1
#define DRA7XX_INTRANSITION_MASK                                (1 << 20)

/*
 * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
 * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
 * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2, PRM_IRQENABLE_MPU
 */
#define DRA7XX_IO_EN_SHIFT                                      9
#define DRA7XX_IO_EN_WIDTH                                      0x1
#define DRA7XX_IO_EN_MASK                                       (1 << 9)

/* Used by PRM_IO_PMCTRL */
#define DRA7XX_IO_ON_STATUS_SHIFT                               5
#define DRA7XX_IO_ON_STATUS_WIDTH                               0x1
#define DRA7XX_IO_ON_STATUS_MASK                                (1 << 5)

/*
 * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
 * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
 * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
 */
#define DRA7XX_IO_ST_SHIFT                                      9
#define DRA7XX_IO_ST_WIDTH                                      0x1
#define DRA7XX_IO_ST_MASK                                       (1 << 9)

/* Used by PM_CORE_PWRSTCTRL */
#define DRA7XX_IPU_L2RAM_ONSTATE_SHIFT                          20
#define DRA7XX_IPU_L2RAM_ONSTATE_WIDTH                          0x2
#define DRA7XX_IPU_L2RAM_ONSTATE_MASK                           (0x3 << 20)

/* Used by PM_CORE_PWRSTCTRL */
#define DRA7XX_IPU_L2RAM_RETSTATE_SHIFT                         10
#define DRA7XX_IPU_L2RAM_RETSTATE_WIDTH                         0x1
#define DRA7XX_IPU_L2RAM_RETSTATE_MASK                          (1 << 10)

/* Used by PM_CORE_PWRSTST */
#define DRA7XX_IPU_L2RAM_STATEST_SHIFT                          8
#define DRA7XX_IPU_L2RAM_STATEST_WIDTH                          0x2
#define DRA7XX_IPU_L2RAM_STATEST_MASK                           (0x3 << 8)

/* Used by PM_CORE_PWRSTCTRL */
#define DRA7XX_IPU_UNICACHE_ONSTATE_SHIFT                       22
#define DRA7XX_IPU_UNICACHE_ONSTATE_WIDTH                       0x2
#define DRA7XX_IPU_UNICACHE_ONSTATE_MASK                        (0x3 << 22)

/* Used by PM_CORE_PWRSTCTRL */
#define DRA7XX_IPU_UNICACHE_RETSTATE_SHIFT                      11
#define DRA7XX_IPU_UNICACHE_RETSTATE_WIDTH                      0x1
#define DRA7XX_IPU_UNICACHE_RETSTATE_MASK                       (1 << 11)

/* Used by PM_CORE_PWRSTST */
#define DRA7XX_IPU_UNICACHE_STATEST_SHIFT                       10
#define DRA7XX_IPU_UNICACHE_STATEST_WIDTH                       0x2
#define DRA7XX_IPU_UNICACHE_STATEST_MASK                        (0x3 << 10)

/* Used by PRM_IO_PMCTRL */
#define DRA7XX_ISOCLK_OVERRIDE_SHIFT                            0
#define DRA7XX_ISOCLK_OVERRIDE_WIDTH                            0x1
#define DRA7XX_ISOCLK_OVERRIDE_MASK                             (1 << 0)

/* Used by PRM_IO_PMCTRL */
#define DRA7XX_ISOCLK_STATUS_SHIFT                              1
#define DRA7XX_ISOCLK_STATUS_WIDTH                              0x1
#define DRA7XX_ISOCLK_STATUS_MASK                               (1 << 1)

/* Used by PRM_IO_PMCTRL */
#define DRA7XX_ISOOVR_EXTEND_SHIFT                              4
#define DRA7XX_ISOOVR_EXTEND_WIDTH                              0x1
#define DRA7XX_ISOOVR_EXTEND_MASK                               (1 << 4)

/* Used by PRM_IO_COUNT */
#define DRA7XX_ISO_2_ON_TIME_SHIFT                              0
#define DRA7XX_ISO_2_ON_TIME_WIDTH                              0x8
#define DRA7XX_ISO_2_ON_TIME_MASK                               (0xff << 0)

/* Used by PM_L3INIT_PWRSTCTRL */
#define DRA7XX_L3INIT_BANK1_ONSTATE_SHIFT                       14
#define DRA7XX_L3INIT_BANK1_ONSTATE_WIDTH                       0x2
#define DRA7XX_L3INIT_BANK1_ONSTATE_MASK                        (0x3 << 14)

/* Used by PM_L3INIT_PWRSTCTRL */
#define DRA7XX_L3INIT_BANK1_RETSTATE_SHIFT                      8
#define DRA7XX_L3INIT_BANK1_RETSTATE_WIDTH                      0x1
#define DRA7XX_L3INIT_BANK1_RETSTATE_MASK                       (1 << 8)

/* Used by PM_L3INIT_PWRSTST */
#define DRA7XX_L3INIT_BANK1_STATEST_SHIFT                       4
#define DRA7XX_L3INIT_BANK1_STATEST_WIDTH                       0x2
#define DRA7XX_L3INIT_BANK1_STATEST_MASK                        (0x3 << 4)

/* Used by PM_L3INIT_PWRSTCTRL */
#define DRA7XX_L3INIT_BANK2_ONSTATE_SHIFT                       16
#define DRA7XX_L3INIT_BANK2_ONSTATE_WIDTH                       0x2
#define DRA7XX_L3INIT_BANK2_ONSTATE_MASK                        (0x3 << 16)

/* Used by PM_L3INIT_PWRSTCTRL */
#define DRA7XX_L3INIT_BANK2_RETSTATE_SHIFT                      9
#define DRA7XX_L3INIT_BANK2_RETSTATE_WIDTH                      0x1
#define DRA7XX_L3INIT_BANK2_RETSTATE_MASK                       (1 << 9)

/* Used by PM_L3INIT_PWRSTST */
#define DRA7XX_L3INIT_BANK2_STATEST_SHIFT                       6
#define DRA7XX_L3INIT_BANK2_STATEST_WIDTH                       0x2
#define DRA7XX_L3INIT_BANK2_STATEST_MASK                        (0x3 << 6)

/* Used by PM_L3INIT_PWRSTST */
#define DRA7XX_L3INIT_GMAC_STATEST_SHIFT                        8
#define DRA7XX_L3INIT_GMAC_STATEST_WIDTH                        0x2
#define DRA7XX_L3INIT_GMAC_STATEST_MASK                         (0x3 << 8)

/*
 * Used by PM_CAM_PWRSTST, PM_CORE_PWRSTST, PM_CUSTEFUSE_PWRSTST,
 * PM_DSP1_PWRSTST, PM_DSP2_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST,
 * PM_EVE1_PWRSTST, PM_EVE2_PWRSTST, PM_EVE3_PWRSTST, PM_EVE4_PWRSTST,
 * PM_GPU_PWRSTST, PM_IPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST,
 * PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_VPE_PWRSTST
 */
#define DRA7XX_LASTPOWERSTATEENTERED_SHIFT                      24
#define DRA7XX_LASTPOWERSTATEENTERED_WIDTH                      0x2
#define DRA7XX_LASTPOWERSTATEENTERED_MASK                       (0x3 << 24)

/* Used by PRM_RSTST */
#define DRA7XX_LLI_RST_SHIFT                                    14
#define DRA7XX_LLI_RST_WIDTH                                    0x1
#define DRA7XX_LLI_RST_MASK                                     (1 << 14)

/*
 * Used by PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_IPU_PWRSTCTRL,
 * PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_MPU_PWRSTCTRL,
 * PM_VPE_PWRSTCTRL
 */
#define DRA7XX_LOGICRETSTATE_SHIFT                              2
#define DRA7XX_LOGICRETSTATE_WIDTH                              0x1
#define DRA7XX_LOGICRETSTATE_MASK                               (1 << 2)

/*
 * Used by PM_CAM_PWRSTST, PM_CORE_PWRSTST, PM_CUSTEFUSE_PWRSTST,
 * PM_DSP1_PWRSTST, PM_DSP2_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST,
 * PM_EVE1_PWRSTST, PM_EVE2_PWRSTST, PM_EVE3_PWRSTST, PM_EVE4_PWRSTST,
 * PM_GPU_PWRSTST, PM_IPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST,
 * PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_VPE_PWRSTST
 */
#define DRA7XX_LOGICSTATEST_SHIFT                               2
#define DRA7XX_LOGICSTATEST_WIDTH                               0x1
#define DRA7XX_LOGICSTATEST_MASK                                (1 << 2)

/*
 * Used by RM_ATL_ATL_CONTEXT, RM_CAM_CSI1_CONTEXT, RM_CAM_CSI2_CONTEXT,
 * RM_CAM_LVDSRX_CONTEXT, RM_CAM_VIP1_CONTEXT, RM_CAM_VIP2_CONTEXT,
 * RM_CAM_VIP3_CONTEXT, RM_COREAON_DUMMY_MODULE1_CONTEXT,
 * RM_COREAON_DUMMY_MODULE2_CONTEXT, RM_COREAON_DUMMY_MODULE3_CONTEXT,
 * RM_COREAON_DUMMY_MODULE4_CONTEXT, RM_COREAON_SMARTREFLEX_CORE_CONTEXT,
 * RM_COREAON_SMARTREFLEX_DSPEVE_CONTEXT, RM_COREAON_SMARTREFLEX_GPU_CONTEXT,
 * RM_COREAON_SMARTREFLEX_IVAHD_CONTEXT, RM_COREAON_SMARTREFLEX_MPU_CONTEXT,
 * RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT, RM_DSP1_DSP1_CONTEXT,
 * RM_DSP2_DSP2_CONTEXT, RM_DSS_BB2D_CONTEXT, RM_DSS_DSS_CONTEXT,
 * RM_DSS_SDVENC_CONTEXT, RM_EMIF_DMM_CONTEXT, RM_EMIF_EMIF1_CONTEXT,
 * RM_EMIF_EMIF2_CONTEXT, RM_EMIF_EMIF_DLL_CONTEXT,
 * RM_EMIF_EMIF_OCP_FW_CONTEXT, RM_EMU_DEBUGSS_CONTEXT, RM_EVE1_EVE1_CONTEXT,
 * RM_EVE2_EVE2_CONTEXT, RM_EVE3_EVE3_CONTEXT, RM_EVE4_EVE4_CONTEXT,
 * RM_GMAC_GMAC_CONTEXT, RM_GPU_GPU_CONTEXT, RM_IPU1_IPU1_CONTEXT,
 * RM_IPU2_IPU2_CONTEXT, RM_IPU_I2C5_CONTEXT, RM_IPU_MCASP1_CONTEXT,
 * RM_IPU_TIMER5_CONTEXT, RM_IPU_TIMER6_CONTEXT, RM_IPU_TIMER7_CONTEXT,
 * RM_IPU_TIMER8_CONTEXT, RM_IVA_IVA_CONTEXT, RM_IVA_SL2_CONTEXT,
 * RM_L3INIT_IEEE1500_2_OCP_CONTEXT, RM_L3INIT_MLB_SS_CONTEXT,
 * RM_L3INIT_OCP2SCP1_CONTEXT, RM_L3INIT_OCP2SCP3_CONTEXT,
 * RM_L3INIT_SATA_CONTEXT, RM_L3INSTR_L3_INSTR_CONTEXT,
 * RM_L3INSTR_L3_MAIN_2_CONTEXT, RM_L3INSTR_OCP_WP_NOC_CONTEXT,
 * RM_L3MAIN1_L3_MAIN_1_CONTEXT, RM_L3MAIN1_OCMC_RAM1_CONTEXT,
 * RM_L3MAIN1_OCMC_RAM2_CONTEXT, RM_L3MAIN1_OCMC_RAM3_CONTEXT,
 * RM_L3MAIN1_OCMC_ROM_CONTEXT, RM_L3MAIN1_SPARE_CME_CONTEXT,
 * RM_L3MAIN1_SPARE_HDMI_CONTEXT, RM_L3MAIN1_SPARE_ICM_CONTEXT,
 * RM_L3MAIN1_SPARE_IVA2_CONTEXT, RM_L3MAIN1_SPARE_SATA2_CONTEXT,
 * RM_L3MAIN1_SPARE_UNKNOWN4_CONTEXT, RM_L3MAIN1_SPARE_UNKNOWN5_CONTEXT,
 * RM_L3MAIN1_SPARE_UNKNOWN6_CONTEXT, RM_L3MAIN1_SPARE_VIDEOPLL1_CONTEXT,
 * RM_L3MAIN1_SPARE_VIDEOPLL2_CONTEXT, RM_L3MAIN1_SPARE_VIDEOPLL3_CONTEXT,
 * RM_L3MAIN1_VCP1_CONTEXT, RM_L3MAIN1_VCP2_CONTEXT,
 * RM_L4CFG_IO_DELAY_BLOCK_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT,
 * RM_L4CFG_OCP2SCP2_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT,
 * RM_L4CFG_SPARE_SMARTREFLEX_RTC_CONTEXT,
 * RM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CONTEXT,
 * RM_L4CFG_SPARE_SMARTREFLEX_WKUP_CONTEXT, RM_L4PER2_DCAN2_CONTEXT,
 * RM_L4PER2_L4PER2_CONTEXT, RM_L4PER2_MCASP2_CONTEXT,
 * RM_L4PER2_MCASP3_CONTEXT, RM_L4PER2_MCASP4_CONTEXT,
 * RM_L4PER2_MCASP5_CONTEXT, RM_L4PER2_MCASP6_CONTEXT,
 * RM_L4PER2_MCASP7_CONTEXT, RM_L4PER2_MCASP8_CONTEXT,
 * RM_L4PER2_PRUSS1_CONTEXT, RM_L4PER2_PRUSS2_CONTEXT,
 * RM_L4PER2_PWMSS1_CONTEXT, RM_L4PER2_PWMSS2_CONTEXT,
 * RM_L4PER2_PWMSS3_CONTEXT, RM_L4PER2_QSPI_CONTEXT, RM_L4PER3_L4PER3_CONTEXT,
 * RM_L4PER3_TIMER13_CONTEXT, RM_L4PER3_TIMER14_CONTEXT,
 * RM_L4PER3_TIMER15_CONTEXT, RM_L4PER3_TIMER16_CONTEXT, RM_L4PER_ELM_CONTEXT,
 * RM_L4PER_HDQ1W_CONTEXT, RM_L4PER_I2C2_CONTEXT, RM_L4PER_I2C3_CONTEXT,
 * RM_L4PER_I2C4_CONTEXT, RM_L4PER_L4PER1_CONTEXT, RM_L4PER_MCSPI1_CONTEXT,
 * RM_L4PER_MCSPI2_CONTEXT, RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT,
 * RM_L4PER_MMC3_CONTEXT, RM_L4PER_MMC4_CONTEXT, RM_L4PER_TIMER10_CONTEXT,
 * RM_L4PER_TIMER11_CONTEXT, RM_L4PER_TIMER2_CONTEXT, RM_L4PER_TIMER3_CONTEXT,
 * RM_L4PER_TIMER4_CONTEXT, RM_L4PER_TIMER9_CONTEXT, RM_L4SEC_FPKA_CONTEXT,
 * RM_MPU_MPU_CONTEXT, RM_RTC_RTCSS_CONTEXT, RM_VPE_VPE_CONTEXT,
 * RM_WKUPAON_ADC_CONTEXT, RM_WKUPAON_COUNTER_32K_CONTEXT,
 * RM_WKUPAON_DCAN1_CONTEXT, RM_WKUPAON_GPIO1_CONTEXT, RM_WKUPAON_KBD_CONTEXT,
 * RM_WKUPAON_L4_WKUP_CONTEXT, RM_WKUPAON_SAR_RAM_CONTEXT,
 * RM_WKUPAON_SPARE_SAFETY1_CONTEXT, RM_WKUPAON_SPARE_SAFETY2_CONTEXT,
 * RM_WKUPAON_SPARE_SAFETY3_CONTEXT, RM_WKUPAON_SPARE_SAFETY4_CONTEXT,
 * RM_WKUPAON_SPARE_UNKNOWN2_CONTEXT, RM_WKUPAON_SPARE_UNKNOWN3_CONTEXT,
 * RM_WKUPAON_TIMER12_CONTEXT, RM_WKUPAON_TIMER1_CONTEXT,
 * RM_WKUPAON_UART10_CONTEXT, RM_WKUPAON_WD_TIMER1_CONTEXT,
 * RM_WKUPAON_WD_TIMER2_CONTEXT
 */
#define DRA7XX_LOSTCONTEXT_DFF_SHIFT                            0
#define DRA7XX_LOSTCONTEXT_DFF_WIDTH                            0x1
#define DRA7XX_LOSTCONTEXT_DFF_MASK                             (1 << 0)

/*
 * Used by RM_DMA_DMA_SYSTEM_CONTEXT, RM_DSS_DSS_CONTEXT, RM_EMIF_DMM_CONTEXT,
 * RM_EMIF_EMIF1_CONTEXT, RM_EMIF_EMIF2_CONTEXT, RM_EMIF_EMIF_OCP_FW_CONTEXT,
 * RM_IPU1_IPU1_CONTEXT, RM_IPU2_IPU2_CONTEXT, RM_IPU_UART6_CONTEXT,
 * RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT,
 * RM_L3INIT_USB_OTG_SS1_CONTEXT, RM_L3INIT_USB_OTG_SS2_CONTEXT,
 * RM_L3INIT_USB_OTG_SS3_CONTEXT, RM_L3INIT_USB_OTG_SS4_CONTEXT,
 * RM_L3INSTR_L3_MAIN_2_CONTEXT, RM_L3INSTR_OCP_WP_NOC_CONTEXT,
 * RM_L3MAIN1_GPMC_CONTEXT, RM_L3MAIN1_L3_MAIN_1_CONTEXT,
 * RM_L3MAIN1_MMU_EDMA_CONTEXT, RM_L3MAIN1_TPCC_CONTEXT,
 * RM_L3MAIN1_TPTC1_CONTEXT, RM_L3MAIN1_TPTC2_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT,
 * RM_L4CFG_MAILBOX10_CONTEXT, RM_L4CFG_MAILBOX11_CONTEXT,
 * RM_L4CFG_MAILBOX12_CONTEXT, RM_L4CFG_MAILBOX13_CONTEXT,
 * RM_L4CFG_MAILBOX1_CONTEXT, RM_L4CFG_MAILBOX2_CONTEXT,
 * RM_L4CFG_MAILBOX3_CONTEXT, RM_L4CFG_MAILBOX4_CONTEXT,
 * RM_L4CFG_MAILBOX5_CONTEXT, RM_L4CFG_MAILBOX6_CONTEXT,
 * RM_L4CFG_MAILBOX7_CONTEXT, RM_L4CFG_MAILBOX8_CONTEXT,
 * RM_L4CFG_MAILBOX9_CONTEXT, RM_L4CFG_SPINLOCK_CONTEXT,
 * RM_L4PER2_L4PER2_CONTEXT, RM_L4PER2_UART7_CONTEXT, RM_L4PER2_UART8_CONTEXT,
 * RM_L4PER2_UART9_CONTEXT, RM_L4PER3_L4PER3_CONTEXT, RM_L4PER_GPIO2_CONTEXT,
 * RM_L4PER_GPIO3_CONTEXT, RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT,
 * RM_L4PER_GPIO6_CONTEXT, RM_L4PER_GPIO7_CONTEXT, RM_L4PER_GPIO8_CONTEXT,
 * RM_L4PER_I2C1_CONTEXT, RM_L4PER_L4PER1_CONTEXT, RM_L4PER_UART1_CONTEXT,
 * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT,
 * RM_L4PER_UART5_CONTEXT, RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT,
 * RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_DMA_CRYPTO_CONTEXT, RM_L4SEC_RNG_CONTEXT,
 * RM_L4SEC_SHA2MD51_CONTEXT, RM_L4SEC_SHA2MD52_CONTEXT, RM_MPU_MPU_CONTEXT
 */
#define DRA7XX_LOSTCONTEXT_RFF_SHIFT                            1
#define DRA7XX_LOSTCONTEXT_RFF_WIDTH                            0x1
#define DRA7XX_LOSTCONTEXT_RFF_MASK                             (1 << 1)

/* Used by RM_ATL_ATL_CONTEXT */
#define DRA7XX_LOSTMEM_ATL_BANK_SHIFT                           8
#define DRA7XX_LOSTMEM_ATL_BANK_WIDTH                           0x1
#define DRA7XX_LOSTMEM_ATL_BANK_MASK                            (1 << 8)

/* Used by RM_L3INSTR_OCP_WP_NOC_CONTEXT */
#define DRA7XX_LOSTMEM_CORE_NRET_BANK_SHIFT                     8
#define DRA7XX_LOSTMEM_CORE_NRET_BANK_WIDTH                     0x1
#define DRA7XX_LOSTMEM_CORE_NRET_BANK_MASK                      (1 << 8)

/*
 * Used by RM_L3MAIN1_OCMC_RAM1_CONTEXT, RM_L3MAIN1_OCMC_RAM2_CONTEXT,
 * RM_L3MAIN1_OCMC_RAM3_CONTEXT
 */
#define DRA7XX_LOSTMEM_CORE_OCMRAM_SHIFT                        8
#define DRA7XX_LOSTMEM_CORE_OCMRAM_WIDTH                        0x1
#define DRA7XX_LOSTMEM_CORE_OCMRAM_MASK                         (1 << 8)

/* Used by RM_L3MAIN1_OCMC_ROM_CONTEXT */
#define DRA7XX_LOSTMEM_CORE_OCMROM_SHIFT                        8
#define DRA7XX_LOSTMEM_CORE_OCMROM_WIDTH                        0x1
#define DRA7XX_LOSTMEM_CORE_OCMROM_MASK                         (1 << 8)

/* Used by RM_DMA_DMA_SYSTEM_CONTEXT */
#define DRA7XX_LOSTMEM_CORE_OTHER_BANK_SHIFT                    8
#define DRA7XX_LOSTMEM_CORE_OTHER_BANK_WIDTH                    0x1
#define DRA7XX_LOSTMEM_CORE_OTHER_BANK_MASK                     (1 << 8)

/* Used by RM_L4PER2_DCAN2_CONTEXT */
#define DRA7XX_LOSTMEM_DCAN_BANK_SHIFT                          8
#define DRA7XX_LOSTMEM_DCAN_BANK_WIDTH                          0x1
#define DRA7XX_LOSTMEM_DCAN_BANK_MASK                           (1 << 8)

/* Used by RM_WKUPAON_DCAN1_CONTEXT */
#define DRA7XX_LOSTMEM_DCAN_MEM_SHIFT                           8
#define DRA7XX_LOSTMEM_DCAN_MEM_WIDTH                           0x1
#define DRA7XX_LOSTMEM_DCAN_MEM_MASK                            (1 << 8)

/* Used by RM_DSP1_DSP1_CONTEXT, RM_DSP2_DSP2_CONTEXT */
#define DRA7XX_LOSTMEM_DSP_EDMA_SHIFT                           10
#define DRA7XX_LOSTMEM_DSP_EDMA_WIDTH                           0x1
#define DRA7XX_LOSTMEM_DSP_EDMA_MASK                            (1 << 10)

/* Used by RM_DSP1_DSP1_CONTEXT, RM_DSP2_DSP2_CONTEXT */
#define DRA7XX_LOSTMEM_DSP_L1_SHIFT                             8
#define DRA7XX_LOSTMEM_DSP_L1_WIDTH                             0x1
#define DRA7XX_LOSTMEM_DSP_L1_MASK                              (1 << 8)

/* Used by RM_DSP1_DSP1_CONTEXT, RM_DSP2_DSP2_CONTEXT */
#define DRA7XX_LOSTMEM_DSP_L2_SHIFT                             9
#define DRA7XX_LOSTMEM_DSP_L2_WIDTH                             0x1
#define DRA7XX_LOSTMEM_DSP_L2_MASK                              (1 << 9)

/* Used by RM_DSS_BB2D_CONTEXT, RM_DSS_DSS_CONTEXT */
#define DRA7XX_LOSTMEM_DSS_MEM_SHIFT                            8
#define DRA7XX_LOSTMEM_DSS_MEM_WIDTH                            0x1
#define DRA7XX_LOSTMEM_DSS_MEM_MASK                             (1 << 8)

/* Used by RM_EMU_DEBUGSS_CONTEXT */
#define DRA7XX_LOSTMEM_EMU_BANK_SHIFT                           8
#define DRA7XX_LOSTMEM_EMU_BANK_WIDTH                           0x1
#define DRA7XX_LOSTMEM_EMU_BANK_MASK                            (1 << 8)

/*
 * Used by RM_EVE1_EVE1_CONTEXT, RM_EVE2_EVE2_CONTEXT, RM_EVE3_EVE3_CONTEXT,
 * RM_EVE4_EVE4_CONTEXT
 */
#define DRA7XX_LOSTMEM_EVE_BANK_SHIFT                           8
#define DRA7XX_LOSTMEM_EVE_BANK_WIDTH                           0x1
#define DRA7XX_LOSTMEM_EVE_BANK_MASK                            (1 << 8)

/* Used by RM_GMAC_GMAC_CONTEXT */
#define DRA7XX_LOSTMEM_GMAC_BANK_SHIFT                          8
#define DRA7XX_LOSTMEM_GMAC_BANK_WIDTH                          0x1
#define DRA7XX_LOSTMEM_GMAC_BANK_MASK                           (1 << 8)

/* Used by RM_GPU_GPU_CONTEXT */
#define DRA7XX_LOSTMEM_GPU_MEM_SHIFT                            8
#define DRA7XX_LOSTMEM_GPU_MEM_WIDTH                            0x1
#define DRA7XX_LOSTMEM_GPU_MEM_MASK                             (1 << 8)

/* Used by RM_IVA_IVA_CONTEXT */
#define DRA7XX_LOSTMEM_HWA_MEM_SHIFT                            10
#define DRA7XX_LOSTMEM_HWA_MEM_WIDTH                            0x1
#define DRA7XX_LOSTMEM_HWA_MEM_MASK                             (1 << 10)

/* Used by RM_IPU1_IPU1_CONTEXT, RM_IPU2_IPU2_CONTEXT */
#define DRA7XX_LOSTMEM_IPU_L2RAM_SHIFT                          9
#define DRA7XX_LOSTMEM_IPU_L2RAM_WIDTH                          0x1
#define DRA7XX_LOSTMEM_IPU_L2RAM_MASK                           (1 << 9)

/* Used by RM_IPU1_IPU1_CONTEXT, RM_IPU2_IPU2_CONTEXT */
#define DRA7XX_LOSTMEM_IPU_UNICACHE_SHIFT                       8
#define DRA7XX_LOSTMEM_IPU_UNICACHE_WIDTH                       0x1
#define DRA7XX_LOSTMEM_IPU_UNICACHE_MASK                        (1 << 8)

/*
 * Used by RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT,
 * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_USB_OTG_SS1_CONTEXT,
 * RM_L3INIT_USB_OTG_SS2_CONTEXT, RM_L3INIT_USB_OTG_SS3_CONTEXT,
 * RM_L3INIT_USB_OTG_SS4_CONTEXT
 */
#define DRA7XX_LOSTMEM_L3INIT_BANK1_SHIFT                       8
#define DRA7XX_LOSTMEM_L3INIT_BANK1_WIDTH                       0x1
#define DRA7XX_LOSTMEM_L3INIT_BANK1_MASK                        (1 << 8)

/* Used by RM_L3INIT_MLB_SS_CONTEXT */
#define DRA7XX_LOSTMEM_MLB_BANK_SHIFT                           8
#define DRA7XX_LOSTMEM_MLB_BANK_WIDTH                           0x1
#define DRA7XX_LOSTMEM_MLB_BANK_MASK                            (1 << 8)

/* Used by RM_MPU_MPU_CONTEXT */
#define DRA7XX_LOSTMEM_MPU_L2_SHIFT                             9
#define DRA7XX_LOSTMEM_MPU_L2_WIDTH                             0x1
#define DRA7XX_LOSTMEM_MPU_L2_MASK                              (1 << 9)

/* Used by RM_MPU_MPU_CONTEXT */
#define DRA7XX_LOSTMEM_MPU_RAM_SHIFT                            10
#define DRA7XX_LOSTMEM_MPU_RAM_WIDTH                            0x1
#define DRA7XX_LOSTMEM_MPU_RAM_MASK                             (1 << 10)

/* Used by RM_L4PER_MMC3_CONTEXT, RM_L4PER_MMC4_CONTEXT, RM_L4SEC_FPKA_CONTEXT */
#define DRA7XX_LOSTMEM_NONRETAINED_BANK_SHIFT                   8
#define DRA7XX_LOSTMEM_NONRETAINED_BANK_WIDTH                   0x1
#define DRA7XX_LOSTMEM_NONRETAINED_BANK_MASK                    (1 << 8)

/* Used by RM_L4PER2_PRUSS1_CONTEXT */
#define DRA7XX_LOSTMEM_PRUSS1_BANK_SHIFT                        8
#define DRA7XX_LOSTMEM_PRUSS1_BANK_WIDTH                        0x1
#define DRA7XX_LOSTMEM_PRUSS1_BANK_MASK                         (1 << 8)

/* Used by RM_L4PER2_PRUSS2_CONTEXT */
#define DRA7XX_LOSTMEM_PRUSS2_BANK_SHIFT                        8
#define DRA7XX_LOSTMEM_PRUSS2_BANK_WIDTH                        0x1
#define DRA7XX_LOSTMEM_PRUSS2_BANK_MASK                         (1 << 8)

/*
 * Used by RM_IPU_UART6_CONTEXT, RM_L4PER2_UART7_CONTEXT,
 * RM_L4PER2_UART8_CONTEXT, RM_L4PER2_UART9_CONTEXT, RM_L4PER_UART1_CONTEXT,
 * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT,
 * RM_L4PER_UART5_CONTEXT, RM_L4SEC_DMA_CRYPTO_CONTEXT,
 * RM_WKUPAON_UART10_CONTEXT
 */
#define DRA7XX_LOSTMEM_RETAINED_BANK_SHIFT                      8
#define DRA7XX_LOSTMEM_RETAINED_BANK_WIDTH                      0x1
#define DRA7XX_LOSTMEM_RETAINED_BANK_MASK                       (1 << 8)

/* Used by RM_IVA_SL2_CONTEXT */
#define DRA7XX_LOSTMEM_SL2_MEM_SHIFT                            8
#define DRA7XX_LOSTMEM_SL2_MEM_WIDTH                            0x1
#define DRA7XX_LOSTMEM_SL2_MEM_MASK                             (1 << 8)

/* Used by RM_IVA_IVA_CONTEXT */
#define DRA7XX_LOSTMEM_TCM1_MEM_SHIFT                           8
#define DRA7XX_LOSTMEM_TCM1_MEM_WIDTH                           0x1
#define DRA7XX_LOSTMEM_TCM1_MEM_MASK                            (1 << 8)

/* Used by RM_IVA_IVA_CONTEXT */
#define DRA7XX_LOSTMEM_TCM2_MEM_SHIFT                           9
#define DRA7XX_LOSTMEM_TCM2_MEM_WIDTH                           0x1
#define DRA7XX_LOSTMEM_TCM2_MEM_MASK                            (1 << 9)

/* Used by RM_L3MAIN1_TPCC_CONTEXT */
#define DRA7XX_LOSTMEM_TPCC_BANK_SHIFT                          8
#define DRA7XX_LOSTMEM_TPCC_BANK_WIDTH                          0x1
#define DRA7XX_LOSTMEM_TPCC_BANK_MASK                           (1 << 8)

/* Used by RM_L3MAIN1_TPTC1_CONTEXT, RM_L3MAIN1_TPTC2_CONTEXT */
#define DRA7XX_LOSTMEM_TPTC_BANK_SHIFT                          8
#define DRA7XX_LOSTMEM_TPTC_BANK_WIDTH                          0x1
#define DRA7XX_LOSTMEM_TPTC_BANK_MASK                           (1 << 8)

/* Used by RM_L3MAIN1_VCP1_CONTEXT, RM_L3MAIN1_VCP2_CONTEXT */
#define DRA7XX_LOSTMEM_VCP_BANK_SHIFT                           8
#define DRA7XX_LOSTMEM_VCP_BANK_WIDTH                           0x1
#define DRA7XX_LOSTMEM_VCP_BANK_MASK                            (1 << 8)

/* Used by RM_CAM_VIP1_CONTEXT, RM_CAM_VIP2_CONTEXT, RM_CAM_VIP3_CONTEXT */
#define DRA7XX_LOSTMEM_VIP_BANK_SHIFT                           8
#define DRA7XX_LOSTMEM_VIP_BANK_WIDTH                           0x1
#define DRA7XX_LOSTMEM_VIP_BANK_MASK                            (1 << 8)

/* Used by RM_VPE_VPE_CONTEXT */
#define DRA7XX_LOSTMEM_VPE_BANK_SHIFT                           8
#define DRA7XX_LOSTMEM_VPE_BANK_WIDTH                           0x1
#define DRA7XX_LOSTMEM_VPE_BANK_MASK                            (1 << 8)

/* Used by RM_WKUPAON_SAR_RAM_CONTEXT */
#define DRA7XX_LOSTMEM_WKUP_BANK_SHIFT                          8
#define DRA7XX_LOSTMEM_WKUP_BANK_WIDTH                          0x1
#define DRA7XX_LOSTMEM_WKUP_BANK_MASK                           (1 << 8)

/*
 * Used by PM_CAM_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_CUSTEFUSE_PWRSTCTRL,
 * PM_DSP1_PWRSTCTRL, PM_DSP2_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_EVE1_PWRSTCTRL,
 * PM_EVE2_PWRSTCTRL, PM_EVE3_PWRSTCTRL, PM_EVE4_PWRSTCTRL, PM_GPU_PWRSTCTRL,
 * PM_IPU_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL,
 * PM_MPU_PWRSTCTRL, PM_VPE_PWRSTCTRL
 */
#define DRA7XX_LOWPOWERSTATECHANGE_SHIFT                        4
#define DRA7XX_LOWPOWERSTATECHANGE_WIDTH                        0x1
#define DRA7XX_LOWPOWERSTATECHANGE_MASK                         (1 << 4)

/* Used by PRM_MODEM_IF_CTRL */
#define DRA7XX_MODEM_SHUTDOWN_IRQ_SHIFT                         9
#define DRA7XX_MODEM_SHUTDOWN_IRQ_WIDTH                         0x1
#define DRA7XX_MODEM_SHUTDOWN_IRQ_MASK                          (1 << 9)

/* Used by PRM_MODEM_IF_CTRL */
#define DRA7XX_MODEM_WAKE_IRQ_SHIFT                             8
#define DRA7XX_MODEM_WAKE_IRQ_WIDTH                             0x1
#define DRA7XX_MODEM_WAKE_IRQ_MASK                              (1 << 8)

/* Used by PM_MPU_PWRSTCTRL */
#define DRA7XX_MPU_L2_ONSTATE_SHIFT                             18
#define DRA7XX_MPU_L2_ONSTATE_WIDTH                             0x2
#define DRA7XX_MPU_L2_ONSTATE_MASK                              (0x3 << 18)

/* Used by PM_MPU_PWRSTCTRL */
#define DRA7XX_MPU_L2_RETSTATE_SHIFT                            9
#define DRA7XX_MPU_L2_RETSTATE_WIDTH                            0x1
#define DRA7XX_MPU_L2_RETSTATE_MASK                             (1 << 9)

/* Used by PM_MPU_PWRSTST */
#define DRA7XX_MPU_L2_STATEST_SHIFT                             6
#define DRA7XX_MPU_L2_STATEST_WIDTH                             0x2
#define DRA7XX_MPU_L2_STATEST_MASK                              (0x3 << 6)

/* Used by PM_MPU_PWRSTCTRL */
#define DRA7XX_MPU_RAM_ONSTATE_SHIFT                            20
#define DRA7XX_MPU_RAM_ONSTATE_WIDTH                            0x2
#define DRA7XX_MPU_RAM_ONSTATE_MASK                             (0x3 << 20)

/* Used by PM_MPU_PWRSTCTRL */
#define DRA7XX_MPU_RAM_RETSTATE_SHIFT                           10
#define DRA7XX_MPU_RAM_RETSTATE_WIDTH                           0x1
#define DRA7XX_MPU_RAM_RETSTATE_MASK                            (1 << 10)

/* Used by PM_MPU_PWRSTST */
#define DRA7XX_MPU_RAM_STATEST_SHIFT                            8
#define DRA7XX_MPU_RAM_STATEST_WIDTH                            0x2
#define DRA7XX_MPU_RAM_STATEST_MASK                             (0x3 << 8)

/* Used by PRM_RSTST */
#define DRA7XX_MPU_SECURITY_VIOL_RST_SHIFT                      2
#define DRA7XX_MPU_SECURITY_VIOL_RST_WIDTH                      0x1
#define DRA7XX_MPU_SECURITY_VIOL_RST_MASK                       (1 << 2)

/* Used by PRM_RSTST */
#define DRA7XX_MPU_WDT_RST_SHIFT                                3
#define DRA7XX_MPU_WDT_RST_WIDTH                                0x1
#define DRA7XX_MPU_WDT_RST_MASK                                 (1 << 3)

/*
 * Used by PRM_ABBLDO_DSPEVE_SETUP, PRM_ABBLDO_GPU_SETUP, PRM_ABBLDO_IVA_SETUP,
 * PRM_ABBLDO_MPU_SETUP
 */
#define DRA7XX_NOCAP_SHIFT                                      4
#define DRA7XX_NOCAP_WIDTH                                      0x1
#define DRA7XX_NOCAP_MASK                                       (1 << 4)

/* Used by PM_L4PER_PWRSTCTRL */
#define DRA7XX_NONRETAINED_BANK_ONSTATE_SHIFT                   18
#define DRA7XX_NONRETAINED_BANK_ONSTATE_WIDTH                   0x2
#define DRA7XX_NONRETAINED_BANK_ONSTATE_MASK                    (0x3 << 18)

/* Used by PM_L4PER_PWRSTCTRL */
#define DRA7XX_NONRETAINED_BANK_RETSTATE_SHIFT                  9
#define DRA7XX_NONRETAINED_BANK_RETSTATE_WIDTH                  0x1
#define DRA7XX_NONRETAINED_BANK_RETSTATE_MASK                   (1 << 9)

/* Used by PM_L4PER_PWRSTST */
#define DRA7XX_NONRETAINED_BANK_STATEST_SHIFT                   6
#define DRA7XX_NONRETAINED_BANK_STATEST_WIDTH                   0x2
#define DRA7XX_NONRETAINED_BANK_STATEST_MASK                    (0x3 << 6)

/* Used by PM_CORE_PWRSTCTRL */
#define DRA7XX_OCP_NRET_BANK_ONSTATE_SHIFT                      24
#define DRA7XX_OCP_NRET_BANK_ONSTATE_WIDTH                      0x2
#define DRA7XX_OCP_NRET_BANK_ONSTATE_MASK                       (0x3 << 24)

/* Used by PM_CORE_PWRSTCTRL */
#define DRA7XX_OCP_NRET_BANK_RETSTATE_SHIFT                     12
#define DRA7XX_OCP_NRET_BANK_RETSTATE_WIDTH                     0x1
#define DRA7XX_OCP_NRET_BANK_RETSTATE_MASK                      (1 << 12)

/* Used by PM_CORE_PWRSTST */
#define DRA7XX_OCP_NRET_BANK_STATEST_SHIFT                      12
#define DRA7XX_OCP_NRET_BANK_STATEST_WIDTH                      0x2
#define DRA7XX_OCP_NRET_BANK_STATEST_MASK                       (0x3 << 12)

/*
 * Used by PRM_ABBLDO_DSPEVE_CTRL, PRM_ABBLDO_GPU_CTRL, PRM_ABBLDO_IVA_CTRL,
 * PRM_ABBLDO_MPU_CTRL
 */
#define DRA7XX_OPP_CHANGE_SHIFT                                 2
#define DRA7XX_OPP_CHANGE_WIDTH                                 0x1
#define DRA7XX_OPP_CHANGE_MASK                                  (1 << 2)

/*
 * Used by PRM_ABBLDO_DSPEVE_CTRL, PRM_ABBLDO_GPU_CTRL, PRM_ABBLDO_IVA_CTRL,
 * PRM_ABBLDO_MPU_CTRL
 */
#define DRA7XX_OPP_SEL_SHIFT                                    0
#define DRA7XX_OPP_SEL_WIDTH                                    0x2
#define DRA7XX_OPP_SEL_MASK                                     (0x3 << 0)

/* Used by PRM_DEBUG_OUT */
#define DRA7XX_OUTPUT_SHIFT                                     0
#define DRA7XX_OUTPUT_WIDTH                                     0x20
#define DRA7XX_OUTPUT_MASK                                      (0xffffffff << 0)

/* Used by PRM_SRAM_COUNT */
#define DRA7XX_PCHARGECNT_VALUE_SHIFT                           0
#define DRA7XX_PCHARGECNT_VALUE_WIDTH                           0x6
#define DRA7XX_PCHARGECNT_VALUE_MASK                            (0x3f << 0)

/* Used by PRM_PSCON_COUNT */
#define DRA7XX_PCHARGE_TIME_SHIFT                               0
#define DRA7XX_PCHARGE_TIME_WIDTH                               0x8
#define DRA7XX_PCHARGE_TIME_MASK                                (0xff << 0)

/* Used by PM_IPU_PWRSTCTRL */
#define DRA7XX_PERIPHMEM_ONSTATE_SHIFT                          20
#define DRA7XX_PERIPHMEM_ONSTATE_WIDTH                          0x2
#define DRA7XX_PERIPHMEM_ONSTATE_MASK                           (0x3 << 20)

/* Used by PM_IPU_PWRSTCTRL */
#define DRA7XX_PERIPHMEM_RETSTATE_SHIFT                         10
#define DRA7XX_PERIPHMEM_RETSTATE_WIDTH                         0x1
#define DRA7XX_PERIPHMEM_RETSTATE_MASK                          (1 << 10)

/* Used by PM_IPU_PWRSTST */
#define DRA7XX_PERIPHMEM_STATEST_SHIFT                          8
#define DRA7XX_PERIPHMEM_STATEST_WIDTH                          0x2
#define DRA7XX_PERIPHMEM_STATEST_MASK                           (0x3 << 8)

/* Used by PRM_PHASE1_CNDP */
#define DRA7XX_PHASE1_CNDP_SHIFT                                0
#define DRA7XX_PHASE1_CNDP_WIDTH                                0x20
#define DRA7XX_PHASE1_CNDP_MASK                                 (0xffffffff << 0)

/* Used by PRM_PHASE2A_CNDP */
#define DRA7XX_PHASE2A_CNDP_SHIFT                               0
#define DRA7XX_PHASE2A_CNDP_WIDTH                               0x20
#define DRA7XX_PHASE2A_CNDP_MASK                                (0xffffffff << 0)

/* Used by PRM_PHASE2B_CNDP */
#define DRA7XX_PHASE2B_CNDP_SHIFT                               0
#define DRA7XX_PHASE2B_CNDP_WIDTH                               0x20
#define DRA7XX_PHASE2B_CNDP_MASK                                (0xffffffff << 0)

/* Used by PRM_PSCON_COUNT */
#define DRA7XX_PONOUT_2_PGOODIN_TIME_SHIFT                      8
#define DRA7XX_PONOUT_2_PGOODIN_TIME_WIDTH                      0x8
#define DRA7XX_PONOUT_2_PGOODIN_TIME_MASK                       (0xff << 8)

/*
 * Used by PM_CAM_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_CUSTEFUSE_PWRSTCTRL,
 * PM_DSP1_PWRSTCTRL, PM_DSP2_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_EMU_PWRSTCTRL,
 * PM_EVE1_PWRSTCTRL, PM_EVE2_PWRSTCTRL, PM_EVE3_PWRSTCTRL, PM_EVE4_PWRSTCTRL,
 * PM_GPU_PWRSTCTRL, PM_IPU_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL,
 * PM_L4PER_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_VPE_PWRSTCTRL
 */
#define DRA7XX_POWERSTATE_SHIFT                                 0
#define DRA7XX_POWERSTATE_WIDTH                                 0x2
#define DRA7XX_POWERSTATE_MASK                                  (0x3 << 0)

/*
 * Used by PM_CAM_PWRSTST, PM_CORE_PWRSTST, PM_CUSTEFUSE_PWRSTST,
 * PM_DSP1_PWRSTST, PM_DSP2_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST,
 * PM_EVE1_PWRSTST, PM_EVE2_PWRSTST, PM_EVE3_PWRSTST, PM_EVE4_PWRSTST,
 * PM_GPU_PWRSTST, PM_IPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST,
 * PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_VPE_PWRSTST
 */
#define DRA7XX_POWERSTATEST_SHIFT                               0
#define DRA7XX_POWERSTATEST_WIDTH                               0x2
#define DRA7XX_POWERSTATEST_MASK                                (0x3 << 0)

/* Used by PRM_PWRREQCTRL */
#define DRA7XX_PWRREQ_COND_SHIFT                                0
#define DRA7XX_PWRREQ_COND_WIDTH                                0x2
#define DRA7XX_PWRREQ_COND_MASK                                 (0x3 << 0)

/*
 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
 * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
 * PRM_VOLTSETUP_MPU_RET_SLEEP
 */
#define DRA7XX_RAMP_DOWN_COUNT_SHIFT                            16
#define DRA7XX_RAMP_DOWN_COUNT_WIDTH                            0x6
#define DRA7XX_RAMP_DOWN_COUNT_MASK                             (0x3f << 16)

/*
 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
 * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
 * PRM_VOLTSETUP_MPU_RET_SLEEP
 */
#define DRA7XX_RAMP_DOWN_PRESCAL_SHIFT                          24
#define DRA7XX_RAMP_DOWN_PRESCAL_WIDTH                          0x2
#define DRA7XX_RAMP_DOWN_PRESCAL_MASK                           (0x3 << 24)

/*
 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
 * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
 * PRM_VOLTSETUP_MPU_RET_SLEEP
 */
#define DRA7XX_RAMP_UP_COUNT_SHIFT                              0
#define DRA7XX_RAMP_UP_COUNT_WIDTH                              0x6
#define DRA7XX_RAMP_UP_COUNT_MASK                               (0x3f << 0)

/*
 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
 * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
 * PRM_VOLTSETUP_MPU_RET_SLEEP
 */
#define DRA7XX_RAMP_UP_PRESCAL_SHIFT                            8
#define DRA7XX_RAMP_UP_PRESCAL_WIDTH                            0x2
#define DRA7XX_RAMP_UP_PRESCAL_MASK                             (0x3 << 8)

/* Used by PM_L4PER_PWRSTCTRL */
#define DRA7XX_RETAINED_BANK_ONSTATE_SHIFT                      16
#define DRA7XX_RETAINED_BANK_ONSTATE_WIDTH                      0x2
#define DRA7XX_RETAINED_BANK_ONSTATE_MASK                       (0x3 << 16)

/* Used by PM_L4PER_PWRSTCTRL */
#define DRA7XX_RETAINED_BANK_RETSTATE_SHIFT                     8
#define DRA7XX_RETAINED_BANK_RETSTATE_WIDTH                     0x1
#define DRA7XX_RETAINED_BANK_RETSTATE_MASK                      (1 << 8)

/* Used by PM_L4PER_PWRSTST */
#define DRA7XX_RETAINED_BANK_STATEST_SHIFT                      4
#define DRA7XX_RETAINED_BANK_STATEST_WIDTH                      0x2
#define DRA7XX_RETAINED_BANK_STATEST_MASK                       (0x3 << 4)

/*
 * Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_DSPEVE_CTRL, PRM_SLDO_GPU_CTRL,
 * PRM_SLDO_IVA_CTRL, PRM_SLDO_MPU_CTRL
 */
#define DRA7XX_RETMODE_ENABLE_SHIFT                             0
#define DRA7XX_RETMODE_ENABLE_WIDTH                             0x1
#define DRA7XX_RETMODE_ENABLE_MASK                              (1 << 0)

/* Used by PRM_RSTTIME */
#define DRA7XX_RSTTIME1_SHIFT                                   0
#define DRA7XX_RSTTIME1_WIDTH                                   0xa
#define DRA7XX_RSTTIME1_MASK                                    (0x3ff << 0)

/* Used by PRM_RSTTIME */
#define DRA7XX_RSTTIME2_SHIFT                                   10
#define DRA7XX_RSTTIME2_WIDTH                                   0x5
#define DRA7XX_RSTTIME2_MASK                                    (0x1f << 10)

/* Used by RM_IPU1_RSTCTRL, RM_IPU1_RSTST, RM_IPU2_RSTCTRL, RM_IPU2_RSTST */
#define DRA7XX_RST_CPU0_SHIFT                                   0
#define DRA7XX_RST_CPU0_WIDTH                                   0x1
#define DRA7XX_RST_CPU0_MASK                                    (1 << 0)

/* Used by RM_IPU1_RSTCTRL, RM_IPU1_RSTST, RM_IPU2_RSTCTRL, RM_IPU2_RSTST */
#define DRA7XX_RST_CPU1_SHIFT                                   1
#define DRA7XX_RST_CPU1_WIDTH                                   0x1
#define DRA7XX_RST_CPU1_MASK                                    (1 << 1)

/* Used by RM_DSP1_RSTCTRL, RM_DSP1_RSTST */
#define DRA7XX_RST_DSP1_SHIFT                                   1
#define DRA7XX_RST_DSP1_WIDTH                                   0x1
#define DRA7XX_RST_DSP1_MASK                                    (1 << 1)

/* Used by RM_DSP1_RSTST */
#define DRA7XX_RST_DSP1_EMU_SHIFT                               2
#define DRA7XX_RST_DSP1_EMU_WIDTH                               0x1
#define DRA7XX_RST_DSP1_EMU_MASK                                (1 << 2)

/* Used by RM_DSP1_RSTST */
#define DRA7XX_RST_DSP1_EMU_REQ_SHIFT                           3
#define DRA7XX_RST_DSP1_EMU_REQ_WIDTH                           0x1
#define DRA7XX_RST_DSP1_EMU_REQ_MASK                            (1 << 3)

/* Used by RM_DSP1_RSTCTRL, RM_DSP1_RSTST */
#define DRA7XX_RST_DSP1_LRST_SHIFT                              0
#define DRA7XX_RST_DSP1_LRST_WIDTH                              0x1
#define DRA7XX_RST_DSP1_LRST_MASK                               (1 << 0)

/* Used by RM_DSP2_RSTCTRL, RM_DSP2_RSTST */
#define DRA7XX_RST_DSP2_SHIFT                                   1
#define DRA7XX_RST_DSP2_WIDTH                                   0x1
#define DRA7XX_RST_DSP2_MASK                                    (1 << 1)

/* Used by RM_DSP2_RSTST */
#define DRA7XX_RST_DSP2_EMU_SHIFT                               2
#define DRA7XX_RST_DSP2_EMU_WIDTH                               0x1
#define DRA7XX_RST_DSP2_EMU_MASK                                (1 << 2)

/* Used by RM_DSP2_RSTST */
#define DRA7XX_RST_DSP2_EMU_REQ_SHIFT                           3
#define DRA7XX_RST_DSP2_EMU_REQ_WIDTH                           0x1
#define DRA7XX_RST_DSP2_EMU_REQ_MASK                            (1 << 3)

/* Used by RM_DSP2_RSTCTRL, RM_DSP2_RSTST */
#define DRA7XX_RST_DSP2_LRST_SHIFT                              0
#define DRA7XX_RST_DSP2_LRST_WIDTH                              0x1
#define DRA7XX_RST_DSP2_LRST_MASK                               (1 << 0)

/* Used by RM_IPU1_RSTST, RM_IPU2_RSTST */
#define DRA7XX_RST_EMULATION_CPU0_SHIFT                         3
#define DRA7XX_RST_EMULATION_CPU0_WIDTH                         0x1
#define DRA7XX_RST_EMULATION_CPU0_MASK                          (1 << 3)

/* Used by RM_IPU1_RSTST, RM_IPU2_RSTST */
#define DRA7XX_RST_EMULATION_CPU1_SHIFT                         4
#define DRA7XX_RST_EMULATION_CPU1_WIDTH                         0x1
#define DRA7XX_RST_EMULATION_CPU1_MASK                          (1 << 4)

/* Used by RM_IVA_RSTST */
#define DRA7XX_RST_EMULATION_SEQ1_SHIFT                         3
#define DRA7XX_RST_EMULATION_SEQ1_WIDTH                         0x1
#define DRA7XX_RST_EMULATION_SEQ1_MASK                          (1 << 3)

/* Used by RM_IVA_RSTST */
#define DRA7XX_RST_EMULATION_SEQ2_SHIFT                         4
#define DRA7XX_RST_EMULATION_SEQ2_WIDTH                         0x1
#define DRA7XX_RST_EMULATION_SEQ2_MASK                          (1 << 4)

/* Used by RM_EVE1_RSTCTRL, RM_EVE1_RSTST */
#define DRA7XX_RST_EVE1_SHIFT                                   1
#define DRA7XX_RST_EVE1_WIDTH                                   0x1
#define DRA7XX_RST_EVE1_MASK                                    (1 << 1)

/* Used by RM_EVE1_RSTST */
#define DRA7XX_RST_EVE1_EMU_SHIFT                               2
#define DRA7XX_RST_EVE1_EMU_WIDTH                               0x1
#define DRA7XX_RST_EVE1_EMU_MASK                                (1 << 2)

/* Used by RM_EVE1_RSTST */
#define DRA7XX_RST_EVE1_EMU_REQ_SHIFT                           3
#define DRA7XX_RST_EVE1_EMU_REQ_WIDTH                           0x1
#define DRA7XX_RST_EVE1_EMU_REQ_MASK                            (1 << 3)

/* Used by RM_EVE1_RSTCTRL, RM_EVE1_RSTST */
#define DRA7XX_RST_EVE1_LRST_SHIFT                              0
#define DRA7XX_RST_EVE1_LRST_WIDTH                              0x1
#define DRA7XX_RST_EVE1_LRST_MASK                               (1 << 0)

/* Used by RM_EVE2_RSTCTRL, RM_EVE2_RSTST */
#define DRA7XX_RST_EVE2_SHIFT                                   1
#define DRA7XX_RST_EVE2_WIDTH                                   0x1
#define DRA7XX_RST_EVE2_MASK                                    (1 << 1)

/* Used by RM_EVE2_RSTST */
#define DRA7XX_RST_EVE2_EMU_SHIFT                               2
#define DRA7XX_RST_EVE2_EMU_WIDTH                               0x1
#define DRA7XX_RST_EVE2_EMU_MASK                                (1 << 2)

/* Used by RM_EVE2_RSTST */
#define DRA7XX_RST_EVE2_EMU_REQ_SHIFT                           3
#define DRA7XX_RST_EVE2_EMU_REQ_WIDTH                           0x1
#define DRA7XX_RST_EVE2_EMU_REQ_MASK                            (1 << 3)

/* Used by RM_EVE2_RSTCTRL, RM_EVE2_RSTST */
#define DRA7XX_RST_EVE2_LRST_SHIFT                              0
#define DRA7XX_RST_EVE2_LRST_WIDTH                              0x1
#define DRA7XX_RST_EVE2_LRST_MASK                               (1 << 0)

/* Used by RM_EVE3_RSTCTRL, RM_EVE3_RSTST */
#define DRA7XX_RST_EVE3_SHIFT                                   1
#define DRA7XX_RST_EVE3_WIDTH                                   0x1
#define DRA7XX_RST_EVE3_MASK                                    (1 << 1)

/* Used by RM_EVE3_RSTST */
#define DRA7XX_RST_EVE3_EMU_SHIFT                               2
#define DRA7XX_RST_EVE3_EMU_WIDTH                               0x1
#define DRA7XX_RST_EVE3_EMU_MASK                                (1 << 2)

/* Used by RM_EVE3_RSTST */
#define DRA7XX_RST_EVE3_EMU_REQ_SHIFT                           3
#define DRA7XX_RST_EVE3_EMU_REQ_WIDTH                           0x1
#define DRA7XX_RST_EVE3_EMU_REQ_MASK                            (1 << 3)

/* Used by RM_EVE3_RSTCTRL, RM_EVE3_RSTST */
#define DRA7XX_RST_EVE3_LRST_SHIFT                              0
#define DRA7XX_RST_EVE3_LRST_WIDTH                              0x1
#define DRA7XX_RST_EVE3_LRST_MASK                               (1 << 0)

/* Used by RM_EVE4_RSTCTRL, RM_EVE4_RSTST */
#define DRA7XX_RST_EVE4_SHIFT                                   1
#define DRA7XX_RST_EVE4_WIDTH                                   0x1
#define DRA7XX_RST_EVE4_MASK                                    (1 << 1)

/* Used by RM_EVE4_RSTST */
#define DRA7XX_RST_EVE4_EMU_SHIFT                               2
#define DRA7XX_RST_EVE4_EMU_WIDTH                               0x1
#define DRA7XX_RST_EVE4_EMU_MASK                                (1 << 2)

/* Used by RM_EVE4_RSTST */
#define DRA7XX_RST_EVE4_EMU_REQ_SHIFT                           3
#define DRA7XX_RST_EVE4_EMU_REQ_WIDTH                           0x1
#define DRA7XX_RST_EVE4_EMU_REQ_MASK                            (1 << 3)

/* Used by RM_EVE4_RSTCTRL, RM_EVE4_RSTST */
#define DRA7XX_RST_EVE4_LRST_SHIFT                              0
#define DRA7XX_RST_EVE4_LRST_WIDTH                              0x1
#define DRA7XX_RST_EVE4_LRST_MASK                               (1 << 0)

/* Used by PRM_RSTCTRL */
#define DRA7XX_RST_GLOBAL_COLD_SW_SHIFT                         1
#define DRA7XX_RST_GLOBAL_COLD_SW_WIDTH                         0x1
#define DRA7XX_RST_GLOBAL_COLD_SW_MASK                          (1 << 1)

/* Used by PRM_RSTCTRL */
#define DRA7XX_RST_GLOBAL_WARM_SW_SHIFT                         0
#define DRA7XX_RST_GLOBAL_WARM_SW_WIDTH                         0x1
#define DRA7XX_RST_GLOBAL_WARM_SW_MASK                          (1 << 0)

/* Used by RM_IPU1_RSTST, RM_IPU2_RSTST */
#define DRA7XX_RST_ICECRUSHER_CPU0_SHIFT                        5
#define DRA7XX_RST_ICECRUSHER_CPU0_WIDTH                        0x1
#define DRA7XX_RST_ICECRUSHER_CPU0_MASK                         (1 << 5)

/* Used by RM_IPU1_RSTST, RM_IPU2_RSTST */
#define DRA7XX_RST_ICECRUSHER_CPU1_SHIFT                        6
#define DRA7XX_RST_ICECRUSHER_CPU1_WIDTH                        0x1
#define DRA7XX_RST_ICECRUSHER_CPU1_MASK                         (1 << 6)

/* Used by RM_IVA_RSTST */
#define DRA7XX_RST_ICECRUSHER_SEQ1_SHIFT                        5
#define DRA7XX_RST_ICECRUSHER_SEQ1_WIDTH                        0x1
#define DRA7XX_RST_ICECRUSHER_SEQ1_MASK                         (1 << 5)

/* Used by RM_IVA_RSTST */
#define DRA7XX_RST_ICECRUSHER_SEQ2_SHIFT                        6
#define DRA7XX_RST_ICECRUSHER_SEQ2_WIDTH                        0x1
#define DRA7XX_RST_ICECRUSHER_SEQ2_MASK                         (1 << 6)

/* Used by RM_IPU1_RSTCTRL, RM_IPU1_RSTST, RM_IPU2_RSTCTRL, RM_IPU2_RSTST */
#define DRA7XX_RST_IPU_SHIFT                                    2
#define DRA7XX_RST_IPU_WIDTH                                    0x1
#define DRA7XX_RST_IPU_MASK                                     (1 << 2)

/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */
#define DRA7XX_RST_LOGIC_SHIFT                                  2
#define DRA7XX_RST_LOGIC_WIDTH                                  0x1
#define DRA7XX_RST_LOGIC_MASK                                   (1 << 2)

/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */
#define DRA7XX_RST_SEQ1_SHIFT                                   0
#define DRA7XX_RST_SEQ1_WIDTH                                   0x1
#define DRA7XX_RST_SEQ1_MASK                                    (1 << 0)

/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */
#define DRA7XX_RST_SEQ2_SHIFT                                   1
#define DRA7XX_RST_SEQ2_WIDTH                                   0x1
#define DRA7XX_RST_SEQ2_MASK                                    (1 << 1)

/* Used by REVISION_PRM */
#define DRA7XX_R_RTL_SHIFT                                      11
#define DRA7XX_R_RTL_WIDTH                                      0x5
#define DRA7XX_R_RTL_MASK                                       (0x1f << 11)

/* Used by REVISION_PRM */
#define DRA7XX_SCHEME_SHIFT                                     30
#define DRA7XX_SCHEME_WIDTH                                     0x2
#define DRA7XX_SCHEME_MASK                                      (0x3 << 30)

/* Used by PRM_RSTST */
#define DRA7XX_SECURE_WDT_RST_SHIFT                             4
#define DRA7XX_SECURE_WDT_RST_WIDTH                             0x1
#define DRA7XX_SECURE_WDT_RST_MASK                              (1 << 4)

/* Used by PRM_DEBUG_CFG1 */
#define DRA7XX_PRM_SEL1_SHIFT                                   0
#define DRA7XX_PRM_SEL1_WIDTH                                   0x9
#define DRA7XX_PRM_SEL1_MASK                                    (0x1ff << 0)

/* Used by PRM_DEBUG_CFG2 */
#define DRA7XX_PRM_SEL2_SHIFT                                   0
#define DRA7XX_PRM_SEL2_WIDTH                                   0x9
#define DRA7XX_PRM_SEL2_MASK                                    (0x1ff << 0)

/* Used by PRM_DEBUG_CFG3 */
#define DRA7XX_PRM_SEL3_SHIFT                                   0
#define DRA7XX_PRM_SEL3_WIDTH                                   0x9
#define DRA7XX_PRM_SEL3_MASK                                    (0x1ff << 0)

/* Used by PM_IVA_PWRSTCTRL */
#define DRA7XX_SL2_MEM_ONSTATE_SHIFT                            18
#define DRA7XX_SL2_MEM_ONSTATE_WIDTH                            0x2
#define DRA7XX_SL2_MEM_ONSTATE_MASK                             (0x3 << 18)

/* Used by PM_IVA_PWRSTCTRL */
#define DRA7XX_SL2_MEM_RETSTATE_SHIFT                           9
#define DRA7XX_SL2_MEM_RETSTATE_WIDTH                           0x1
#define DRA7XX_SL2_MEM_RETSTATE_MASK                            (1 << 9)

/* Used by PM_IVA_PWRSTST */
#define DRA7XX_SL2_MEM_STATEST_SHIFT                            6
#define DRA7XX_SL2_MEM_STATEST_WIDTH                            0x2
#define DRA7XX_SL2_MEM_STATEST_MASK                             (0x3 << 6)

/* Used by PRM_SRAM_COUNT */
#define DRA7XX_SLPCNT_VALUE_SHIFT                               16
#define DRA7XX_SLPCNT_VALUE_WIDTH                               0x8
#define DRA7XX_SLPCNT_VALUE_MASK                                (0xff << 16)

/*
 * Used by PRM_ABBLDO_DSPEVE_SETUP, PRM_ABBLDO_GPU_SETUP, PRM_ABBLDO_IVA_SETUP,
 * PRM_ABBLDO_MPU_SETUP
 */
#define DRA7XX_SR2EN_SHIFT                                      0
#define DRA7XX_SR2EN_WIDTH                                      0x1
#define DRA7XX_SR2EN_MASK                                       (1 << 0)

/*
 * Used by PRM_ABBLDO_DSPEVE_CTRL, PRM_ABBLDO_GPU_CTRL, PRM_ABBLDO_IVA_CTRL,
 * PRM_ABBLDO_MPU_CTRL
 */
#define DRA7XX_SR2_IN_TRANSITION_SHIFT                          6
#define DRA7XX_SR2_IN_TRANSITION_WIDTH                          0x1
#define DRA7XX_SR2_IN_TRANSITION_MASK                           (1 << 6)

/*
 * Used by PRM_ABBLDO_DSPEVE_CTRL, PRM_ABBLDO_GPU_CTRL, PRM_ABBLDO_IVA_CTRL,
 * PRM_ABBLDO_MPU_CTRL
 */
#define DRA7XX_SR2_STATUS_SHIFT                                 3
#define DRA7XX_SR2_STATUS_WIDTH                                 0x2
#define DRA7XX_SR2_STATUS_MASK                                  (0x3 << 3)

/*
 * Used by PRM_ABBLDO_DSPEVE_SETUP, PRM_ABBLDO_GPU_SETUP, PRM_ABBLDO_IVA_SETUP,
 * PRM_ABBLDO_MPU_SETUP
 */
#define DRA7XX_SR2_WTCNT_VALUE_SHIFT                            8
#define DRA7XX_SR2_WTCNT_VALUE_WIDTH                            0x8
#define DRA7XX_SR2_WTCNT_VALUE_MASK                             (0xff << 8)

/*
 * Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_DSPEVE_CTRL, PRM_SLDO_GPU_CTRL,
 * PRM_SLDO_IVA_CTRL, PRM_SLDO_MPU_CTRL
 */
#define DRA7XX_SRAMLDO_STATUS_SHIFT                             8
#define DRA7XX_SRAMLDO_STATUS_WIDTH                             0x1
#define DRA7XX_SRAMLDO_STATUS_MASK                              (1 << 8)

/*
 * Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_DSPEVE_CTRL, PRM_SLDO_GPU_CTRL,
 * PRM_SLDO_IVA_CTRL, PRM_SLDO_MPU_CTRL
 */
#define DRA7XX_SRAM_IN_TRANSITION_SHIFT                         9
#define DRA7XX_SRAM_IN_TRANSITION_WIDTH                         0x1
#define DRA7XX_SRAM_IN_TRANSITION_MASK                          (1 << 9)

/* Used by PRM_VOLTSETUP_WARMRESET */
#define DRA7XX_STABLE_COUNT_SHIFT                               0
#define DRA7XX_STABLE_COUNT_WIDTH                               0x6
#define DRA7XX_STABLE_COUNT_MASK                                (0x3f << 0)

/* Used by PRM_VOLTSETUP_WARMRESET */
#define DRA7XX_STABLE_PRESCAL_SHIFT                             8
#define DRA7XX_STABLE_PRESCAL_WIDTH                             0x2
#define DRA7XX_STABLE_PRESCAL_MASK                              (0x3 << 8)

/* Used by PRM_BANDGAP_SETUP */
#define DRA7XX_STARTUP_COUNT_SHIFT                              0
#define DRA7XX_STARTUP_COUNT_WIDTH                              0x8
#define DRA7XX_STARTUP_COUNT_MASK                               (0xff << 0)

/* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */
#define DRA7XX_STARTUP_COUNT_24_31_SHIFT                        24
#define DRA7XX_STARTUP_COUNT_24_31_WIDTH                        0x8
#define DRA7XX_STARTUP_COUNT_24_31_MASK                         (0xff << 24)

/* Used by PM_IVA_PWRSTCTRL */
#define DRA7XX_TCM1_MEM_ONSTATE_SHIFT                           20
#define DRA7XX_TCM1_MEM_ONSTATE_WIDTH                           0x2
#define DRA7XX_TCM1_MEM_ONSTATE_MASK                            (0x3 << 20)

/* Used by PM_IVA_PWRSTCTRL */
#define DRA7XX_TCM1_MEM_RETSTATE_SHIFT                          10
#define DRA7XX_TCM1_MEM_RETSTATE_WIDTH                          0x1
#define DRA7XX_TCM1_MEM_RETSTATE_MASK                           (1 << 10)

/* Used by PM_IVA_PWRSTST */
#define DRA7XX_TCM1_MEM_STATEST_SHIFT                           8
#define DRA7XX_TCM1_MEM_STATEST_WIDTH                           0x2
#define DRA7XX_TCM1_MEM_STATEST_MASK                            (0x3 << 8)

/* Used by PM_IVA_PWRSTCTRL */
#define DRA7XX_TCM2_MEM_ONSTATE_SHIFT                           22
#define DRA7XX_TCM2_MEM_ONSTATE_WIDTH                           0x2
#define DRA7XX_TCM2_MEM_ONSTATE_MASK                            (0x3 << 22)

/* Used by PM_IVA_PWRSTCTRL */
#define DRA7XX_TCM2_MEM_RETSTATE_SHIFT                          11
#define DRA7XX_TCM2_MEM_RETSTATE_WIDTH                          0x1
#define DRA7XX_TCM2_MEM_RETSTATE_MASK                           (1 << 11)

/* Used by PM_IVA_PWRSTST */
#define DRA7XX_TCM2_MEM_STATEST_SHIFT                           10
#define DRA7XX_TCM2_MEM_STATEST_WIDTH                           0x2
#define DRA7XX_TCM2_MEM_STATEST_MASK                            (0x3 << 10)

/* Used by PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2, PRM_IRQENABLE_MPU */
#define DRA7XX_TRANSITION_EN_SHIFT                              8
#define DRA7XX_TRANSITION_EN_WIDTH                              0x1
#define DRA7XX_TRANSITION_EN_MASK                               (1 << 8)

/* Used by PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU */
#define DRA7XX_TRANSITION_ST_SHIFT                              8
#define DRA7XX_TRANSITION_ST_WIDTH                              0x1
#define DRA7XX_TRANSITION_ST_MASK                               (1 << 8)

/* Used by PRM_RSTST */
#define DRA7XX_TSHUT_CORE_RST_SHIFT                             13
#define DRA7XX_TSHUT_CORE_RST_WIDTH                             0x1
#define DRA7XX_TSHUT_CORE_RST_MASK                              (1 << 13)

/* Used by PRM_RSTST */
#define DRA7XX_TSHUT_DSPEVE_RST_SHIFT                           15
#define DRA7XX_TSHUT_DSPEVE_RST_WIDTH                           0x1
#define DRA7XX_TSHUT_DSPEVE_RST_MASK                            (1 << 15)

/* Used by PRM_RSTST */
#define DRA7XX_TSHUT_IVA_RST_SHIFT                              16
#define DRA7XX_TSHUT_IVA_RST_WIDTH                              0x1
#define DRA7XX_TSHUT_IVA_RST_MASK                               (1 << 16)

/* Used by PRM_RSTST */
#define DRA7XX_TSHUT_MM_RST_SHIFT                               12
#define DRA7XX_TSHUT_MM_RST_WIDTH                               0x1
#define DRA7XX_TSHUT_MM_RST_MASK                                (1 << 12)

/* Used by PRM_RSTST */
#define DRA7XX_TSHUT_MPU_RST_SHIFT                              11
#define DRA7XX_TSHUT_MPU_RST_WIDTH                              0x1
#define DRA7XX_TSHUT_MPU_RST_MASK                               (1 << 11)

/* Used by PRM_VOLTCTRL */
#define DRA7XX_VDD_CORE_I2C_DISABLE_SHIFT                       12
#define DRA7XX_VDD_CORE_I2C_DISABLE_WIDTH                       0x1
#define DRA7XX_VDD_CORE_I2C_DISABLE_MASK                        (1 << 12)

/* Used by PRM_RSTST */
#define DRA7XX_VDD_CORE_VOLT_MGR_RST_SHIFT                      8
#define DRA7XX_VDD_CORE_VOLT_MGR_RST_WIDTH                      0x1
#define DRA7XX_VDD_CORE_VOLT_MGR_RST_MASK                       (1 << 8)

/* Used by PRM_VOLTCTRL */
#define DRA7XX_VDD_MM_I2C_DISABLE_SHIFT                         14
#define DRA7XX_VDD_MM_I2C_DISABLE_WIDTH                         0x1
#define DRA7XX_VDD_MM_I2C_DISABLE_MASK                          (1 << 14)

/* Used by PRM_VOLTCTRL */
#define DRA7XX_VDD_MM_PRESENCE_SHIFT                            9
#define DRA7XX_VDD_MM_PRESENCE_WIDTH                            0x1
#define DRA7XX_VDD_MM_PRESENCE_MASK                             (1 << 9)

/* Used by PRM_RSTST */
#define DRA7XX_VDD_MM_VOLT_MGR_RST_SHIFT                        7
#define DRA7XX_VDD_MM_VOLT_MGR_RST_WIDTH                        0x1
#define DRA7XX_VDD_MM_VOLT_MGR_RST_MASK                         (1 << 7)

/* Used by PRM_VOLTCTRL */
#define DRA7XX_VDD_MPU_I2C_DISABLE_SHIFT                        13
#define DRA7XX_VDD_MPU_I2C_DISABLE_WIDTH                        0x1
#define DRA7XX_VDD_MPU_I2C_DISABLE_MASK                         (1 << 13)

/* Used by PRM_VOLTCTRL */
#define DRA7XX_VDD_MPU_PRESENCE_SHIFT                           8
#define DRA7XX_VDD_MPU_PRESENCE_WIDTH                           0x1
#define DRA7XX_VDD_MPU_PRESENCE_MASK                            (1 << 8)

/* Used by PRM_RSTST */
#define DRA7XX_VDD_MPU_VOLT_MGR_RST_SHIFT                       6
#define DRA7XX_VDD_MPU_VOLT_MGR_RST_WIDTH                       0x1
#define DRA7XX_VDD_MPU_VOLT_MGR_RST_MASK                        (1 << 6)

/* Used by PM_CAM_PWRSTCTRL */
#define DRA7XX_VIP_BANK_ONSTATE_SHIFT                           16
#define DRA7XX_VIP_BANK_ONSTATE_WIDTH                           0x2
#define DRA7XX_VIP_BANK_ONSTATE_MASK                            (0x3 << 16)

/* Used by PM_CAM_PWRSTST */
#define DRA7XX_VIP_BANK_STATEST_SHIFT                           4
#define DRA7XX_VIP_BANK_STATEST_WIDTH                           0x2
#define DRA7XX_VIP_BANK_STATEST_MASK                            (0x3 << 4)

/* Used by PRM_VOLTST_MM, PRM_VOLTST_MPU */
#define DRA7XX_VOLTSTATEST_SHIFT                                0
#define DRA7XX_VOLTSTATEST_WIDTH                                0x2
#define DRA7XX_VOLTSTATEST_MASK                                 (0x3 << 0)

/* Used by PM_VPE_PWRSTCTRL */
#define DRA7XX_VPE_BANK_ONSTATE_SHIFT                           16
#define DRA7XX_VPE_BANK_ONSTATE_WIDTH                           0x2
#define DRA7XX_VPE_BANK_ONSTATE_MASK                            (0x3 << 16)

/* Used by PM_VPE_PWRSTCTRL */
#define DRA7XX_VPE_BANK_RETSTATE_SHIFT                          8
#define DRA7XX_VPE_BANK_RETSTATE_WIDTH                          0x1
#define DRA7XX_VPE_BANK_RETSTATE_MASK                           (1 << 8)

/* Used by PM_VPE_PWRSTST */
#define DRA7XX_VPE_BANK_STATEST_SHIFT                           4
#define DRA7XX_VPE_BANK_STATEST_WIDTH                           0x2
#define DRA7XX_VPE_BANK_STATEST_MASK                            (0x3 << 4)

/* Used by PRM_SRAM_COUNT */
#define DRA7XX_VSETUPCNT_VALUE_SHIFT                            8
#define DRA7XX_VSETUPCNT_VALUE_WIDTH                            0x8
#define DRA7XX_VSETUPCNT_VALUE_MASK                             (0xff << 8)

/* Used by PM_WKUPAON_ADC_WKDEP */
#define DRA7XX_WKUPDEP_ADC_DSP1_SHIFT                           2
#define DRA7XX_WKUPDEP_ADC_DSP1_WIDTH                           0x1
#define DRA7XX_WKUPDEP_ADC_DSP1_MASK                            (1 << 2)

/* Used by PM_WKUPAON_ADC_WKDEP */
#define DRA7XX_WKUPDEP_ADC_DSP2_SHIFT                           5
#define DRA7XX_WKUPDEP_ADC_DSP2_WIDTH                           0x1
#define DRA7XX_WKUPDEP_ADC_DSP2_MASK                            (1 << 5)

/* Used by PM_WKUPAON_ADC_WKDEP */
#define DRA7XX_WKUPDEP_ADC_EVE1_SHIFT                           6
#define DRA7XX_WKUPDEP_ADC_EVE1_WIDTH                           0x1
#define DRA7XX_WKUPDEP_ADC_EVE1_MASK                            (1 << 6)

/* Used by PM_WKUPAON_ADC_WKDEP */
#define DRA7XX_WKUPDEP_ADC_EVE2_SHIFT                           7
#define DRA7XX_WKUPDEP_ADC_EVE2_WIDTH                           0x1
#define DRA7XX_WKUPDEP_ADC_EVE2_MASK                            (1 << 7)

/* Used by PM_WKUPAON_ADC_WKDEP */
#define DRA7XX_WKUPDEP_ADC_EVE3_SHIFT                           8
#define DRA7XX_WKUPDEP_ADC_EVE3_WIDTH                           0x1
#define DRA7XX_WKUPDEP_ADC_EVE3_MASK                            (1 << 8)

/* Used by PM_WKUPAON_ADC_WKDEP */
#define DRA7XX_WKUPDEP_ADC_EVE4_SHIFT                           9
#define DRA7XX_WKUPDEP_ADC_EVE4_WIDTH                           0x1
#define DRA7XX_WKUPDEP_ADC_EVE4_MASK                            (1 << 9)

/* Used by PM_WKUPAON_ADC_WKDEP */
#define DRA7XX_WKUPDEP_ADC_IPU1_SHIFT                           4
#define DRA7XX_WKUPDEP_ADC_IPU1_WIDTH                           0x1
#define DRA7XX_WKUPDEP_ADC_IPU1_MASK                            (1 << 4)

/* Used by PM_WKUPAON_ADC_WKDEP */
#define DRA7XX_WKUPDEP_ADC_IPU2_SHIFT                           1
#define DRA7XX_WKUPDEP_ADC_IPU2_WIDTH                           0x1
#define DRA7XX_WKUPDEP_ADC_IPU2_MASK                            (1 << 1)

/* Used by PM_WKUPAON_ADC_WKDEP */
#define DRA7XX_WKUPDEP_ADC_MPU_SHIFT                            0
#define DRA7XX_WKUPDEP_ADC_MPU_WIDTH                            0x1
#define DRA7XX_WKUPDEP_ADC_MPU_MASK                             (1 << 0)

/* Used by PM_WKUPAON_DCAN1_WKDEP */
#define DRA7XX_WKUPDEP_DCAN1_DSP1_SHIFT                         2
#define DRA7XX_WKUPDEP_DCAN1_DSP1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_DCAN1_DSP1_MASK                          (1 << 2)

/* Used by PM_WKUPAON_DCAN1_WKDEP */
#define DRA7XX_WKUPDEP_DCAN1_DSP2_SHIFT                         5
#define DRA7XX_WKUPDEP_DCAN1_DSP2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_DCAN1_DSP2_MASK                          (1 << 5)

/* Used by PM_WKUPAON_DCAN1_WKDEP */
#define DRA7XX_WKUPDEP_DCAN1_EVE1_SHIFT                         6
#define DRA7XX_WKUPDEP_DCAN1_EVE1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_DCAN1_EVE1_MASK                          (1 << 6)

/* Used by PM_WKUPAON_DCAN1_WKDEP */
#define DRA7XX_WKUPDEP_DCAN1_EVE2_SHIFT                         7
#define DRA7XX_WKUPDEP_DCAN1_EVE2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_DCAN1_EVE2_MASK                          (1 << 7)

/* Used by PM_WKUPAON_DCAN1_WKDEP */
#define DRA7XX_WKUPDEP_DCAN1_EVE3_SHIFT                         8
#define DRA7XX_WKUPDEP_DCAN1_EVE3_WIDTH                         0x1
#define DRA7XX_WKUPDEP_DCAN1_EVE3_MASK                          (1 << 8)

/* Used by PM_WKUPAON_DCAN1_WKDEP */
#define DRA7XX_WKUPDEP_DCAN1_EVE4_SHIFT                         9
#define DRA7XX_WKUPDEP_DCAN1_EVE4_WIDTH                         0x1
#define DRA7XX_WKUPDEP_DCAN1_EVE4_MASK                          (1 << 9)

/* Used by PM_WKUPAON_DCAN1_WKDEP */
#define DRA7XX_WKUPDEP_DCAN1_IPU1_SHIFT                         4
#define DRA7XX_WKUPDEP_DCAN1_IPU1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_DCAN1_IPU1_MASK                          (1 << 4)

/* Used by PM_WKUPAON_DCAN1_WKDEP */
#define DRA7XX_WKUPDEP_DCAN1_IPU2_SHIFT                         1
#define DRA7XX_WKUPDEP_DCAN1_IPU2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_DCAN1_IPU2_MASK                          (1 << 1)

/* Used by PM_WKUPAON_DCAN1_WKDEP */
#define DRA7XX_WKUPDEP_DCAN1_MPU_SHIFT                          0
#define DRA7XX_WKUPDEP_DCAN1_MPU_WIDTH                          0x1
#define DRA7XX_WKUPDEP_DCAN1_MPU_MASK                           (1 << 0)

/* Used by PM_WKUPAON_DCAN1_WKDEP */
#define DRA7XX_WKUPDEP_DCAN1_SDMA_SHIFT                         3
#define DRA7XX_WKUPDEP_DCAN1_SDMA_WIDTH                         0x1
#define DRA7XX_WKUPDEP_DCAN1_SDMA_MASK                          (1 << 3)

/* Used by PM_L4PER2_DCAN2_WKDEP */
#define DRA7XX_WKUPDEP_DCAN2_DSP1_SHIFT                         2
#define DRA7XX_WKUPDEP_DCAN2_DSP1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_DCAN2_DSP1_MASK                          (1 << 2)

/* Used by PM_L4PER2_DCAN2_WKDEP */
#define DRA7XX_WKUPDEP_DCAN2_DSP2_SHIFT                         5
#define DRA7XX_WKUPDEP_DCAN2_DSP2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_DCAN2_DSP2_MASK                          (1 << 5)

/* Used by PM_L4PER2_DCAN2_WKDEP */
#define DRA7XX_WKUPDEP_DCAN2_EVE1_SHIFT                         6
#define DRA7XX_WKUPDEP_DCAN2_EVE1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_DCAN2_EVE1_MASK                          (1 << 6)

/* Used by PM_L4PER2_DCAN2_WKDEP */
#define DRA7XX_WKUPDEP_DCAN2_EVE2_SHIFT                         7
#define DRA7XX_WKUPDEP_DCAN2_EVE2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_DCAN2_EVE2_MASK                          (1 << 7)

/* Used by PM_L4PER2_DCAN2_WKDEP */
#define DRA7XX_WKUPDEP_DCAN2_EVE3_SHIFT                         8
#define DRA7XX_WKUPDEP_DCAN2_EVE3_WIDTH                         0x1
#define DRA7XX_WKUPDEP_DCAN2_EVE3_MASK                          (1 << 8)

/* Used by PM_L4PER2_DCAN2_WKDEP */
#define DRA7XX_WKUPDEP_DCAN2_EVE4_SHIFT                         9
#define DRA7XX_WKUPDEP_DCAN2_EVE4_WIDTH                         0x1
#define DRA7XX_WKUPDEP_DCAN2_EVE4_MASK                          (1 << 9)

/* Used by PM_L4PER2_DCAN2_WKDEP */
#define DRA7XX_WKUPDEP_DCAN2_IPU1_SHIFT                         4
#define DRA7XX_WKUPDEP_DCAN2_IPU1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_DCAN2_IPU1_MASK                          (1 << 4)

/* Used by PM_L4PER2_DCAN2_WKDEP */
#define DRA7XX_WKUPDEP_DCAN2_IPU2_SHIFT                         1
#define DRA7XX_WKUPDEP_DCAN2_IPU2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_DCAN2_IPU2_MASK                          (1 << 1)

/* Used by PM_L4PER2_DCAN2_WKDEP */
#define DRA7XX_WKUPDEP_DCAN2_MPU_SHIFT                          0
#define DRA7XX_WKUPDEP_DCAN2_MPU_WIDTH                          0x1
#define DRA7XX_WKUPDEP_DCAN2_MPU_MASK                           (1 << 0)

/* Used by PM_L4PER2_DCAN2_WKDEP */
#define DRA7XX_WKUPDEP_DCAN2_SDMA_SHIFT                         3
#define DRA7XX_WKUPDEP_DCAN2_SDMA_WIDTH                         0x1
#define DRA7XX_WKUPDEP_DCAN2_SDMA_MASK                          (1 << 3)

/* Used by PM_DSS_DSS_WKDEP */
#define DRA7XX_WKUPDEP_DISPC_DSP1_SHIFT                         2
#define DRA7XX_WKUPDEP_DISPC_DSP1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_DISPC_DSP1_MASK                          (1 << 2)

/* Used by PM_DSS_DSS_WKDEP */
#define DRA7XX_WKUPDEP_DISPC_DSP2_SHIFT                         5
#define DRA7XX_WKUPDEP_DISPC_DSP2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_DISPC_DSP2_MASK                          (1 << 5)

/* Used by PM_DSS_DSS_WKDEP */
#define DRA7XX_WKUPDEP_DISPC_EVE1_SHIFT                         6
#define DRA7XX_WKUPDEP_DISPC_EVE1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_DISPC_EVE1_MASK                          (1 << 6)

/* Used by PM_DSS_DSS_WKDEP */
#define DRA7XX_WKUPDEP_DISPC_EVE2_SHIFT                         7
#define DRA7XX_WKUPDEP_DISPC_EVE2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_DISPC_EVE2_MASK                          (1 << 7)

/* Used by PM_DSS_DSS_WKDEP */
#define DRA7XX_WKUPDEP_DISPC_EVE3_SHIFT                         8
#define DRA7XX_WKUPDEP_DISPC_EVE3_WIDTH                         0x1
#define DRA7XX_WKUPDEP_DISPC_EVE3_MASK                          (1 << 8)

/* Used by PM_DSS_DSS_WKDEP */
#define DRA7XX_WKUPDEP_DISPC_EVE4_SHIFT                         9
#define DRA7XX_WKUPDEP_DISPC_EVE4_WIDTH                         0x1
#define DRA7XX_WKUPDEP_DISPC_EVE4_MASK                          (1 << 9)

/* Used by PM_DSS_DSS_WKDEP */
#define DRA7XX_WKUPDEP_DISPC_IPU1_SHIFT                         4
#define DRA7XX_WKUPDEP_DISPC_IPU1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_DISPC_IPU1_MASK                          (1 << 4)

/* Used by PM_DSS_DSS_WKDEP */
#define DRA7XX_WKUPDEP_DISPC_IPU2_SHIFT                         1
#define DRA7XX_WKUPDEP_DISPC_IPU2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_DISPC_IPU2_MASK                          (1 << 1)

/* Used by PM_DSS_DSS_WKDEP */
#define DRA7XX_WKUPDEP_DISPC_MPU_SHIFT                          0
#define DRA7XX_WKUPDEP_DISPC_MPU_WIDTH                          0x1
#define DRA7XX_WKUPDEP_DISPC_MPU_MASK                           (1 << 0)

/* Used by PM_DSS_DSS_WKDEP */
#define DRA7XX_WKUPDEP_DISPC_SDMA_SHIFT                         3
#define DRA7XX_WKUPDEP_DISPC_SDMA_WIDTH                         0x1
#define DRA7XX_WKUPDEP_DISPC_SDMA_MASK                          (1 << 3)

/* Used by PM_DSS_DSS_WKDEP */
#define DRA7XX_WKUPDEP_DSI1_A_DSP1_SHIFT                        12
#define DRA7XX_WKUPDEP_DSI1_A_DSP1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_DSI1_A_DSP1_MASK                         (1 << 12)

/* Used by PM_DSS_DSS_WKDEP */
#define DRA7XX_WKUPDEP_DSI1_A_DSP2_SHIFT                        15
#define DRA7XX_WKUPDEP_DSI1_A_DSP2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_DSI1_A_DSP2_MASK                         (1 << 15)

/* Used by PM_DSS_DSS_WKDEP */
#define DRA7XX_WKUPDEP_DSI1_A_EVE1_SHIFT                        16
#define DRA7XX_WKUPDEP_DSI1_A_EVE1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_DSI1_A_EVE1_MASK                         (1 << 16)

/* Used by PM_DSS_DSS_WKDEP */
#define DRA7XX_WKUPDEP_DSI1_A_EVE2_SHIFT                        17
#define DRA7XX_WKUPDEP_DSI1_A_EVE2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_DSI1_A_EVE2_MASK                         (1 << 17)

/* Used by PM_DSS_DSS_WKDEP */
#define DRA7XX_WKUPDEP_DSI1_A_EVE3_SHIFT                        18
#define DRA7XX_WKUPDEP_DSI1_A_EVE3_WIDTH                        0x1
#define DRA7XX_WKUPDEP_DSI1_A_EVE3_MASK                         (1 << 18)

/* Used by PM_DSS_DSS_WKDEP */
#define DRA7XX_WKUPDEP_DSI1_A_EVE4_SHIFT                        19
#define DRA7XX_WKUPDEP_DSI1_A_EVE4_WIDTH                        0x1
#define DRA7XX_WKUPDEP_DSI1_A_EVE4_MASK                         (1 << 19)

/* Used by PM_DSS_DSS_WKDEP */
#define DRA7XX_WKUPDEP_DSI1_A_IPU1_SHIFT                        14
#define DRA7XX_WKUPDEP_DSI1_A_IPU1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_DSI1_A_IPU1_MASK                         (1 << 14)

/* Used by PM_DSS_DSS_WKDEP */
#define DRA7XX_WKUPDEP_DSI1_A_IPU2_SHIFT                        11
#define DRA7XX_WKUPDEP_DSI1_A_IPU2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_DSI1_A_IPU2_MASK                         (1 << 11)

/* Used by PM_DSS_DSS_WKDEP */
#define DRA7XX_WKUPDEP_DSI1_A_MPU_SHIFT                         10
#define DRA7XX_WKUPDEP_DSI1_A_MPU_WIDTH                         0x1
#define DRA7XX_WKUPDEP_DSI1_A_MPU_MASK                          (1 << 10)

/* Used by PM_DSS_DSS_WKDEP */
#define DRA7XX_WKUPDEP_DSI1_A_SDMA_SHIFT                        13
#define DRA7XX_WKUPDEP_DSI1_A_SDMA_WIDTH                        0x1
#define DRA7XX_WKUPDEP_DSI1_A_SDMA_MASK                         (1 << 13)

/* Used by PM_DSS_DSS_WKDEP */
#define DRA7XX_WKUPDEP_DSI1_B_DSP1_SHIFT                        22
#define DRA7XX_WKUPDEP_DSI1_B_DSP1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_DSI1_B_DSP1_MASK                         (1 << 22)

/* Used by PM_DSS_DSS_WKDEP */
#define DRA7XX_WKUPDEP_DSI1_B_DSP2_SHIFT                        25
#define DRA7XX_WKUPDEP_DSI1_B_DSP2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_DSI1_B_DSP2_MASK                         (1 << 25)

/* Used by PM_DSS_DSS_WKDEP */
#define DRA7XX_WKUPDEP_DSI1_B_EVE1_SHIFT                        26
#define DRA7XX_WKUPDEP_DSI1_B_EVE1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_DSI1_B_EVE1_MASK                         (1 << 26)

/* Used by PM_DSS_DSS_WKDEP */
#define DRA7XX_WKUPDEP_DSI1_B_EVE2_SHIFT                        27
#define DRA7XX_WKUPDEP_DSI1_B_EVE2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_DSI1_B_EVE2_MASK                         (1 << 27)

/* Used by PM_DSS_DSS_WKDEP */
#define DRA7XX_WKUPDEP_DSI1_B_EVE3_SHIFT                        28
#define DRA7XX_WKUPDEP_DSI1_B_EVE3_WIDTH                        0x1
#define DRA7XX_WKUPDEP_DSI1_B_EVE3_MASK                         (1 << 28)

/* Used by PM_DSS_DSS_WKDEP */
#define DRA7XX_WKUPDEP_DSI1_B_EVE4_SHIFT                        29
#define DRA7XX_WKUPDEP_DSI1_B_EVE4_WIDTH                        0x1
#define DRA7XX_WKUPDEP_DSI1_B_EVE4_MASK                         (1 << 29)

/* Used by PM_DSS_DSS_WKDEP */
#define DRA7XX_WKUPDEP_DSI1_B_IPU1_SHIFT                        24
#define DRA7XX_WKUPDEP_DSI1_B_IPU1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_DSI1_B_IPU1_MASK                         (1 << 24)

/* Used by PM_DSS_DSS_WKDEP */
#define DRA7XX_WKUPDEP_DSI1_B_IPU2_SHIFT                        21
#define DRA7XX_WKUPDEP_DSI1_B_IPU2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_DSI1_B_IPU2_MASK                         (1 << 21)

/* Used by PM_DSS_DSS_WKDEP */
#define DRA7XX_WKUPDEP_DSI1_B_MPU_SHIFT                         20
#define DRA7XX_WKUPDEP_DSI1_B_MPU_WIDTH                         0x1
#define DRA7XX_WKUPDEP_DSI1_B_MPU_MASK                          (1 << 20)

/* Used by PM_DSS_DSS_WKDEP */
#define DRA7XX_WKUPDEP_DSI1_B_SDMA_SHIFT                        23
#define DRA7XX_WKUPDEP_DSI1_B_SDMA_WIDTH                        0x1
#define DRA7XX_WKUPDEP_DSI1_B_SDMA_MASK                         (1 << 23)

/* Used by PM_DSS_DSS2_WKDEP */
#define DRA7XX_WKUPDEP_DSI1_C_DSP1_SHIFT                        12
#define DRA7XX_WKUPDEP_DSI1_C_DSP1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_DSI1_C_DSP1_MASK                         (1 << 12)

/* Used by PM_DSS_DSS2_WKDEP */
#define DRA7XX_WKUPDEP_DSI1_C_DSP2_SHIFT                        15
#define DRA7XX_WKUPDEP_DSI1_C_DSP2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_DSI1_C_DSP2_MASK                         (1 << 15)

/* Used by PM_DSS_DSS2_WKDEP */
#define DRA7XX_WKUPDEP_DSI1_C_EVE1_SHIFT                        16
#define DRA7XX_WKUPDEP_DSI1_C_EVE1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_DSI1_C_EVE1_MASK                         (1 << 16)

/* Used by PM_DSS_DSS2_WKDEP */
#define DRA7XX_WKUPDEP_DSI1_C_EVE2_SHIFT                        17
#define DRA7XX_WKUPDEP_DSI1_C_EVE2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_DSI1_C_EVE2_MASK                         (1 << 17)

/* Used by PM_DSS_DSS2_WKDEP */
#define DRA7XX_WKUPDEP_DSI1_C_EVE3_SHIFT                        18
#define DRA7XX_WKUPDEP_DSI1_C_EVE3_WIDTH                        0x1
#define DRA7XX_WKUPDEP_DSI1_C_EVE3_MASK                         (1 << 18)

/* Used by PM_DSS_DSS2_WKDEP */
#define DRA7XX_WKUPDEP_DSI1_C_EVE4_SHIFT                        19
#define DRA7XX_WKUPDEP_DSI1_C_EVE4_WIDTH                        0x1
#define DRA7XX_WKUPDEP_DSI1_C_EVE4_MASK                         (1 << 19)

/* Used by PM_DSS_DSS2_WKDEP */
#define DRA7XX_WKUPDEP_DSI1_C_IPU1_SHIFT                        14
#define DRA7XX_WKUPDEP_DSI1_C_IPU1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_DSI1_C_IPU1_MASK                         (1 << 14)

/* Used by PM_DSS_DSS2_WKDEP */
#define DRA7XX_WKUPDEP_DSI1_C_IPU2_SHIFT                        11
#define DRA7XX_WKUPDEP_DSI1_C_IPU2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_DSI1_C_IPU2_MASK                         (1 << 11)

/* Used by PM_DSS_DSS2_WKDEP */
#define DRA7XX_WKUPDEP_DSI1_C_MPU_SHIFT                         10
#define DRA7XX_WKUPDEP_DSI1_C_MPU_WIDTH                         0x1
#define DRA7XX_WKUPDEP_DSI1_C_MPU_MASK                          (1 << 10)

/* Used by PM_DSS_DSS2_WKDEP */
#define DRA7XX_WKUPDEP_DSI1_C_SDMA_SHIFT                        13
#define DRA7XX_WKUPDEP_DSI1_C_SDMA_WIDTH                        0x1
#define DRA7XX_WKUPDEP_DSI1_C_SDMA_MASK                         (1 << 13)

/* Used by PM_EVE1_EVE1_WKDEP */
#define DRA7XX_WKUPDEP_EVE1_DSP1_SHIFT                          2
#define DRA7XX_WKUPDEP_EVE1_DSP1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_EVE1_DSP1_MASK                           (1 << 2)

/* Used by PM_EVE1_EVE1_WKDEP */
#define DRA7XX_WKUPDEP_EVE1_DSP2_SHIFT                          5
#define DRA7XX_WKUPDEP_EVE1_DSP2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_EVE1_DSP2_MASK                           (1 << 5)

/* Used by PM_EVE1_EVE1_WKDEP */
#define DRA7XX_WKUPDEP_EVE1_EVE2_SHIFT                          7
#define DRA7XX_WKUPDEP_EVE1_EVE2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_EVE1_EVE2_MASK                           (1 << 7)

/* Used by PM_EVE1_EVE1_WKDEP */
#define DRA7XX_WKUPDEP_EVE1_EVE3_SHIFT                          8
#define DRA7XX_WKUPDEP_EVE1_EVE3_WIDTH                          0x1
#define DRA7XX_WKUPDEP_EVE1_EVE3_MASK                           (1 << 8)

/* Used by PM_EVE1_EVE1_WKDEP */
#define DRA7XX_WKUPDEP_EVE1_EVE4_SHIFT                          9
#define DRA7XX_WKUPDEP_EVE1_EVE4_WIDTH                          0x1
#define DRA7XX_WKUPDEP_EVE1_EVE4_MASK                           (1 << 9)

/* Used by PM_EVE1_EVE1_WKDEP */
#define DRA7XX_WKUPDEP_EVE1_IPU1_SHIFT                          4
#define DRA7XX_WKUPDEP_EVE1_IPU1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_EVE1_IPU1_MASK                           (1 << 4)

/* Used by PM_EVE1_EVE1_WKDEP */
#define DRA7XX_WKUPDEP_EVE1_IPU2_SHIFT                          1
#define DRA7XX_WKUPDEP_EVE1_IPU2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_EVE1_IPU2_MASK                           (1 << 1)

/* Used by PM_EVE1_EVE1_WKDEP */
#define DRA7XX_WKUPDEP_EVE1_MPU_SHIFT                           0
#define DRA7XX_WKUPDEP_EVE1_MPU_WIDTH                           0x1
#define DRA7XX_WKUPDEP_EVE1_MPU_MASK                            (1 << 0)

/* Used by PM_EVE1_EVE1_WKDEP */
#define DRA7XX_WKUPDEP_EVE1_SDMA_SHIFT                          3
#define DRA7XX_WKUPDEP_EVE1_SDMA_WIDTH                          0x1
#define DRA7XX_WKUPDEP_EVE1_SDMA_MASK                           (1 << 3)

/* Used by PM_EVE2_EVE2_WKDEP */
#define DRA7XX_WKUPDEP_EVE2_DSP1_SHIFT                          2
#define DRA7XX_WKUPDEP_EVE2_DSP1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_EVE2_DSP1_MASK                           (1 << 2)

/* Used by PM_EVE2_EVE2_WKDEP */
#define DRA7XX_WKUPDEP_EVE2_DSP2_SHIFT                          5
#define DRA7XX_WKUPDEP_EVE2_DSP2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_EVE2_DSP2_MASK                           (1 << 5)

/* Used by PM_EVE2_EVE2_WKDEP */
#define DRA7XX_WKUPDEP_EVE2_EVE1_SHIFT                          6
#define DRA7XX_WKUPDEP_EVE2_EVE1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_EVE2_EVE1_MASK                           (1 << 6)

/* Used by PM_EVE2_EVE2_WKDEP */
#define DRA7XX_WKUPDEP_EVE2_EVE3_SHIFT                          8
#define DRA7XX_WKUPDEP_EVE2_EVE3_WIDTH                          0x1
#define DRA7XX_WKUPDEP_EVE2_EVE3_MASK                           (1 << 8)

/* Used by PM_EVE2_EVE2_WKDEP */
#define DRA7XX_WKUPDEP_EVE2_EVE4_SHIFT                          9
#define DRA7XX_WKUPDEP_EVE2_EVE4_WIDTH                          0x1
#define DRA7XX_WKUPDEP_EVE2_EVE4_MASK                           (1 << 9)

/* Used by PM_EVE2_EVE2_WKDEP */
#define DRA7XX_WKUPDEP_EVE2_IPU1_SHIFT                          4
#define DRA7XX_WKUPDEP_EVE2_IPU1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_EVE2_IPU1_MASK                           (1 << 4)

/* Used by PM_EVE2_EVE2_WKDEP */
#define DRA7XX_WKUPDEP_EVE2_IPU2_SHIFT                          1
#define DRA7XX_WKUPDEP_EVE2_IPU2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_EVE2_IPU2_MASK                           (1 << 1)

/* Used by PM_EVE2_EVE2_WKDEP */
#define DRA7XX_WKUPDEP_EVE2_MPU_SHIFT                           0
#define DRA7XX_WKUPDEP_EVE2_MPU_WIDTH                           0x1
#define DRA7XX_WKUPDEP_EVE2_MPU_MASK                            (1 << 0)

/* Used by PM_EVE2_EVE2_WKDEP */
#define DRA7XX_WKUPDEP_EVE2_SDMA_SHIFT                          3
#define DRA7XX_WKUPDEP_EVE2_SDMA_WIDTH                          0x1
#define DRA7XX_WKUPDEP_EVE2_SDMA_MASK                           (1 << 3)

/* Used by PM_EVE3_EVE3_WKDEP */
#define DRA7XX_WKUPDEP_EVE3_DSP1_SHIFT                          2
#define DRA7XX_WKUPDEP_EVE3_DSP1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_EVE3_DSP1_MASK                           (1 << 2)

/* Used by PM_EVE3_EVE3_WKDEP */
#define DRA7XX_WKUPDEP_EVE3_DSP2_SHIFT                          5
#define DRA7XX_WKUPDEP_EVE3_DSP2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_EVE3_DSP2_MASK                           (1 << 5)

/* Used by PM_EVE3_EVE3_WKDEP */
#define DRA7XX_WKUPDEP_EVE3_EVE1_SHIFT                          6
#define DRA7XX_WKUPDEP_EVE3_EVE1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_EVE3_EVE1_MASK                           (1 << 6)

/* Used by PM_EVE3_EVE3_WKDEP */
#define DRA7XX_WKUPDEP_EVE3_EVE2_SHIFT                          7
#define DRA7XX_WKUPDEP_EVE3_EVE2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_EVE3_EVE2_MASK                           (1 << 7)

/* Used by PM_EVE3_EVE3_WKDEP */
#define DRA7XX_WKUPDEP_EVE3_EVE4_SHIFT                          9
#define DRA7XX_WKUPDEP_EVE3_EVE4_WIDTH                          0x1
#define DRA7XX_WKUPDEP_EVE3_EVE4_MASK                           (1 << 9)

/* Used by PM_EVE3_EVE3_WKDEP */
#define DRA7XX_WKUPDEP_EVE3_IPU1_SHIFT                          4
#define DRA7XX_WKUPDEP_EVE3_IPU1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_EVE3_IPU1_MASK                           (1 << 4)

/* Used by PM_EVE3_EVE3_WKDEP */
#define DRA7XX_WKUPDEP_EVE3_IPU2_SHIFT                          1
#define DRA7XX_WKUPDEP_EVE3_IPU2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_EVE3_IPU2_MASK                           (1 << 1)

/* Used by PM_EVE3_EVE3_WKDEP */
#define DRA7XX_WKUPDEP_EVE3_MPU_SHIFT                           0
#define DRA7XX_WKUPDEP_EVE3_MPU_WIDTH                           0x1
#define DRA7XX_WKUPDEP_EVE3_MPU_MASK                            (1 << 0)

/* Used by PM_EVE3_EVE3_WKDEP */
#define DRA7XX_WKUPDEP_EVE3_SDMA_SHIFT                          3
#define DRA7XX_WKUPDEP_EVE3_SDMA_WIDTH                          0x1
#define DRA7XX_WKUPDEP_EVE3_SDMA_MASK                           (1 << 3)

/* Used by PM_EVE4_EVE4_WKDEP */
#define DRA7XX_WKUPDEP_EVE4_DSP1_SHIFT                          2
#define DRA7XX_WKUPDEP_EVE4_DSP1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_EVE4_DSP1_MASK                           (1 << 2)

/* Used by PM_EVE4_EVE4_WKDEP */
#define DRA7XX_WKUPDEP_EVE4_DSP2_SHIFT                          5
#define DRA7XX_WKUPDEP_EVE4_DSP2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_EVE4_DSP2_MASK                           (1 << 5)

/* Used by PM_EVE4_EVE4_WKDEP */
#define DRA7XX_WKUPDEP_EVE4_EVE1_SHIFT                          6
#define DRA7XX_WKUPDEP_EVE4_EVE1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_EVE4_EVE1_MASK                           (1 << 6)

/* Used by PM_EVE4_EVE4_WKDEP */
#define DRA7XX_WKUPDEP_EVE4_EVE2_SHIFT                          7
#define DRA7XX_WKUPDEP_EVE4_EVE2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_EVE4_EVE2_MASK                           (1 << 7)

/* Used by PM_EVE4_EVE4_WKDEP */
#define DRA7XX_WKUPDEP_EVE4_EVE3_SHIFT                          8
#define DRA7XX_WKUPDEP_EVE4_EVE3_WIDTH                          0x1
#define DRA7XX_WKUPDEP_EVE4_EVE3_MASK                           (1 << 8)

/* Used by PM_EVE4_EVE4_WKDEP */
#define DRA7XX_WKUPDEP_EVE4_IPU1_SHIFT                          4
#define DRA7XX_WKUPDEP_EVE4_IPU1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_EVE4_IPU1_MASK                           (1 << 4)

/* Used by PM_EVE4_EVE4_WKDEP */
#define DRA7XX_WKUPDEP_EVE4_IPU2_SHIFT                          1
#define DRA7XX_WKUPDEP_EVE4_IPU2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_EVE4_IPU2_MASK                           (1 << 1)

/* Used by PM_EVE4_EVE4_WKDEP */
#define DRA7XX_WKUPDEP_EVE4_MPU_SHIFT                           0
#define DRA7XX_WKUPDEP_EVE4_MPU_WIDTH                           0x1
#define DRA7XX_WKUPDEP_EVE4_MPU_MASK                            (1 << 0)

/* Used by PM_EVE4_EVE4_WKDEP */
#define DRA7XX_WKUPDEP_EVE4_SDMA_SHIFT                          3
#define DRA7XX_WKUPDEP_EVE4_SDMA_WIDTH                          0x1
#define DRA7XX_WKUPDEP_EVE4_SDMA_MASK                           (1 << 3)

/* Used by PM_WKUPAON_GPIO1_WKDEP */
#define DRA7XX_WKUPDEP_GPIO1_IRQ1_DSP1_SHIFT                    2
#define DRA7XX_WKUPDEP_GPIO1_IRQ1_DSP1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO1_IRQ1_DSP1_MASK                     (1 << 2)

/* Used by PM_WKUPAON_GPIO1_WKDEP */
#define DRA7XX_WKUPDEP_GPIO1_IRQ1_DSP2_SHIFT                    5
#define DRA7XX_WKUPDEP_GPIO1_IRQ1_DSP2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO1_IRQ1_DSP2_MASK                     (1 << 5)

/* Used by PM_WKUPAON_GPIO1_WKDEP */
#define DRA7XX_WKUPDEP_GPIO1_IRQ1_EVE1_SHIFT                    6
#define DRA7XX_WKUPDEP_GPIO1_IRQ1_EVE1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO1_IRQ1_EVE1_MASK                     (1 << 6)

/* Used by PM_WKUPAON_GPIO1_WKDEP */
#define DRA7XX_WKUPDEP_GPIO1_IRQ1_EVE2_SHIFT                    7
#define DRA7XX_WKUPDEP_GPIO1_IRQ1_EVE2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO1_IRQ1_EVE2_MASK                     (1 << 7)

/* Used by PM_WKUPAON_GPIO1_WKDEP */
#define DRA7XX_WKUPDEP_GPIO1_IRQ1_EVE3_SHIFT                    8
#define DRA7XX_WKUPDEP_GPIO1_IRQ1_EVE3_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO1_IRQ1_EVE3_MASK                     (1 << 8)

/* Used by PM_WKUPAON_GPIO1_WKDEP */
#define DRA7XX_WKUPDEP_GPIO1_IRQ1_EVE4_SHIFT                    9
#define DRA7XX_WKUPDEP_GPIO1_IRQ1_EVE4_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO1_IRQ1_EVE4_MASK                     (1 << 9)

/* Used by PM_WKUPAON_GPIO1_WKDEP */
#define DRA7XX_WKUPDEP_GPIO1_IRQ1_IPU1_SHIFT                    4
#define DRA7XX_WKUPDEP_GPIO1_IRQ1_IPU1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO1_IRQ1_IPU1_MASK                     (1 << 4)

/* Used by PM_WKUPAON_GPIO1_WKDEP */
#define DRA7XX_WKUPDEP_GPIO1_IRQ1_IPU2_SHIFT                    1
#define DRA7XX_WKUPDEP_GPIO1_IRQ1_IPU2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO1_IRQ1_IPU2_MASK                     (1 << 1)

/* Used by PM_WKUPAON_GPIO1_WKDEP */
#define DRA7XX_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT                     0
#define DRA7XX_WKUPDEP_GPIO1_IRQ1_MPU_WIDTH                     0x1
#define DRA7XX_WKUPDEP_GPIO1_IRQ1_MPU_MASK                      (1 << 0)

/* Used by PM_WKUPAON_GPIO1_WKDEP */
#define DRA7XX_WKUPDEP_GPIO1_IRQ2_DSP1_SHIFT                    12
#define DRA7XX_WKUPDEP_GPIO1_IRQ2_DSP1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO1_IRQ2_DSP1_MASK                     (1 << 12)

/* Used by PM_WKUPAON_GPIO1_WKDEP */
#define DRA7XX_WKUPDEP_GPIO1_IRQ2_DSP2_SHIFT                    15
#define DRA7XX_WKUPDEP_GPIO1_IRQ2_DSP2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO1_IRQ2_DSP2_MASK                     (1 << 15)

/* Used by PM_WKUPAON_GPIO1_WKDEP */
#define DRA7XX_WKUPDEP_GPIO1_IRQ2_EVE1_SHIFT                    16
#define DRA7XX_WKUPDEP_GPIO1_IRQ2_EVE1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO1_IRQ2_EVE1_MASK                     (1 << 16)

/* Used by PM_WKUPAON_GPIO1_WKDEP */
#define DRA7XX_WKUPDEP_GPIO1_IRQ2_EVE2_SHIFT                    17
#define DRA7XX_WKUPDEP_GPIO1_IRQ2_EVE2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO1_IRQ2_EVE2_MASK                     (1 << 17)

/* Used by PM_WKUPAON_GPIO1_WKDEP */
#define DRA7XX_WKUPDEP_GPIO1_IRQ2_EVE3_SHIFT                    18
#define DRA7XX_WKUPDEP_GPIO1_IRQ2_EVE3_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO1_IRQ2_EVE3_MASK                     (1 << 18)

/* Used by PM_WKUPAON_GPIO1_WKDEP */
#define DRA7XX_WKUPDEP_GPIO1_IRQ2_EVE4_SHIFT                    19
#define DRA7XX_WKUPDEP_GPIO1_IRQ2_EVE4_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO1_IRQ2_EVE4_MASK                     (1 << 19)

/* Used by PM_WKUPAON_GPIO1_WKDEP */
#define DRA7XX_WKUPDEP_GPIO1_IRQ2_IPU1_SHIFT                    14
#define DRA7XX_WKUPDEP_GPIO1_IRQ2_IPU1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO1_IRQ2_IPU1_MASK                     (1 << 14)

/* Used by PM_WKUPAON_GPIO1_WKDEP */
#define DRA7XX_WKUPDEP_GPIO1_IRQ2_IPU2_SHIFT                    11
#define DRA7XX_WKUPDEP_GPIO1_IRQ2_IPU2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO1_IRQ2_IPU2_MASK                     (1 << 11)

/* Used by PM_WKUPAON_GPIO1_WKDEP */
#define DRA7XX_WKUPDEP_GPIO1_IRQ2_MPU_SHIFT                     10
#define DRA7XX_WKUPDEP_GPIO1_IRQ2_MPU_WIDTH                     0x1
#define DRA7XX_WKUPDEP_GPIO1_IRQ2_MPU_MASK                      (1 << 10)

/* Used by PM_L4PER_GPIO2_WKDEP */
#define DRA7XX_WKUPDEP_GPIO2_IRQ1_DSP1_SHIFT                    2
#define DRA7XX_WKUPDEP_GPIO2_IRQ1_DSP1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO2_IRQ1_DSP1_MASK                     (1 << 2)

/* Used by PM_L4PER_GPIO2_WKDEP */
#define DRA7XX_WKUPDEP_GPIO2_IRQ1_DSP2_SHIFT                    5
#define DRA7XX_WKUPDEP_GPIO2_IRQ1_DSP2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO2_IRQ1_DSP2_MASK                     (1 << 5)

/* Used by PM_L4PER_GPIO2_WKDEP */
#define DRA7XX_WKUPDEP_GPIO2_IRQ1_EVE1_SHIFT                    6
#define DRA7XX_WKUPDEP_GPIO2_IRQ1_EVE1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO2_IRQ1_EVE1_MASK                     (1 << 6)

/* Used by PM_L4PER_GPIO2_WKDEP */
#define DRA7XX_WKUPDEP_GPIO2_IRQ1_EVE2_SHIFT                    7
#define DRA7XX_WKUPDEP_GPIO2_IRQ1_EVE2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO2_IRQ1_EVE2_MASK                     (1 << 7)

/* Used by PM_L4PER_GPIO2_WKDEP */
#define DRA7XX_WKUPDEP_GPIO2_IRQ1_EVE3_SHIFT                    8
#define DRA7XX_WKUPDEP_GPIO2_IRQ1_EVE3_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO2_IRQ1_EVE3_MASK                     (1 << 8)

/* Used by PM_L4PER_GPIO2_WKDEP */
#define DRA7XX_WKUPDEP_GPIO2_IRQ1_EVE4_SHIFT                    9
#define DRA7XX_WKUPDEP_GPIO2_IRQ1_EVE4_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO2_IRQ1_EVE4_MASK                     (1 << 9)

/* Used by PM_L4PER_GPIO2_WKDEP */
#define DRA7XX_WKUPDEP_GPIO2_IRQ1_IPU1_SHIFT                    4
#define DRA7XX_WKUPDEP_GPIO2_IRQ1_IPU1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO2_IRQ1_IPU1_MASK                     (1 << 4)

/* Used by PM_L4PER_GPIO2_WKDEP */
#define DRA7XX_WKUPDEP_GPIO2_IRQ1_IPU2_SHIFT                    1
#define DRA7XX_WKUPDEP_GPIO2_IRQ1_IPU2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO2_IRQ1_IPU2_MASK                     (1 << 1)

/* Used by PM_L4PER_GPIO2_WKDEP */
#define DRA7XX_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT                     0
#define DRA7XX_WKUPDEP_GPIO2_IRQ1_MPU_WIDTH                     0x1
#define DRA7XX_WKUPDEP_GPIO2_IRQ1_MPU_MASK                      (1 << 0)

/* Used by PM_L4PER_GPIO2_WKDEP */
#define DRA7XX_WKUPDEP_GPIO2_IRQ2_DSP1_SHIFT                    12
#define DRA7XX_WKUPDEP_GPIO2_IRQ2_DSP1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO2_IRQ2_DSP1_MASK                     (1 << 12)

/* Used by PM_L4PER_GPIO2_WKDEP */
#define DRA7XX_WKUPDEP_GPIO2_IRQ2_DSP2_SHIFT                    15
#define DRA7XX_WKUPDEP_GPIO2_IRQ2_DSP2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO2_IRQ2_DSP2_MASK                     (1 << 15)

/* Used by PM_L4PER_GPIO2_WKDEP */
#define DRA7XX_WKUPDEP_GPIO2_IRQ2_EVE1_SHIFT                    16
#define DRA7XX_WKUPDEP_GPIO2_IRQ2_EVE1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO2_IRQ2_EVE1_MASK                     (1 << 16)

/* Used by PM_L4PER_GPIO2_WKDEP */
#define DRA7XX_WKUPDEP_GPIO2_IRQ2_EVE2_SHIFT                    17
#define DRA7XX_WKUPDEP_GPIO2_IRQ2_EVE2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO2_IRQ2_EVE2_MASK                     (1 << 17)

/* Used by PM_L4PER_GPIO2_WKDEP */
#define DRA7XX_WKUPDEP_GPIO2_IRQ2_EVE3_SHIFT                    18
#define DRA7XX_WKUPDEP_GPIO2_IRQ2_EVE3_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO2_IRQ2_EVE3_MASK                     (1 << 18)

/* Used by PM_L4PER_GPIO2_WKDEP */
#define DRA7XX_WKUPDEP_GPIO2_IRQ2_EVE4_SHIFT                    19
#define DRA7XX_WKUPDEP_GPIO2_IRQ2_EVE4_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO2_IRQ2_EVE4_MASK                     (1 << 19)

/* Used by PM_L4PER_GPIO2_WKDEP */
#define DRA7XX_WKUPDEP_GPIO2_IRQ2_IPU1_SHIFT                    14
#define DRA7XX_WKUPDEP_GPIO2_IRQ2_IPU1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO2_IRQ2_IPU1_MASK                     (1 << 14)

/* Used by PM_L4PER_GPIO2_WKDEP */
#define DRA7XX_WKUPDEP_GPIO2_IRQ2_IPU2_SHIFT                    11
#define DRA7XX_WKUPDEP_GPIO2_IRQ2_IPU2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO2_IRQ2_IPU2_MASK                     (1 << 11)

/* Used by PM_L4PER_GPIO2_WKDEP */
#define DRA7XX_WKUPDEP_GPIO2_IRQ2_MPU_SHIFT                     10
#define DRA7XX_WKUPDEP_GPIO2_IRQ2_MPU_WIDTH                     0x1
#define DRA7XX_WKUPDEP_GPIO2_IRQ2_MPU_MASK                      (1 << 10)

/* Used by PM_L4PER_GPIO3_WKDEP */
#define DRA7XX_WKUPDEP_GPIO3_IRQ1_DSP1_SHIFT                    2
#define DRA7XX_WKUPDEP_GPIO3_IRQ1_DSP1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO3_IRQ1_DSP1_MASK                     (1 << 2)

/* Used by PM_L4PER_GPIO3_WKDEP */
#define DRA7XX_WKUPDEP_GPIO3_IRQ1_DSP2_SHIFT                    5
#define DRA7XX_WKUPDEP_GPIO3_IRQ1_DSP2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO3_IRQ1_DSP2_MASK                     (1 << 5)

/* Used by PM_L4PER_GPIO3_WKDEP */
#define DRA7XX_WKUPDEP_GPIO3_IRQ1_EVE1_SHIFT                    6
#define DRA7XX_WKUPDEP_GPIO3_IRQ1_EVE1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO3_IRQ1_EVE1_MASK                     (1 << 6)

/* Used by PM_L4PER_GPIO3_WKDEP */
#define DRA7XX_WKUPDEP_GPIO3_IRQ1_EVE2_SHIFT                    7
#define DRA7XX_WKUPDEP_GPIO3_IRQ1_EVE2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO3_IRQ1_EVE2_MASK                     (1 << 7)

/* Used by PM_L4PER_GPIO3_WKDEP */
#define DRA7XX_WKUPDEP_GPIO3_IRQ1_EVE3_SHIFT                    8
#define DRA7XX_WKUPDEP_GPIO3_IRQ1_EVE3_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO3_IRQ1_EVE3_MASK                     (1 << 8)

/* Used by PM_L4PER_GPIO3_WKDEP */
#define DRA7XX_WKUPDEP_GPIO3_IRQ1_EVE4_SHIFT                    9
#define DRA7XX_WKUPDEP_GPIO3_IRQ1_EVE4_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO3_IRQ1_EVE4_MASK                     (1 << 9)

/* Used by PM_L4PER_GPIO3_WKDEP */
#define DRA7XX_WKUPDEP_GPIO3_IRQ1_IPU1_SHIFT                    4
#define DRA7XX_WKUPDEP_GPIO3_IRQ1_IPU1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO3_IRQ1_IPU1_MASK                     (1 << 4)

/* Used by PM_L4PER_GPIO3_WKDEP */
#define DRA7XX_WKUPDEP_GPIO3_IRQ1_IPU2_SHIFT                    1
#define DRA7XX_WKUPDEP_GPIO3_IRQ1_IPU2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO3_IRQ1_IPU2_MASK                     (1 << 1)

/* Used by PM_L4PER_GPIO3_WKDEP */
#define DRA7XX_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT                     0
#define DRA7XX_WKUPDEP_GPIO3_IRQ1_MPU_WIDTH                     0x1
#define DRA7XX_WKUPDEP_GPIO3_IRQ1_MPU_MASK                      (1 << 0)

/* Used by PM_L4PER_GPIO3_WKDEP */
#define DRA7XX_WKUPDEP_GPIO3_IRQ2_DSP1_SHIFT                    12
#define DRA7XX_WKUPDEP_GPIO3_IRQ2_DSP1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO3_IRQ2_DSP1_MASK                     (1 << 12)

/* Used by PM_L4PER_GPIO3_WKDEP */
#define DRA7XX_WKUPDEP_GPIO3_IRQ2_DSP2_SHIFT                    15
#define DRA7XX_WKUPDEP_GPIO3_IRQ2_DSP2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO3_IRQ2_DSP2_MASK                     (1 << 15)

/* Used by PM_L4PER_GPIO3_WKDEP */
#define DRA7XX_WKUPDEP_GPIO3_IRQ2_EVE1_SHIFT                    16
#define DRA7XX_WKUPDEP_GPIO3_IRQ2_EVE1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO3_IRQ2_EVE1_MASK                     (1 << 16)

/* Used by PM_L4PER_GPIO3_WKDEP */
#define DRA7XX_WKUPDEP_GPIO3_IRQ2_EVE2_SHIFT                    17
#define DRA7XX_WKUPDEP_GPIO3_IRQ2_EVE2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO3_IRQ2_EVE2_MASK                     (1 << 17)

/* Used by PM_L4PER_GPIO3_WKDEP */
#define DRA7XX_WKUPDEP_GPIO3_IRQ2_EVE3_SHIFT                    18
#define DRA7XX_WKUPDEP_GPIO3_IRQ2_EVE3_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO3_IRQ2_EVE3_MASK                     (1 << 18)

/* Used by PM_L4PER_GPIO3_WKDEP */
#define DRA7XX_WKUPDEP_GPIO3_IRQ2_EVE4_SHIFT                    19
#define DRA7XX_WKUPDEP_GPIO3_IRQ2_EVE4_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO3_IRQ2_EVE4_MASK                     (1 << 19)

/* Used by PM_L4PER_GPIO3_WKDEP */
#define DRA7XX_WKUPDEP_GPIO3_IRQ2_IPU1_SHIFT                    14
#define DRA7XX_WKUPDEP_GPIO3_IRQ2_IPU1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO3_IRQ2_IPU1_MASK                     (1 << 14)

/* Used by PM_L4PER_GPIO3_WKDEP */
#define DRA7XX_WKUPDEP_GPIO3_IRQ2_IPU2_SHIFT                    11
#define DRA7XX_WKUPDEP_GPIO3_IRQ2_IPU2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO3_IRQ2_IPU2_MASK                     (1 << 11)

/* Used by PM_L4PER_GPIO3_WKDEP */
#define DRA7XX_WKUPDEP_GPIO3_IRQ2_MPU_SHIFT                     10
#define DRA7XX_WKUPDEP_GPIO3_IRQ2_MPU_WIDTH                     0x1
#define DRA7XX_WKUPDEP_GPIO3_IRQ2_MPU_MASK                      (1 << 10)

/* Used by PM_L4PER_GPIO4_WKDEP */
#define DRA7XX_WKUPDEP_GPIO4_IRQ1_DSP1_SHIFT                    2
#define DRA7XX_WKUPDEP_GPIO4_IRQ1_DSP1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO4_IRQ1_DSP1_MASK                     (1 << 2)

/* Used by PM_L4PER_GPIO4_WKDEP */
#define DRA7XX_WKUPDEP_GPIO4_IRQ1_DSP2_SHIFT                    5
#define DRA7XX_WKUPDEP_GPIO4_IRQ1_DSP2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO4_IRQ1_DSP2_MASK                     (1 << 5)

/* Used by PM_L4PER_GPIO4_WKDEP */
#define DRA7XX_WKUPDEP_GPIO4_IRQ1_EVE1_SHIFT                    6
#define DRA7XX_WKUPDEP_GPIO4_IRQ1_EVE1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO4_IRQ1_EVE1_MASK                     (1 << 6)

/* Used by PM_L4PER_GPIO4_WKDEP */
#define DRA7XX_WKUPDEP_GPIO4_IRQ1_EVE2_SHIFT                    7
#define DRA7XX_WKUPDEP_GPIO4_IRQ1_EVE2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO4_IRQ1_EVE2_MASK                     (1 << 7)

/* Used by PM_L4PER_GPIO4_WKDEP */
#define DRA7XX_WKUPDEP_GPIO4_IRQ1_EVE3_SHIFT                    8
#define DRA7XX_WKUPDEP_GPIO4_IRQ1_EVE3_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO4_IRQ1_EVE3_MASK                     (1 << 8)

/* Used by PM_L4PER_GPIO4_WKDEP */
#define DRA7XX_WKUPDEP_GPIO4_IRQ1_EVE4_SHIFT                    9
#define DRA7XX_WKUPDEP_GPIO4_IRQ1_EVE4_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO4_IRQ1_EVE4_MASK                     (1 << 9)

/* Used by PM_L4PER_GPIO4_WKDEP */
#define DRA7XX_WKUPDEP_GPIO4_IRQ1_IPU1_SHIFT                    4
#define DRA7XX_WKUPDEP_GPIO4_IRQ1_IPU1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO4_IRQ1_IPU1_MASK                     (1 << 4)

/* Used by PM_L4PER_GPIO4_WKDEP */
#define DRA7XX_WKUPDEP_GPIO4_IRQ1_IPU2_SHIFT                    1
#define DRA7XX_WKUPDEP_GPIO4_IRQ1_IPU2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO4_IRQ1_IPU2_MASK                     (1 << 1)

/* Used by PM_L4PER_GPIO4_WKDEP */
#define DRA7XX_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT                     0
#define DRA7XX_WKUPDEP_GPIO4_IRQ1_MPU_WIDTH                     0x1
#define DRA7XX_WKUPDEP_GPIO4_IRQ1_MPU_MASK                      (1 << 0)

/* Used by PM_L4PER_GPIO4_WKDEP */
#define DRA7XX_WKUPDEP_GPIO4_IRQ2_DSP1_SHIFT                    12
#define DRA7XX_WKUPDEP_GPIO4_IRQ2_DSP1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO4_IRQ2_DSP1_MASK                     (1 << 12)

/* Used by PM_L4PER_GPIO4_WKDEP */
#define DRA7XX_WKUPDEP_GPIO4_IRQ2_DSP2_SHIFT                    15
#define DRA7XX_WKUPDEP_GPIO4_IRQ2_DSP2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO4_IRQ2_DSP2_MASK                     (1 << 15)

/* Used by PM_L4PER_GPIO4_WKDEP */
#define DRA7XX_WKUPDEP_GPIO4_IRQ2_EVE1_SHIFT                    16
#define DRA7XX_WKUPDEP_GPIO4_IRQ2_EVE1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO4_IRQ2_EVE1_MASK                     (1 << 16)

/* Used by PM_L4PER_GPIO4_WKDEP */
#define DRA7XX_WKUPDEP_GPIO4_IRQ2_EVE2_SHIFT                    17
#define DRA7XX_WKUPDEP_GPIO4_IRQ2_EVE2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO4_IRQ2_EVE2_MASK                     (1 << 17)

/* Used by PM_L4PER_GPIO4_WKDEP */
#define DRA7XX_WKUPDEP_GPIO4_IRQ2_EVE3_SHIFT                    18
#define DRA7XX_WKUPDEP_GPIO4_IRQ2_EVE3_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO4_IRQ2_EVE3_MASK                     (1 << 18)

/* Used by PM_L4PER_GPIO4_WKDEP */
#define DRA7XX_WKUPDEP_GPIO4_IRQ2_EVE4_SHIFT                    19
#define DRA7XX_WKUPDEP_GPIO4_IRQ2_EVE4_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO4_IRQ2_EVE4_MASK                     (1 << 19)

/* Used by PM_L4PER_GPIO4_WKDEP */
#define DRA7XX_WKUPDEP_GPIO4_IRQ2_IPU1_SHIFT                    14
#define DRA7XX_WKUPDEP_GPIO4_IRQ2_IPU1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO4_IRQ2_IPU1_MASK                     (1 << 14)

/* Used by PM_L4PER_GPIO4_WKDEP */
#define DRA7XX_WKUPDEP_GPIO4_IRQ2_IPU2_SHIFT                    11
#define DRA7XX_WKUPDEP_GPIO4_IRQ2_IPU2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO4_IRQ2_IPU2_MASK                     (1 << 11)

/* Used by PM_L4PER_GPIO4_WKDEP */
#define DRA7XX_WKUPDEP_GPIO4_IRQ2_MPU_SHIFT                     10
#define DRA7XX_WKUPDEP_GPIO4_IRQ2_MPU_WIDTH                     0x1
#define DRA7XX_WKUPDEP_GPIO4_IRQ2_MPU_MASK                      (1 << 10)

/* Used by PM_L4PER_GPIO5_WKDEP */
#define DRA7XX_WKUPDEP_GPIO5_IRQ1_DSP1_SHIFT                    2
#define DRA7XX_WKUPDEP_GPIO5_IRQ1_DSP1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO5_IRQ1_DSP1_MASK                     (1 << 2)

/* Used by PM_L4PER_GPIO5_WKDEP */
#define DRA7XX_WKUPDEP_GPIO5_IRQ1_DSP2_SHIFT                    5
#define DRA7XX_WKUPDEP_GPIO5_IRQ1_DSP2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO5_IRQ1_DSP2_MASK                     (1 << 5)

/* Used by PM_L4PER_GPIO5_WKDEP */
#define DRA7XX_WKUPDEP_GPIO5_IRQ1_EVE1_SHIFT                    6
#define DRA7XX_WKUPDEP_GPIO5_IRQ1_EVE1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO5_IRQ1_EVE1_MASK                     (1 << 6)

/* Used by PM_L4PER_GPIO5_WKDEP */
#define DRA7XX_WKUPDEP_GPIO5_IRQ1_EVE2_SHIFT                    7
#define DRA7XX_WKUPDEP_GPIO5_IRQ1_EVE2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO5_IRQ1_EVE2_MASK                     (1 << 7)

/* Used by PM_L4PER_GPIO5_WKDEP */
#define DRA7XX_WKUPDEP_GPIO5_IRQ1_EVE3_SHIFT                    8
#define DRA7XX_WKUPDEP_GPIO5_IRQ1_EVE3_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO5_IRQ1_EVE3_MASK                     (1 << 8)

/* Used by PM_L4PER_GPIO5_WKDEP */
#define DRA7XX_WKUPDEP_GPIO5_IRQ1_EVE4_SHIFT                    9
#define DRA7XX_WKUPDEP_GPIO5_IRQ1_EVE4_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO5_IRQ1_EVE4_MASK                     (1 << 9)

/* Used by PM_L4PER_GPIO5_WKDEP */
#define DRA7XX_WKUPDEP_GPIO5_IRQ1_IPU1_SHIFT                    4
#define DRA7XX_WKUPDEP_GPIO5_IRQ1_IPU1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO5_IRQ1_IPU1_MASK                     (1 << 4)

/* Used by PM_L4PER_GPIO5_WKDEP */
#define DRA7XX_WKUPDEP_GPIO5_IRQ1_IPU2_SHIFT                    1
#define DRA7XX_WKUPDEP_GPIO5_IRQ1_IPU2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO5_IRQ1_IPU2_MASK                     (1 << 1)

/* Used by PM_L4PER_GPIO5_WKDEP */
#define DRA7XX_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT                     0
#define DRA7XX_WKUPDEP_GPIO5_IRQ1_MPU_WIDTH                     0x1
#define DRA7XX_WKUPDEP_GPIO5_IRQ1_MPU_MASK                      (1 << 0)

/* Used by PM_L4PER_GPIO5_WKDEP */
#define DRA7XX_WKUPDEP_GPIO5_IRQ2_DSP1_SHIFT                    12
#define DRA7XX_WKUPDEP_GPIO5_IRQ2_DSP1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO5_IRQ2_DSP1_MASK                     (1 << 12)

/* Used by PM_L4PER_GPIO5_WKDEP */
#define DRA7XX_WKUPDEP_GPIO5_IRQ2_DSP2_SHIFT                    15
#define DRA7XX_WKUPDEP_GPIO5_IRQ2_DSP2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO5_IRQ2_DSP2_MASK                     (1 << 15)

/* Used by PM_L4PER_GPIO5_WKDEP */
#define DRA7XX_WKUPDEP_GPIO5_IRQ2_EVE1_SHIFT                    16
#define DRA7XX_WKUPDEP_GPIO5_IRQ2_EVE1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO5_IRQ2_EVE1_MASK                     (1 << 16)

/* Used by PM_L4PER_GPIO5_WKDEP */
#define DRA7XX_WKUPDEP_GPIO5_IRQ2_EVE2_SHIFT                    17
#define DRA7XX_WKUPDEP_GPIO5_IRQ2_EVE2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO5_IRQ2_EVE2_MASK                     (1 << 17)

/* Used by PM_L4PER_GPIO5_WKDEP */
#define DRA7XX_WKUPDEP_GPIO5_IRQ2_EVE3_SHIFT                    18
#define DRA7XX_WKUPDEP_GPIO5_IRQ2_EVE3_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO5_IRQ2_EVE3_MASK                     (1 << 18)

/* Used by PM_L4PER_GPIO5_WKDEP */
#define DRA7XX_WKUPDEP_GPIO5_IRQ2_EVE4_SHIFT                    19
#define DRA7XX_WKUPDEP_GPIO5_IRQ2_EVE4_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO5_IRQ2_EVE4_MASK                     (1 << 19)

/* Used by PM_L4PER_GPIO5_WKDEP */
#define DRA7XX_WKUPDEP_GPIO5_IRQ2_IPU1_SHIFT                    14
#define DRA7XX_WKUPDEP_GPIO5_IRQ2_IPU1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO5_IRQ2_IPU1_MASK                     (1 << 14)

/* Used by PM_L4PER_GPIO5_WKDEP */
#define DRA7XX_WKUPDEP_GPIO5_IRQ2_IPU2_SHIFT                    11
#define DRA7XX_WKUPDEP_GPIO5_IRQ2_IPU2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO5_IRQ2_IPU2_MASK                     (1 << 11)

/* Used by PM_L4PER_GPIO5_WKDEP */
#define DRA7XX_WKUPDEP_GPIO5_IRQ2_MPU_SHIFT                     10
#define DRA7XX_WKUPDEP_GPIO5_IRQ2_MPU_WIDTH                     0x1
#define DRA7XX_WKUPDEP_GPIO5_IRQ2_MPU_MASK                      (1 << 10)

/* Used by PM_L4PER_GPIO6_WKDEP */
#define DRA7XX_WKUPDEP_GPIO6_IRQ1_DSP1_SHIFT                    2
#define DRA7XX_WKUPDEP_GPIO6_IRQ1_DSP1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO6_IRQ1_DSP1_MASK                     (1 << 2)

/* Used by PM_L4PER_GPIO6_WKDEP */
#define DRA7XX_WKUPDEP_GPIO6_IRQ1_DSP2_SHIFT                    5
#define DRA7XX_WKUPDEP_GPIO6_IRQ1_DSP2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO6_IRQ1_DSP2_MASK                     (1 << 5)

/* Used by PM_L4PER_GPIO6_WKDEP */
#define DRA7XX_WKUPDEP_GPIO6_IRQ1_EVE1_SHIFT                    6
#define DRA7XX_WKUPDEP_GPIO6_IRQ1_EVE1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO6_IRQ1_EVE1_MASK                     (1 << 6)

/* Used by PM_L4PER_GPIO6_WKDEP */
#define DRA7XX_WKUPDEP_GPIO6_IRQ1_EVE2_SHIFT                    7
#define DRA7XX_WKUPDEP_GPIO6_IRQ1_EVE2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO6_IRQ1_EVE2_MASK                     (1 << 7)

/* Used by PM_L4PER_GPIO6_WKDEP */
#define DRA7XX_WKUPDEP_GPIO6_IRQ1_EVE3_SHIFT                    8
#define DRA7XX_WKUPDEP_GPIO6_IRQ1_EVE3_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO6_IRQ1_EVE3_MASK                     (1 << 8)

/* Used by PM_L4PER_GPIO6_WKDEP */
#define DRA7XX_WKUPDEP_GPIO6_IRQ1_EVE4_SHIFT                    9
#define DRA7XX_WKUPDEP_GPIO6_IRQ1_EVE4_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO6_IRQ1_EVE4_MASK                     (1 << 9)

/* Used by PM_L4PER_GPIO6_WKDEP */
#define DRA7XX_WKUPDEP_GPIO6_IRQ1_IPU1_SHIFT                    4
#define DRA7XX_WKUPDEP_GPIO6_IRQ1_IPU1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO6_IRQ1_IPU1_MASK                     (1 << 4)

/* Used by PM_L4PER_GPIO6_WKDEP */
#define DRA7XX_WKUPDEP_GPIO6_IRQ1_IPU2_SHIFT                    1
#define DRA7XX_WKUPDEP_GPIO6_IRQ1_IPU2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO6_IRQ1_IPU2_MASK                     (1 << 1)

/* Used by PM_L4PER_GPIO6_WKDEP */
#define DRA7XX_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT                     0
#define DRA7XX_WKUPDEP_GPIO6_IRQ1_MPU_WIDTH                     0x1
#define DRA7XX_WKUPDEP_GPIO6_IRQ1_MPU_MASK                      (1 << 0)

/* Used by PM_L4PER_GPIO6_WKDEP */
#define DRA7XX_WKUPDEP_GPIO6_IRQ2_DSP1_SHIFT                    12
#define DRA7XX_WKUPDEP_GPIO6_IRQ2_DSP1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO6_IRQ2_DSP1_MASK                     (1 << 12)

/* Used by PM_L4PER_GPIO6_WKDEP */
#define DRA7XX_WKUPDEP_GPIO6_IRQ2_DSP2_SHIFT                    15
#define DRA7XX_WKUPDEP_GPIO6_IRQ2_DSP2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO6_IRQ2_DSP2_MASK                     (1 << 15)

/* Used by PM_L4PER_GPIO6_WKDEP */
#define DRA7XX_WKUPDEP_GPIO6_IRQ2_EVE1_SHIFT                    16
#define DRA7XX_WKUPDEP_GPIO6_IRQ2_EVE1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO6_IRQ2_EVE1_MASK                     (1 << 16)

/* Used by PM_L4PER_GPIO6_WKDEP */
#define DRA7XX_WKUPDEP_GPIO6_IRQ2_EVE2_SHIFT                    17
#define DRA7XX_WKUPDEP_GPIO6_IRQ2_EVE2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO6_IRQ2_EVE2_MASK                     (1 << 17)

/* Used by PM_L4PER_GPIO6_WKDEP */
#define DRA7XX_WKUPDEP_GPIO6_IRQ2_EVE3_SHIFT                    18
#define DRA7XX_WKUPDEP_GPIO6_IRQ2_EVE3_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO6_IRQ2_EVE3_MASK                     (1 << 18)

/* Used by PM_L4PER_GPIO6_WKDEP */
#define DRA7XX_WKUPDEP_GPIO6_IRQ2_EVE4_SHIFT                    19
#define DRA7XX_WKUPDEP_GPIO6_IRQ2_EVE4_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO6_IRQ2_EVE4_MASK                     (1 << 19)

/* Used by PM_L4PER_GPIO6_WKDEP */
#define DRA7XX_WKUPDEP_GPIO6_IRQ2_IPU1_SHIFT                    14
#define DRA7XX_WKUPDEP_GPIO6_IRQ2_IPU1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO6_IRQ2_IPU1_MASK                     (1 << 14)

/* Used by PM_L4PER_GPIO6_WKDEP */
#define DRA7XX_WKUPDEP_GPIO6_IRQ2_IPU2_SHIFT                    11
#define DRA7XX_WKUPDEP_GPIO6_IRQ2_IPU2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO6_IRQ2_IPU2_MASK                     (1 << 11)

/* Used by PM_L4PER_GPIO6_WKDEP */
#define DRA7XX_WKUPDEP_GPIO6_IRQ2_MPU_SHIFT                     10
#define DRA7XX_WKUPDEP_GPIO6_IRQ2_MPU_WIDTH                     0x1
#define DRA7XX_WKUPDEP_GPIO6_IRQ2_MPU_MASK                      (1 << 10)

/* Used by PM_L4PER_GPIO7_WKDEP */
#define DRA7XX_WKUPDEP_GPIO7_IRQ1_DSP1_SHIFT                    2
#define DRA7XX_WKUPDEP_GPIO7_IRQ1_DSP1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO7_IRQ1_DSP1_MASK                     (1 << 2)

/* Used by PM_L4PER_GPIO7_WKDEP */
#define DRA7XX_WKUPDEP_GPIO7_IRQ1_DSP2_SHIFT                    5
#define DRA7XX_WKUPDEP_GPIO7_IRQ1_DSP2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO7_IRQ1_DSP2_MASK                     (1 << 5)

/* Used by PM_L4PER_GPIO7_WKDEP */
#define DRA7XX_WKUPDEP_GPIO7_IRQ1_EVE1_SHIFT                    6
#define DRA7XX_WKUPDEP_GPIO7_IRQ1_EVE1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO7_IRQ1_EVE1_MASK                     (1 << 6)

/* Used by PM_L4PER_GPIO7_WKDEP */
#define DRA7XX_WKUPDEP_GPIO7_IRQ1_EVE2_SHIFT                    7
#define DRA7XX_WKUPDEP_GPIO7_IRQ1_EVE2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO7_IRQ1_EVE2_MASK                     (1 << 7)

/* Used by PM_L4PER_GPIO7_WKDEP */
#define DRA7XX_WKUPDEP_GPIO7_IRQ1_EVE3_SHIFT                    8
#define DRA7XX_WKUPDEP_GPIO7_IRQ1_EVE3_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO7_IRQ1_EVE3_MASK                     (1 << 8)

/* Used by PM_L4PER_GPIO7_WKDEP */
#define DRA7XX_WKUPDEP_GPIO7_IRQ1_EVE4_SHIFT                    9
#define DRA7XX_WKUPDEP_GPIO7_IRQ1_EVE4_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO7_IRQ1_EVE4_MASK                     (1 << 9)

/* Used by PM_L4PER_GPIO7_WKDEP */
#define DRA7XX_WKUPDEP_GPIO7_IRQ1_IPU1_SHIFT                    4
#define DRA7XX_WKUPDEP_GPIO7_IRQ1_IPU1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO7_IRQ1_IPU1_MASK                     (1 << 4)

/* Used by PM_L4PER_GPIO7_WKDEP */
#define DRA7XX_WKUPDEP_GPIO7_IRQ1_IPU2_SHIFT                    1
#define DRA7XX_WKUPDEP_GPIO7_IRQ1_IPU2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO7_IRQ1_IPU2_MASK                     (1 << 1)

/* Used by PM_L4PER_GPIO7_WKDEP */
#define DRA7XX_WKUPDEP_GPIO7_IRQ1_MPU_SHIFT                     0
#define DRA7XX_WKUPDEP_GPIO7_IRQ1_MPU_WIDTH                     0x1
#define DRA7XX_WKUPDEP_GPIO7_IRQ1_MPU_MASK                      (1 << 0)

/* Used by PM_L4PER_GPIO7_WKDEP */
#define DRA7XX_WKUPDEP_GPIO7_IRQ2_DSP1_SHIFT                    12
#define DRA7XX_WKUPDEP_GPIO7_IRQ2_DSP1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO7_IRQ2_DSP1_MASK                     (1 << 12)

/* Used by PM_L4PER_GPIO7_WKDEP */
#define DRA7XX_WKUPDEP_GPIO7_IRQ2_DSP2_SHIFT                    15
#define DRA7XX_WKUPDEP_GPIO7_IRQ2_DSP2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO7_IRQ2_DSP2_MASK                     (1 << 15)

/* Used by PM_L4PER_GPIO7_WKDEP */
#define DRA7XX_WKUPDEP_GPIO7_IRQ2_EVE1_SHIFT                    16
#define DRA7XX_WKUPDEP_GPIO7_IRQ2_EVE1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO7_IRQ2_EVE1_MASK                     (1 << 16)

/* Used by PM_L4PER_GPIO7_WKDEP */
#define DRA7XX_WKUPDEP_GPIO7_IRQ2_EVE2_SHIFT                    17
#define DRA7XX_WKUPDEP_GPIO7_IRQ2_EVE2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO7_IRQ2_EVE2_MASK                     (1 << 17)

/* Used by PM_L4PER_GPIO7_WKDEP */
#define DRA7XX_WKUPDEP_GPIO7_IRQ2_EVE3_SHIFT                    18
#define DRA7XX_WKUPDEP_GPIO7_IRQ2_EVE3_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO7_IRQ2_EVE3_MASK                     (1 << 18)

/* Used by PM_L4PER_GPIO7_WKDEP */
#define DRA7XX_WKUPDEP_GPIO7_IRQ2_EVE4_SHIFT                    19
#define DRA7XX_WKUPDEP_GPIO7_IRQ2_EVE4_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO7_IRQ2_EVE4_MASK                     (1 << 19)

/* Used by PM_L4PER_GPIO7_WKDEP */
#define DRA7XX_WKUPDEP_GPIO7_IRQ2_IPU1_SHIFT                    14
#define DRA7XX_WKUPDEP_GPIO7_IRQ2_IPU1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO7_IRQ2_IPU1_MASK                     (1 << 14)

/* Used by PM_L4PER_GPIO7_WKDEP */
#define DRA7XX_WKUPDEP_GPIO7_IRQ2_IPU2_SHIFT                    11
#define DRA7XX_WKUPDEP_GPIO7_IRQ2_IPU2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO7_IRQ2_IPU2_MASK                     (1 << 11)

/* Used by PM_L4PER_GPIO7_WKDEP */
#define DRA7XX_WKUPDEP_GPIO7_IRQ2_MPU_SHIFT                     10
#define DRA7XX_WKUPDEP_GPIO7_IRQ2_MPU_WIDTH                     0x1
#define DRA7XX_WKUPDEP_GPIO7_IRQ2_MPU_MASK                      (1 << 10)

/* Used by PM_L4PER_GPIO8_WKDEP */
#define DRA7XX_WKUPDEP_GPIO8_IRQ1_DSP1_SHIFT                    2
#define DRA7XX_WKUPDEP_GPIO8_IRQ1_DSP1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO8_IRQ1_DSP1_MASK                     (1 << 2)

/* Used by PM_L4PER_GPIO8_WKDEP */
#define DRA7XX_WKUPDEP_GPIO8_IRQ1_DSP2_SHIFT                    5
#define DRA7XX_WKUPDEP_GPIO8_IRQ1_DSP2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO8_IRQ1_DSP2_MASK                     (1 << 5)

/* Used by PM_L4PER_GPIO8_WKDEP */
#define DRA7XX_WKUPDEP_GPIO8_IRQ1_EVE1_SHIFT                    6
#define DRA7XX_WKUPDEP_GPIO8_IRQ1_EVE1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO8_IRQ1_EVE1_MASK                     (1 << 6)

/* Used by PM_L4PER_GPIO8_WKDEP */
#define DRA7XX_WKUPDEP_GPIO8_IRQ1_EVE2_SHIFT                    7
#define DRA7XX_WKUPDEP_GPIO8_IRQ1_EVE2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO8_IRQ1_EVE2_MASK                     (1 << 7)

/* Used by PM_L4PER_GPIO8_WKDEP */
#define DRA7XX_WKUPDEP_GPIO8_IRQ1_EVE3_SHIFT                    8
#define DRA7XX_WKUPDEP_GPIO8_IRQ1_EVE3_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO8_IRQ1_EVE3_MASK                     (1 << 8)

/* Used by PM_L4PER_GPIO8_WKDEP */
#define DRA7XX_WKUPDEP_GPIO8_IRQ1_EVE4_SHIFT                    9
#define DRA7XX_WKUPDEP_GPIO8_IRQ1_EVE4_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO8_IRQ1_EVE4_MASK                     (1 << 9)

/* Used by PM_L4PER_GPIO8_WKDEP */
#define DRA7XX_WKUPDEP_GPIO8_IRQ1_IPU1_SHIFT                    4
#define DRA7XX_WKUPDEP_GPIO8_IRQ1_IPU1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO8_IRQ1_IPU1_MASK                     (1 << 4)

/* Used by PM_L4PER_GPIO8_WKDEP */
#define DRA7XX_WKUPDEP_GPIO8_IRQ1_IPU2_SHIFT                    1
#define DRA7XX_WKUPDEP_GPIO8_IRQ1_IPU2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO8_IRQ1_IPU2_MASK                     (1 << 1)

/* Used by PM_L4PER_GPIO8_WKDEP */
#define DRA7XX_WKUPDEP_GPIO8_IRQ1_MPU_SHIFT                     0
#define DRA7XX_WKUPDEP_GPIO8_IRQ1_MPU_WIDTH                     0x1
#define DRA7XX_WKUPDEP_GPIO8_IRQ1_MPU_MASK                      (1 << 0)

/* Used by PM_L4PER_GPIO8_WKDEP */
#define DRA7XX_WKUPDEP_GPIO8_IRQ2_DSP1_SHIFT                    12
#define DRA7XX_WKUPDEP_GPIO8_IRQ2_DSP1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO8_IRQ2_DSP1_MASK                     (1 << 12)

/* Used by PM_L4PER_GPIO8_WKDEP */
#define DRA7XX_WKUPDEP_GPIO8_IRQ2_DSP2_SHIFT                    15
#define DRA7XX_WKUPDEP_GPIO8_IRQ2_DSP2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO8_IRQ2_DSP2_MASK                     (1 << 15)

/* Used by PM_L4PER_GPIO8_WKDEP */
#define DRA7XX_WKUPDEP_GPIO8_IRQ2_EVE1_SHIFT                    16
#define DRA7XX_WKUPDEP_GPIO8_IRQ2_EVE1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO8_IRQ2_EVE1_MASK                     (1 << 16)

/* Used by PM_L4PER_GPIO8_WKDEP */
#define DRA7XX_WKUPDEP_GPIO8_IRQ2_EVE2_SHIFT                    17
#define DRA7XX_WKUPDEP_GPIO8_IRQ2_EVE2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO8_IRQ2_EVE2_MASK                     (1 << 17)

/* Used by PM_L4PER_GPIO8_WKDEP */
#define DRA7XX_WKUPDEP_GPIO8_IRQ2_EVE3_SHIFT                    18
#define DRA7XX_WKUPDEP_GPIO8_IRQ2_EVE3_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO8_IRQ2_EVE3_MASK                     (1 << 18)

/* Used by PM_L4PER_GPIO8_WKDEP */
#define DRA7XX_WKUPDEP_GPIO8_IRQ2_EVE4_SHIFT                    19
#define DRA7XX_WKUPDEP_GPIO8_IRQ2_EVE4_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO8_IRQ2_EVE4_MASK                     (1 << 19)

/* Used by PM_L4PER_GPIO8_WKDEP */
#define DRA7XX_WKUPDEP_GPIO8_IRQ2_IPU1_SHIFT                    14
#define DRA7XX_WKUPDEP_GPIO8_IRQ2_IPU1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO8_IRQ2_IPU1_MASK                     (1 << 14)

/* Used by PM_L4PER_GPIO8_WKDEP */
#define DRA7XX_WKUPDEP_GPIO8_IRQ2_IPU2_SHIFT                    11
#define DRA7XX_WKUPDEP_GPIO8_IRQ2_IPU2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_GPIO8_IRQ2_IPU2_MASK                     (1 << 11)

/* Used by PM_L4PER_GPIO8_WKDEP */
#define DRA7XX_WKUPDEP_GPIO8_IRQ2_MPU_SHIFT                     10
#define DRA7XX_WKUPDEP_GPIO8_IRQ2_MPU_WIDTH                     0x1
#define DRA7XX_WKUPDEP_GPIO8_IRQ2_MPU_MASK                      (1 << 10)

/* Used by PM_DSS_DSS2_WKDEP */
#define DRA7XX_WKUPDEP_HDMIDMA_DSP1_SHIFT                       22
#define DRA7XX_WKUPDEP_HDMIDMA_DSP1_WIDTH                       0x1
#define DRA7XX_WKUPDEP_HDMIDMA_DSP1_MASK                        (1 << 22)

/* Used by PM_DSS_DSS2_WKDEP */
#define DRA7XX_WKUPDEP_HDMIDMA_DSP2_SHIFT                       25
#define DRA7XX_WKUPDEP_HDMIDMA_DSP2_WIDTH                       0x1
#define DRA7XX_WKUPDEP_HDMIDMA_DSP2_MASK                        (1 << 25)

/* Used by PM_DSS_DSS2_WKDEP */
#define DRA7XX_WKUPDEP_HDMIDMA_SDMA_SHIFT                       23
#define DRA7XX_WKUPDEP_HDMIDMA_SDMA_WIDTH                       0x1
#define DRA7XX_WKUPDEP_HDMIDMA_SDMA_MASK                        (1 << 23)

/* Used by PM_DSS_DSS2_WKDEP */
#define DRA7XX_WKUPDEP_HDMIIRQ_DSP1_SHIFT                       2
#define DRA7XX_WKUPDEP_HDMIIRQ_DSP1_WIDTH                       0x1
#define DRA7XX_WKUPDEP_HDMIIRQ_DSP1_MASK                        (1 << 2)

/* Used by PM_DSS_DSS2_WKDEP */
#define DRA7XX_WKUPDEP_HDMIIRQ_DSP2_SHIFT                       5
#define DRA7XX_WKUPDEP_HDMIIRQ_DSP2_WIDTH                       0x1
#define DRA7XX_WKUPDEP_HDMIIRQ_DSP2_MASK                        (1 << 5)

/* Used by PM_DSS_DSS2_WKDEP */
#define DRA7XX_WKUPDEP_HDMIIRQ_EVE1_SHIFT                       6
#define DRA7XX_WKUPDEP_HDMIIRQ_EVE1_WIDTH                       0x1
#define DRA7XX_WKUPDEP_HDMIIRQ_EVE1_MASK                        (1 << 6)

/* Used by PM_DSS_DSS2_WKDEP */
#define DRA7XX_WKUPDEP_HDMIIRQ_EVE2_SHIFT                       7
#define DRA7XX_WKUPDEP_HDMIIRQ_EVE2_WIDTH                       0x1
#define DRA7XX_WKUPDEP_HDMIIRQ_EVE2_MASK                        (1 << 7)

/* Used by PM_DSS_DSS2_WKDEP */
#define DRA7XX_WKUPDEP_HDMIIRQ_EVE3_SHIFT                       8
#define DRA7XX_WKUPDEP_HDMIIRQ_EVE3_WIDTH                       0x1
#define DRA7XX_WKUPDEP_HDMIIRQ_EVE3_MASK                        (1 << 8)

/* Used by PM_DSS_DSS2_WKDEP */
#define DRA7XX_WKUPDEP_HDMIIRQ_EVE4_SHIFT                       9
#define DRA7XX_WKUPDEP_HDMIIRQ_EVE4_WIDTH                       0x1
#define DRA7XX_WKUPDEP_HDMIIRQ_EVE4_MASK                        (1 << 9)

/* Used by PM_DSS_DSS2_WKDEP */
#define DRA7XX_WKUPDEP_HDMIIRQ_IPU1_SHIFT                       4
#define DRA7XX_WKUPDEP_HDMIIRQ_IPU1_WIDTH                       0x1
#define DRA7XX_WKUPDEP_HDMIIRQ_IPU1_MASK                        (1 << 4)

/* Used by PM_DSS_DSS2_WKDEP */
#define DRA7XX_WKUPDEP_HDMIIRQ_IPU2_SHIFT                       1
#define DRA7XX_WKUPDEP_HDMIIRQ_IPU2_WIDTH                       0x1
#define DRA7XX_WKUPDEP_HDMIIRQ_IPU2_MASK                        (1 << 1)

/* Used by PM_DSS_DSS2_WKDEP */
#define DRA7XX_WKUPDEP_HDMIIRQ_MPU_SHIFT                        0
#define DRA7XX_WKUPDEP_HDMIIRQ_MPU_WIDTH                        0x1
#define DRA7XX_WKUPDEP_HDMIIRQ_MPU_MASK                         (1 << 0)

/* Used by PM_L4PER_I2C1_WKDEP */
#define DRA7XX_WKUPDEP_I2C1_DMA_DSP1_SHIFT                      12
#define DRA7XX_WKUPDEP_I2C1_DMA_DSP1_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C1_DMA_DSP1_MASK                       (1 << 12)

/* Used by PM_L4PER_I2C1_WKDEP */
#define DRA7XX_WKUPDEP_I2C1_DMA_DSP2_SHIFT                      15
#define DRA7XX_WKUPDEP_I2C1_DMA_DSP2_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C1_DMA_DSP2_MASK                       (1 << 15)

/* Used by PM_L4PER_I2C1_WKDEP */
#define DRA7XX_WKUPDEP_I2C1_DMA_SDMA_SHIFT                      13
#define DRA7XX_WKUPDEP_I2C1_DMA_SDMA_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C1_DMA_SDMA_MASK                       (1 << 13)

/* Used by PM_L4PER_I2C1_WKDEP */
#define DRA7XX_WKUPDEP_I2C1_IRQ_DSP1_SHIFT                      2
#define DRA7XX_WKUPDEP_I2C1_IRQ_DSP1_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C1_IRQ_DSP1_MASK                       (1 << 2)

/* Used by PM_L4PER_I2C1_WKDEP */
#define DRA7XX_WKUPDEP_I2C1_IRQ_DSP2_SHIFT                      5
#define DRA7XX_WKUPDEP_I2C1_IRQ_DSP2_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C1_IRQ_DSP2_MASK                       (1 << 5)

/* Used by PM_L4PER_I2C1_WKDEP */
#define DRA7XX_WKUPDEP_I2C1_IRQ_EVE1_SHIFT                      6
#define DRA7XX_WKUPDEP_I2C1_IRQ_EVE1_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C1_IRQ_EVE1_MASK                       (1 << 6)

/* Used by PM_L4PER_I2C1_WKDEP */
#define DRA7XX_WKUPDEP_I2C1_IRQ_EVE2_SHIFT                      7
#define DRA7XX_WKUPDEP_I2C1_IRQ_EVE2_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C1_IRQ_EVE2_MASK                       (1 << 7)

/* Used by PM_L4PER_I2C1_WKDEP */
#define DRA7XX_WKUPDEP_I2C1_IRQ_EVE3_SHIFT                      8
#define DRA7XX_WKUPDEP_I2C1_IRQ_EVE3_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C1_IRQ_EVE3_MASK                       (1 << 8)

/* Used by PM_L4PER_I2C1_WKDEP */
#define DRA7XX_WKUPDEP_I2C1_IRQ_EVE4_SHIFT                      9
#define DRA7XX_WKUPDEP_I2C1_IRQ_EVE4_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C1_IRQ_EVE4_MASK                       (1 << 9)

/* Used by PM_L4PER_I2C1_WKDEP */
#define DRA7XX_WKUPDEP_I2C1_IRQ_IPU1_SHIFT                      4
#define DRA7XX_WKUPDEP_I2C1_IRQ_IPU1_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C1_IRQ_IPU1_MASK                       (1 << 4)

/* Used by PM_L4PER_I2C1_WKDEP */
#define DRA7XX_WKUPDEP_I2C1_IRQ_IPU2_SHIFT                      1
#define DRA7XX_WKUPDEP_I2C1_IRQ_IPU2_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C1_IRQ_IPU2_MASK                       (1 << 1)

/* Used by PM_L4PER_I2C1_WKDEP */
#define DRA7XX_WKUPDEP_I2C1_IRQ_MPU_SHIFT                       0
#define DRA7XX_WKUPDEP_I2C1_IRQ_MPU_WIDTH                       0x1
#define DRA7XX_WKUPDEP_I2C1_IRQ_MPU_MASK                        (1 << 0)

/* Used by PM_L4PER_I2C2_WKDEP */
#define DRA7XX_WKUPDEP_I2C2_DMA_DSP1_SHIFT                      12
#define DRA7XX_WKUPDEP_I2C2_DMA_DSP1_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C2_DMA_DSP1_MASK                       (1 << 12)

/* Used by PM_L4PER_I2C2_WKDEP */
#define DRA7XX_WKUPDEP_I2C2_DMA_DSP2_SHIFT                      15
#define DRA7XX_WKUPDEP_I2C2_DMA_DSP2_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C2_DMA_DSP2_MASK                       (1 << 15)

/* Used by PM_L4PER_I2C2_WKDEP */
#define DRA7XX_WKUPDEP_I2C2_DMA_SDMA_SHIFT                      13
#define DRA7XX_WKUPDEP_I2C2_DMA_SDMA_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C2_DMA_SDMA_MASK                       (1 << 13)

/* Used by PM_L4PER_I2C2_WKDEP */
#define DRA7XX_WKUPDEP_I2C2_IRQ_DSP1_SHIFT                      2
#define DRA7XX_WKUPDEP_I2C2_IRQ_DSP1_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C2_IRQ_DSP1_MASK                       (1 << 2)

/* Used by PM_L4PER_I2C2_WKDEP */
#define DRA7XX_WKUPDEP_I2C2_IRQ_DSP2_SHIFT                      5
#define DRA7XX_WKUPDEP_I2C2_IRQ_DSP2_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C2_IRQ_DSP2_MASK                       (1 << 5)

/* Used by PM_L4PER_I2C2_WKDEP */
#define DRA7XX_WKUPDEP_I2C2_IRQ_EVE1_SHIFT                      6
#define DRA7XX_WKUPDEP_I2C2_IRQ_EVE1_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C2_IRQ_EVE1_MASK                       (1 << 6)

/* Used by PM_L4PER_I2C2_WKDEP */
#define DRA7XX_WKUPDEP_I2C2_IRQ_EVE2_SHIFT                      7
#define DRA7XX_WKUPDEP_I2C2_IRQ_EVE2_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C2_IRQ_EVE2_MASK                       (1 << 7)

/* Used by PM_L4PER_I2C2_WKDEP */
#define DRA7XX_WKUPDEP_I2C2_IRQ_EVE3_SHIFT                      8
#define DRA7XX_WKUPDEP_I2C2_IRQ_EVE3_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C2_IRQ_EVE3_MASK                       (1 << 8)

/* Used by PM_L4PER_I2C2_WKDEP */
#define DRA7XX_WKUPDEP_I2C2_IRQ_EVE4_SHIFT                      9
#define DRA7XX_WKUPDEP_I2C2_IRQ_EVE4_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C2_IRQ_EVE4_MASK                       (1 << 9)

/* Used by PM_L4PER_I2C2_WKDEP */
#define DRA7XX_WKUPDEP_I2C2_IRQ_IPU1_SHIFT                      4
#define DRA7XX_WKUPDEP_I2C2_IRQ_IPU1_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C2_IRQ_IPU1_MASK                       (1 << 4)

/* Used by PM_L4PER_I2C2_WKDEP */
#define DRA7XX_WKUPDEP_I2C2_IRQ_IPU2_SHIFT                      1
#define DRA7XX_WKUPDEP_I2C2_IRQ_IPU2_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C2_IRQ_IPU2_MASK                       (1 << 1)

/* Used by PM_L4PER_I2C2_WKDEP */
#define DRA7XX_WKUPDEP_I2C2_IRQ_MPU_SHIFT                       0
#define DRA7XX_WKUPDEP_I2C2_IRQ_MPU_WIDTH                       0x1
#define DRA7XX_WKUPDEP_I2C2_IRQ_MPU_MASK                        (1 << 0)

/* Used by PM_L4PER_I2C3_WKDEP */
#define DRA7XX_WKUPDEP_I2C3_DMA_DSP1_SHIFT                      12
#define DRA7XX_WKUPDEP_I2C3_DMA_DSP1_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C3_DMA_DSP1_MASK                       (1 << 12)

/* Used by PM_L4PER_I2C3_WKDEP */
#define DRA7XX_WKUPDEP_I2C3_DMA_DSP2_SHIFT                      15
#define DRA7XX_WKUPDEP_I2C3_DMA_DSP2_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C3_DMA_DSP2_MASK                       (1 << 15)

/* Used by PM_L4PER_I2C3_WKDEP */
#define DRA7XX_WKUPDEP_I2C3_DMA_SDMA_SHIFT                      13
#define DRA7XX_WKUPDEP_I2C3_DMA_SDMA_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C3_DMA_SDMA_MASK                       (1 << 13)

/* Used by PM_L4PER_I2C3_WKDEP */
#define DRA7XX_WKUPDEP_I2C3_IRQ_DSP1_SHIFT                      2
#define DRA7XX_WKUPDEP_I2C3_IRQ_DSP1_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C3_IRQ_DSP1_MASK                       (1 << 2)

/* Used by PM_L4PER_I2C3_WKDEP */
#define DRA7XX_WKUPDEP_I2C3_IRQ_DSP2_SHIFT                      5
#define DRA7XX_WKUPDEP_I2C3_IRQ_DSP2_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C3_IRQ_DSP2_MASK                       (1 << 5)

/* Used by PM_L4PER_I2C3_WKDEP */
#define DRA7XX_WKUPDEP_I2C3_IRQ_EVE1_SHIFT                      6
#define DRA7XX_WKUPDEP_I2C3_IRQ_EVE1_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C3_IRQ_EVE1_MASK                       (1 << 6)

/* Used by PM_L4PER_I2C3_WKDEP */
#define DRA7XX_WKUPDEP_I2C3_IRQ_EVE2_SHIFT                      7
#define DRA7XX_WKUPDEP_I2C3_IRQ_EVE2_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C3_IRQ_EVE2_MASK                       (1 << 7)

/* Used by PM_L4PER_I2C3_WKDEP */
#define DRA7XX_WKUPDEP_I2C3_IRQ_EVE3_SHIFT                      8
#define DRA7XX_WKUPDEP_I2C3_IRQ_EVE3_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C3_IRQ_EVE3_MASK                       (1 << 8)

/* Used by PM_L4PER_I2C3_WKDEP */
#define DRA7XX_WKUPDEP_I2C3_IRQ_EVE4_SHIFT                      9
#define DRA7XX_WKUPDEP_I2C3_IRQ_EVE4_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C3_IRQ_EVE4_MASK                       (1 << 9)

/* Used by PM_L4PER_I2C3_WKDEP */
#define DRA7XX_WKUPDEP_I2C3_IRQ_IPU1_SHIFT                      4
#define DRA7XX_WKUPDEP_I2C3_IRQ_IPU1_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C3_IRQ_IPU1_MASK                       (1 << 4)

/* Used by PM_L4PER_I2C3_WKDEP */
#define DRA7XX_WKUPDEP_I2C3_IRQ_IPU2_SHIFT                      1
#define DRA7XX_WKUPDEP_I2C3_IRQ_IPU2_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C3_IRQ_IPU2_MASK                       (1 << 1)

/* Used by PM_L4PER_I2C3_WKDEP */
#define DRA7XX_WKUPDEP_I2C3_IRQ_MPU_SHIFT                       0
#define DRA7XX_WKUPDEP_I2C3_IRQ_MPU_WIDTH                       0x1
#define DRA7XX_WKUPDEP_I2C3_IRQ_MPU_MASK                        (1 << 0)

/* Used by PM_L4PER_I2C4_WKDEP */
#define DRA7XX_WKUPDEP_I2C4_DMA_DSP1_SHIFT                      12
#define DRA7XX_WKUPDEP_I2C4_DMA_DSP1_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C4_DMA_DSP1_MASK                       (1 << 12)

/* Used by PM_L4PER_I2C4_WKDEP */
#define DRA7XX_WKUPDEP_I2C4_DMA_DSP2_SHIFT                      15
#define DRA7XX_WKUPDEP_I2C4_DMA_DSP2_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C4_DMA_DSP2_MASK                       (1 << 15)

/* Used by PM_L4PER_I2C4_WKDEP */
#define DRA7XX_WKUPDEP_I2C4_DMA_SDMA_SHIFT                      13
#define DRA7XX_WKUPDEP_I2C4_DMA_SDMA_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C4_DMA_SDMA_MASK                       (1 << 13)

/* Used by PM_L4PER_I2C4_WKDEP */
#define DRA7XX_WKUPDEP_I2C4_IRQ_DSP1_SHIFT                      2
#define DRA7XX_WKUPDEP_I2C4_IRQ_DSP1_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C4_IRQ_DSP1_MASK                       (1 << 2)

/* Used by PM_L4PER_I2C4_WKDEP */
#define DRA7XX_WKUPDEP_I2C4_IRQ_DSP2_SHIFT                      5
#define DRA7XX_WKUPDEP_I2C4_IRQ_DSP2_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C4_IRQ_DSP2_MASK                       (1 << 5)

/* Used by PM_L4PER_I2C4_WKDEP */
#define DRA7XX_WKUPDEP_I2C4_IRQ_EVE1_SHIFT                      6
#define DRA7XX_WKUPDEP_I2C4_IRQ_EVE1_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C4_IRQ_EVE1_MASK                       (1 << 6)

/* Used by PM_L4PER_I2C4_WKDEP */
#define DRA7XX_WKUPDEP_I2C4_IRQ_EVE2_SHIFT                      7
#define DRA7XX_WKUPDEP_I2C4_IRQ_EVE2_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C4_IRQ_EVE2_MASK                       (1 << 7)

/* Used by PM_L4PER_I2C4_WKDEP */
#define DRA7XX_WKUPDEP_I2C4_IRQ_EVE3_SHIFT                      8
#define DRA7XX_WKUPDEP_I2C4_IRQ_EVE3_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C4_IRQ_EVE3_MASK                       (1 << 8)

/* Used by PM_L4PER_I2C4_WKDEP */
#define DRA7XX_WKUPDEP_I2C4_IRQ_EVE4_SHIFT                      9
#define DRA7XX_WKUPDEP_I2C4_IRQ_EVE4_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C4_IRQ_EVE4_MASK                       (1 << 9)

/* Used by PM_L4PER_I2C4_WKDEP */
#define DRA7XX_WKUPDEP_I2C4_IRQ_IPU1_SHIFT                      4
#define DRA7XX_WKUPDEP_I2C4_IRQ_IPU1_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C4_IRQ_IPU1_MASK                       (1 << 4)

/* Used by PM_L4PER_I2C4_WKDEP */
#define DRA7XX_WKUPDEP_I2C4_IRQ_IPU2_SHIFT                      1
#define DRA7XX_WKUPDEP_I2C4_IRQ_IPU2_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C4_IRQ_IPU2_MASK                       (1 << 1)

/* Used by PM_L4PER_I2C4_WKDEP */
#define DRA7XX_WKUPDEP_I2C4_IRQ_MPU_SHIFT                       0
#define DRA7XX_WKUPDEP_I2C4_IRQ_MPU_WIDTH                       0x1
#define DRA7XX_WKUPDEP_I2C4_IRQ_MPU_MASK                        (1 << 0)

/* Used by PM_IPU_I2C5_WKDEP */
#define DRA7XX_WKUPDEP_I2C5_DMA_DSP1_SHIFT                      12
#define DRA7XX_WKUPDEP_I2C5_DMA_DSP1_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C5_DMA_DSP1_MASK                       (1 << 12)

/* Used by PM_IPU_I2C5_WKDEP */
#define DRA7XX_WKUPDEP_I2C5_DMA_DSP2_SHIFT                      15
#define DRA7XX_WKUPDEP_I2C5_DMA_DSP2_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C5_DMA_DSP2_MASK                       (1 << 15)

/* Used by PM_IPU_I2C5_WKDEP */
#define DRA7XX_WKUPDEP_I2C5_DMA_SDMA_SHIFT                      13
#define DRA7XX_WKUPDEP_I2C5_DMA_SDMA_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C5_DMA_SDMA_MASK                       (1 << 13)

/* Used by PM_IPU_I2C5_WKDEP */
#define DRA7XX_WKUPDEP_I2C5_IRQ_DSP1_SHIFT                      2
#define DRA7XX_WKUPDEP_I2C5_IRQ_DSP1_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C5_IRQ_DSP1_MASK                       (1 << 2)

/* Used by PM_IPU_I2C5_WKDEP */
#define DRA7XX_WKUPDEP_I2C5_IRQ_DSP2_SHIFT                      5
#define DRA7XX_WKUPDEP_I2C5_IRQ_DSP2_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C5_IRQ_DSP2_MASK                       (1 << 5)

/* Used by PM_IPU_I2C5_WKDEP */
#define DRA7XX_WKUPDEP_I2C5_IRQ_EVE1_SHIFT                      6
#define DRA7XX_WKUPDEP_I2C5_IRQ_EVE1_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C5_IRQ_EVE1_MASK                       (1 << 6)

/* Used by PM_IPU_I2C5_WKDEP */
#define DRA7XX_WKUPDEP_I2C5_IRQ_EVE2_SHIFT                      7
#define DRA7XX_WKUPDEP_I2C5_IRQ_EVE2_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C5_IRQ_EVE2_MASK                       (1 << 7)

/* Used by PM_IPU_I2C5_WKDEP */
#define DRA7XX_WKUPDEP_I2C5_IRQ_EVE3_SHIFT                      8
#define DRA7XX_WKUPDEP_I2C5_IRQ_EVE3_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C5_IRQ_EVE3_MASK                       (1 << 8)

/* Used by PM_IPU_I2C5_WKDEP */
#define DRA7XX_WKUPDEP_I2C5_IRQ_EVE4_SHIFT                      9
#define DRA7XX_WKUPDEP_I2C5_IRQ_EVE4_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C5_IRQ_EVE4_MASK                       (1 << 9)

/* Used by PM_IPU_I2C5_WKDEP */
#define DRA7XX_WKUPDEP_I2C5_IRQ_IPU1_SHIFT                      4
#define DRA7XX_WKUPDEP_I2C5_IRQ_IPU1_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C5_IRQ_IPU1_MASK                       (1 << 4)

/* Used by PM_IPU_I2C5_WKDEP */
#define DRA7XX_WKUPDEP_I2C5_IRQ_IPU2_SHIFT                      1
#define DRA7XX_WKUPDEP_I2C5_IRQ_IPU2_WIDTH                      0x1
#define DRA7XX_WKUPDEP_I2C5_IRQ_IPU2_MASK                       (1 << 1)

/* Used by PM_IPU_I2C5_WKDEP */
#define DRA7XX_WKUPDEP_I2C5_IRQ_MPU_SHIFT                       0
#define DRA7XX_WKUPDEP_I2C5_IRQ_MPU_WIDTH                       0x1
#define DRA7XX_WKUPDEP_I2C5_IRQ_MPU_MASK                        (1 << 0)

/* Used by PM_WKUPAON_KBD_WKDEP */
#define DRA7XX_WKUPDEP_KBD_DSP1_SHIFT                           2
#define DRA7XX_WKUPDEP_KBD_DSP1_WIDTH                           0x1
#define DRA7XX_WKUPDEP_KBD_DSP1_MASK                            (1 << 2)

/* Used by PM_WKUPAON_KBD_WKDEP */
#define DRA7XX_WKUPDEP_KBD_DSP2_SHIFT                           5
#define DRA7XX_WKUPDEP_KBD_DSP2_WIDTH                           0x1
#define DRA7XX_WKUPDEP_KBD_DSP2_MASK                            (1 << 5)

/* Used by PM_WKUPAON_KBD_WKDEP */
#define DRA7XX_WKUPDEP_KBD_EVE1_SHIFT                           6
#define DRA7XX_WKUPDEP_KBD_EVE1_WIDTH                           0x1
#define DRA7XX_WKUPDEP_KBD_EVE1_MASK                            (1 << 6)

/* Used by PM_WKUPAON_KBD_WKDEP */
#define DRA7XX_WKUPDEP_KBD_EVE2_SHIFT                           7
#define DRA7XX_WKUPDEP_KBD_EVE2_WIDTH                           0x1
#define DRA7XX_WKUPDEP_KBD_EVE2_MASK                            (1 << 7)

/* Used by PM_WKUPAON_KBD_WKDEP */
#define DRA7XX_WKUPDEP_KBD_EVE3_SHIFT                           8
#define DRA7XX_WKUPDEP_KBD_EVE3_WIDTH                           0x1
#define DRA7XX_WKUPDEP_KBD_EVE3_MASK                            (1 << 8)

/* Used by PM_WKUPAON_KBD_WKDEP */
#define DRA7XX_WKUPDEP_KBD_EVE4_SHIFT                           9
#define DRA7XX_WKUPDEP_KBD_EVE4_WIDTH                           0x1
#define DRA7XX_WKUPDEP_KBD_EVE4_MASK                            (1 << 9)

/* Used by PM_WKUPAON_KBD_WKDEP */
#define DRA7XX_WKUPDEP_KBD_IPU1_SHIFT                           4
#define DRA7XX_WKUPDEP_KBD_IPU1_WIDTH                           0x1
#define DRA7XX_WKUPDEP_KBD_IPU1_MASK                            (1 << 4)

/* Used by PM_WKUPAON_KBD_WKDEP */
#define DRA7XX_WKUPDEP_KBD_IPU2_SHIFT                           1
#define DRA7XX_WKUPDEP_KBD_IPU2_WIDTH                           0x1
#define DRA7XX_WKUPDEP_KBD_IPU2_MASK                            (1 << 1)

/* Used by PM_WKUPAON_KBD_WKDEP */
#define DRA7XX_WKUPDEP_KBD_MPU_SHIFT                            0
#define DRA7XX_WKUPDEP_KBD_MPU_WIDTH                            0x1
#define DRA7XX_WKUPDEP_KBD_MPU_MASK                             (1 << 0)

/* Used by PM_IPU_MCASP1_WKDEP */
#define DRA7XX_WKUPDEP_MCASP1_DMA_DSP1_SHIFT                    12
#define DRA7XX_WKUPDEP_MCASP1_DMA_DSP1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP1_DMA_DSP1_MASK                     (1 << 12)

/* Used by PM_IPU_MCASP1_WKDEP */
#define DRA7XX_WKUPDEP_MCASP1_DMA_DSP2_SHIFT                    15
#define DRA7XX_WKUPDEP_MCASP1_DMA_DSP2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP1_DMA_DSP2_MASK                     (1 << 15)

/* Used by PM_IPU_MCASP1_WKDEP */
#define DRA7XX_WKUPDEP_MCASP1_DMA_SDMA_SHIFT                    13
#define DRA7XX_WKUPDEP_MCASP1_DMA_SDMA_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP1_DMA_SDMA_MASK                     (1 << 13)

/* Used by PM_IPU_MCASP1_WKDEP */
#define DRA7XX_WKUPDEP_MCASP1_IRQ_DSP1_SHIFT                    2
#define DRA7XX_WKUPDEP_MCASP1_IRQ_DSP1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP1_IRQ_DSP1_MASK                     (1 << 2)

/* Used by PM_IPU_MCASP1_WKDEP */
#define DRA7XX_WKUPDEP_MCASP1_IRQ_DSP2_SHIFT                    5
#define DRA7XX_WKUPDEP_MCASP1_IRQ_DSP2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP1_IRQ_DSP2_MASK                     (1 << 5)

/* Used by PM_IPU_MCASP1_WKDEP */
#define DRA7XX_WKUPDEP_MCASP1_IRQ_EVE1_SHIFT                    6
#define DRA7XX_WKUPDEP_MCASP1_IRQ_EVE1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP1_IRQ_EVE1_MASK                     (1 << 6)

/* Used by PM_IPU_MCASP1_WKDEP */
#define DRA7XX_WKUPDEP_MCASP1_IRQ_EVE2_SHIFT                    7
#define DRA7XX_WKUPDEP_MCASP1_IRQ_EVE2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP1_IRQ_EVE2_MASK                     (1 << 7)

/* Used by PM_IPU_MCASP1_WKDEP */
#define DRA7XX_WKUPDEP_MCASP1_IRQ_EVE3_SHIFT                    8
#define DRA7XX_WKUPDEP_MCASP1_IRQ_EVE3_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP1_IRQ_EVE3_MASK                     (1 << 8)

/* Used by PM_IPU_MCASP1_WKDEP */
#define DRA7XX_WKUPDEP_MCASP1_IRQ_EVE4_SHIFT                    9
#define DRA7XX_WKUPDEP_MCASP1_IRQ_EVE4_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP1_IRQ_EVE4_MASK                     (1 << 9)

/* Used by PM_IPU_MCASP1_WKDEP */
#define DRA7XX_WKUPDEP_MCASP1_IRQ_IPU1_SHIFT                    4
#define DRA7XX_WKUPDEP_MCASP1_IRQ_IPU1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP1_IRQ_IPU1_MASK                     (1 << 4)

/* Used by PM_IPU_MCASP1_WKDEP */
#define DRA7XX_WKUPDEP_MCASP1_IRQ_IPU2_SHIFT                    1
#define DRA7XX_WKUPDEP_MCASP1_IRQ_IPU2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP1_IRQ_IPU2_MASK                     (1 << 1)

/* Used by PM_IPU_MCASP1_WKDEP */
#define DRA7XX_WKUPDEP_MCASP1_IRQ_MPU_SHIFT                     0
#define DRA7XX_WKUPDEP_MCASP1_IRQ_MPU_WIDTH                     0x1
#define DRA7XX_WKUPDEP_MCASP1_IRQ_MPU_MASK                      (1 << 0)

/* Used by PM_L4PER2_MCASP2_WKDEP */
#define DRA7XX_WKUPDEP_MCASP2_DMA_DSP1_SHIFT                    12
#define DRA7XX_WKUPDEP_MCASP2_DMA_DSP1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP2_DMA_DSP1_MASK                     (1 << 12)

/* Used by PM_L4PER2_MCASP2_WKDEP */
#define DRA7XX_WKUPDEP_MCASP2_DMA_DSP2_SHIFT                    15
#define DRA7XX_WKUPDEP_MCASP2_DMA_DSP2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP2_DMA_DSP2_MASK                     (1 << 15)

/* Used by PM_L4PER2_MCASP2_WKDEP */
#define DRA7XX_WKUPDEP_MCASP2_DMA_SDMA_SHIFT                    13
#define DRA7XX_WKUPDEP_MCASP2_DMA_SDMA_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP2_DMA_SDMA_MASK                     (1 << 13)

/* Used by PM_L4PER2_MCASP2_WKDEP */
#define DRA7XX_WKUPDEP_MCASP2_IRQ_DSP1_SHIFT                    2
#define DRA7XX_WKUPDEP_MCASP2_IRQ_DSP1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP2_IRQ_DSP1_MASK                     (1 << 2)

/* Used by PM_L4PER2_MCASP2_WKDEP */
#define DRA7XX_WKUPDEP_MCASP2_IRQ_DSP2_SHIFT                    5
#define DRA7XX_WKUPDEP_MCASP2_IRQ_DSP2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP2_IRQ_DSP2_MASK                     (1 << 5)

/* Used by PM_L4PER2_MCASP2_WKDEP */
#define DRA7XX_WKUPDEP_MCASP2_IRQ_EVE1_SHIFT                    6
#define DRA7XX_WKUPDEP_MCASP2_IRQ_EVE1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP2_IRQ_EVE1_MASK                     (1 << 6)

/* Used by PM_L4PER2_MCASP2_WKDEP */
#define DRA7XX_WKUPDEP_MCASP2_IRQ_EVE2_SHIFT                    7
#define DRA7XX_WKUPDEP_MCASP2_IRQ_EVE2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP2_IRQ_EVE2_MASK                     (1 << 7)

/* Used by PM_L4PER2_MCASP2_WKDEP */
#define DRA7XX_WKUPDEP_MCASP2_IRQ_EVE3_SHIFT                    8
#define DRA7XX_WKUPDEP_MCASP2_IRQ_EVE3_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP2_IRQ_EVE3_MASK                     (1 << 8)

/* Used by PM_L4PER2_MCASP2_WKDEP */
#define DRA7XX_WKUPDEP_MCASP2_IRQ_EVE4_SHIFT                    9
#define DRA7XX_WKUPDEP_MCASP2_IRQ_EVE4_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP2_IRQ_EVE4_MASK                     (1 << 9)

/* Used by PM_L4PER2_MCASP2_WKDEP */
#define DRA7XX_WKUPDEP_MCASP2_IRQ_IPU1_SHIFT                    4
#define DRA7XX_WKUPDEP_MCASP2_IRQ_IPU1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP2_IRQ_IPU1_MASK                     (1 << 4)

/* Used by PM_L4PER2_MCASP2_WKDEP */
#define DRA7XX_WKUPDEP_MCASP2_IRQ_IPU2_SHIFT                    1
#define DRA7XX_WKUPDEP_MCASP2_IRQ_IPU2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP2_IRQ_IPU2_MASK                     (1 << 1)

/* Used by PM_L4PER2_MCASP2_WKDEP */
#define DRA7XX_WKUPDEP_MCASP2_IRQ_MPU_SHIFT                     0
#define DRA7XX_WKUPDEP_MCASP2_IRQ_MPU_WIDTH                     0x1
#define DRA7XX_WKUPDEP_MCASP2_IRQ_MPU_MASK                      (1 << 0)

/* Used by PM_L4PER2_MCASP3_WKDEP */
#define DRA7XX_WKUPDEP_MCASP3_DMA_DSP1_SHIFT                    12
#define DRA7XX_WKUPDEP_MCASP3_DMA_DSP1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP3_DMA_DSP1_MASK                     (1 << 12)

/* Used by PM_L4PER2_MCASP3_WKDEP */
#define DRA7XX_WKUPDEP_MCASP3_DMA_DSP2_SHIFT                    15
#define DRA7XX_WKUPDEP_MCASP3_DMA_DSP2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP3_DMA_DSP2_MASK                     (1 << 15)

/* Used by PM_L4PER2_MCASP3_WKDEP */
#define DRA7XX_WKUPDEP_MCASP3_DMA_SDMA_SHIFT                    13
#define DRA7XX_WKUPDEP_MCASP3_DMA_SDMA_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP3_DMA_SDMA_MASK                     (1 << 13)

/* Used by PM_L4PER2_MCASP3_WKDEP */
#define DRA7XX_WKUPDEP_MCASP3_IRQ_DSP1_SHIFT                    2
#define DRA7XX_WKUPDEP_MCASP3_IRQ_DSP1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP3_IRQ_DSP1_MASK                     (1 << 2)

/* Used by PM_L4PER2_MCASP3_WKDEP */
#define DRA7XX_WKUPDEP_MCASP3_IRQ_DSP2_SHIFT                    5
#define DRA7XX_WKUPDEP_MCASP3_IRQ_DSP2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP3_IRQ_DSP2_MASK                     (1 << 5)

/* Used by PM_L4PER2_MCASP3_WKDEP */
#define DRA7XX_WKUPDEP_MCASP3_IRQ_EVE1_SHIFT                    6
#define DRA7XX_WKUPDEP_MCASP3_IRQ_EVE1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP3_IRQ_EVE1_MASK                     (1 << 6)

/* Used by PM_L4PER2_MCASP3_WKDEP */
#define DRA7XX_WKUPDEP_MCASP3_IRQ_EVE2_SHIFT                    7
#define DRA7XX_WKUPDEP_MCASP3_IRQ_EVE2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP3_IRQ_EVE2_MASK                     (1 << 7)

/* Used by PM_L4PER2_MCASP3_WKDEP */
#define DRA7XX_WKUPDEP_MCASP3_IRQ_EVE3_SHIFT                    8
#define DRA7XX_WKUPDEP_MCASP3_IRQ_EVE3_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP3_IRQ_EVE3_MASK                     (1 << 8)

/* Used by PM_L4PER2_MCASP3_WKDEP */
#define DRA7XX_WKUPDEP_MCASP3_IRQ_EVE4_SHIFT                    9
#define DRA7XX_WKUPDEP_MCASP3_IRQ_EVE4_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP3_IRQ_EVE4_MASK                     (1 << 9)

/* Used by PM_L4PER2_MCASP3_WKDEP */
#define DRA7XX_WKUPDEP_MCASP3_IRQ_IPU1_SHIFT                    4
#define DRA7XX_WKUPDEP_MCASP3_IRQ_IPU1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP3_IRQ_IPU1_MASK                     (1 << 4)

/* Used by PM_L4PER2_MCASP3_WKDEP */
#define DRA7XX_WKUPDEP_MCASP3_IRQ_IPU2_SHIFT                    1
#define DRA7XX_WKUPDEP_MCASP3_IRQ_IPU2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP3_IRQ_IPU2_MASK                     (1 << 1)

/* Used by PM_L4PER2_MCASP3_WKDEP */
#define DRA7XX_WKUPDEP_MCASP3_IRQ_MPU_SHIFT                     0
#define DRA7XX_WKUPDEP_MCASP3_IRQ_MPU_WIDTH                     0x1
#define DRA7XX_WKUPDEP_MCASP3_IRQ_MPU_MASK                      (1 << 0)

/* Used by PM_L4PER2_MCASP4_WKDEP */
#define DRA7XX_WKUPDEP_MCASP4_DMA_DSP1_SHIFT                    12
#define DRA7XX_WKUPDEP_MCASP4_DMA_DSP1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP4_DMA_DSP1_MASK                     (1 << 12)

/* Used by PM_L4PER2_MCASP4_WKDEP */
#define DRA7XX_WKUPDEP_MCASP4_DMA_DSP2_SHIFT                    15
#define DRA7XX_WKUPDEP_MCASP4_DMA_DSP2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP4_DMA_DSP2_MASK                     (1 << 15)

/* Used by PM_L4PER2_MCASP4_WKDEP */
#define DRA7XX_WKUPDEP_MCASP4_DMA_SDMA_SHIFT                    13
#define DRA7XX_WKUPDEP_MCASP4_DMA_SDMA_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP4_DMA_SDMA_MASK                     (1 << 13)

/* Used by PM_L4PER2_MCASP4_WKDEP */
#define DRA7XX_WKUPDEP_MCASP4_IRQ_DSP1_SHIFT                    2
#define DRA7XX_WKUPDEP_MCASP4_IRQ_DSP1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP4_IRQ_DSP1_MASK                     (1 << 2)

/* Used by PM_L4PER2_MCASP4_WKDEP */
#define DRA7XX_WKUPDEP_MCASP4_IRQ_DSP2_SHIFT                    5
#define DRA7XX_WKUPDEP_MCASP4_IRQ_DSP2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP4_IRQ_DSP2_MASK                     (1 << 5)

/* Used by PM_L4PER2_MCASP4_WKDEP */
#define DRA7XX_WKUPDEP_MCASP4_IRQ_EVE1_SHIFT                    6
#define DRA7XX_WKUPDEP_MCASP4_IRQ_EVE1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP4_IRQ_EVE1_MASK                     (1 << 6)

/* Used by PM_L4PER2_MCASP4_WKDEP */
#define DRA7XX_WKUPDEP_MCASP4_IRQ_EVE2_SHIFT                    7
#define DRA7XX_WKUPDEP_MCASP4_IRQ_EVE2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP4_IRQ_EVE2_MASK                     (1 << 7)

/* Used by PM_L4PER2_MCASP4_WKDEP */
#define DRA7XX_WKUPDEP_MCASP4_IRQ_EVE3_SHIFT                    8
#define DRA7XX_WKUPDEP_MCASP4_IRQ_EVE3_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP4_IRQ_EVE3_MASK                     (1 << 8)

/* Used by PM_L4PER2_MCASP4_WKDEP */
#define DRA7XX_WKUPDEP_MCASP4_IRQ_EVE4_SHIFT                    9
#define DRA7XX_WKUPDEP_MCASP4_IRQ_EVE4_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP4_IRQ_EVE4_MASK                     (1 << 9)

/* Used by PM_L4PER2_MCASP4_WKDEP */
#define DRA7XX_WKUPDEP_MCASP4_IRQ_IPU1_SHIFT                    4
#define DRA7XX_WKUPDEP_MCASP4_IRQ_IPU1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP4_IRQ_IPU1_MASK                     (1 << 4)

/* Used by PM_L4PER2_MCASP4_WKDEP */
#define DRA7XX_WKUPDEP_MCASP4_IRQ_IPU2_SHIFT                    1
#define DRA7XX_WKUPDEP_MCASP4_IRQ_IPU2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP4_IRQ_IPU2_MASK                     (1 << 1)

/* Used by PM_L4PER2_MCASP4_WKDEP */
#define DRA7XX_WKUPDEP_MCASP4_IRQ_MPU_SHIFT                     0
#define DRA7XX_WKUPDEP_MCASP4_IRQ_MPU_WIDTH                     0x1
#define DRA7XX_WKUPDEP_MCASP4_IRQ_MPU_MASK                      (1 << 0)

/* Used by PM_L4PER2_MCASP5_WKDEP */
#define DRA7XX_WKUPDEP_MCASP5_DMA_DSP1_SHIFT                    12
#define DRA7XX_WKUPDEP_MCASP5_DMA_DSP1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP5_DMA_DSP1_MASK                     (1 << 12)

/* Used by PM_L4PER2_MCASP5_WKDEP */
#define DRA7XX_WKUPDEP_MCASP5_DMA_DSP2_SHIFT                    15
#define DRA7XX_WKUPDEP_MCASP5_DMA_DSP2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP5_DMA_DSP2_MASK                     (1 << 15)

/* Used by PM_L4PER2_MCASP5_WKDEP */
#define DRA7XX_WKUPDEP_MCASP5_DMA_SDMA_SHIFT                    13
#define DRA7XX_WKUPDEP_MCASP5_DMA_SDMA_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP5_DMA_SDMA_MASK                     (1 << 13)

/* Used by PM_L4PER2_MCASP5_WKDEP */
#define DRA7XX_WKUPDEP_MCASP5_IRQ_DSP1_SHIFT                    2
#define DRA7XX_WKUPDEP_MCASP5_IRQ_DSP1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP5_IRQ_DSP1_MASK                     (1 << 2)

/* Used by PM_L4PER2_MCASP5_WKDEP */
#define DRA7XX_WKUPDEP_MCASP5_IRQ_DSP2_SHIFT                    5
#define DRA7XX_WKUPDEP_MCASP5_IRQ_DSP2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP5_IRQ_DSP2_MASK                     (1 << 5)

/* Used by PM_L4PER2_MCASP5_WKDEP */
#define DRA7XX_WKUPDEP_MCASP5_IRQ_EVE1_SHIFT                    6
#define DRA7XX_WKUPDEP_MCASP5_IRQ_EVE1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP5_IRQ_EVE1_MASK                     (1 << 6)

/* Used by PM_L4PER2_MCASP5_WKDEP */
#define DRA7XX_WKUPDEP_MCASP5_IRQ_EVE2_SHIFT                    7
#define DRA7XX_WKUPDEP_MCASP5_IRQ_EVE2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP5_IRQ_EVE2_MASK                     (1 << 7)

/* Used by PM_L4PER2_MCASP5_WKDEP */
#define DRA7XX_WKUPDEP_MCASP5_IRQ_EVE3_SHIFT                    8
#define DRA7XX_WKUPDEP_MCASP5_IRQ_EVE3_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP5_IRQ_EVE3_MASK                     (1 << 8)

/* Used by PM_L4PER2_MCASP5_WKDEP */
#define DRA7XX_WKUPDEP_MCASP5_IRQ_EVE4_SHIFT                    9
#define DRA7XX_WKUPDEP_MCASP5_IRQ_EVE4_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP5_IRQ_EVE4_MASK                     (1 << 9)

/* Used by PM_L4PER2_MCASP5_WKDEP */
#define DRA7XX_WKUPDEP_MCASP5_IRQ_IPU1_SHIFT                    4
#define DRA7XX_WKUPDEP_MCASP5_IRQ_IPU1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP5_IRQ_IPU1_MASK                     (1 << 4)

/* Used by PM_L4PER2_MCASP5_WKDEP */
#define DRA7XX_WKUPDEP_MCASP5_IRQ_IPU2_SHIFT                    1
#define DRA7XX_WKUPDEP_MCASP5_IRQ_IPU2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP5_IRQ_IPU2_MASK                     (1 << 1)

/* Used by PM_L4PER2_MCASP5_WKDEP */
#define DRA7XX_WKUPDEP_MCASP5_IRQ_MPU_SHIFT                     0
#define DRA7XX_WKUPDEP_MCASP5_IRQ_MPU_WIDTH                     0x1
#define DRA7XX_WKUPDEP_MCASP5_IRQ_MPU_MASK                      (1 << 0)

/* Used by PM_L4PER2_MCASP6_WKDEP */
#define DRA7XX_WKUPDEP_MCASP6_DMA_DSP1_SHIFT                    12
#define DRA7XX_WKUPDEP_MCASP6_DMA_DSP1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP6_DMA_DSP1_MASK                     (1 << 12)

/* Used by PM_L4PER2_MCASP6_WKDEP */
#define DRA7XX_WKUPDEP_MCASP6_DMA_DSP2_SHIFT                    15
#define DRA7XX_WKUPDEP_MCASP6_DMA_DSP2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP6_DMA_DSP2_MASK                     (1 << 15)

/* Used by PM_L4PER2_MCASP6_WKDEP */
#define DRA7XX_WKUPDEP_MCASP6_DMA_SDMA_SHIFT                    13
#define DRA7XX_WKUPDEP_MCASP6_DMA_SDMA_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP6_DMA_SDMA_MASK                     (1 << 13)

/* Used by PM_L4PER2_MCASP6_WKDEP */
#define DRA7XX_WKUPDEP_MCASP6_IRQ_DSP1_SHIFT                    2
#define DRA7XX_WKUPDEP_MCASP6_IRQ_DSP1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP6_IRQ_DSP1_MASK                     (1 << 2)

/* Used by PM_L4PER2_MCASP6_WKDEP */
#define DRA7XX_WKUPDEP_MCASP6_IRQ_DSP2_SHIFT                    5
#define DRA7XX_WKUPDEP_MCASP6_IRQ_DSP2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP6_IRQ_DSP2_MASK                     (1 << 5)

/* Used by PM_L4PER2_MCASP6_WKDEP */
#define DRA7XX_WKUPDEP_MCASP6_IRQ_EVE1_SHIFT                    6
#define DRA7XX_WKUPDEP_MCASP6_IRQ_EVE1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP6_IRQ_EVE1_MASK                     (1 << 6)

/* Used by PM_L4PER2_MCASP6_WKDEP */
#define DRA7XX_WKUPDEP_MCASP6_IRQ_EVE2_SHIFT                    7
#define DRA7XX_WKUPDEP_MCASP6_IRQ_EVE2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP6_IRQ_EVE2_MASK                     (1 << 7)

/* Used by PM_L4PER2_MCASP6_WKDEP */
#define DRA7XX_WKUPDEP_MCASP6_IRQ_EVE3_SHIFT                    8
#define DRA7XX_WKUPDEP_MCASP6_IRQ_EVE3_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP6_IRQ_EVE3_MASK                     (1 << 8)

/* Used by PM_L4PER2_MCASP6_WKDEP */
#define DRA7XX_WKUPDEP_MCASP6_IRQ_EVE4_SHIFT                    9
#define DRA7XX_WKUPDEP_MCASP6_IRQ_EVE4_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP6_IRQ_EVE4_MASK                     (1 << 9)

/* Used by PM_L4PER2_MCASP6_WKDEP */
#define DRA7XX_WKUPDEP_MCASP6_IRQ_IPU1_SHIFT                    4
#define DRA7XX_WKUPDEP_MCASP6_IRQ_IPU1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP6_IRQ_IPU1_MASK                     (1 << 4)

/* Used by PM_L4PER2_MCASP6_WKDEP */
#define DRA7XX_WKUPDEP_MCASP6_IRQ_IPU2_SHIFT                    1
#define DRA7XX_WKUPDEP_MCASP6_IRQ_IPU2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP6_IRQ_IPU2_MASK                     (1 << 1)

/* Used by PM_L4PER2_MCASP6_WKDEP */
#define DRA7XX_WKUPDEP_MCASP6_IRQ_MPU_SHIFT                     0
#define DRA7XX_WKUPDEP_MCASP6_IRQ_MPU_WIDTH                     0x1
#define DRA7XX_WKUPDEP_MCASP6_IRQ_MPU_MASK                      (1 << 0)

/* Used by PM_L4PER2_MCASP7_WKDEP */
#define DRA7XX_WKUPDEP_MCASP7_DMA_DSP1_SHIFT                    12
#define DRA7XX_WKUPDEP_MCASP7_DMA_DSP1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP7_DMA_DSP1_MASK                     (1 << 12)

/* Used by PM_L4PER2_MCASP7_WKDEP */
#define DRA7XX_WKUPDEP_MCASP7_DMA_DSP2_SHIFT                    15
#define DRA7XX_WKUPDEP_MCASP7_DMA_DSP2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP7_DMA_DSP2_MASK                     (1 << 15)

/* Used by PM_L4PER2_MCASP7_WKDEP */
#define DRA7XX_WKUPDEP_MCASP7_DMA_SDMA_SHIFT                    13
#define DRA7XX_WKUPDEP_MCASP7_DMA_SDMA_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP7_DMA_SDMA_MASK                     (1 << 13)

/* Used by PM_L4PER2_MCASP7_WKDEP */
#define DRA7XX_WKUPDEP_MCASP7_IRQ_DSP1_SHIFT                    2
#define DRA7XX_WKUPDEP_MCASP7_IRQ_DSP1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP7_IRQ_DSP1_MASK                     (1 << 2)

/* Used by PM_L4PER2_MCASP7_WKDEP */
#define DRA7XX_WKUPDEP_MCASP7_IRQ_DSP2_SHIFT                    5
#define DRA7XX_WKUPDEP_MCASP7_IRQ_DSP2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP7_IRQ_DSP2_MASK                     (1 << 5)

/* Used by PM_L4PER2_MCASP7_WKDEP */
#define DRA7XX_WKUPDEP_MCASP7_IRQ_EVE1_SHIFT                    6
#define DRA7XX_WKUPDEP_MCASP7_IRQ_EVE1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP7_IRQ_EVE1_MASK                     (1 << 6)

/* Used by PM_L4PER2_MCASP7_WKDEP */
#define DRA7XX_WKUPDEP_MCASP7_IRQ_EVE2_SHIFT                    7
#define DRA7XX_WKUPDEP_MCASP7_IRQ_EVE2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP7_IRQ_EVE2_MASK                     (1 << 7)

/* Used by PM_L4PER2_MCASP7_WKDEP */
#define DRA7XX_WKUPDEP_MCASP7_IRQ_EVE3_SHIFT                    8
#define DRA7XX_WKUPDEP_MCASP7_IRQ_EVE3_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP7_IRQ_EVE3_MASK                     (1 << 8)

/* Used by PM_L4PER2_MCASP7_WKDEP */
#define DRA7XX_WKUPDEP_MCASP7_IRQ_EVE4_SHIFT                    9
#define DRA7XX_WKUPDEP_MCASP7_IRQ_EVE4_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP7_IRQ_EVE4_MASK                     (1 << 9)

/* Used by PM_L4PER2_MCASP7_WKDEP */
#define DRA7XX_WKUPDEP_MCASP7_IRQ_IPU1_SHIFT                    4
#define DRA7XX_WKUPDEP_MCASP7_IRQ_IPU1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP7_IRQ_IPU1_MASK                     (1 << 4)

/* Used by PM_L4PER2_MCASP7_WKDEP */
#define DRA7XX_WKUPDEP_MCASP7_IRQ_IPU2_SHIFT                    1
#define DRA7XX_WKUPDEP_MCASP7_IRQ_IPU2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP7_IRQ_IPU2_MASK                     (1 << 1)

/* Used by PM_L4PER2_MCASP7_WKDEP */
#define DRA7XX_WKUPDEP_MCASP7_IRQ_MPU_SHIFT                     0
#define DRA7XX_WKUPDEP_MCASP7_IRQ_MPU_WIDTH                     0x1
#define DRA7XX_WKUPDEP_MCASP7_IRQ_MPU_MASK                      (1 << 0)

/* Used by PM_L4PER2_MCASP8_WKDEP */
#define DRA7XX_WKUPDEP_MCASP8_DMA_DSP1_SHIFT                    12
#define DRA7XX_WKUPDEP_MCASP8_DMA_DSP1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP8_DMA_DSP1_MASK                     (1 << 12)

/* Used by PM_L4PER2_MCASP8_WKDEP */
#define DRA7XX_WKUPDEP_MCASP8_DMA_DSP2_SHIFT                    15
#define DRA7XX_WKUPDEP_MCASP8_DMA_DSP2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP8_DMA_DSP2_MASK                     (1 << 15)

/* Used by PM_L4PER2_MCASP8_WKDEP */
#define DRA7XX_WKUPDEP_MCASP8_DMA_SDMA_SHIFT                    13
#define DRA7XX_WKUPDEP_MCASP8_DMA_SDMA_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP8_DMA_SDMA_MASK                     (1 << 13)

/* Used by PM_L4PER2_MCASP8_WKDEP */
#define DRA7XX_WKUPDEP_MCASP8_IRQ_DSP1_SHIFT                    2
#define DRA7XX_WKUPDEP_MCASP8_IRQ_DSP1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP8_IRQ_DSP1_MASK                     (1 << 2)

/* Used by PM_L4PER2_MCASP8_WKDEP */
#define DRA7XX_WKUPDEP_MCASP8_IRQ_DSP2_SHIFT                    5
#define DRA7XX_WKUPDEP_MCASP8_IRQ_DSP2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP8_IRQ_DSP2_MASK                     (1 << 5)

/* Used by PM_L4PER2_MCASP8_WKDEP */
#define DRA7XX_WKUPDEP_MCASP8_IRQ_EVE1_SHIFT                    6
#define DRA7XX_WKUPDEP_MCASP8_IRQ_EVE1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP8_IRQ_EVE1_MASK                     (1 << 6)

/* Used by PM_L4PER2_MCASP8_WKDEP */
#define DRA7XX_WKUPDEP_MCASP8_IRQ_EVE2_SHIFT                    7
#define DRA7XX_WKUPDEP_MCASP8_IRQ_EVE2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP8_IRQ_EVE2_MASK                     (1 << 7)

/* Used by PM_L4PER2_MCASP8_WKDEP */
#define DRA7XX_WKUPDEP_MCASP8_IRQ_EVE3_SHIFT                    8
#define DRA7XX_WKUPDEP_MCASP8_IRQ_EVE3_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP8_IRQ_EVE3_MASK                     (1 << 8)

/* Used by PM_L4PER2_MCASP8_WKDEP */
#define DRA7XX_WKUPDEP_MCASP8_IRQ_EVE4_SHIFT                    9
#define DRA7XX_WKUPDEP_MCASP8_IRQ_EVE4_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP8_IRQ_EVE4_MASK                     (1 << 9)

/* Used by PM_L4PER2_MCASP8_WKDEP */
#define DRA7XX_WKUPDEP_MCASP8_IRQ_IPU1_SHIFT                    4
#define DRA7XX_WKUPDEP_MCASP8_IRQ_IPU1_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP8_IRQ_IPU1_MASK                     (1 << 4)

/* Used by PM_L4PER2_MCASP8_WKDEP */
#define DRA7XX_WKUPDEP_MCASP8_IRQ_IPU2_SHIFT                    1
#define DRA7XX_WKUPDEP_MCASP8_IRQ_IPU2_WIDTH                    0x1
#define DRA7XX_WKUPDEP_MCASP8_IRQ_IPU2_MASK                     (1 << 1)

/* Used by PM_L4PER2_MCASP8_WKDEP */
#define DRA7XX_WKUPDEP_MCASP8_IRQ_MPU_SHIFT                     0
#define DRA7XX_WKUPDEP_MCASP8_IRQ_MPU_WIDTH                     0x1
#define DRA7XX_WKUPDEP_MCASP8_IRQ_MPU_MASK                      (1 << 0)

/* Used by PM_L4PER_MCSPI1_WKDEP */
#define DRA7XX_WKUPDEP_MCSPI1_DSP1_SHIFT                        2
#define DRA7XX_WKUPDEP_MCSPI1_DSP1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_MCSPI1_DSP1_MASK                         (1 << 2)

/* Used by PM_L4PER_MCSPI1_WKDEP */
#define DRA7XX_WKUPDEP_MCSPI1_DSP2_SHIFT                        5
#define DRA7XX_WKUPDEP_MCSPI1_DSP2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_MCSPI1_DSP2_MASK                         (1 << 5)

/* Used by PM_L4PER_MCSPI1_WKDEP */
#define DRA7XX_WKUPDEP_MCSPI1_EVE1_SHIFT                        6
#define DRA7XX_WKUPDEP_MCSPI1_EVE1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_MCSPI1_EVE1_MASK                         (1 << 6)

/* Used by PM_L4PER_MCSPI1_WKDEP */
#define DRA7XX_WKUPDEP_MCSPI1_EVE2_SHIFT                        7
#define DRA7XX_WKUPDEP_MCSPI1_EVE2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_MCSPI1_EVE2_MASK                         (1 << 7)

/* Used by PM_L4PER_MCSPI1_WKDEP */
#define DRA7XX_WKUPDEP_MCSPI1_EVE3_SHIFT                        8
#define DRA7XX_WKUPDEP_MCSPI1_EVE3_WIDTH                        0x1
#define DRA7XX_WKUPDEP_MCSPI1_EVE3_MASK                         (1 << 8)

/* Used by PM_L4PER_MCSPI1_WKDEP */
#define DRA7XX_WKUPDEP_MCSPI1_EVE4_SHIFT                        9
#define DRA7XX_WKUPDEP_MCSPI1_EVE4_WIDTH                        0x1
#define DRA7XX_WKUPDEP_MCSPI1_EVE4_MASK                         (1 << 9)

/* Used by PM_L4PER_MCSPI1_WKDEP */
#define DRA7XX_WKUPDEP_MCSPI1_IPU1_SHIFT                        4
#define DRA7XX_WKUPDEP_MCSPI1_IPU1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_MCSPI1_IPU1_MASK                         (1 << 4)

/* Used by PM_L4PER_MCSPI1_WKDEP */
#define DRA7XX_WKUPDEP_MCSPI1_IPU2_SHIFT                        1
#define DRA7XX_WKUPDEP_MCSPI1_IPU2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_MCSPI1_IPU2_MASK                         (1 << 1)

/* Used by PM_L4PER_MCSPI1_WKDEP */
#define DRA7XX_WKUPDEP_MCSPI1_MPU_SHIFT                         0
#define DRA7XX_WKUPDEP_MCSPI1_MPU_WIDTH                         0x1
#define DRA7XX_WKUPDEP_MCSPI1_MPU_MASK                          (1 << 0)

/* Used by PM_L4PER_MCSPI1_WKDEP */
#define DRA7XX_WKUPDEP_MCSPI1_SDMA_SHIFT                        3
#define DRA7XX_WKUPDEP_MCSPI1_SDMA_WIDTH                        0x1
#define DRA7XX_WKUPDEP_MCSPI1_SDMA_MASK                         (1 << 3)

/* Used by PM_L4PER_MCSPI2_WKDEP */
#define DRA7XX_WKUPDEP_MCSPI2_DSP1_SHIFT                        2
#define DRA7XX_WKUPDEP_MCSPI2_DSP1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_MCSPI2_DSP1_MASK                         (1 << 2)

/* Used by PM_L4PER_MCSPI2_WKDEP */
#define DRA7XX_WKUPDEP_MCSPI2_DSP2_SHIFT                        5
#define DRA7XX_WKUPDEP_MCSPI2_DSP2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_MCSPI2_DSP2_MASK                         (1 << 5)

/* Used by PM_L4PER_MCSPI2_WKDEP */
#define DRA7XX_WKUPDEP_MCSPI2_EVE1_SHIFT                        6
#define DRA7XX_WKUPDEP_MCSPI2_EVE1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_MCSPI2_EVE1_MASK                         (1 << 6)

/* Used by PM_L4PER_MCSPI2_WKDEP */
#define DRA7XX_WKUPDEP_MCSPI2_EVE2_SHIFT                        7
#define DRA7XX_WKUPDEP_MCSPI2_EVE2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_MCSPI2_EVE2_MASK                         (1 << 7)

/* Used by PM_L4PER_MCSPI2_WKDEP */
#define DRA7XX_WKUPDEP_MCSPI2_EVE3_SHIFT                        8
#define DRA7XX_WKUPDEP_MCSPI2_EVE3_WIDTH                        0x1
#define DRA7XX_WKUPDEP_MCSPI2_EVE3_MASK                         (1 << 8)

/* Used by PM_L4PER_MCSPI2_WKDEP */
#define DRA7XX_WKUPDEP_MCSPI2_EVE4_SHIFT                        9
#define DRA7XX_WKUPDEP_MCSPI2_EVE4_WIDTH                        0x1
#define DRA7XX_WKUPDEP_MCSPI2_EVE4_MASK                         (1 << 9)

/* Used by PM_L4PER_MCSPI2_WKDEP */
#define DRA7XX_WKUPDEP_MCSPI2_IPU1_SHIFT                        4
#define DRA7XX_WKUPDEP_MCSPI2_IPU1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_MCSPI2_IPU1_MASK                         (1 << 4)

/* Used by PM_L4PER_MCSPI2_WKDEP */
#define DRA7XX_WKUPDEP_MCSPI2_IPU2_SHIFT                        1
#define DRA7XX_WKUPDEP_MCSPI2_IPU2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_MCSPI2_IPU2_MASK                         (1 << 1)

/* Used by PM_L4PER_MCSPI2_WKDEP */
#define DRA7XX_WKUPDEP_MCSPI2_MPU_SHIFT                         0
#define DRA7XX_WKUPDEP_MCSPI2_MPU_WIDTH                         0x1
#define DRA7XX_WKUPDEP_MCSPI2_MPU_MASK                          (1 << 0)

/* Used by PM_L4PER_MCSPI2_WKDEP */
#define DRA7XX_WKUPDEP_MCSPI2_SDMA_SHIFT                        3
#define DRA7XX_WKUPDEP_MCSPI2_SDMA_WIDTH                        0x1
#define DRA7XX_WKUPDEP_MCSPI2_SDMA_MASK                         (1 << 3)

/* Used by PM_L4PER_MCSPI3_WKDEP */
#define DRA7XX_WKUPDEP_MCSPI3_DSP1_SHIFT                        2
#define DRA7XX_WKUPDEP_MCSPI3_DSP1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_MCSPI3_DSP1_MASK                         (1 << 2)

/* Used by PM_L4PER_MCSPI3_WKDEP */
#define DRA7XX_WKUPDEP_MCSPI3_DSP2_SHIFT                        5
#define DRA7XX_WKUPDEP_MCSPI3_DSP2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_MCSPI3_DSP2_MASK                         (1 << 5)

/* Used by PM_L4PER_MCSPI3_WKDEP */
#define DRA7XX_WKUPDEP_MCSPI3_EVE1_SHIFT                        6
#define DRA7XX_WKUPDEP_MCSPI3_EVE1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_MCSPI3_EVE1_MASK                         (1 << 6)

/* Used by PM_L4PER_MCSPI3_WKDEP */
#define DRA7XX_WKUPDEP_MCSPI3_EVE2_SHIFT                        7
#define DRA7XX_WKUPDEP_MCSPI3_EVE2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_MCSPI3_EVE2_MASK                         (1 << 7)

/* Used by PM_L4PER_MCSPI3_WKDEP */
#define DRA7XX_WKUPDEP_MCSPI3_EVE3_SHIFT                        8
#define DRA7XX_WKUPDEP_MCSPI3_EVE3_WIDTH                        0x1
#define DRA7XX_WKUPDEP_MCSPI3_EVE3_MASK                         (1 << 8)

/* Used by PM_L4PER_MCSPI3_WKDEP */
#define DRA7XX_WKUPDEP_MCSPI3_EVE4_SHIFT                        9
#define DRA7XX_WKUPDEP_MCSPI3_EVE4_WIDTH                        0x1
#define DRA7XX_WKUPDEP_MCSPI3_EVE4_MASK                         (1 << 9)

/* Used by PM_L4PER_MCSPI3_WKDEP */
#define DRA7XX_WKUPDEP_MCSPI3_IPU1_SHIFT                        4
#define DRA7XX_WKUPDEP_MCSPI3_IPU1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_MCSPI3_IPU1_MASK                         (1 << 4)

/* Used by PM_L4PER_MCSPI3_WKDEP */
#define DRA7XX_WKUPDEP_MCSPI3_IPU2_SHIFT                        1
#define DRA7XX_WKUPDEP_MCSPI3_IPU2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_MCSPI3_IPU2_MASK                         (1 << 1)

/* Used by PM_L4PER_MCSPI3_WKDEP */
#define DRA7XX_WKUPDEP_MCSPI3_MPU_SHIFT                         0
#define DRA7XX_WKUPDEP_MCSPI3_MPU_WIDTH                         0x1
#define DRA7XX_WKUPDEP_MCSPI3_MPU_MASK                          (1 << 0)

/* Used by PM_L4PER_MCSPI3_WKDEP */
#define DRA7XX_WKUPDEP_MCSPI3_SDMA_SHIFT                        3
#define DRA7XX_WKUPDEP_MCSPI3_SDMA_WIDTH                        0x1
#define DRA7XX_WKUPDEP_MCSPI3_SDMA_MASK                         (1 << 3)

/* Used by PM_L4PER_MCSPI4_WKDEP */
#define DRA7XX_WKUPDEP_MCSPI4_DSP1_SHIFT                        2
#define DRA7XX_WKUPDEP_MCSPI4_DSP1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_MCSPI4_DSP1_MASK                         (1 << 2)

/* Used by PM_L4PER_MCSPI4_WKDEP */
#define DRA7XX_WKUPDEP_MCSPI4_DSP2_SHIFT                        5
#define DRA7XX_WKUPDEP_MCSPI4_DSP2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_MCSPI4_DSP2_MASK                         (1 << 5)

/* Used by PM_L4PER_MCSPI4_WKDEP */
#define DRA7XX_WKUPDEP_MCSPI4_EVE1_SHIFT                        6
#define DRA7XX_WKUPDEP_MCSPI4_EVE1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_MCSPI4_EVE1_MASK                         (1 << 6)

/* Used by PM_L4PER_MCSPI4_WKDEP */
#define DRA7XX_WKUPDEP_MCSPI4_EVE2_SHIFT                        7
#define DRA7XX_WKUPDEP_MCSPI4_EVE2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_MCSPI4_EVE2_MASK                         (1 << 7)

/* Used by PM_L4PER_MCSPI4_WKDEP */
#define DRA7XX_WKUPDEP_MCSPI4_EVE3_SHIFT                        8
#define DRA7XX_WKUPDEP_MCSPI4_EVE3_WIDTH                        0x1
#define DRA7XX_WKUPDEP_MCSPI4_EVE3_MASK                         (1 << 8)

/* Used by PM_L4PER_MCSPI4_WKDEP */
#define DRA7XX_WKUPDEP_MCSPI4_EVE4_SHIFT                        9
#define DRA7XX_WKUPDEP_MCSPI4_EVE4_WIDTH                        0x1
#define DRA7XX_WKUPDEP_MCSPI4_EVE4_MASK                         (1 << 9)

/* Used by PM_L4PER_MCSPI4_WKDEP */
#define DRA7XX_WKUPDEP_MCSPI4_IPU1_SHIFT                        4
#define DRA7XX_WKUPDEP_MCSPI4_IPU1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_MCSPI4_IPU1_MASK                         (1 << 4)

/* Used by PM_L4PER_MCSPI4_WKDEP */
#define DRA7XX_WKUPDEP_MCSPI4_IPU2_SHIFT                        1
#define DRA7XX_WKUPDEP_MCSPI4_IPU2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_MCSPI4_IPU2_MASK                         (1 << 1)

/* Used by PM_L4PER_MCSPI4_WKDEP */
#define DRA7XX_WKUPDEP_MCSPI4_MPU_SHIFT                         0
#define DRA7XX_WKUPDEP_MCSPI4_MPU_WIDTH                         0x1
#define DRA7XX_WKUPDEP_MCSPI4_MPU_MASK                          (1 << 0)

/* Used by PM_L4PER_MCSPI4_WKDEP */
#define DRA7XX_WKUPDEP_MCSPI4_SDMA_SHIFT                        3
#define DRA7XX_WKUPDEP_MCSPI4_SDMA_WIDTH                        0x1
#define DRA7XX_WKUPDEP_MCSPI4_SDMA_MASK                         (1 << 3)

/* Used by PM_L3INIT_MMC1_WKDEP */
#define DRA7XX_WKUPDEP_MMC1_DSP1_SHIFT                          2
#define DRA7XX_WKUPDEP_MMC1_DSP1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_MMC1_DSP1_MASK                           (1 << 2)

/* Used by PM_L3INIT_MMC1_WKDEP */
#define DRA7XX_WKUPDEP_MMC1_DSP2_SHIFT                          5
#define DRA7XX_WKUPDEP_MMC1_DSP2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_MMC1_DSP2_MASK                           (1 << 5)

/* Used by PM_L3INIT_MMC1_WKDEP */
#define DRA7XX_WKUPDEP_MMC1_EVE1_SHIFT                          6
#define DRA7XX_WKUPDEP_MMC1_EVE1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_MMC1_EVE1_MASK                           (1 << 6)

/* Used by PM_L3INIT_MMC1_WKDEP */
#define DRA7XX_WKUPDEP_MMC1_EVE2_SHIFT                          7
#define DRA7XX_WKUPDEP_MMC1_EVE2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_MMC1_EVE2_MASK                           (1 << 7)

/* Used by PM_L3INIT_MMC1_WKDEP */
#define DRA7XX_WKUPDEP_MMC1_EVE3_SHIFT                          8
#define DRA7XX_WKUPDEP_MMC1_EVE3_WIDTH                          0x1
#define DRA7XX_WKUPDEP_MMC1_EVE3_MASK                           (1 << 8)

/* Used by PM_L3INIT_MMC1_WKDEP */
#define DRA7XX_WKUPDEP_MMC1_EVE4_SHIFT                          9
#define DRA7XX_WKUPDEP_MMC1_EVE4_WIDTH                          0x1
#define DRA7XX_WKUPDEP_MMC1_EVE4_MASK                           (1 << 9)

/* Used by PM_L3INIT_MMC1_WKDEP */
#define DRA7XX_WKUPDEP_MMC1_IPU1_SHIFT                          4
#define DRA7XX_WKUPDEP_MMC1_IPU1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_MMC1_IPU1_MASK                           (1 << 4)

/* Used by PM_L3INIT_MMC1_WKDEP */
#define DRA7XX_WKUPDEP_MMC1_IPU2_SHIFT                          1
#define DRA7XX_WKUPDEP_MMC1_IPU2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_MMC1_IPU2_MASK                           (1 << 1)

/* Used by PM_L3INIT_MMC1_WKDEP */
#define DRA7XX_WKUPDEP_MMC1_MPU_SHIFT                           0
#define DRA7XX_WKUPDEP_MMC1_MPU_WIDTH                           0x1
#define DRA7XX_WKUPDEP_MMC1_MPU_MASK                            (1 << 0)

/* Used by PM_L3INIT_MMC1_WKDEP */
#define DRA7XX_WKUPDEP_MMC1_SDMA_SHIFT                          3
#define DRA7XX_WKUPDEP_MMC1_SDMA_WIDTH                          0x1
#define DRA7XX_WKUPDEP_MMC1_SDMA_MASK                           (1 << 3)

/* Used by PM_L3INIT_MMC2_WKDEP */
#define DRA7XX_WKUPDEP_MMC2_DSP1_SHIFT                          2
#define DRA7XX_WKUPDEP_MMC2_DSP1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_MMC2_DSP1_MASK                           (1 << 2)

/* Used by PM_L3INIT_MMC2_WKDEP */
#define DRA7XX_WKUPDEP_MMC2_DSP2_SHIFT                          5
#define DRA7XX_WKUPDEP_MMC2_DSP2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_MMC2_DSP2_MASK                           (1 << 5)

/* Used by PM_L3INIT_MMC2_WKDEP */
#define DRA7XX_WKUPDEP_MMC2_EVE1_SHIFT                          6
#define DRA7XX_WKUPDEP_MMC2_EVE1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_MMC2_EVE1_MASK                           (1 << 6)

/* Used by PM_L3INIT_MMC2_WKDEP */
#define DRA7XX_WKUPDEP_MMC2_EVE2_SHIFT                          7
#define DRA7XX_WKUPDEP_MMC2_EVE2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_MMC2_EVE2_MASK                           (1 << 7)

/* Used by PM_L3INIT_MMC2_WKDEP */
#define DRA7XX_WKUPDEP_MMC2_EVE3_SHIFT                          8
#define DRA7XX_WKUPDEP_MMC2_EVE3_WIDTH                          0x1
#define DRA7XX_WKUPDEP_MMC2_EVE3_MASK                           (1 << 8)

/* Used by PM_L3INIT_MMC2_WKDEP */
#define DRA7XX_WKUPDEP_MMC2_EVE4_SHIFT                          9
#define DRA7XX_WKUPDEP_MMC2_EVE4_WIDTH                          0x1
#define DRA7XX_WKUPDEP_MMC2_EVE4_MASK                           (1 << 9)

/* Used by PM_L3INIT_MMC2_WKDEP */
#define DRA7XX_WKUPDEP_MMC2_IPU1_SHIFT                          4
#define DRA7XX_WKUPDEP_MMC2_IPU1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_MMC2_IPU1_MASK                           (1 << 4)

/* Used by PM_L3INIT_MMC2_WKDEP */
#define DRA7XX_WKUPDEP_MMC2_IPU2_SHIFT                          1
#define DRA7XX_WKUPDEP_MMC2_IPU2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_MMC2_IPU2_MASK                           (1 << 1)

/* Used by PM_L3INIT_MMC2_WKDEP */
#define DRA7XX_WKUPDEP_MMC2_MPU_SHIFT                           0
#define DRA7XX_WKUPDEP_MMC2_MPU_WIDTH                           0x1
#define DRA7XX_WKUPDEP_MMC2_MPU_MASK                            (1 << 0)

/* Used by PM_L3INIT_MMC2_WKDEP */
#define DRA7XX_WKUPDEP_MMC2_SDMA_SHIFT                          3
#define DRA7XX_WKUPDEP_MMC2_SDMA_WIDTH                          0x1
#define DRA7XX_WKUPDEP_MMC2_SDMA_MASK                           (1 << 3)

/* Used by PM_L4PER_MMC3_WKDEP */
#define DRA7XX_WKUPDEP_MMC3_DSP1_SHIFT                          2
#define DRA7XX_WKUPDEP_MMC3_DSP1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_MMC3_DSP1_MASK                           (1 << 2)

/* Used by PM_L4PER_MMC3_WKDEP */
#define DRA7XX_WKUPDEP_MMC3_DSP2_SHIFT                          5
#define DRA7XX_WKUPDEP_MMC3_DSP2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_MMC3_DSP2_MASK                           (1 << 5)

/* Used by PM_L4PER_MMC3_WKDEP */
#define DRA7XX_WKUPDEP_MMC3_EVE1_SHIFT                          6
#define DRA7XX_WKUPDEP_MMC3_EVE1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_MMC3_EVE1_MASK                           (1 << 6)

/* Used by PM_L4PER_MMC3_WKDEP */
#define DRA7XX_WKUPDEP_MMC3_EVE2_SHIFT                          7
#define DRA7XX_WKUPDEP_MMC3_EVE2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_MMC3_EVE2_MASK                           (1 << 7)

/* Used by PM_L4PER_MMC3_WKDEP */
#define DRA7XX_WKUPDEP_MMC3_EVE3_SHIFT                          8
#define DRA7XX_WKUPDEP_MMC3_EVE3_WIDTH                          0x1
#define DRA7XX_WKUPDEP_MMC3_EVE3_MASK                           (1 << 8)

/* Used by PM_L4PER_MMC3_WKDEP */
#define DRA7XX_WKUPDEP_MMC3_EVE4_SHIFT                          9
#define DRA7XX_WKUPDEP_MMC3_EVE4_WIDTH                          0x1
#define DRA7XX_WKUPDEP_MMC3_EVE4_MASK                           (1 << 9)

/* Used by PM_L4PER_MMC3_WKDEP */
#define DRA7XX_WKUPDEP_MMC3_IPU1_SHIFT                          4
#define DRA7XX_WKUPDEP_MMC3_IPU1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_MMC3_IPU1_MASK                           (1 << 4)

/* Used by PM_L4PER_MMC3_WKDEP */
#define DRA7XX_WKUPDEP_MMC3_IPU2_SHIFT                          1
#define DRA7XX_WKUPDEP_MMC3_IPU2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_MMC3_IPU2_MASK                           (1 << 1)

/* Used by PM_L4PER_MMC3_WKDEP */
#define DRA7XX_WKUPDEP_MMC3_MPU_SHIFT                           0
#define DRA7XX_WKUPDEP_MMC3_MPU_WIDTH                           0x1
#define DRA7XX_WKUPDEP_MMC3_MPU_MASK                            (1 << 0)

/* Used by PM_L4PER_MMC3_WKDEP */
#define DRA7XX_WKUPDEP_MMC3_SDMA_SHIFT                          3
#define DRA7XX_WKUPDEP_MMC3_SDMA_WIDTH                          0x1
#define DRA7XX_WKUPDEP_MMC3_SDMA_MASK                           (1 << 3)

/* Used by PM_L4PER_MMC4_WKDEP */
#define DRA7XX_WKUPDEP_MMC4_DSP1_SHIFT                          2
#define DRA7XX_WKUPDEP_MMC4_DSP1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_MMC4_DSP1_MASK                           (1 << 2)

/* Used by PM_L4PER_MMC4_WKDEP */
#define DRA7XX_WKUPDEP_MMC4_DSP2_SHIFT                          5
#define DRA7XX_WKUPDEP_MMC4_DSP2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_MMC4_DSP2_MASK                           (1 << 5)

/* Used by PM_L4PER_MMC4_WKDEP */
#define DRA7XX_WKUPDEP_MMC4_EVE1_SHIFT                          6
#define DRA7XX_WKUPDEP_MMC4_EVE1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_MMC4_EVE1_MASK                           (1 << 6)

/* Used by PM_L4PER_MMC4_WKDEP */
#define DRA7XX_WKUPDEP_MMC4_EVE2_SHIFT                          7
#define DRA7XX_WKUPDEP_MMC4_EVE2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_MMC4_EVE2_MASK                           (1 << 7)

/* Used by PM_L4PER_MMC4_WKDEP */
#define DRA7XX_WKUPDEP_MMC4_EVE3_SHIFT                          8
#define DRA7XX_WKUPDEP_MMC4_EVE3_WIDTH                          0x1
#define DRA7XX_WKUPDEP_MMC4_EVE3_MASK                           (1 << 8)

/* Used by PM_L4PER_MMC4_WKDEP */
#define DRA7XX_WKUPDEP_MMC4_EVE4_SHIFT                          9
#define DRA7XX_WKUPDEP_MMC4_EVE4_WIDTH                          0x1
#define DRA7XX_WKUPDEP_MMC4_EVE4_MASK                           (1 << 9)

/* Used by PM_L4PER_MMC4_WKDEP */
#define DRA7XX_WKUPDEP_MMC4_IPU1_SHIFT                          4
#define DRA7XX_WKUPDEP_MMC4_IPU1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_MMC4_IPU1_MASK                           (1 << 4)

/* Used by PM_L4PER_MMC4_WKDEP */
#define DRA7XX_WKUPDEP_MMC4_IPU2_SHIFT                          1
#define DRA7XX_WKUPDEP_MMC4_IPU2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_MMC4_IPU2_MASK                           (1 << 1)

/* Used by PM_L4PER_MMC4_WKDEP */
#define DRA7XX_WKUPDEP_MMC4_MPU_SHIFT                           0
#define DRA7XX_WKUPDEP_MMC4_MPU_WIDTH                           0x1
#define DRA7XX_WKUPDEP_MMC4_MPU_MASK                            (1 << 0)

/* Used by PM_L4PER_MMC4_WKDEP */
#define DRA7XX_WKUPDEP_MMC4_SDMA_SHIFT                          3
#define DRA7XX_WKUPDEP_MMC4_SDMA_WIDTH                          0x1
#define DRA7XX_WKUPDEP_MMC4_SDMA_MASK                           (1 << 3)

/* Used by PM_L3MAIN1_OCMC_RAM1_WKDEP */
#define DRA7XX_WKUPDEP_OCMC_RAM1_DSP1_SHIFT                     2
#define DRA7XX_WKUPDEP_OCMC_RAM1_DSP1_WIDTH                     0x1
#define DRA7XX_WKUPDEP_OCMC_RAM1_DSP1_MASK                      (1 << 2)

/* Used by PM_L3MAIN1_OCMC_RAM1_WKDEP */
#define DRA7XX_WKUPDEP_OCMC_RAM1_DSP2_SHIFT                     5
#define DRA7XX_WKUPDEP_OCMC_RAM1_DSP2_WIDTH                     0x1
#define DRA7XX_WKUPDEP_OCMC_RAM1_DSP2_MASK                      (1 << 5)

/* Used by PM_L3MAIN1_OCMC_RAM1_WKDEP */
#define DRA7XX_WKUPDEP_OCMC_RAM1_EVE1_SHIFT                     6
#define DRA7XX_WKUPDEP_OCMC_RAM1_EVE1_WIDTH                     0x1
#define DRA7XX_WKUPDEP_OCMC_RAM1_EVE1_MASK                      (1 << 6)

/* Used by PM_L3MAIN1_OCMC_RAM1_WKDEP */
#define DRA7XX_WKUPDEP_OCMC_RAM1_EVE2_SHIFT                     7
#define DRA7XX_WKUPDEP_OCMC_RAM1_EVE2_WIDTH                     0x1
#define DRA7XX_WKUPDEP_OCMC_RAM1_EVE2_MASK                      (1 << 7)

/* Used by PM_L3MAIN1_OCMC_RAM1_WKDEP */
#define DRA7XX_WKUPDEP_OCMC_RAM1_EVE3_SHIFT                     8
#define DRA7XX_WKUPDEP_OCMC_RAM1_EVE3_WIDTH                     0x1
#define DRA7XX_WKUPDEP_OCMC_RAM1_EVE3_MASK                      (1 << 8)

/* Used by PM_L3MAIN1_OCMC_RAM1_WKDEP */
#define DRA7XX_WKUPDEP_OCMC_RAM1_EVE4_SHIFT                     9
#define DRA7XX_WKUPDEP_OCMC_RAM1_EVE4_WIDTH                     0x1
#define DRA7XX_WKUPDEP_OCMC_RAM1_EVE4_MASK                      (1 << 9)

/* Used by PM_L3MAIN1_OCMC_RAM1_WKDEP */
#define DRA7XX_WKUPDEP_OCMC_RAM1_IPU1_SHIFT                     4
#define DRA7XX_WKUPDEP_OCMC_RAM1_IPU1_WIDTH                     0x1
#define DRA7XX_WKUPDEP_OCMC_RAM1_IPU1_MASK                      (1 << 4)

/* Used by PM_L3MAIN1_OCMC_RAM1_WKDEP */
#define DRA7XX_WKUPDEP_OCMC_RAM1_IPU2_SHIFT                     1
#define DRA7XX_WKUPDEP_OCMC_RAM1_IPU2_WIDTH                     0x1
#define DRA7XX_WKUPDEP_OCMC_RAM1_IPU2_MASK                      (1 << 1)

/* Used by PM_L3MAIN1_OCMC_RAM1_WKDEP */
#define DRA7XX_WKUPDEP_OCMC_RAM1_MPU_SHIFT                      0
#define DRA7XX_WKUPDEP_OCMC_RAM1_MPU_WIDTH                      0x1
#define DRA7XX_WKUPDEP_OCMC_RAM1_MPU_MASK                       (1 << 0)

/* Used by PM_L3MAIN1_OCMC_RAM2_WKDEP */
#define DRA7XX_WKUPDEP_OCMC_RAM2_DSP1_SHIFT                     2
#define DRA7XX_WKUPDEP_OCMC_RAM2_DSP1_WIDTH                     0x1
#define DRA7XX_WKUPDEP_OCMC_RAM2_DSP1_MASK                      (1 << 2)

/* Used by PM_L3MAIN1_OCMC_RAM2_WKDEP */
#define DRA7XX_WKUPDEP_OCMC_RAM2_DSP2_SHIFT                     5
#define DRA7XX_WKUPDEP_OCMC_RAM2_DSP2_WIDTH                     0x1
#define DRA7XX_WKUPDEP_OCMC_RAM2_DSP2_MASK                      (1 << 5)

/* Used by PM_L3MAIN1_OCMC_RAM2_WKDEP */
#define DRA7XX_WKUPDEP_OCMC_RAM2_EVE1_SHIFT                     6
#define DRA7XX_WKUPDEP_OCMC_RAM2_EVE1_WIDTH                     0x1
#define DRA7XX_WKUPDEP_OCMC_RAM2_EVE1_MASK                      (1 << 6)

/* Used by PM_L3MAIN1_OCMC_RAM2_WKDEP */
#define DRA7XX_WKUPDEP_OCMC_RAM2_EVE2_SHIFT                     7
#define DRA7XX_WKUPDEP_OCMC_RAM2_EVE2_WIDTH                     0x1
#define DRA7XX_WKUPDEP_OCMC_RAM2_EVE2_MASK                      (1 << 7)

/* Used by PM_L3MAIN1_OCMC_RAM2_WKDEP */
#define DRA7XX_WKUPDEP_OCMC_RAM2_EVE3_SHIFT                     8
#define DRA7XX_WKUPDEP_OCMC_RAM2_EVE3_WIDTH                     0x1
#define DRA7XX_WKUPDEP_OCMC_RAM2_EVE3_MASK                      (1 << 8)

/* Used by PM_L3MAIN1_OCMC_RAM2_WKDEP */
#define DRA7XX_WKUPDEP_OCMC_RAM2_EVE4_SHIFT                     9
#define DRA7XX_WKUPDEP_OCMC_RAM2_EVE4_WIDTH                     0x1
#define DRA7XX_WKUPDEP_OCMC_RAM2_EVE4_MASK                      (1 << 9)

/* Used by PM_L3MAIN1_OCMC_RAM2_WKDEP */
#define DRA7XX_WKUPDEP_OCMC_RAM2_IPU1_SHIFT                     4
#define DRA7XX_WKUPDEP_OCMC_RAM2_IPU1_WIDTH                     0x1
#define DRA7XX_WKUPDEP_OCMC_RAM2_IPU1_MASK                      (1 << 4)

/* Used by PM_L3MAIN1_OCMC_RAM2_WKDEP */
#define DRA7XX_WKUPDEP_OCMC_RAM2_IPU2_SHIFT                     1
#define DRA7XX_WKUPDEP_OCMC_RAM2_IPU2_WIDTH                     0x1
#define DRA7XX_WKUPDEP_OCMC_RAM2_IPU2_MASK                      (1 << 1)

/* Used by PM_L3MAIN1_OCMC_RAM2_WKDEP */
#define DRA7XX_WKUPDEP_OCMC_RAM2_MPU_SHIFT                      0
#define DRA7XX_WKUPDEP_OCMC_RAM2_MPU_WIDTH                      0x1
#define DRA7XX_WKUPDEP_OCMC_RAM2_MPU_MASK                       (1 << 0)

/* Used by PM_L3MAIN1_OCMC_RAM3_WKDEP */
#define DRA7XX_WKUPDEP_OCMC_RAM3_DSP1_SHIFT                     2
#define DRA7XX_WKUPDEP_OCMC_RAM3_DSP1_WIDTH                     0x1
#define DRA7XX_WKUPDEP_OCMC_RAM3_DSP1_MASK                      (1 << 2)

/* Used by PM_L3MAIN1_OCMC_RAM3_WKDEP */
#define DRA7XX_WKUPDEP_OCMC_RAM3_DSP2_SHIFT                     5
#define DRA7XX_WKUPDEP_OCMC_RAM3_DSP2_WIDTH                     0x1
#define DRA7XX_WKUPDEP_OCMC_RAM3_DSP2_MASK                      (1 << 5)

/* Used by PM_L3MAIN1_OCMC_RAM3_WKDEP */
#define DRA7XX_WKUPDEP_OCMC_RAM3_EVE1_SHIFT                     6
#define DRA7XX_WKUPDEP_OCMC_RAM3_EVE1_WIDTH                     0x1
#define DRA7XX_WKUPDEP_OCMC_RAM3_EVE1_MASK                      (1 << 6)

/* Used by PM_L3MAIN1_OCMC_RAM3_WKDEP */
#define DRA7XX_WKUPDEP_OCMC_RAM3_EVE2_SHIFT                     7
#define DRA7XX_WKUPDEP_OCMC_RAM3_EVE2_WIDTH                     0x1
#define DRA7XX_WKUPDEP_OCMC_RAM3_EVE2_MASK                      (1 << 7)

/* Used by PM_L3MAIN1_OCMC_RAM3_WKDEP */
#define DRA7XX_WKUPDEP_OCMC_RAM3_EVE3_SHIFT                     8
#define DRA7XX_WKUPDEP_OCMC_RAM3_EVE3_WIDTH                     0x1
#define DRA7XX_WKUPDEP_OCMC_RAM3_EVE3_MASK                      (1 << 8)

/* Used by PM_L3MAIN1_OCMC_RAM3_WKDEP */
#define DRA7XX_WKUPDEP_OCMC_RAM3_EVE4_SHIFT                     9
#define DRA7XX_WKUPDEP_OCMC_RAM3_EVE4_WIDTH                     0x1
#define DRA7XX_WKUPDEP_OCMC_RAM3_EVE4_MASK                      (1 << 9)

/* Used by PM_L3MAIN1_OCMC_RAM3_WKDEP */
#define DRA7XX_WKUPDEP_OCMC_RAM3_IPU1_SHIFT                     4
#define DRA7XX_WKUPDEP_OCMC_RAM3_IPU1_WIDTH                     0x1
#define DRA7XX_WKUPDEP_OCMC_RAM3_IPU1_MASK                      (1 << 4)

/* Used by PM_L3MAIN1_OCMC_RAM3_WKDEP */
#define DRA7XX_WKUPDEP_OCMC_RAM3_IPU2_SHIFT                     1
#define DRA7XX_WKUPDEP_OCMC_RAM3_IPU2_WIDTH                     0x1
#define DRA7XX_WKUPDEP_OCMC_RAM3_IPU2_MASK                      (1 << 1)

/* Used by PM_L3MAIN1_OCMC_RAM3_WKDEP */
#define DRA7XX_WKUPDEP_OCMC_RAM3_MPU_SHIFT                      0
#define DRA7XX_WKUPDEP_OCMC_RAM3_MPU_WIDTH                      0x1
#define DRA7XX_WKUPDEP_OCMC_RAM3_MPU_MASK                       (1 << 0)

/* Used by PM_L4PER2_QSPI_WKDEP */
#define DRA7XX_WKUPDEP_QSPI_DSP1_SHIFT                          2
#define DRA7XX_WKUPDEP_QSPI_DSP1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_QSPI_DSP1_MASK                           (1 << 2)

/* Used by PM_L4PER2_QSPI_WKDEP */
#define DRA7XX_WKUPDEP_QSPI_DSP2_SHIFT                          5
#define DRA7XX_WKUPDEP_QSPI_DSP2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_QSPI_DSP2_MASK                           (1 << 5)

/* Used by PM_L4PER2_QSPI_WKDEP */
#define DRA7XX_WKUPDEP_QSPI_EVE1_SHIFT                          6
#define DRA7XX_WKUPDEP_QSPI_EVE1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_QSPI_EVE1_MASK                           (1 << 6)

/* Used by PM_L4PER2_QSPI_WKDEP */
#define DRA7XX_WKUPDEP_QSPI_EVE2_SHIFT                          7
#define DRA7XX_WKUPDEP_QSPI_EVE2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_QSPI_EVE2_MASK                           (1 << 7)

/* Used by PM_L4PER2_QSPI_WKDEP */
#define DRA7XX_WKUPDEP_QSPI_EVE3_SHIFT                          8
#define DRA7XX_WKUPDEP_QSPI_EVE3_WIDTH                          0x1
#define DRA7XX_WKUPDEP_QSPI_EVE3_MASK                           (1 << 8)

/* Used by PM_L4PER2_QSPI_WKDEP */
#define DRA7XX_WKUPDEP_QSPI_EVE4_SHIFT                          9
#define DRA7XX_WKUPDEP_QSPI_EVE4_WIDTH                          0x1
#define DRA7XX_WKUPDEP_QSPI_EVE4_MASK                           (1 << 9)

/* Used by PM_L4PER2_QSPI_WKDEP */
#define DRA7XX_WKUPDEP_QSPI_IPU1_SHIFT                          4
#define DRA7XX_WKUPDEP_QSPI_IPU1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_QSPI_IPU1_MASK                           (1 << 4)

/* Used by PM_L4PER2_QSPI_WKDEP */
#define DRA7XX_WKUPDEP_QSPI_IPU2_SHIFT                          1
#define DRA7XX_WKUPDEP_QSPI_IPU2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_QSPI_IPU2_MASK                           (1 << 1)

/* Used by PM_L4PER2_QSPI_WKDEP */
#define DRA7XX_WKUPDEP_QSPI_MPU_SHIFT                           0
#define DRA7XX_WKUPDEP_QSPI_MPU_WIDTH                           0x1
#define DRA7XX_WKUPDEP_QSPI_MPU_MASK                            (1 << 0)

/* Used by PM_RTC_RTCSS_WKDEP */
#define DRA7XX_WKUPDEP_RTC_IRQ1_DSP1_SHIFT                      2
#define DRA7XX_WKUPDEP_RTC_IRQ1_DSP1_WIDTH                      0x1
#define DRA7XX_WKUPDEP_RTC_IRQ1_DSP1_MASK                       (1 << 2)

/* Used by PM_RTC_RTCSS_WKDEP */
#define DRA7XX_WKUPDEP_RTC_IRQ1_DSP2_SHIFT                      5
#define DRA7XX_WKUPDEP_RTC_IRQ1_DSP2_WIDTH                      0x1
#define DRA7XX_WKUPDEP_RTC_IRQ1_DSP2_MASK                       (1 << 5)

/* Used by PM_RTC_RTCSS_WKDEP */
#define DRA7XX_WKUPDEP_RTC_IRQ1_EVE1_SHIFT                      6
#define DRA7XX_WKUPDEP_RTC_IRQ1_EVE1_WIDTH                      0x1
#define DRA7XX_WKUPDEP_RTC_IRQ1_EVE1_MASK                       (1 << 6)

/* Used by PM_RTC_RTCSS_WKDEP */
#define DRA7XX_WKUPDEP_RTC_IRQ1_EVE2_SHIFT                      7
#define DRA7XX_WKUPDEP_RTC_IRQ1_EVE2_WIDTH                      0x1
#define DRA7XX_WKUPDEP_RTC_IRQ1_EVE2_MASK                       (1 << 7)

/* Used by PM_RTC_RTCSS_WKDEP */
#define DRA7XX_WKUPDEP_RTC_IRQ1_EVE3_SHIFT                      8
#define DRA7XX_WKUPDEP_RTC_IRQ1_EVE3_WIDTH                      0x1
#define DRA7XX_WKUPDEP_RTC_IRQ1_EVE3_MASK                       (1 << 8)

/* Used by PM_RTC_RTCSS_WKDEP */
#define DRA7XX_WKUPDEP_RTC_IRQ1_EVE4_SHIFT                      9
#define DRA7XX_WKUPDEP_RTC_IRQ1_EVE4_WIDTH                      0x1
#define DRA7XX_WKUPDEP_RTC_IRQ1_EVE4_MASK                       (1 << 9)

/* Used by PM_RTC_RTCSS_WKDEP */
#define DRA7XX_WKUPDEP_RTC_IRQ1_IPU1_SHIFT                      4
#define DRA7XX_WKUPDEP_RTC_IRQ1_IPU1_WIDTH                      0x1
#define DRA7XX_WKUPDEP_RTC_IRQ1_IPU1_MASK                       (1 << 4)

/* Used by PM_RTC_RTCSS_WKDEP */
#define DRA7XX_WKUPDEP_RTC_IRQ1_IPU2_SHIFT                      1
#define DRA7XX_WKUPDEP_RTC_IRQ1_IPU2_WIDTH                      0x1
#define DRA7XX_WKUPDEP_RTC_IRQ1_IPU2_MASK                       (1 << 1)

/* Used by PM_RTC_RTCSS_WKDEP */
#define DRA7XX_WKUPDEP_RTC_IRQ1_MPU_SHIFT                       0
#define DRA7XX_WKUPDEP_RTC_IRQ1_MPU_WIDTH                       0x1
#define DRA7XX_WKUPDEP_RTC_IRQ1_MPU_MASK                        (1 << 0)

/* Used by PM_RTC_RTCSS_WKDEP */
#define DRA7XX_WKUPDEP_RTC_IRQ2_DSP1_SHIFT                      12
#define DRA7XX_WKUPDEP_RTC_IRQ2_DSP1_WIDTH                      0x1
#define DRA7XX_WKUPDEP_RTC_IRQ2_DSP1_MASK                       (1 << 12)

/* Used by PM_RTC_RTCSS_WKDEP */
#define DRA7XX_WKUPDEP_RTC_IRQ2_DSP2_SHIFT                      15
#define DRA7XX_WKUPDEP_RTC_IRQ2_DSP2_WIDTH                      0x1
#define DRA7XX_WKUPDEP_RTC_IRQ2_DSP2_MASK                       (1 << 15)

/* Used by PM_RTC_RTCSS_WKDEP */
#define DRA7XX_WKUPDEP_RTC_IRQ2_EVE1_SHIFT                      16
#define DRA7XX_WKUPDEP_RTC_IRQ2_EVE1_WIDTH                      0x1
#define DRA7XX_WKUPDEP_RTC_IRQ2_EVE1_MASK                       (1 << 16)

/* Used by PM_RTC_RTCSS_WKDEP */
#define DRA7XX_WKUPDEP_RTC_IRQ2_EVE2_SHIFT                      17
#define DRA7XX_WKUPDEP_RTC_IRQ2_EVE2_WIDTH                      0x1
#define DRA7XX_WKUPDEP_RTC_IRQ2_EVE2_MASK                       (1 << 17)

/* Used by PM_RTC_RTCSS_WKDEP */
#define DRA7XX_WKUPDEP_RTC_IRQ2_EVE3_SHIFT                      18
#define DRA7XX_WKUPDEP_RTC_IRQ2_EVE3_WIDTH                      0x1
#define DRA7XX_WKUPDEP_RTC_IRQ2_EVE3_MASK                       (1 << 18)

/* Used by PM_RTC_RTCSS_WKDEP */
#define DRA7XX_WKUPDEP_RTC_IRQ2_EVE4_SHIFT                      19
#define DRA7XX_WKUPDEP_RTC_IRQ2_EVE4_WIDTH                      0x1
#define DRA7XX_WKUPDEP_RTC_IRQ2_EVE4_MASK                       (1 << 19)

/* Used by PM_RTC_RTCSS_WKDEP */
#define DRA7XX_WKUPDEP_RTC_IRQ2_IPU1_SHIFT                      14
#define DRA7XX_WKUPDEP_RTC_IRQ2_IPU1_WIDTH                      0x1
#define DRA7XX_WKUPDEP_RTC_IRQ2_IPU1_MASK                       (1 << 14)

/* Used by PM_RTC_RTCSS_WKDEP */
#define DRA7XX_WKUPDEP_RTC_IRQ2_IPU2_SHIFT                      11
#define DRA7XX_WKUPDEP_RTC_IRQ2_IPU2_WIDTH                      0x1
#define DRA7XX_WKUPDEP_RTC_IRQ2_IPU2_MASK                       (1 << 11)

/* Used by PM_RTC_RTCSS_WKDEP */
#define DRA7XX_WKUPDEP_RTC_IRQ2_MPU_SHIFT                       10
#define DRA7XX_WKUPDEP_RTC_IRQ2_MPU_WIDTH                       0x1
#define DRA7XX_WKUPDEP_RTC_IRQ2_MPU_MASK                        (1 << 10)

/* Used by PM_L3INIT_SATA_WKDEP */
#define DRA7XX_WKUPDEP_SATA_DSP1_SHIFT                          2
#define DRA7XX_WKUPDEP_SATA_DSP1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_SATA_DSP1_MASK                           (1 << 2)

/* Used by PM_L3INIT_SATA_WKDEP */
#define DRA7XX_WKUPDEP_SATA_DSP2_SHIFT                          5
#define DRA7XX_WKUPDEP_SATA_DSP2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_SATA_DSP2_MASK                           (1 << 5)

/* Used by PM_L3INIT_SATA_WKDEP */
#define DRA7XX_WKUPDEP_SATA_EVE1_SHIFT                          6
#define DRA7XX_WKUPDEP_SATA_EVE1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_SATA_EVE1_MASK                           (1 << 6)

/* Used by PM_L3INIT_SATA_WKDEP */
#define DRA7XX_WKUPDEP_SATA_EVE2_SHIFT                          7
#define DRA7XX_WKUPDEP_SATA_EVE2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_SATA_EVE2_MASK                           (1 << 7)

/* Used by PM_L3INIT_SATA_WKDEP */
#define DRA7XX_WKUPDEP_SATA_EVE3_SHIFT                          8
#define DRA7XX_WKUPDEP_SATA_EVE3_WIDTH                          0x1
#define DRA7XX_WKUPDEP_SATA_EVE3_MASK                           (1 << 8)

/* Used by PM_L3INIT_SATA_WKDEP */
#define DRA7XX_WKUPDEP_SATA_EVE4_SHIFT                          9
#define DRA7XX_WKUPDEP_SATA_EVE4_WIDTH                          0x1
#define DRA7XX_WKUPDEP_SATA_EVE4_MASK                           (1 << 9)

/* Used by PM_L3INIT_SATA_WKDEP */
#define DRA7XX_WKUPDEP_SATA_IPU1_SHIFT                          4
#define DRA7XX_WKUPDEP_SATA_IPU1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_SATA_IPU1_MASK                           (1 << 4)

/* Used by PM_L3INIT_SATA_WKDEP */
#define DRA7XX_WKUPDEP_SATA_IPU2_SHIFT                          1
#define DRA7XX_WKUPDEP_SATA_IPU2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_SATA_IPU2_MASK                           (1 << 1)

/* Used by PM_L3INIT_SATA_WKDEP */
#define DRA7XX_WKUPDEP_SATA_MPU_SHIFT                           0
#define DRA7XX_WKUPDEP_SATA_MPU_WIDTH                           0x1
#define DRA7XX_WKUPDEP_SATA_MPU_MASK                            (1 << 0)

/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_DSP1_SHIFT              2
#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_DSP1_WIDTH              0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_DSP1_MASK               (1 << 2)

/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_DSP2_SHIFT              5
#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_DSP2_WIDTH              0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_DSP2_MASK               (1 << 5)

/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_EVE1_SHIFT              6
#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_EVE1_WIDTH              0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_EVE1_MASK               (1 << 6)

/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_EVE2_SHIFT              7
#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_EVE2_WIDTH              0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_EVE2_MASK               (1 << 7)

/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_EVE3_SHIFT              8
#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_EVE3_WIDTH              0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_EVE3_MASK               (1 << 8)

/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_EVE4_SHIFT              9
#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_EVE4_WIDTH              0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_EVE4_MASK               (1 << 9)

/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_IPU1_SHIFT              4
#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_IPU1_WIDTH              0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_IPU1_MASK               (1 << 4)

/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_IPU2_SHIFT              1
#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_IPU2_WIDTH              0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_IPU2_MASK               (1 << 1)

/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_MPU_SHIFT               0
#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_MPU_WIDTH               0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_MPU_MASK                (1 << 0)

/* Used by PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_DSP1_SHIFT            2
#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_DSP1_WIDTH            0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_DSP1_MASK             (1 << 2)

/* Used by PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_DSP2_SHIFT            5
#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_DSP2_WIDTH            0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_DSP2_MASK             (1 << 5)

/* Used by PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_EVE1_SHIFT            6
#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_EVE1_WIDTH            0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_EVE1_MASK             (1 << 6)

/* Used by PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_EVE2_SHIFT            7
#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_EVE2_WIDTH            0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_EVE2_MASK             (1 << 7)

/* Used by PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_EVE3_SHIFT            8
#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_EVE3_WIDTH            0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_EVE3_MASK             (1 << 8)

/* Used by PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_EVE4_SHIFT            9
#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_EVE4_WIDTH            0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_EVE4_MASK             (1 << 9)

/* Used by PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_IPU1_SHIFT            4
#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_IPU1_WIDTH            0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_IPU1_MASK             (1 << 4)

/* Used by PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_IPU2_SHIFT            1
#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_IPU2_WIDTH            0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_IPU2_MASK             (1 << 1)

/* Used by PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_MPU_SHIFT             0
#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_MPU_WIDTH             0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_MPU_MASK              (1 << 0)

/* Used by PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_SDMA_SHIFT            3
#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_SDMA_WIDTH            0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_SDMA_MASK             (1 << 3)

/* Used by PM_COREAON_SMARTREFLEX_GPU_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_DSP1_SHIFT               2
#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_DSP1_WIDTH               0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_DSP1_MASK                (1 << 2)

/* Used by PM_COREAON_SMARTREFLEX_GPU_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_DSP2_SHIFT               5
#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_DSP2_WIDTH               0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_DSP2_MASK                (1 << 5)

/* Used by PM_COREAON_SMARTREFLEX_GPU_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_EVE1_SHIFT               6
#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_EVE1_WIDTH               0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_EVE1_MASK                (1 << 6)

/* Used by PM_COREAON_SMARTREFLEX_GPU_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_EVE2_SHIFT               7
#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_EVE2_WIDTH               0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_EVE2_MASK                (1 << 7)

/* Used by PM_COREAON_SMARTREFLEX_GPU_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_EVE3_SHIFT               8
#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_EVE3_WIDTH               0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_EVE3_MASK                (1 << 8)

/* Used by PM_COREAON_SMARTREFLEX_GPU_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_EVE4_SHIFT               9
#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_EVE4_WIDTH               0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_EVE4_MASK                (1 << 9)

/* Used by PM_COREAON_SMARTREFLEX_GPU_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_IPU1_SHIFT               4
#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_IPU1_WIDTH               0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_IPU1_MASK                (1 << 4)

/* Used by PM_COREAON_SMARTREFLEX_GPU_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_IPU2_SHIFT               1
#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_IPU2_WIDTH               0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_IPU2_MASK                (1 << 1)

/* Used by PM_COREAON_SMARTREFLEX_GPU_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_MPU_SHIFT                0
#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_MPU_WIDTH                0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_MPU_MASK                 (1 << 0)

/* Used by PM_COREAON_SMARTREFLEX_IVAHD_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_DSP1_SHIFT             2
#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_DSP1_WIDTH             0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_DSP1_MASK              (1 << 2)

/* Used by PM_COREAON_SMARTREFLEX_IVAHD_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_DSP2_SHIFT             5
#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_DSP2_WIDTH             0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_DSP2_MASK              (1 << 5)

/* Used by PM_COREAON_SMARTREFLEX_IVAHD_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_EVE1_SHIFT             6
#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_EVE1_WIDTH             0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_EVE1_MASK              (1 << 6)

/* Used by PM_COREAON_SMARTREFLEX_IVAHD_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_EVE2_SHIFT             7
#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_EVE2_WIDTH             0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_EVE2_MASK              (1 << 7)

/* Used by PM_COREAON_SMARTREFLEX_IVAHD_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_EVE3_SHIFT             8
#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_EVE3_WIDTH             0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_EVE3_MASK              (1 << 8)

/* Used by PM_COREAON_SMARTREFLEX_IVAHD_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_EVE4_SHIFT             9
#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_EVE4_WIDTH             0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_EVE4_MASK              (1 << 9)

/* Used by PM_COREAON_SMARTREFLEX_IVAHD_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_IPU1_SHIFT             4
#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_IPU1_WIDTH             0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_IPU1_MASK              (1 << 4)

/* Used by PM_COREAON_SMARTREFLEX_IVAHD_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_IPU2_SHIFT             1
#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_IPU2_WIDTH             0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_IPU2_MASK              (1 << 1)

/* Used by PM_COREAON_SMARTREFLEX_IVAHD_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_MPU_SHIFT              0
#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_MPU_WIDTH              0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_MPU_MASK               (1 << 0)

/* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_DSP1_SHIFT               2
#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_DSP1_WIDTH               0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_DSP1_MASK                (1 << 2)

/* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_DSP2_SHIFT               5
#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_DSP2_WIDTH               0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_DSP2_MASK                (1 << 5)

/* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_EVE1_SHIFT               6
#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_EVE1_WIDTH               0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_EVE1_MASK                (1 << 6)

/* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_EVE2_SHIFT               7
#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_EVE2_WIDTH               0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_EVE2_MASK                (1 << 7)

/* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_EVE3_SHIFT               8
#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_EVE3_WIDTH               0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_EVE3_MASK                (1 << 8)

/* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_EVE4_SHIFT               9
#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_EVE4_WIDTH               0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_EVE4_MASK                (1 << 9)

/* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_IPU1_SHIFT               4
#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_IPU1_WIDTH               0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_IPU1_MASK                (1 << 4)

/* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_IPU2_SHIFT               1
#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_IPU2_WIDTH               0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_IPU2_MASK                (1 << 1)

/* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */
#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_MPU_SHIFT                0
#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_MPU_WIDTH                0x1
#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_MPU_MASK                 (1 << 0)

/* Used by PM_L4PER_TIMER10_WKDEP */
#define DRA7XX_WKUPDEP_TIMER10_DSP1_SHIFT                       2
#define DRA7XX_WKUPDEP_TIMER10_DSP1_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER10_DSP1_MASK                        (1 << 2)

/* Used by PM_L4PER_TIMER10_WKDEP */
#define DRA7XX_WKUPDEP_TIMER10_DSP2_SHIFT                       5
#define DRA7XX_WKUPDEP_TIMER10_DSP2_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER10_DSP2_MASK                        (1 << 5)

/* Used by PM_L4PER_TIMER10_WKDEP */
#define DRA7XX_WKUPDEP_TIMER10_EVE1_SHIFT                       6
#define DRA7XX_WKUPDEP_TIMER10_EVE1_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER10_EVE1_MASK                        (1 << 6)

/* Used by PM_L4PER_TIMER10_WKDEP */
#define DRA7XX_WKUPDEP_TIMER10_EVE2_SHIFT                       7
#define DRA7XX_WKUPDEP_TIMER10_EVE2_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER10_EVE2_MASK                        (1 << 7)

/* Used by PM_L4PER_TIMER10_WKDEP */
#define DRA7XX_WKUPDEP_TIMER10_EVE3_SHIFT                       8
#define DRA7XX_WKUPDEP_TIMER10_EVE3_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER10_EVE3_MASK                        (1 << 8)

/* Used by PM_L4PER_TIMER10_WKDEP */
#define DRA7XX_WKUPDEP_TIMER10_EVE4_SHIFT                       9
#define DRA7XX_WKUPDEP_TIMER10_EVE4_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER10_EVE4_MASK                        (1 << 9)

/* Used by PM_L4PER_TIMER10_WKDEP */
#define DRA7XX_WKUPDEP_TIMER10_IPU1_SHIFT                       4
#define DRA7XX_WKUPDEP_TIMER10_IPU1_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER10_IPU1_MASK                        (1 << 4)

/* Used by PM_L4PER_TIMER10_WKDEP */
#define DRA7XX_WKUPDEP_TIMER10_IPU2_SHIFT                       1
#define DRA7XX_WKUPDEP_TIMER10_IPU2_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER10_IPU2_MASK                        (1 << 1)

/* Used by PM_L4PER_TIMER10_WKDEP */
#define DRA7XX_WKUPDEP_TIMER10_MPU_SHIFT                        0
#define DRA7XX_WKUPDEP_TIMER10_MPU_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER10_MPU_MASK                         (1 << 0)

/* Used by PM_L4PER_TIMER11_WKDEP */
#define DRA7XX_WKUPDEP_TIMER11_DSP1_SHIFT                       2
#define DRA7XX_WKUPDEP_TIMER11_DSP1_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER11_DSP1_MASK                        (1 << 2)

/* Used by PM_L4PER_TIMER11_WKDEP */
#define DRA7XX_WKUPDEP_TIMER11_DSP2_SHIFT                       5
#define DRA7XX_WKUPDEP_TIMER11_DSP2_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER11_DSP2_MASK                        (1 << 5)

/* Used by PM_L4PER_TIMER11_WKDEP */
#define DRA7XX_WKUPDEP_TIMER11_EVE1_SHIFT                       6
#define DRA7XX_WKUPDEP_TIMER11_EVE1_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER11_EVE1_MASK                        (1 << 6)

/* Used by PM_L4PER_TIMER11_WKDEP */
#define DRA7XX_WKUPDEP_TIMER11_EVE2_SHIFT                       7
#define DRA7XX_WKUPDEP_TIMER11_EVE2_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER11_EVE2_MASK                        (1 << 7)

/* Used by PM_L4PER_TIMER11_WKDEP */
#define DRA7XX_WKUPDEP_TIMER11_EVE3_SHIFT                       8
#define DRA7XX_WKUPDEP_TIMER11_EVE3_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER11_EVE3_MASK                        (1 << 8)

/* Used by PM_L4PER_TIMER11_WKDEP */
#define DRA7XX_WKUPDEP_TIMER11_EVE4_SHIFT                       9
#define DRA7XX_WKUPDEP_TIMER11_EVE4_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER11_EVE4_MASK                        (1 << 9)

/* Used by PM_L4PER_TIMER11_WKDEP */
#define DRA7XX_WKUPDEP_TIMER11_IPU1_SHIFT                       4
#define DRA7XX_WKUPDEP_TIMER11_IPU1_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER11_IPU1_MASK                        (1 << 4)

/* Used by PM_L4PER_TIMER11_WKDEP */
#define DRA7XX_WKUPDEP_TIMER11_IPU2_SHIFT                       1
#define DRA7XX_WKUPDEP_TIMER11_IPU2_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER11_IPU2_MASK                        (1 << 1)

/* Used by PM_L4PER_TIMER11_WKDEP */
#define DRA7XX_WKUPDEP_TIMER11_MPU_SHIFT                        0
#define DRA7XX_WKUPDEP_TIMER11_MPU_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER11_MPU_MASK                         (1 << 0)

/* Used by PM_WKUPAON_TIMER12_WKDEP */
#define DRA7XX_WKUPDEP_TIMER12_DSP1_SHIFT                       2
#define DRA7XX_WKUPDEP_TIMER12_DSP1_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER12_DSP1_MASK                        (1 << 2)

/* Used by PM_WKUPAON_TIMER12_WKDEP */
#define DRA7XX_WKUPDEP_TIMER12_DSP2_SHIFT                       5
#define DRA7XX_WKUPDEP_TIMER12_DSP2_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER12_DSP2_MASK                        (1 << 5)

/* Used by PM_WKUPAON_TIMER12_WKDEP */
#define DRA7XX_WKUPDEP_TIMER12_EVE1_SHIFT                       6
#define DRA7XX_WKUPDEP_TIMER12_EVE1_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER12_EVE1_MASK                        (1 << 6)

/* Used by PM_WKUPAON_TIMER12_WKDEP */
#define DRA7XX_WKUPDEP_TIMER12_EVE2_SHIFT                       7
#define DRA7XX_WKUPDEP_TIMER12_EVE2_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER12_EVE2_MASK                        (1 << 7)

/* Used by PM_WKUPAON_TIMER12_WKDEP */
#define DRA7XX_WKUPDEP_TIMER12_EVE3_SHIFT                       8
#define DRA7XX_WKUPDEP_TIMER12_EVE3_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER12_EVE3_MASK                        (1 << 8)

/* Used by PM_WKUPAON_TIMER12_WKDEP */
#define DRA7XX_WKUPDEP_TIMER12_EVE4_SHIFT                       9
#define DRA7XX_WKUPDEP_TIMER12_EVE4_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER12_EVE4_MASK                        (1 << 9)

/* Used by PM_WKUPAON_TIMER12_WKDEP */
#define DRA7XX_WKUPDEP_TIMER12_IPU1_SHIFT                       4
#define DRA7XX_WKUPDEP_TIMER12_IPU1_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER12_IPU1_MASK                        (1 << 4)

/* Used by PM_WKUPAON_TIMER12_WKDEP */
#define DRA7XX_WKUPDEP_TIMER12_IPU2_SHIFT                       1
#define DRA7XX_WKUPDEP_TIMER12_IPU2_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER12_IPU2_MASK                        (1 << 1)

/* Used by PM_WKUPAON_TIMER12_WKDEP */
#define DRA7XX_WKUPDEP_TIMER12_MPU_SHIFT                        0
#define DRA7XX_WKUPDEP_TIMER12_MPU_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER12_MPU_MASK                         (1 << 0)

/* Used by PM_L4PER_TIMER13_WKDEP */
#define DRA7XX_WKUPDEP_TIMER13_DSP1_SHIFT                       2
#define DRA7XX_WKUPDEP_TIMER13_DSP1_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER13_DSP1_MASK                        (1 << 2)

/* Used by PM_L4PER_TIMER13_WKDEP */
#define DRA7XX_WKUPDEP_TIMER13_DSP2_SHIFT                       5
#define DRA7XX_WKUPDEP_TIMER13_DSP2_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER13_DSP2_MASK                        (1 << 5)

/* Used by PM_L4PER_TIMER13_WKDEP */
#define DRA7XX_WKUPDEP_TIMER13_EVE1_SHIFT                       6
#define DRA7XX_WKUPDEP_TIMER13_EVE1_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER13_EVE1_MASK                        (1 << 6)

/* Used by PM_L4PER_TIMER13_WKDEP */
#define DRA7XX_WKUPDEP_TIMER13_EVE2_SHIFT                       7
#define DRA7XX_WKUPDEP_TIMER13_EVE2_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER13_EVE2_MASK                        (1 << 7)

/* Used by PM_L4PER_TIMER13_WKDEP */
#define DRA7XX_WKUPDEP_TIMER13_EVE3_SHIFT                       8
#define DRA7XX_WKUPDEP_TIMER13_EVE3_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER13_EVE3_MASK                        (1 << 8)

/* Used by PM_L4PER_TIMER13_WKDEP */
#define DRA7XX_WKUPDEP_TIMER13_EVE4_SHIFT                       9
#define DRA7XX_WKUPDEP_TIMER13_EVE4_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER13_EVE4_MASK                        (1 << 9)

/* Used by PM_L4PER_TIMER13_WKDEP */
#define DRA7XX_WKUPDEP_TIMER13_IPU1_SHIFT                       4
#define DRA7XX_WKUPDEP_TIMER13_IPU1_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER13_IPU1_MASK                        (1 << 4)

/* Used by PM_L4PER_TIMER13_WKDEP */
#define DRA7XX_WKUPDEP_TIMER13_IPU2_SHIFT                       1
#define DRA7XX_WKUPDEP_TIMER13_IPU2_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER13_IPU2_MASK                        (1 << 1)

/* Used by PM_L4PER_TIMER13_WKDEP */
#define DRA7XX_WKUPDEP_TIMER13_MPU_SHIFT                        0
#define DRA7XX_WKUPDEP_TIMER13_MPU_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER13_MPU_MASK                         (1 << 0)

/* Used by PM_L4PER_TIMER14_WKDEP */
#define DRA7XX_WKUPDEP_TIMER14_DSP1_SHIFT                       2
#define DRA7XX_WKUPDEP_TIMER14_DSP1_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER14_DSP1_MASK                        (1 << 2)

/* Used by PM_L4PER_TIMER14_WKDEP */
#define DRA7XX_WKUPDEP_TIMER14_DSP2_SHIFT                       5
#define DRA7XX_WKUPDEP_TIMER14_DSP2_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER14_DSP2_MASK                        (1 << 5)

/* Used by PM_L4PER_TIMER14_WKDEP */
#define DRA7XX_WKUPDEP_TIMER14_EVE1_SHIFT                       6
#define DRA7XX_WKUPDEP_TIMER14_EVE1_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER14_EVE1_MASK                        (1 << 6)

/* Used by PM_L4PER_TIMER14_WKDEP */
#define DRA7XX_WKUPDEP_TIMER14_EVE2_SHIFT                       7
#define DRA7XX_WKUPDEP_TIMER14_EVE2_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER14_EVE2_MASK                        (1 << 7)

/* Used by PM_L4PER_TIMER14_WKDEP */
#define DRA7XX_WKUPDEP_TIMER14_EVE3_SHIFT                       8
#define DRA7XX_WKUPDEP_TIMER14_EVE3_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER14_EVE3_MASK                        (1 << 8)

/* Used by PM_L4PER_TIMER14_WKDEP */
#define DRA7XX_WKUPDEP_TIMER14_EVE4_SHIFT                       9
#define DRA7XX_WKUPDEP_TIMER14_EVE4_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER14_EVE4_MASK                        (1 << 9)

/* Used by PM_L4PER_TIMER14_WKDEP */
#define DRA7XX_WKUPDEP_TIMER14_IPU1_SHIFT                       4
#define DRA7XX_WKUPDEP_TIMER14_IPU1_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER14_IPU1_MASK                        (1 << 4)

/* Used by PM_L4PER_TIMER14_WKDEP */
#define DRA7XX_WKUPDEP_TIMER14_IPU2_SHIFT                       1
#define DRA7XX_WKUPDEP_TIMER14_IPU2_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER14_IPU2_MASK                        (1 << 1)

/* Used by PM_L4PER_TIMER14_WKDEP */
#define DRA7XX_WKUPDEP_TIMER14_MPU_SHIFT                        0
#define DRA7XX_WKUPDEP_TIMER14_MPU_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER14_MPU_MASK                         (1 << 0)

/* Used by PM_L4PER_TIMER15_WKDEP */
#define DRA7XX_WKUPDEP_TIMER15_DSP1_SHIFT                       2
#define DRA7XX_WKUPDEP_TIMER15_DSP1_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER15_DSP1_MASK                        (1 << 2)

/* Used by PM_L4PER_TIMER15_WKDEP */
#define DRA7XX_WKUPDEP_TIMER15_DSP2_SHIFT                       5
#define DRA7XX_WKUPDEP_TIMER15_DSP2_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER15_DSP2_MASK                        (1 << 5)

/* Used by PM_L4PER_TIMER15_WKDEP */
#define DRA7XX_WKUPDEP_TIMER15_EVE1_SHIFT                       6
#define DRA7XX_WKUPDEP_TIMER15_EVE1_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER15_EVE1_MASK                        (1 << 6)

/* Used by PM_L4PER_TIMER15_WKDEP */
#define DRA7XX_WKUPDEP_TIMER15_EVE2_SHIFT                       7
#define DRA7XX_WKUPDEP_TIMER15_EVE2_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER15_EVE2_MASK                        (1 << 7)

/* Used by PM_L4PER_TIMER15_WKDEP */
#define DRA7XX_WKUPDEP_TIMER15_EVE3_SHIFT                       8
#define DRA7XX_WKUPDEP_TIMER15_EVE3_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER15_EVE3_MASK                        (1 << 8)

/* Used by PM_L4PER_TIMER15_WKDEP */
#define DRA7XX_WKUPDEP_TIMER15_EVE4_SHIFT                       9
#define DRA7XX_WKUPDEP_TIMER15_EVE4_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER15_EVE4_MASK                        (1 << 9)

/* Used by PM_L4PER_TIMER15_WKDEP */
#define DRA7XX_WKUPDEP_TIMER15_IPU1_SHIFT                       4
#define DRA7XX_WKUPDEP_TIMER15_IPU1_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER15_IPU1_MASK                        (1 << 4)

/* Used by PM_L4PER_TIMER15_WKDEP */
#define DRA7XX_WKUPDEP_TIMER15_IPU2_SHIFT                       1
#define DRA7XX_WKUPDEP_TIMER15_IPU2_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER15_IPU2_MASK                        (1 << 1)

/* Used by PM_L4PER_TIMER15_WKDEP */
#define DRA7XX_WKUPDEP_TIMER15_MPU_SHIFT                        0
#define DRA7XX_WKUPDEP_TIMER15_MPU_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER15_MPU_MASK                         (1 << 0)

/* Used by PM_L4PER_TIMER16_WKDEP */
#define DRA7XX_WKUPDEP_TIMER16_DSP1_SHIFT                       2
#define DRA7XX_WKUPDEP_TIMER16_DSP1_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER16_DSP1_MASK                        (1 << 2)

/* Used by PM_L4PER_TIMER16_WKDEP */
#define DRA7XX_WKUPDEP_TIMER16_DSP2_SHIFT                       5
#define DRA7XX_WKUPDEP_TIMER16_DSP2_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER16_DSP2_MASK                        (1 << 5)

/* Used by PM_L4PER_TIMER16_WKDEP */
#define DRA7XX_WKUPDEP_TIMER16_EVE1_SHIFT                       6
#define DRA7XX_WKUPDEP_TIMER16_EVE1_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER16_EVE1_MASK                        (1 << 6)

/* Used by PM_L4PER_TIMER16_WKDEP */
#define DRA7XX_WKUPDEP_TIMER16_EVE2_SHIFT                       7
#define DRA7XX_WKUPDEP_TIMER16_EVE2_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER16_EVE2_MASK                        (1 << 7)

/* Used by PM_L4PER_TIMER16_WKDEP */
#define DRA7XX_WKUPDEP_TIMER16_EVE3_SHIFT                       8
#define DRA7XX_WKUPDEP_TIMER16_EVE3_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER16_EVE3_MASK                        (1 << 8)

/* Used by PM_L4PER_TIMER16_WKDEP */
#define DRA7XX_WKUPDEP_TIMER16_EVE4_SHIFT                       9
#define DRA7XX_WKUPDEP_TIMER16_EVE4_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER16_EVE4_MASK                        (1 << 9)

/* Used by PM_L4PER_TIMER16_WKDEP */
#define DRA7XX_WKUPDEP_TIMER16_IPU1_SHIFT                       4
#define DRA7XX_WKUPDEP_TIMER16_IPU1_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER16_IPU1_MASK                        (1 << 4)

/* Used by PM_L4PER_TIMER16_WKDEP */
#define DRA7XX_WKUPDEP_TIMER16_IPU2_SHIFT                       1
#define DRA7XX_WKUPDEP_TIMER16_IPU2_WIDTH                       0x1
#define DRA7XX_WKUPDEP_TIMER16_IPU2_MASK                        (1 << 1)

/* Used by PM_L4PER_TIMER16_WKDEP */
#define DRA7XX_WKUPDEP_TIMER16_MPU_SHIFT                        0
#define DRA7XX_WKUPDEP_TIMER16_MPU_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER16_MPU_MASK                         (1 << 0)

/* Used by PM_WKUPAON_TIMER1_WKDEP */
#define DRA7XX_WKUPDEP_TIMER1_DSP1_SHIFT                        2
#define DRA7XX_WKUPDEP_TIMER1_DSP1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER1_DSP1_MASK                         (1 << 2)

/* Used by PM_WKUPAON_TIMER1_WKDEP */
#define DRA7XX_WKUPDEP_TIMER1_DSP2_SHIFT                        5
#define DRA7XX_WKUPDEP_TIMER1_DSP2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER1_DSP2_MASK                         (1 << 5)

/* Used by PM_WKUPAON_TIMER1_WKDEP */
#define DRA7XX_WKUPDEP_TIMER1_EVE1_SHIFT                        6
#define DRA7XX_WKUPDEP_TIMER1_EVE1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER1_EVE1_MASK                         (1 << 6)

/* Used by PM_WKUPAON_TIMER1_WKDEP */
#define DRA7XX_WKUPDEP_TIMER1_EVE2_SHIFT                        7
#define DRA7XX_WKUPDEP_TIMER1_EVE2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER1_EVE2_MASK                         (1 << 7)

/* Used by PM_WKUPAON_TIMER1_WKDEP */
#define DRA7XX_WKUPDEP_TIMER1_EVE3_SHIFT                        8
#define DRA7XX_WKUPDEP_TIMER1_EVE3_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER1_EVE3_MASK                         (1 << 8)

/* Used by PM_WKUPAON_TIMER1_WKDEP */
#define DRA7XX_WKUPDEP_TIMER1_EVE4_SHIFT                        9
#define DRA7XX_WKUPDEP_TIMER1_EVE4_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER1_EVE4_MASK                         (1 << 9)

/* Used by PM_WKUPAON_TIMER1_WKDEP */
#define DRA7XX_WKUPDEP_TIMER1_IPU1_SHIFT                        4
#define DRA7XX_WKUPDEP_TIMER1_IPU1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER1_IPU1_MASK                         (1 << 4)

/* Used by PM_WKUPAON_TIMER1_WKDEP */
#define DRA7XX_WKUPDEP_TIMER1_IPU2_SHIFT                        1
#define DRA7XX_WKUPDEP_TIMER1_IPU2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER1_IPU2_MASK                         (1 << 1)

/* Used by PM_WKUPAON_TIMER1_WKDEP */
#define DRA7XX_WKUPDEP_TIMER1_MPU_SHIFT                         0
#define DRA7XX_WKUPDEP_TIMER1_MPU_WIDTH                         0x1
#define DRA7XX_WKUPDEP_TIMER1_MPU_MASK                          (1 << 0)

/* Used by PM_L4PER_TIMER2_WKDEP */
#define DRA7XX_WKUPDEP_TIMER2_DSP1_SHIFT                        2
#define DRA7XX_WKUPDEP_TIMER2_DSP1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER2_DSP1_MASK                         (1 << 2)

/* Used by PM_L4PER_TIMER2_WKDEP */
#define DRA7XX_WKUPDEP_TIMER2_DSP2_SHIFT                        5
#define DRA7XX_WKUPDEP_TIMER2_DSP2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER2_DSP2_MASK                         (1 << 5)

/* Used by PM_L4PER_TIMER2_WKDEP */
#define DRA7XX_WKUPDEP_TIMER2_EVE1_SHIFT                        6
#define DRA7XX_WKUPDEP_TIMER2_EVE1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER2_EVE1_MASK                         (1 << 6)

/* Used by PM_L4PER_TIMER2_WKDEP */
#define DRA7XX_WKUPDEP_TIMER2_EVE2_SHIFT                        7
#define DRA7XX_WKUPDEP_TIMER2_EVE2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER2_EVE2_MASK                         (1 << 7)

/* Used by PM_L4PER_TIMER2_WKDEP */
#define DRA7XX_WKUPDEP_TIMER2_EVE3_SHIFT                        8
#define DRA7XX_WKUPDEP_TIMER2_EVE3_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER2_EVE3_MASK                         (1 << 8)

/* Used by PM_L4PER_TIMER2_WKDEP */
#define DRA7XX_WKUPDEP_TIMER2_EVE4_SHIFT                        9
#define DRA7XX_WKUPDEP_TIMER2_EVE4_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER2_EVE4_MASK                         (1 << 9)

/* Used by PM_L4PER_TIMER2_WKDEP */
#define DRA7XX_WKUPDEP_TIMER2_IPU1_SHIFT                        4
#define DRA7XX_WKUPDEP_TIMER2_IPU1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER2_IPU1_MASK                         (1 << 4)

/* Used by PM_L4PER_TIMER2_WKDEP */
#define DRA7XX_WKUPDEP_TIMER2_IPU2_SHIFT                        1
#define DRA7XX_WKUPDEP_TIMER2_IPU2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER2_IPU2_MASK                         (1 << 1)

/* Used by PM_L4PER_TIMER2_WKDEP */
#define DRA7XX_WKUPDEP_TIMER2_MPU_SHIFT                         0
#define DRA7XX_WKUPDEP_TIMER2_MPU_WIDTH                         0x1
#define DRA7XX_WKUPDEP_TIMER2_MPU_MASK                          (1 << 0)

/* Used by PM_L4PER_TIMER3_WKDEP */
#define DRA7XX_WKUPDEP_TIMER3_DSP1_SHIFT                        2
#define DRA7XX_WKUPDEP_TIMER3_DSP1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER3_DSP1_MASK                         (1 << 2)

/* Used by PM_L4PER_TIMER3_WKDEP */
#define DRA7XX_WKUPDEP_TIMER3_DSP2_SHIFT                        5
#define DRA7XX_WKUPDEP_TIMER3_DSP2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER3_DSP2_MASK                         (1 << 5)

/* Used by PM_L4PER_TIMER3_WKDEP */
#define DRA7XX_WKUPDEP_TIMER3_EVE1_SHIFT                        6
#define DRA7XX_WKUPDEP_TIMER3_EVE1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER3_EVE1_MASK                         (1 << 6)

/* Used by PM_L4PER_TIMER3_WKDEP */
#define DRA7XX_WKUPDEP_TIMER3_EVE2_SHIFT                        7
#define DRA7XX_WKUPDEP_TIMER3_EVE2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER3_EVE2_MASK                         (1 << 7)

/* Used by PM_L4PER_TIMER3_WKDEP */
#define DRA7XX_WKUPDEP_TIMER3_EVE3_SHIFT                        8
#define DRA7XX_WKUPDEP_TIMER3_EVE3_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER3_EVE3_MASK                         (1 << 8)

/* Used by PM_L4PER_TIMER3_WKDEP */
#define DRA7XX_WKUPDEP_TIMER3_EVE4_SHIFT                        9
#define DRA7XX_WKUPDEP_TIMER3_EVE4_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER3_EVE4_MASK                         (1 << 9)

/* Used by PM_L4PER_TIMER3_WKDEP */
#define DRA7XX_WKUPDEP_TIMER3_IPU1_SHIFT                        4
#define DRA7XX_WKUPDEP_TIMER3_IPU1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER3_IPU1_MASK                         (1 << 4)

/* Used by PM_L4PER_TIMER3_WKDEP */
#define DRA7XX_WKUPDEP_TIMER3_IPU2_SHIFT                        1
#define DRA7XX_WKUPDEP_TIMER3_IPU2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER3_IPU2_MASK                         (1 << 1)

/* Used by PM_L4PER_TIMER3_WKDEP */
#define DRA7XX_WKUPDEP_TIMER3_MPU_SHIFT                         0
#define DRA7XX_WKUPDEP_TIMER3_MPU_WIDTH                         0x1
#define DRA7XX_WKUPDEP_TIMER3_MPU_MASK                          (1 << 0)

/* Used by PM_L4PER_TIMER4_WKDEP */
#define DRA7XX_WKUPDEP_TIMER4_DSP1_SHIFT                        2
#define DRA7XX_WKUPDEP_TIMER4_DSP1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER4_DSP1_MASK                         (1 << 2)

/* Used by PM_L4PER_TIMER4_WKDEP */
#define DRA7XX_WKUPDEP_TIMER4_DSP2_SHIFT                        5
#define DRA7XX_WKUPDEP_TIMER4_DSP2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER4_DSP2_MASK                         (1 << 5)

/* Used by PM_L4PER_TIMER4_WKDEP */
#define DRA7XX_WKUPDEP_TIMER4_EVE1_SHIFT                        6
#define DRA7XX_WKUPDEP_TIMER4_EVE1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER4_EVE1_MASK                         (1 << 6)

/* Used by PM_L4PER_TIMER4_WKDEP */
#define DRA7XX_WKUPDEP_TIMER4_EVE2_SHIFT                        7
#define DRA7XX_WKUPDEP_TIMER4_EVE2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER4_EVE2_MASK                         (1 << 7)

/* Used by PM_L4PER_TIMER4_WKDEP */
#define DRA7XX_WKUPDEP_TIMER4_EVE3_SHIFT                        8
#define DRA7XX_WKUPDEP_TIMER4_EVE3_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER4_EVE3_MASK                         (1 << 8)

/* Used by PM_L4PER_TIMER4_WKDEP */
#define DRA7XX_WKUPDEP_TIMER4_EVE4_SHIFT                        9
#define DRA7XX_WKUPDEP_TIMER4_EVE4_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER4_EVE4_MASK                         (1 << 9)

/* Used by PM_L4PER_TIMER4_WKDEP */
#define DRA7XX_WKUPDEP_TIMER4_IPU1_SHIFT                        4
#define DRA7XX_WKUPDEP_TIMER4_IPU1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER4_IPU1_MASK                         (1 << 4)

/* Used by PM_L4PER_TIMER4_WKDEP */
#define DRA7XX_WKUPDEP_TIMER4_IPU2_SHIFT                        1
#define DRA7XX_WKUPDEP_TIMER4_IPU2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER4_IPU2_MASK                         (1 << 1)

/* Used by PM_L4PER_TIMER4_WKDEP */
#define DRA7XX_WKUPDEP_TIMER4_MPU_SHIFT                         0
#define DRA7XX_WKUPDEP_TIMER4_MPU_WIDTH                         0x1
#define DRA7XX_WKUPDEP_TIMER4_MPU_MASK                          (1 << 0)

/* Used by PM_IPU_TIMER5_WKDEP */
#define DRA7XX_WKUPDEP_TIMER5_DSP1_SHIFT                        2
#define DRA7XX_WKUPDEP_TIMER5_DSP1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER5_DSP1_MASK                         (1 << 2)

/* Used by PM_IPU_TIMER5_WKDEP */
#define DRA7XX_WKUPDEP_TIMER5_DSP2_SHIFT                        5
#define DRA7XX_WKUPDEP_TIMER5_DSP2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER5_DSP2_MASK                         (1 << 5)

/* Used by PM_IPU_TIMER5_WKDEP */
#define DRA7XX_WKUPDEP_TIMER5_EVE1_SHIFT                        6
#define DRA7XX_WKUPDEP_TIMER5_EVE1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER5_EVE1_MASK                         (1 << 6)

/* Used by PM_IPU_TIMER5_WKDEP */
#define DRA7XX_WKUPDEP_TIMER5_EVE2_SHIFT                        7
#define DRA7XX_WKUPDEP_TIMER5_EVE2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER5_EVE2_MASK                         (1 << 7)

/* Used by PM_IPU_TIMER5_WKDEP */
#define DRA7XX_WKUPDEP_TIMER5_EVE3_SHIFT                        8
#define DRA7XX_WKUPDEP_TIMER5_EVE3_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER5_EVE3_MASK                         (1 << 8)

/* Used by PM_IPU_TIMER5_WKDEP */
#define DRA7XX_WKUPDEP_TIMER5_EVE4_SHIFT                        9
#define DRA7XX_WKUPDEP_TIMER5_EVE4_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER5_EVE4_MASK                         (1 << 9)

/* Used by PM_IPU_TIMER5_WKDEP */
#define DRA7XX_WKUPDEP_TIMER5_IPU1_SHIFT                        4
#define DRA7XX_WKUPDEP_TIMER5_IPU1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER5_IPU1_MASK                         (1 << 4)

/* Used by PM_IPU_TIMER5_WKDEP */
#define DRA7XX_WKUPDEP_TIMER5_IPU2_SHIFT                        1
#define DRA7XX_WKUPDEP_TIMER5_IPU2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER5_IPU2_MASK                         (1 << 1)

/* Used by PM_IPU_TIMER5_WKDEP */
#define DRA7XX_WKUPDEP_TIMER5_MPU_SHIFT                         0
#define DRA7XX_WKUPDEP_TIMER5_MPU_WIDTH                         0x1
#define DRA7XX_WKUPDEP_TIMER5_MPU_MASK                          (1 << 0)

/* Used by PM_IPU_TIMER6_WKDEP */
#define DRA7XX_WKUPDEP_TIMER6_DSP1_SHIFT                        2
#define DRA7XX_WKUPDEP_TIMER6_DSP1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER6_DSP1_MASK                         (1 << 2)

/* Used by PM_IPU_TIMER6_WKDEP */
#define DRA7XX_WKUPDEP_TIMER6_DSP2_SHIFT                        5
#define DRA7XX_WKUPDEP_TIMER6_DSP2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER6_DSP2_MASK                         (1 << 5)

/* Used by PM_IPU_TIMER6_WKDEP */
#define DRA7XX_WKUPDEP_TIMER6_EVE1_SHIFT                        6
#define DRA7XX_WKUPDEP_TIMER6_EVE1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER6_EVE1_MASK                         (1 << 6)

/* Used by PM_IPU_TIMER6_WKDEP */
#define DRA7XX_WKUPDEP_TIMER6_EVE2_SHIFT                        7
#define DRA7XX_WKUPDEP_TIMER6_EVE2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER6_EVE2_MASK                         (1 << 7)

/* Used by PM_IPU_TIMER6_WKDEP */
#define DRA7XX_WKUPDEP_TIMER6_EVE3_SHIFT                        8
#define DRA7XX_WKUPDEP_TIMER6_EVE3_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER6_EVE3_MASK                         (1 << 8)

/* Used by PM_IPU_TIMER6_WKDEP */
#define DRA7XX_WKUPDEP_TIMER6_EVE4_SHIFT                        9
#define DRA7XX_WKUPDEP_TIMER6_EVE4_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER6_EVE4_MASK                         (1 << 9)

/* Used by PM_IPU_TIMER6_WKDEP */
#define DRA7XX_WKUPDEP_TIMER6_IPU1_SHIFT                        4
#define DRA7XX_WKUPDEP_TIMER6_IPU1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER6_IPU1_MASK                         (1 << 4)

/* Used by PM_IPU_TIMER6_WKDEP */
#define DRA7XX_WKUPDEP_TIMER6_IPU2_SHIFT                        1
#define DRA7XX_WKUPDEP_TIMER6_IPU2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER6_IPU2_MASK                         (1 << 1)

/* Used by PM_IPU_TIMER6_WKDEP */
#define DRA7XX_WKUPDEP_TIMER6_MPU_SHIFT                         0
#define DRA7XX_WKUPDEP_TIMER6_MPU_WIDTH                         0x1
#define DRA7XX_WKUPDEP_TIMER6_MPU_MASK                          (1 << 0)

/* Used by PM_IPU_TIMER7_WKDEP */
#define DRA7XX_WKUPDEP_TIMER7_DSP1_SHIFT                        2
#define DRA7XX_WKUPDEP_TIMER7_DSP1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER7_DSP1_MASK                         (1 << 2)

/* Used by PM_IPU_TIMER7_WKDEP */
#define DRA7XX_WKUPDEP_TIMER7_DSP2_SHIFT                        5
#define DRA7XX_WKUPDEP_TIMER7_DSP2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER7_DSP2_MASK                         (1 << 5)

/* Used by PM_IPU_TIMER7_WKDEP */
#define DRA7XX_WKUPDEP_TIMER7_EVE1_SHIFT                        6
#define DRA7XX_WKUPDEP_TIMER7_EVE1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER7_EVE1_MASK                         (1 << 6)

/* Used by PM_IPU_TIMER7_WKDEP */
#define DRA7XX_WKUPDEP_TIMER7_EVE2_SHIFT                        7
#define DRA7XX_WKUPDEP_TIMER7_EVE2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER7_EVE2_MASK                         (1 << 7)

/* Used by PM_IPU_TIMER7_WKDEP */
#define DRA7XX_WKUPDEP_TIMER7_EVE3_SHIFT                        8
#define DRA7XX_WKUPDEP_TIMER7_EVE3_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER7_EVE3_MASK                         (1 << 8)

/* Used by PM_IPU_TIMER7_WKDEP */
#define DRA7XX_WKUPDEP_TIMER7_EVE4_SHIFT                        9
#define DRA7XX_WKUPDEP_TIMER7_EVE4_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER7_EVE4_MASK                         (1 << 9)

/* Used by PM_IPU_TIMER7_WKDEP */
#define DRA7XX_WKUPDEP_TIMER7_IPU1_SHIFT                        4
#define DRA7XX_WKUPDEP_TIMER7_IPU1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER7_IPU1_MASK                         (1 << 4)

/* Used by PM_IPU_TIMER7_WKDEP */
#define DRA7XX_WKUPDEP_TIMER7_IPU2_SHIFT                        1
#define DRA7XX_WKUPDEP_TIMER7_IPU2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER7_IPU2_MASK                         (1 << 1)

/* Used by PM_IPU_TIMER7_WKDEP */
#define DRA7XX_WKUPDEP_TIMER7_MPU_SHIFT                         0
#define DRA7XX_WKUPDEP_TIMER7_MPU_WIDTH                         0x1
#define DRA7XX_WKUPDEP_TIMER7_MPU_MASK                          (1 << 0)

/* Used by PM_IPU_TIMER8_WKDEP */
#define DRA7XX_WKUPDEP_TIMER8_DSP1_SHIFT                        2
#define DRA7XX_WKUPDEP_TIMER8_DSP1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER8_DSP1_MASK                         (1 << 2)

/* Used by PM_IPU_TIMER8_WKDEP */
#define DRA7XX_WKUPDEP_TIMER8_DSP2_SHIFT                        5
#define DRA7XX_WKUPDEP_TIMER8_DSP2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER8_DSP2_MASK                         (1 << 5)

/* Used by PM_IPU_TIMER8_WKDEP */
#define DRA7XX_WKUPDEP_TIMER8_EVE1_SHIFT                        6
#define DRA7XX_WKUPDEP_TIMER8_EVE1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER8_EVE1_MASK                         (1 << 6)

/* Used by PM_IPU_TIMER8_WKDEP */
#define DRA7XX_WKUPDEP_TIMER8_EVE2_SHIFT                        7
#define DRA7XX_WKUPDEP_TIMER8_EVE2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER8_EVE2_MASK                         (1 << 7)

/* Used by PM_IPU_TIMER8_WKDEP */
#define DRA7XX_WKUPDEP_TIMER8_EVE3_SHIFT                        8
#define DRA7XX_WKUPDEP_TIMER8_EVE3_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER8_EVE3_MASK                         (1 << 8)

/* Used by PM_IPU_TIMER8_WKDEP */
#define DRA7XX_WKUPDEP_TIMER8_EVE4_SHIFT                        9
#define DRA7XX_WKUPDEP_TIMER8_EVE4_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER8_EVE4_MASK                         (1 << 9)

/* Used by PM_IPU_TIMER8_WKDEP */
#define DRA7XX_WKUPDEP_TIMER8_IPU1_SHIFT                        4
#define DRA7XX_WKUPDEP_TIMER8_IPU1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER8_IPU1_MASK                         (1 << 4)

/* Used by PM_IPU_TIMER8_WKDEP */
#define DRA7XX_WKUPDEP_TIMER8_IPU2_SHIFT                        1
#define DRA7XX_WKUPDEP_TIMER8_IPU2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER8_IPU2_MASK                         (1 << 1)

/* Used by PM_IPU_TIMER8_WKDEP */
#define DRA7XX_WKUPDEP_TIMER8_MPU_SHIFT                         0
#define DRA7XX_WKUPDEP_TIMER8_MPU_WIDTH                         0x1
#define DRA7XX_WKUPDEP_TIMER8_MPU_MASK                          (1 << 0)

/* Used by PM_L4PER_TIMER9_WKDEP */
#define DRA7XX_WKUPDEP_TIMER9_DSP1_SHIFT                        2
#define DRA7XX_WKUPDEP_TIMER9_DSP1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER9_DSP1_MASK                         (1 << 2)

/* Used by PM_L4PER_TIMER9_WKDEP */
#define DRA7XX_WKUPDEP_TIMER9_DSP2_SHIFT                        5
#define DRA7XX_WKUPDEP_TIMER9_DSP2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER9_DSP2_MASK                         (1 << 5)

/* Used by PM_L4PER_TIMER9_WKDEP */
#define DRA7XX_WKUPDEP_TIMER9_EVE1_SHIFT                        6
#define DRA7XX_WKUPDEP_TIMER9_EVE1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER9_EVE1_MASK                         (1 << 6)

/* Used by PM_L4PER_TIMER9_WKDEP */
#define DRA7XX_WKUPDEP_TIMER9_EVE2_SHIFT                        7
#define DRA7XX_WKUPDEP_TIMER9_EVE2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER9_EVE2_MASK                         (1 << 7)

/* Used by PM_L4PER_TIMER9_WKDEP */
#define DRA7XX_WKUPDEP_TIMER9_EVE3_SHIFT                        8
#define DRA7XX_WKUPDEP_TIMER9_EVE3_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER9_EVE3_MASK                         (1 << 8)

/* Used by PM_L4PER_TIMER9_WKDEP */
#define DRA7XX_WKUPDEP_TIMER9_EVE4_SHIFT                        9
#define DRA7XX_WKUPDEP_TIMER9_EVE4_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER9_EVE4_MASK                         (1 << 9)

/* Used by PM_L4PER_TIMER9_WKDEP */
#define DRA7XX_WKUPDEP_TIMER9_IPU1_SHIFT                        4
#define DRA7XX_WKUPDEP_TIMER9_IPU1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER9_IPU1_MASK                         (1 << 4)

/* Used by PM_L4PER_TIMER9_WKDEP */
#define DRA7XX_WKUPDEP_TIMER9_IPU2_SHIFT                        1
#define DRA7XX_WKUPDEP_TIMER9_IPU2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_TIMER9_IPU2_MASK                         (1 << 1)

/* Used by PM_L4PER_TIMER9_WKDEP */
#define DRA7XX_WKUPDEP_TIMER9_MPU_SHIFT                         0
#define DRA7XX_WKUPDEP_TIMER9_MPU_WIDTH                         0x1
#define DRA7XX_WKUPDEP_TIMER9_MPU_MASK                          (1 << 0)

/* Used by PM_L3MAIN1_TPCC_WKDEP */
#define DRA7XX_WKUPDEP_TPCC_DSP1_SHIFT                          2
#define DRA7XX_WKUPDEP_TPCC_DSP1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_TPCC_DSP1_MASK                           (1 << 2)

/* Used by PM_L3MAIN1_TPCC_WKDEP */
#define DRA7XX_WKUPDEP_TPCC_DSP2_SHIFT                          5
#define DRA7XX_WKUPDEP_TPCC_DSP2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_TPCC_DSP2_MASK                           (1 << 5)

/* Used by PM_L3MAIN1_TPCC_WKDEP */
#define DRA7XX_WKUPDEP_TPCC_EVE1_SHIFT                          6
#define DRA7XX_WKUPDEP_TPCC_EVE1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_TPCC_EVE1_MASK                           (1 << 6)

/* Used by PM_L3MAIN1_TPCC_WKDEP */
#define DRA7XX_WKUPDEP_TPCC_EVE2_SHIFT                          7
#define DRA7XX_WKUPDEP_TPCC_EVE2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_TPCC_EVE2_MASK                           (1 << 7)

/* Used by PM_L3MAIN1_TPCC_WKDEP */
#define DRA7XX_WKUPDEP_TPCC_EVE3_SHIFT                          8
#define DRA7XX_WKUPDEP_TPCC_EVE3_WIDTH                          0x1
#define DRA7XX_WKUPDEP_TPCC_EVE3_MASK                           (1 << 8)

/* Used by PM_L3MAIN1_TPCC_WKDEP */
#define DRA7XX_WKUPDEP_TPCC_EVE4_SHIFT                          9
#define DRA7XX_WKUPDEP_TPCC_EVE4_WIDTH                          0x1
#define DRA7XX_WKUPDEP_TPCC_EVE4_MASK                           (1 << 9)

/* Used by PM_L3MAIN1_TPCC_WKDEP */
#define DRA7XX_WKUPDEP_TPCC_IPU1_SHIFT                          4
#define DRA7XX_WKUPDEP_TPCC_IPU1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_TPCC_IPU1_MASK                           (1 << 4)

/* Used by PM_L3MAIN1_TPCC_WKDEP */
#define DRA7XX_WKUPDEP_TPCC_IPU2_SHIFT                          1
#define DRA7XX_WKUPDEP_TPCC_IPU2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_TPCC_IPU2_MASK                           (1 << 1)

/* Used by PM_L3MAIN1_TPCC_WKDEP */
#define DRA7XX_WKUPDEP_TPCC_MPU_SHIFT                           0
#define DRA7XX_WKUPDEP_TPCC_MPU_WIDTH                           0x1
#define DRA7XX_WKUPDEP_TPCC_MPU_MASK                            (1 << 0)

/* Used by PM_L3MAIN1_TPTC1_WKDEP */
#define DRA7XX_WKUPDEP_TPTC1_DSP1_SHIFT                         2
#define DRA7XX_WKUPDEP_TPTC1_DSP1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_TPTC1_DSP1_MASK                          (1 << 2)

/* Used by PM_L3MAIN1_TPTC1_WKDEP */
#define DRA7XX_WKUPDEP_TPTC1_DSP2_SHIFT                         5
#define DRA7XX_WKUPDEP_TPTC1_DSP2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_TPTC1_DSP2_MASK                          (1 << 5)

/* Used by PM_L3MAIN1_TPTC1_WKDEP */
#define DRA7XX_WKUPDEP_TPTC1_EVE1_SHIFT                         6
#define DRA7XX_WKUPDEP_TPTC1_EVE1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_TPTC1_EVE1_MASK                          (1 << 6)

/* Used by PM_L3MAIN1_TPTC1_WKDEP */
#define DRA7XX_WKUPDEP_TPTC1_EVE2_SHIFT                         7
#define DRA7XX_WKUPDEP_TPTC1_EVE2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_TPTC1_EVE2_MASK                          (1 << 7)

/* Used by PM_L3MAIN1_TPTC1_WKDEP */
#define DRA7XX_WKUPDEP_TPTC1_EVE3_SHIFT                         8
#define DRA7XX_WKUPDEP_TPTC1_EVE3_WIDTH                         0x1
#define DRA7XX_WKUPDEP_TPTC1_EVE3_MASK                          (1 << 8)

/* Used by PM_L3MAIN1_TPTC1_WKDEP */
#define DRA7XX_WKUPDEP_TPTC1_EVE4_SHIFT                         9
#define DRA7XX_WKUPDEP_TPTC1_EVE4_WIDTH                         0x1
#define DRA7XX_WKUPDEP_TPTC1_EVE4_MASK                          (1 << 9)

/* Used by PM_L3MAIN1_TPTC1_WKDEP */
#define DRA7XX_WKUPDEP_TPTC1_IPU1_SHIFT                         4
#define DRA7XX_WKUPDEP_TPTC1_IPU1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_TPTC1_IPU1_MASK                          (1 << 4)

/* Used by PM_L3MAIN1_TPTC1_WKDEP */
#define DRA7XX_WKUPDEP_TPTC1_IPU2_SHIFT                         1
#define DRA7XX_WKUPDEP_TPTC1_IPU2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_TPTC1_IPU2_MASK                          (1 << 1)

/* Used by PM_L3MAIN1_TPTC1_WKDEP */
#define DRA7XX_WKUPDEP_TPTC1_MPU_SHIFT                          0
#define DRA7XX_WKUPDEP_TPTC1_MPU_WIDTH                          0x1
#define DRA7XX_WKUPDEP_TPTC1_MPU_MASK                           (1 << 0)

/* Used by PM_L3MAIN1_TPTC2_WKDEP */
#define DRA7XX_WKUPDEP_TPTC2_DSP1_SHIFT                         2
#define DRA7XX_WKUPDEP_TPTC2_DSP1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_TPTC2_DSP1_MASK                          (1 << 2)

/* Used by PM_L3MAIN1_TPTC2_WKDEP */
#define DRA7XX_WKUPDEP_TPTC2_DSP2_SHIFT                         5
#define DRA7XX_WKUPDEP_TPTC2_DSP2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_TPTC2_DSP2_MASK                          (1 << 5)

/* Used by PM_L3MAIN1_TPTC2_WKDEP */
#define DRA7XX_WKUPDEP_TPTC2_EVE1_SHIFT                         6
#define DRA7XX_WKUPDEP_TPTC2_EVE1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_TPTC2_EVE1_MASK                          (1 << 6)

/* Used by PM_L3MAIN1_TPTC2_WKDEP */
#define DRA7XX_WKUPDEP_TPTC2_EVE2_SHIFT                         7
#define DRA7XX_WKUPDEP_TPTC2_EVE2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_TPTC2_EVE2_MASK                          (1 << 7)

/* Used by PM_L3MAIN1_TPTC2_WKDEP */
#define DRA7XX_WKUPDEP_TPTC2_EVE3_SHIFT                         8
#define DRA7XX_WKUPDEP_TPTC2_EVE3_WIDTH                         0x1
#define DRA7XX_WKUPDEP_TPTC2_EVE3_MASK                          (1 << 8)

/* Used by PM_L3MAIN1_TPTC2_WKDEP */
#define DRA7XX_WKUPDEP_TPTC2_EVE4_SHIFT                         9
#define DRA7XX_WKUPDEP_TPTC2_EVE4_WIDTH                         0x1
#define DRA7XX_WKUPDEP_TPTC2_EVE4_MASK                          (1 << 9)

/* Used by PM_L3MAIN1_TPTC2_WKDEP */
#define DRA7XX_WKUPDEP_TPTC2_IPU1_SHIFT                         4
#define DRA7XX_WKUPDEP_TPTC2_IPU1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_TPTC2_IPU1_MASK                          (1 << 4)

/* Used by PM_L3MAIN1_TPTC2_WKDEP */
#define DRA7XX_WKUPDEP_TPTC2_IPU2_SHIFT                         1
#define DRA7XX_WKUPDEP_TPTC2_IPU2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_TPTC2_IPU2_MASK                          (1 << 1)

/* Used by PM_L3MAIN1_TPTC2_WKDEP */
#define DRA7XX_WKUPDEP_TPTC2_MPU_SHIFT                          0
#define DRA7XX_WKUPDEP_TPTC2_MPU_WIDTH                          0x1
#define DRA7XX_WKUPDEP_TPTC2_MPU_MASK                           (1 << 0)

/* Used by PM_WKUPAON_UART10_WKDEP */
#define DRA7XX_WKUPDEP_UART10_DSP1_SHIFT                        2
#define DRA7XX_WKUPDEP_UART10_DSP1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_UART10_DSP1_MASK                         (1 << 2)

/* Used by PM_WKUPAON_UART10_WKDEP */
#define DRA7XX_WKUPDEP_UART10_DSP2_SHIFT                        5
#define DRA7XX_WKUPDEP_UART10_DSP2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_UART10_DSP2_MASK                         (1 << 5)

/* Used by PM_WKUPAON_UART10_WKDEP */
#define DRA7XX_WKUPDEP_UART10_EVE1_SHIFT                        6
#define DRA7XX_WKUPDEP_UART10_EVE1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_UART10_EVE1_MASK                         (1 << 6)

/* Used by PM_WKUPAON_UART10_WKDEP */
#define DRA7XX_WKUPDEP_UART10_EVE2_SHIFT                        7
#define DRA7XX_WKUPDEP_UART10_EVE2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_UART10_EVE2_MASK                         (1 << 7)

/* Used by PM_WKUPAON_UART10_WKDEP */
#define DRA7XX_WKUPDEP_UART10_EVE3_SHIFT                        8
#define DRA7XX_WKUPDEP_UART10_EVE3_WIDTH                        0x1
#define DRA7XX_WKUPDEP_UART10_EVE3_MASK                         (1 << 8)

/* Used by PM_WKUPAON_UART10_WKDEP */
#define DRA7XX_WKUPDEP_UART10_EVE4_SHIFT                        9
#define DRA7XX_WKUPDEP_UART10_EVE4_WIDTH                        0x1
#define DRA7XX_WKUPDEP_UART10_EVE4_MASK                         (1 << 9)

/* Used by PM_WKUPAON_UART10_WKDEP */
#define DRA7XX_WKUPDEP_UART10_IPU1_SHIFT                        4
#define DRA7XX_WKUPDEP_UART10_IPU1_WIDTH                        0x1
#define DRA7XX_WKUPDEP_UART10_IPU1_MASK                         (1 << 4)

/* Used by PM_WKUPAON_UART10_WKDEP */
#define DRA7XX_WKUPDEP_UART10_IPU2_SHIFT                        1
#define DRA7XX_WKUPDEP_UART10_IPU2_WIDTH                        0x1
#define DRA7XX_WKUPDEP_UART10_IPU2_MASK                         (1 << 1)

/* Used by PM_WKUPAON_UART10_WKDEP */
#define DRA7XX_WKUPDEP_UART10_MPU_SHIFT                         0
#define DRA7XX_WKUPDEP_UART10_MPU_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART10_MPU_MASK                          (1 << 0)

/* Used by PM_WKUPAON_UART10_WKDEP */
#define DRA7XX_WKUPDEP_UART10_SDMA_SHIFT                        3
#define DRA7XX_WKUPDEP_UART10_SDMA_WIDTH                        0x1
#define DRA7XX_WKUPDEP_UART10_SDMA_MASK                         (1 << 3)

/* Used by PM_L4PER_UART1_WKDEP */
#define DRA7XX_WKUPDEP_UART1_DSP1_SHIFT                         2
#define DRA7XX_WKUPDEP_UART1_DSP1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART1_DSP1_MASK                          (1 << 2)

/* Used by PM_L4PER_UART1_WKDEP */
#define DRA7XX_WKUPDEP_UART1_DSP2_SHIFT                         5
#define DRA7XX_WKUPDEP_UART1_DSP2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART1_DSP2_MASK                          (1 << 5)

/* Used by PM_L4PER_UART1_WKDEP */
#define DRA7XX_WKUPDEP_UART1_EVE1_SHIFT                         6
#define DRA7XX_WKUPDEP_UART1_EVE1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART1_EVE1_MASK                          (1 << 6)

/* Used by PM_L4PER_UART1_WKDEP */
#define DRA7XX_WKUPDEP_UART1_EVE2_SHIFT                         7
#define DRA7XX_WKUPDEP_UART1_EVE2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART1_EVE2_MASK                          (1 << 7)

/* Used by PM_L4PER_UART1_WKDEP */
#define DRA7XX_WKUPDEP_UART1_EVE3_SHIFT                         8
#define DRA7XX_WKUPDEP_UART1_EVE3_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART1_EVE3_MASK                          (1 << 8)

/* Used by PM_L4PER_UART1_WKDEP */
#define DRA7XX_WKUPDEP_UART1_EVE4_SHIFT                         9
#define DRA7XX_WKUPDEP_UART1_EVE4_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART1_EVE4_MASK                          (1 << 9)

/* Used by PM_L4PER_UART1_WKDEP */
#define DRA7XX_WKUPDEP_UART1_IPU1_SHIFT                         4
#define DRA7XX_WKUPDEP_UART1_IPU1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART1_IPU1_MASK                          (1 << 4)

/* Used by PM_L4PER_UART1_WKDEP */
#define DRA7XX_WKUPDEP_UART1_IPU2_SHIFT                         1
#define DRA7XX_WKUPDEP_UART1_IPU2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART1_IPU2_MASK                          (1 << 1)

/* Used by PM_L4PER_UART1_WKDEP */
#define DRA7XX_WKUPDEP_UART1_MPU_SHIFT                          0
#define DRA7XX_WKUPDEP_UART1_MPU_WIDTH                          0x1
#define DRA7XX_WKUPDEP_UART1_MPU_MASK                           (1 << 0)

/* Used by PM_L4PER_UART1_WKDEP */
#define DRA7XX_WKUPDEP_UART1_SDMA_SHIFT                         3
#define DRA7XX_WKUPDEP_UART1_SDMA_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART1_SDMA_MASK                          (1 << 3)

/* Used by PM_L4PER_UART2_WKDEP */
#define DRA7XX_WKUPDEP_UART2_DSP1_SHIFT                         2
#define DRA7XX_WKUPDEP_UART2_DSP1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART2_DSP1_MASK                          (1 << 2)

/* Used by PM_L4PER_UART2_WKDEP */
#define DRA7XX_WKUPDEP_UART2_DSP2_SHIFT                         5
#define DRA7XX_WKUPDEP_UART2_DSP2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART2_DSP2_MASK                          (1 << 5)

/* Used by PM_L4PER_UART2_WKDEP */
#define DRA7XX_WKUPDEP_UART2_EVE1_SHIFT                         6
#define DRA7XX_WKUPDEP_UART2_EVE1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART2_EVE1_MASK                          (1 << 6)

/* Used by PM_L4PER_UART2_WKDEP */
#define DRA7XX_WKUPDEP_UART2_EVE2_SHIFT                         7
#define DRA7XX_WKUPDEP_UART2_EVE2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART2_EVE2_MASK                          (1 << 7)

/* Used by PM_L4PER_UART2_WKDEP */
#define DRA7XX_WKUPDEP_UART2_EVE3_SHIFT                         8
#define DRA7XX_WKUPDEP_UART2_EVE3_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART2_EVE3_MASK                          (1 << 8)

/* Used by PM_L4PER_UART2_WKDEP */
#define DRA7XX_WKUPDEP_UART2_EVE4_SHIFT                         9
#define DRA7XX_WKUPDEP_UART2_EVE4_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART2_EVE4_MASK                          (1 << 9)

/* Used by PM_L4PER_UART2_WKDEP */
#define DRA7XX_WKUPDEP_UART2_IPU1_SHIFT                         4
#define DRA7XX_WKUPDEP_UART2_IPU1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART2_IPU1_MASK                          (1 << 4)

/* Used by PM_L4PER_UART2_WKDEP */
#define DRA7XX_WKUPDEP_UART2_IPU2_SHIFT                         1
#define DRA7XX_WKUPDEP_UART2_IPU2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART2_IPU2_MASK                          (1 << 1)

/* Used by PM_L4PER_UART2_WKDEP */
#define DRA7XX_WKUPDEP_UART2_MPU_SHIFT                          0
#define DRA7XX_WKUPDEP_UART2_MPU_WIDTH                          0x1
#define DRA7XX_WKUPDEP_UART2_MPU_MASK                           (1 << 0)

/* Used by PM_L4PER_UART2_WKDEP */
#define DRA7XX_WKUPDEP_UART2_SDMA_SHIFT                         3
#define DRA7XX_WKUPDEP_UART2_SDMA_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART2_SDMA_MASK                          (1 << 3)

/* Used by PM_L4PER_UART3_WKDEP */
#define DRA7XX_WKUPDEP_UART3_DSP1_SHIFT                         2
#define DRA7XX_WKUPDEP_UART3_DSP1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART3_DSP1_MASK                          (1 << 2)

/* Used by PM_L4PER_UART3_WKDEP */
#define DRA7XX_WKUPDEP_UART3_DSP2_SHIFT                         5
#define DRA7XX_WKUPDEP_UART3_DSP2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART3_DSP2_MASK                          (1 << 5)

/* Used by PM_L4PER_UART3_WKDEP */
#define DRA7XX_WKUPDEP_UART3_EVE1_SHIFT                         6
#define DRA7XX_WKUPDEP_UART3_EVE1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART3_EVE1_MASK                          (1 << 6)

/* Used by PM_L4PER_UART3_WKDEP */
#define DRA7XX_WKUPDEP_UART3_EVE2_SHIFT                         7
#define DRA7XX_WKUPDEP_UART3_EVE2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART3_EVE2_MASK                          (1 << 7)

/* Used by PM_L4PER_UART3_WKDEP */
#define DRA7XX_WKUPDEP_UART3_EVE3_SHIFT                         8
#define DRA7XX_WKUPDEP_UART3_EVE3_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART3_EVE3_MASK                          (1 << 8)

/* Used by PM_L4PER_UART3_WKDEP */
#define DRA7XX_WKUPDEP_UART3_EVE4_SHIFT                         9
#define DRA7XX_WKUPDEP_UART3_EVE4_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART3_EVE4_MASK                          (1 << 9)

/* Used by PM_L4PER_UART3_WKDEP */
#define DRA7XX_WKUPDEP_UART3_IPU1_SHIFT                         4
#define DRA7XX_WKUPDEP_UART3_IPU1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART3_IPU1_MASK                          (1 << 4)

/* Used by PM_L4PER_UART3_WKDEP */
#define DRA7XX_WKUPDEP_UART3_IPU2_SHIFT                         1
#define DRA7XX_WKUPDEP_UART3_IPU2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART3_IPU2_MASK                          (1 << 1)

/* Used by PM_L4PER_UART3_WKDEP */
#define DRA7XX_WKUPDEP_UART3_MPU_SHIFT                          0
#define DRA7XX_WKUPDEP_UART3_MPU_WIDTH                          0x1
#define DRA7XX_WKUPDEP_UART3_MPU_MASK                           (1 << 0)

/* Used by PM_L4PER_UART3_WKDEP */
#define DRA7XX_WKUPDEP_UART3_SDMA_SHIFT                         3
#define DRA7XX_WKUPDEP_UART3_SDMA_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART3_SDMA_MASK                          (1 << 3)

/* Used by PM_L4PER_UART4_WKDEP */
#define DRA7XX_WKUPDEP_UART4_DSP1_SHIFT                         2
#define DRA7XX_WKUPDEP_UART4_DSP1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART4_DSP1_MASK                          (1 << 2)

/* Used by PM_L4PER_UART4_WKDEP */
#define DRA7XX_WKUPDEP_UART4_DSP2_SHIFT                         5
#define DRA7XX_WKUPDEP_UART4_DSP2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART4_DSP2_MASK                          (1 << 5)

/* Used by PM_L4PER_UART4_WKDEP */
#define DRA7XX_WKUPDEP_UART4_EVE1_SHIFT                         6
#define DRA7XX_WKUPDEP_UART4_EVE1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART4_EVE1_MASK                          (1 << 6)

/* Used by PM_L4PER_UART4_WKDEP */
#define DRA7XX_WKUPDEP_UART4_EVE2_SHIFT                         7
#define DRA7XX_WKUPDEP_UART4_EVE2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART4_EVE2_MASK                          (1 << 7)

/* Used by PM_L4PER_UART4_WKDEP */
#define DRA7XX_WKUPDEP_UART4_EVE3_SHIFT                         8
#define DRA7XX_WKUPDEP_UART4_EVE3_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART4_EVE3_MASK                          (1 << 8)

/* Used by PM_L4PER_UART4_WKDEP */
#define DRA7XX_WKUPDEP_UART4_EVE4_SHIFT                         9
#define DRA7XX_WKUPDEP_UART4_EVE4_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART4_EVE4_MASK                          (1 << 9)

/* Used by PM_L4PER_UART4_WKDEP */
#define DRA7XX_WKUPDEP_UART4_IPU1_SHIFT                         4
#define DRA7XX_WKUPDEP_UART4_IPU1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART4_IPU1_MASK                          (1 << 4)

/* Used by PM_L4PER_UART4_WKDEP */
#define DRA7XX_WKUPDEP_UART4_IPU2_SHIFT                         1
#define DRA7XX_WKUPDEP_UART4_IPU2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART4_IPU2_MASK                          (1 << 1)

/* Used by PM_L4PER_UART4_WKDEP */
#define DRA7XX_WKUPDEP_UART4_MPU_SHIFT                          0
#define DRA7XX_WKUPDEP_UART4_MPU_WIDTH                          0x1
#define DRA7XX_WKUPDEP_UART4_MPU_MASK                           (1 << 0)

/* Used by PM_L4PER_UART4_WKDEP */
#define DRA7XX_WKUPDEP_UART4_SDMA_SHIFT                         3
#define DRA7XX_WKUPDEP_UART4_SDMA_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART4_SDMA_MASK                          (1 << 3)

/* Used by PM_L4PER_UART5_WKDEP */
#define DRA7XX_WKUPDEP_UART5_DSP1_SHIFT                         2
#define DRA7XX_WKUPDEP_UART5_DSP1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART5_DSP1_MASK                          (1 << 2)

/* Used by PM_L4PER_UART5_WKDEP */
#define DRA7XX_WKUPDEP_UART5_DSP2_SHIFT                         5
#define DRA7XX_WKUPDEP_UART5_DSP2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART5_DSP2_MASK                          (1 << 5)

/* Used by PM_L4PER_UART5_WKDEP */
#define DRA7XX_WKUPDEP_UART5_EVE1_SHIFT                         6
#define DRA7XX_WKUPDEP_UART5_EVE1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART5_EVE1_MASK                          (1 << 6)

/* Used by PM_L4PER_UART5_WKDEP */
#define DRA7XX_WKUPDEP_UART5_EVE2_SHIFT                         7
#define DRA7XX_WKUPDEP_UART5_EVE2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART5_EVE2_MASK                          (1 << 7)

/* Used by PM_L4PER_UART5_WKDEP */
#define DRA7XX_WKUPDEP_UART5_EVE3_SHIFT                         8
#define DRA7XX_WKUPDEP_UART5_EVE3_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART5_EVE3_MASK                          (1 << 8)

/* Used by PM_L4PER_UART5_WKDEP */
#define DRA7XX_WKUPDEP_UART5_EVE4_SHIFT                         9
#define DRA7XX_WKUPDEP_UART5_EVE4_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART5_EVE4_MASK                          (1 << 9)

/* Used by PM_L4PER_UART5_WKDEP */
#define DRA7XX_WKUPDEP_UART5_IPU1_SHIFT                         4
#define DRA7XX_WKUPDEP_UART5_IPU1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART5_IPU1_MASK                          (1 << 4)

/* Used by PM_L4PER_UART5_WKDEP */
#define DRA7XX_WKUPDEP_UART5_IPU2_SHIFT                         1
#define DRA7XX_WKUPDEP_UART5_IPU2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART5_IPU2_MASK                          (1 << 1)

/* Used by PM_L4PER_UART5_WKDEP */
#define DRA7XX_WKUPDEP_UART5_MPU_SHIFT                          0
#define DRA7XX_WKUPDEP_UART5_MPU_WIDTH                          0x1
#define DRA7XX_WKUPDEP_UART5_MPU_MASK                           (1 << 0)

/* Used by PM_L4PER_UART5_WKDEP */
#define DRA7XX_WKUPDEP_UART5_SDMA_SHIFT                         3
#define DRA7XX_WKUPDEP_UART5_SDMA_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART5_SDMA_MASK                          (1 << 3)

/* Used by PM_IPU_UART6_WKDEP */
#define DRA7XX_WKUPDEP_UART6_DSP1_SHIFT                         2
#define DRA7XX_WKUPDEP_UART6_DSP1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART6_DSP1_MASK                          (1 << 2)

/* Used by PM_IPU_UART6_WKDEP */
#define DRA7XX_WKUPDEP_UART6_DSP2_SHIFT                         5
#define DRA7XX_WKUPDEP_UART6_DSP2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART6_DSP2_MASK                          (1 << 5)

/* Used by PM_IPU_UART6_WKDEP */
#define DRA7XX_WKUPDEP_UART6_EVE1_SHIFT                         6
#define DRA7XX_WKUPDEP_UART6_EVE1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART6_EVE1_MASK                          (1 << 6)

/* Used by PM_IPU_UART6_WKDEP */
#define DRA7XX_WKUPDEP_UART6_EVE2_SHIFT                         7
#define DRA7XX_WKUPDEP_UART6_EVE2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART6_EVE2_MASK                          (1 << 7)

/* Used by PM_IPU_UART6_WKDEP */
#define DRA7XX_WKUPDEP_UART6_EVE3_SHIFT                         8
#define DRA7XX_WKUPDEP_UART6_EVE3_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART6_EVE3_MASK                          (1 << 8)

/* Used by PM_IPU_UART6_WKDEP */
#define DRA7XX_WKUPDEP_UART6_EVE4_SHIFT                         9
#define DRA7XX_WKUPDEP_UART6_EVE4_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART6_EVE4_MASK                          (1 << 9)

/* Used by PM_IPU_UART6_WKDEP */
#define DRA7XX_WKUPDEP_UART6_IPU1_SHIFT                         4
#define DRA7XX_WKUPDEP_UART6_IPU1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART6_IPU1_MASK                          (1 << 4)

/* Used by PM_IPU_UART6_WKDEP */
#define DRA7XX_WKUPDEP_UART6_IPU2_SHIFT                         1
#define DRA7XX_WKUPDEP_UART6_IPU2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART6_IPU2_MASK                          (1 << 1)

/* Used by PM_IPU_UART6_WKDEP */
#define DRA7XX_WKUPDEP_UART6_MPU_SHIFT                          0
#define DRA7XX_WKUPDEP_UART6_MPU_WIDTH                          0x1
#define DRA7XX_WKUPDEP_UART6_MPU_MASK                           (1 << 0)

/* Used by PM_IPU_UART6_WKDEP */
#define DRA7XX_WKUPDEP_UART6_SDMA_SHIFT                         3
#define DRA7XX_WKUPDEP_UART6_SDMA_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART6_SDMA_MASK                          (1 << 3)

/* Used by PM_L4PER2_UART7_WKDEP */
#define DRA7XX_WKUPDEP_UART7_DSP1_SHIFT                         2
#define DRA7XX_WKUPDEP_UART7_DSP1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART7_DSP1_MASK                          (1 << 2)

/* Used by PM_L4PER2_UART7_WKDEP */
#define DRA7XX_WKUPDEP_UART7_DSP2_SHIFT                         5
#define DRA7XX_WKUPDEP_UART7_DSP2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART7_DSP2_MASK                          (1 << 5)

/* Used by PM_L4PER2_UART7_WKDEP */
#define DRA7XX_WKUPDEP_UART7_EVE1_SHIFT                         6
#define DRA7XX_WKUPDEP_UART7_EVE1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART7_EVE1_MASK                          (1 << 6)

/* Used by PM_L4PER2_UART7_WKDEP */
#define DRA7XX_WKUPDEP_UART7_EVE2_SHIFT                         7
#define DRA7XX_WKUPDEP_UART7_EVE2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART7_EVE2_MASK                          (1 << 7)

/* Used by PM_L4PER2_UART7_WKDEP */
#define DRA7XX_WKUPDEP_UART7_EVE3_SHIFT                         8
#define DRA7XX_WKUPDEP_UART7_EVE3_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART7_EVE3_MASK                          (1 << 8)

/* Used by PM_L4PER2_UART7_WKDEP */
#define DRA7XX_WKUPDEP_UART7_EVE4_SHIFT                         9
#define DRA7XX_WKUPDEP_UART7_EVE4_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART7_EVE4_MASK                          (1 << 9)

/* Used by PM_L4PER2_UART7_WKDEP */
#define DRA7XX_WKUPDEP_UART7_IPU1_SHIFT                         4
#define DRA7XX_WKUPDEP_UART7_IPU1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART7_IPU1_MASK                          (1 << 4)

/* Used by PM_L4PER2_UART7_WKDEP */
#define DRA7XX_WKUPDEP_UART7_IPU2_SHIFT                         1
#define DRA7XX_WKUPDEP_UART7_IPU2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART7_IPU2_MASK                          (1 << 1)

/* Used by PM_L4PER2_UART7_WKDEP */
#define DRA7XX_WKUPDEP_UART7_MPU_SHIFT                          0
#define DRA7XX_WKUPDEP_UART7_MPU_WIDTH                          0x1
#define DRA7XX_WKUPDEP_UART7_MPU_MASK                           (1 << 0)

/* Used by PM_L4PER2_UART7_WKDEP */
#define DRA7XX_WKUPDEP_UART7_SDMA_SHIFT                         3
#define DRA7XX_WKUPDEP_UART7_SDMA_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART7_SDMA_MASK                          (1 << 3)

/* Used by PM_L4PER2_UART8_WKDEP */
#define DRA7XX_WKUPDEP_UART8_DSP1_SHIFT                         2
#define DRA7XX_WKUPDEP_UART8_DSP1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART8_DSP1_MASK                          (1 << 2)

/* Used by PM_L4PER2_UART8_WKDEP */
#define DRA7XX_WKUPDEP_UART8_DSP2_SHIFT                         5
#define DRA7XX_WKUPDEP_UART8_DSP2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART8_DSP2_MASK                          (1 << 5)

/* Used by PM_L4PER2_UART8_WKDEP */
#define DRA7XX_WKUPDEP_UART8_EVE1_SHIFT                         6
#define DRA7XX_WKUPDEP_UART8_EVE1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART8_EVE1_MASK                          (1 << 6)

/* Used by PM_L4PER2_UART8_WKDEP */
#define DRA7XX_WKUPDEP_UART8_EVE2_SHIFT                         7
#define DRA7XX_WKUPDEP_UART8_EVE2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART8_EVE2_MASK                          (1 << 7)

/* Used by PM_L4PER2_UART8_WKDEP */
#define DRA7XX_WKUPDEP_UART8_EVE3_SHIFT                         8
#define DRA7XX_WKUPDEP_UART8_EVE3_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART8_EVE3_MASK                          (1 << 8)

/* Used by PM_L4PER2_UART8_WKDEP */
#define DRA7XX_WKUPDEP_UART8_EVE4_SHIFT                         9
#define DRA7XX_WKUPDEP_UART8_EVE4_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART8_EVE4_MASK                          (1 << 9)

/* Used by PM_L4PER2_UART8_WKDEP */
#define DRA7XX_WKUPDEP_UART8_IPU1_SHIFT                         4
#define DRA7XX_WKUPDEP_UART8_IPU1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART8_IPU1_MASK                          (1 << 4)

/* Used by PM_L4PER2_UART8_WKDEP */
#define DRA7XX_WKUPDEP_UART8_IPU2_SHIFT                         1
#define DRA7XX_WKUPDEP_UART8_IPU2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART8_IPU2_MASK                          (1 << 1)

/* Used by PM_L4PER2_UART8_WKDEP */
#define DRA7XX_WKUPDEP_UART8_MPU_SHIFT                          0
#define DRA7XX_WKUPDEP_UART8_MPU_WIDTH                          0x1
#define DRA7XX_WKUPDEP_UART8_MPU_MASK                           (1 << 0)

/* Used by PM_L4PER2_UART8_WKDEP */
#define DRA7XX_WKUPDEP_UART8_SDMA_SHIFT                         3
#define DRA7XX_WKUPDEP_UART8_SDMA_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART8_SDMA_MASK                          (1 << 3)

/* Used by PM_L4PER2_UART9_WKDEP */
#define DRA7XX_WKUPDEP_UART9_DSP1_SHIFT                         2
#define DRA7XX_WKUPDEP_UART9_DSP1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART9_DSP1_MASK                          (1 << 2)

/* Used by PM_L4PER2_UART9_WKDEP */
#define DRA7XX_WKUPDEP_UART9_DSP2_SHIFT                         5
#define DRA7XX_WKUPDEP_UART9_DSP2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART9_DSP2_MASK                          (1 << 5)

/* Used by PM_L4PER2_UART9_WKDEP */
#define DRA7XX_WKUPDEP_UART9_EVE1_SHIFT                         6
#define DRA7XX_WKUPDEP_UART9_EVE1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART9_EVE1_MASK                          (1 << 6)

/* Used by PM_L4PER2_UART9_WKDEP */
#define DRA7XX_WKUPDEP_UART9_EVE2_SHIFT                         7
#define DRA7XX_WKUPDEP_UART9_EVE2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART9_EVE2_MASK                          (1 << 7)

/* Used by PM_L4PER2_UART9_WKDEP */
#define DRA7XX_WKUPDEP_UART9_EVE3_SHIFT                         8
#define DRA7XX_WKUPDEP_UART9_EVE3_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART9_EVE3_MASK                          (1 << 8)

/* Used by PM_L4PER2_UART9_WKDEP */
#define DRA7XX_WKUPDEP_UART9_EVE4_SHIFT                         9
#define DRA7XX_WKUPDEP_UART9_EVE4_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART9_EVE4_MASK                          (1 << 9)

/* Used by PM_L4PER2_UART9_WKDEP */
#define DRA7XX_WKUPDEP_UART9_IPU1_SHIFT                         4
#define DRA7XX_WKUPDEP_UART9_IPU1_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART9_IPU1_MASK                          (1 << 4)

/* Used by PM_L4PER2_UART9_WKDEP */
#define DRA7XX_WKUPDEP_UART9_IPU2_SHIFT                         1
#define DRA7XX_WKUPDEP_UART9_IPU2_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART9_IPU2_MASK                          (1 << 1)

/* Used by PM_L4PER2_UART9_WKDEP */
#define DRA7XX_WKUPDEP_UART9_MPU_SHIFT                          0
#define DRA7XX_WKUPDEP_UART9_MPU_WIDTH                          0x1
#define DRA7XX_WKUPDEP_UART9_MPU_MASK                           (1 << 0)

/* Used by PM_L4PER2_UART9_WKDEP */
#define DRA7XX_WKUPDEP_UART9_SDMA_SHIFT                         3
#define DRA7XX_WKUPDEP_UART9_SDMA_WIDTH                         0x1
#define DRA7XX_WKUPDEP_UART9_SDMA_MASK                          (1 << 3)

/* Used by PM_L3INIT_USB_OTG_SS1_WKDEP */
#define DRA7XX_WKUPDEP_USB_OTG_SS1_DSP1_SHIFT                   2
#define DRA7XX_WKUPDEP_USB_OTG_SS1_DSP1_WIDTH                   0x1
#define DRA7XX_WKUPDEP_USB_OTG_SS1_DSP1_MASK                    (1 << 2)

/* Used by PM_L3INIT_USB_OTG_SS1_WKDEP */
#define DRA7XX_WKUPDEP_USB_OTG_SS1_DSP2_SHIFT                   5
#define DRA7XX_WKUPDEP_USB_OTG_SS1_DSP2_WIDTH                   0x1
#define DRA7XX_WKUPDEP_USB_OTG_SS1_DSP2_MASK                    (1 << 5)

/* Used by PM_L3INIT_USB_OTG_SS1_WKDEP */
#define DRA7XX_WKUPDEP_USB_OTG_SS1_EVE1_SHIFT                   6
#define DRA7XX_WKUPDEP_USB_OTG_SS1_EVE1_WIDTH                   0x1
#define DRA7XX_WKUPDEP_USB_OTG_SS1_EVE1_MASK                    (1 << 6)

/* Used by PM_L3INIT_USB_OTG_SS1_WKDEP */
#define DRA7XX_WKUPDEP_USB_OTG_SS1_EVE2_SHIFT                   7
#define DRA7XX_WKUPDEP_USB_OTG_SS1_EVE2_WIDTH                   0x1
#define DRA7XX_WKUPDEP_USB_OTG_SS1_EVE2_MASK                    (1 << 7)

/* Used by PM_L3INIT_USB_OTG_SS1_WKDEP */
#define DRA7XX_WKUPDEP_USB_OTG_SS1_EVE3_SHIFT                   8
#define DRA7XX_WKUPDEP_USB_OTG_SS1_EVE3_WIDTH                   0x1
#define DRA7XX_WKUPDEP_USB_OTG_SS1_EVE3_MASK                    (1 << 8)

/* Used by PM_L3INIT_USB_OTG_SS1_WKDEP */
#define DRA7XX_WKUPDEP_USB_OTG_SS1_EVE4_SHIFT                   9
#define DRA7XX_WKUPDEP_USB_OTG_SS1_EVE4_WIDTH                   0x1
#define DRA7XX_WKUPDEP_USB_OTG_SS1_EVE4_MASK                    (1 << 9)

/* Used by PM_L3INIT_USB_OTG_SS1_WKDEP */
#define DRA7XX_WKUPDEP_USB_OTG_SS1_IPU1_SHIFT                   4
#define DRA7XX_WKUPDEP_USB_OTG_SS1_IPU1_WIDTH                   0x1
#define DRA7XX_WKUPDEP_USB_OTG_SS1_IPU1_MASK                    (1 << 4)

/* Used by PM_L3INIT_USB_OTG_SS1_WKDEP */
#define DRA7XX_WKUPDEP_USB_OTG_SS1_IPU2_SHIFT                   1
#define DRA7XX_WKUPDEP_USB_OTG_SS1_IPU2_WIDTH                   0x1
#define DRA7XX_WKUPDEP_USB_OTG_SS1_IPU2_MASK                    (1 << 1)

/* Used by PM_L3INIT_USB_OTG_SS1_WKDEP */
#define DRA7XX_WKUPDEP_USB_OTG_SS1_MPU_SHIFT                    0
#define DRA7XX_WKUPDEP_USB_OTG_SS1_MPU_WIDTH                    0x1
#define DRA7XX_WKUPDEP_USB_OTG_SS1_MPU_MASK                     (1 << 0)

/* Used by PM_L3INIT_USB_OTG_SS2_WKDEP */
#define DRA7XX_WKUPDEP_USB_OTG_SS2_DSP1_SHIFT                   2
#define DRA7XX_WKUPDEP_USB_OTG_SS2_DSP1_WIDTH                   0x1
#define DRA7XX_WKUPDEP_USB_OTG_SS2_DSP1_MASK                    (1 << 2)

/* Used by PM_L3INIT_USB_OTG_SS2_WKDEP */
#define DRA7XX_WKUPDEP_USB_OTG_SS2_DSP2_SHIFT                   5
#define DRA7XX_WKUPDEP_USB_OTG_SS2_DSP2_WIDTH                   0x1
#define DRA7XX_WKUPDEP_USB_OTG_SS2_DSP2_MASK                    (1 << 5)

/* Used by PM_L3INIT_USB_OTG_SS2_WKDEP */
#define DRA7XX_WKUPDEP_USB_OTG_SS2_EVE1_SHIFT                   6
#define DRA7XX_WKUPDEP_USB_OTG_SS2_EVE1_WIDTH                   0x1
#define DRA7XX_WKUPDEP_USB_OTG_SS2_EVE1_MASK                    (1 << 6)

/* Used by PM_L3INIT_USB_OTG_SS2_WKDEP */
#define DRA7XX_WKUPDEP_USB_OTG_SS2_EVE2_SHIFT                   7
#define DRA7XX_WKUPDEP_USB_OTG_SS2_EVE2_WIDTH                   0x1
#define DRA7XX_WKUPDEP_USB_OTG_SS2_EVE2_MASK                    (1 << 7)

/* Used by PM_L3INIT_USB_OTG_SS2_WKDEP */
#define DRA7XX_WKUPDEP_USB_OTG_SS2_EVE3_SHIFT                   8
#define DRA7XX_WKUPDEP_USB_OTG_SS2_EVE3_WIDTH                   0x1
#define DRA7XX_WKUPDEP_USB_OTG_SS2_EVE3_MASK                    (1 << 8)

/* Used by PM_L3INIT_USB_OTG_SS2_WKDEP */
#define DRA7XX_WKUPDEP_USB_OTG_SS2_EVE4_SHIFT                   9
#define DRA7XX_WKUPDEP_USB_OTG_SS2_EVE4_WIDTH                   0x1
#define DRA7XX_WKUPDEP_USB_OTG_SS2_EVE4_MASK                    (1 << 9)

/* Used by PM_L3INIT_USB_OTG_SS2_WKDEP */
#define DRA7XX_WKUPDEP_USB_OTG_SS2_IPU1_SHIFT                   4
#define DRA7XX_WKUPDEP_USB_OTG_SS2_IPU1_WIDTH                   0x1
#define DRA7XX_WKUPDEP_USB_OTG_SS2_IPU1_MASK                    (1 << 4)

/* Used by PM_L3INIT_USB_OTG_SS2_WKDEP */
#define DRA7XX_WKUPDEP_USB_OTG_SS2_IPU2_SHIFT                   1
#define DRA7XX_WKUPDEP_USB_OTG_SS2_IPU2_WIDTH                   0x1
#define DRA7XX_WKUPDEP_USB_OTG_SS2_IPU2_MASK                    (1 << 1)

/* Used by PM_L3INIT_USB_OTG_SS2_WKDEP */
#define DRA7XX_WKUPDEP_USB_OTG_SS2_MPU_SHIFT                    0
#define DRA7XX_WKUPDEP_USB_OTG_SS2_MPU_WIDTH                    0x1
#define DRA7XX_WKUPDEP_USB_OTG_SS2_MPU_MASK                     (1 << 0)

/* Used by PM_L3INIT_USB_OTG_SS3_WKDEP */
#define DRA7XX_WKUPDEP_USB_OTG_SS3_DSP1_SHIFT                   2
#define DRA7XX_WKUPDEP_USB_OTG_SS3_DSP1_WIDTH                   0x1
#define DRA7XX_WKUPDEP_USB_OTG_SS3_DSP1_MASK                    (1 << 2)

/* Used by PM_L3INIT_USB_OTG_SS3_WKDEP */
#define DRA7XX_WKUPDEP_USB_OTG_SS3_DSP2_SHIFT                   5
#define DRA7XX_WKUPDEP_USB_OTG_SS3_DSP2_WIDTH                   0x1
#define DRA7XX_WKUPDEP_USB_OTG_SS3_DSP2_MASK                    (1 << 5)

/* Used by PM_L3INIT_USB_OTG_SS3_WKDEP */
#define DRA7XX_WKUPDEP_USB_OTG_SS3_EVE1_SHIFT                   6
#define DRA7XX_WKUPDEP_USB_OTG_SS3_EVE1_WIDTH                   0x1
#define DRA7XX_WKUPDEP_USB_OTG_SS3_EVE1_MASK                    (1 << 6)

/* Used by PM_L3INIT_USB_OTG_SS3_WKDEP */
#define DRA7XX_WKUPDEP_USB_OTG_SS3_EVE2_SHIFT                   7
#define DRA7XX_WKUPDEP_USB_OTG_SS3_EVE2_WIDTH                   0x1
#define DRA7XX_WKUPDEP_USB_OTG_SS3_EVE2_MASK                    (1 << 7)

/* Used by PM_L3INIT_USB_OTG_SS3_WKDEP */
#define DRA7XX_WKUPDEP_USB_OTG_SS3_EVE3_SHIFT                   8
#define DRA7XX_WKUPDEP_USB_OTG_SS3_EVE3_WIDTH                   0x1
#define DRA7XX_WKUPDEP_USB_OTG_SS3_EVE3_MASK                    (1 << 8)

/* Used by PM_L3INIT_USB_OTG_SS3_WKDEP */
#define DRA7XX_WKUPDEP_USB_OTG_SS3_EVE4_SHIFT                   9
#define DRA7XX_WKUPDEP_USB_OTG_SS3_EVE4_WIDTH                   0x1
#define DRA7XX_WKUPDEP_USB_OTG_SS3_EVE4_MASK                    (1 << 9)

/* Used by PM_L3INIT_USB_OTG_SS3_WKDEP */
#define DRA7XX_WKUPDEP_USB_OTG_SS3_IPU1_SHIFT                   4
#define DRA7XX_WKUPDEP_USB_OTG_SS3_IPU1_WIDTH                   0x1
#define DRA7XX_WKUPDEP_USB_OTG_SS3_IPU1_MASK                    (1 << 4)

/* Used by PM_L3INIT_USB_OTG_SS3_WKDEP */
#define DRA7XX_WKUPDEP_USB_OTG_SS3_IPU2_SHIFT                   1
#define DRA7XX_WKUPDEP_USB_OTG_SS3_IPU2_WIDTH                   0x1
#define DRA7XX_WKUPDEP_USB_OTG_SS3_IPU2_MASK                    (1 << 1)

/* Used by PM_L3INIT_USB_OTG_SS3_WKDEP */
#define DRA7XX_WKUPDEP_USB_OTG_SS3_MPU_SHIFT                    0
#define DRA7XX_WKUPDEP_USB_OTG_SS3_MPU_WIDTH                    0x1
#define DRA7XX_WKUPDEP_USB_OTG_SS3_MPU_MASK                     (1 << 0)

/* Used by PM_L3INIT_USB_OTG_SS4_WKDEP */
#define DRA7XX_WKUPDEP_USB_OTG_SS4_DSP1_SHIFT                   2
#define DRA7XX_WKUPDEP_USB_OTG_SS4_DSP1_WIDTH                   0x1
#define DRA7XX_WKUPDEP_USB_OTG_SS4_DSP1_MASK                    (1 << 2)

/* Used by PM_L3INIT_USB_OTG_SS4_WKDEP */
#define DRA7XX_WKUPDEP_USB_OTG_SS4_DSP2_SHIFT                   5
#define DRA7XX_WKUPDEP_USB_OTG_SS4_DSP2_WIDTH                   0x1
#define DRA7XX_WKUPDEP_USB_OTG_SS4_DSP2_MASK                    (1 << 5)

/* Used by PM_L3INIT_USB_OTG_SS4_WKDEP */
#define DRA7XX_WKUPDEP_USB_OTG_SS4_EVE1_SHIFT                   6
#define DRA7XX_WKUPDEP_USB_OTG_SS4_EVE1_WIDTH                   0x1
#define DRA7XX_WKUPDEP_USB_OTG_SS4_EVE1_MASK                    (1 << 6)

/* Used by PM_L3INIT_USB_OTG_SS4_WKDEP */
#define DRA7XX_WKUPDEP_USB_OTG_SS4_EVE2_SHIFT                   7
#define DRA7XX_WKUPDEP_USB_OTG_SS4_EVE2_WIDTH                   0x1
#define DRA7XX_WKUPDEP_USB_OTG_SS4_EVE2_MASK                    (1 << 7)

/* Used by PM_L3INIT_USB_OTG_SS4_WKDEP */
#define DRA7XX_WKUPDEP_USB_OTG_SS4_EVE3_SHIFT                   8
#define DRA7XX_WKUPDEP_USB_OTG_SS4_EVE3_WIDTH                   0x1
#define DRA7XX_WKUPDEP_USB_OTG_SS4_EVE3_MASK                    (1 << 8)

/* Used by PM_L3INIT_USB_OTG_SS4_WKDEP */
#define DRA7XX_WKUPDEP_USB_OTG_SS4_EVE4_SHIFT                   9
#define DRA7XX_WKUPDEP_USB_OTG_SS4_EVE4_WIDTH                   0x1
#define DRA7XX_WKUPDEP_USB_OTG_SS4_EVE4_MASK                    (1 << 9)

/* Used by PM_L3INIT_USB_OTG_SS4_WKDEP */
#define DRA7XX_WKUPDEP_USB_OTG_SS4_IPU1_SHIFT                   4
#define DRA7XX_WKUPDEP_USB_OTG_SS4_IPU1_WIDTH                   0x1
#define DRA7XX_WKUPDEP_USB_OTG_SS4_IPU1_MASK                    (1 << 4)

/* Used by PM_L3INIT_USB_OTG_SS4_WKDEP */
#define DRA7XX_WKUPDEP_USB_OTG_SS4_IPU2_SHIFT                   1
#define DRA7XX_WKUPDEP_USB_OTG_SS4_IPU2_WIDTH                   0x1
#define DRA7XX_WKUPDEP_USB_OTG_SS4_IPU2_MASK                    (1 << 1)

/* Used by PM_L3INIT_USB_OTG_SS4_WKDEP */
#define DRA7XX_WKUPDEP_USB_OTG_SS4_MPU_SHIFT                    0
#define DRA7XX_WKUPDEP_USB_OTG_SS4_MPU_WIDTH                    0x1
#define DRA7XX_WKUPDEP_USB_OTG_SS4_MPU_MASK                     (1 << 0)

/* Used by PM_CAM_VIP1_WKDEP */
#define DRA7XX_WKUPDEP_VIP1_DSP1_SHIFT                          2
#define DRA7XX_WKUPDEP_VIP1_DSP1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_VIP1_DSP1_MASK                           (1 << 2)

/* Used by PM_CAM_VIP1_WKDEP */
#define DRA7XX_WKUPDEP_VIP1_DSP2_SHIFT                          5
#define DRA7XX_WKUPDEP_VIP1_DSP2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_VIP1_DSP2_MASK                           (1 << 5)

/* Used by PM_CAM_VIP1_WKDEP */
#define DRA7XX_WKUPDEP_VIP1_EVE1_SHIFT                          6
#define DRA7XX_WKUPDEP_VIP1_EVE1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_VIP1_EVE1_MASK                           (1 << 6)

/* Used by PM_CAM_VIP1_WKDEP */
#define DRA7XX_WKUPDEP_VIP1_EVE2_SHIFT                          7
#define DRA7XX_WKUPDEP_VIP1_EVE2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_VIP1_EVE2_MASK                           (1 << 7)

/* Used by PM_CAM_VIP1_WKDEP */
#define DRA7XX_WKUPDEP_VIP1_EVE3_SHIFT                          8
#define DRA7XX_WKUPDEP_VIP1_EVE3_WIDTH                          0x1
#define DRA7XX_WKUPDEP_VIP1_EVE3_MASK                           (1 << 8)

/* Used by PM_CAM_VIP1_WKDEP */
#define DRA7XX_WKUPDEP_VIP1_EVE4_SHIFT                          9
#define DRA7XX_WKUPDEP_VIP1_EVE4_WIDTH                          0x1
#define DRA7XX_WKUPDEP_VIP1_EVE4_MASK                           (1 << 9)

/* Used by PM_CAM_VIP1_WKDEP */
#define DRA7XX_WKUPDEP_VIP1_IPU1_SHIFT                          4
#define DRA7XX_WKUPDEP_VIP1_IPU1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_VIP1_IPU1_MASK                           (1 << 4)

/* Used by PM_CAM_VIP1_WKDEP */
#define DRA7XX_WKUPDEP_VIP1_IPU2_SHIFT                          1
#define DRA7XX_WKUPDEP_VIP1_IPU2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_VIP1_IPU2_MASK                           (1 << 1)

/* Used by PM_CAM_VIP1_WKDEP */
#define DRA7XX_WKUPDEP_VIP1_MPU_SHIFT                           0
#define DRA7XX_WKUPDEP_VIP1_MPU_WIDTH                           0x1
#define DRA7XX_WKUPDEP_VIP1_MPU_MASK                            (1 << 0)

/* Used by PM_CAM_VIP2_WKDEP */
#define DRA7XX_WKUPDEP_VIP2_DSP1_SHIFT                          2
#define DRA7XX_WKUPDEP_VIP2_DSP1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_VIP2_DSP1_MASK                           (1 << 2)

/* Used by PM_CAM_VIP2_WKDEP */
#define DRA7XX_WKUPDEP_VIP2_DSP2_SHIFT                          5
#define DRA7XX_WKUPDEP_VIP2_DSP2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_VIP2_DSP2_MASK                           (1 << 5)

/* Used by PM_CAM_VIP2_WKDEP */
#define DRA7XX_WKUPDEP_VIP2_EVE1_SHIFT                          6
#define DRA7XX_WKUPDEP_VIP2_EVE1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_VIP2_EVE1_MASK                           (1 << 6)

/* Used by PM_CAM_VIP2_WKDEP */
#define DRA7XX_WKUPDEP_VIP2_EVE2_SHIFT                          7
#define DRA7XX_WKUPDEP_VIP2_EVE2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_VIP2_EVE2_MASK                           (1 << 7)

/* Used by PM_CAM_VIP2_WKDEP */
#define DRA7XX_WKUPDEP_VIP2_EVE3_SHIFT                          8
#define DRA7XX_WKUPDEP_VIP2_EVE3_WIDTH                          0x1
#define DRA7XX_WKUPDEP_VIP2_EVE3_MASK                           (1 << 8)

/* Used by PM_CAM_VIP2_WKDEP */
#define DRA7XX_WKUPDEP_VIP2_EVE4_SHIFT                          9
#define DRA7XX_WKUPDEP_VIP2_EVE4_WIDTH                          0x1
#define DRA7XX_WKUPDEP_VIP2_EVE4_MASK                           (1 << 9)

/* Used by PM_CAM_VIP2_WKDEP */
#define DRA7XX_WKUPDEP_VIP2_IPU1_SHIFT                          4
#define DRA7XX_WKUPDEP_VIP2_IPU1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_VIP2_IPU1_MASK                           (1 << 4)

/* Used by PM_CAM_VIP2_WKDEP */
#define DRA7XX_WKUPDEP_VIP2_IPU2_SHIFT                          1
#define DRA7XX_WKUPDEP_VIP2_IPU2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_VIP2_IPU2_MASK                           (1 << 1)

/* Used by PM_CAM_VIP2_WKDEP */
#define DRA7XX_WKUPDEP_VIP2_MPU_SHIFT                           0
#define DRA7XX_WKUPDEP_VIP2_MPU_WIDTH                           0x1
#define DRA7XX_WKUPDEP_VIP2_MPU_MASK                            (1 << 0)

/* Used by PM_CAM_VIP3_WKDEP */
#define DRA7XX_WKUPDEP_VIP3_DSP1_SHIFT                          2
#define DRA7XX_WKUPDEP_VIP3_DSP1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_VIP3_DSP1_MASK                           (1 << 2)

/* Used by PM_CAM_VIP3_WKDEP */
#define DRA7XX_WKUPDEP_VIP3_DSP2_SHIFT                          5
#define DRA7XX_WKUPDEP_VIP3_DSP2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_VIP3_DSP2_MASK                           (1 << 5)

/* Used by PM_CAM_VIP3_WKDEP */
#define DRA7XX_WKUPDEP_VIP3_EVE1_SHIFT                          6
#define DRA7XX_WKUPDEP_VIP3_EVE1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_VIP3_EVE1_MASK                           (1 << 6)

/* Used by PM_CAM_VIP3_WKDEP */
#define DRA7XX_WKUPDEP_VIP3_EVE2_SHIFT                          7
#define DRA7XX_WKUPDEP_VIP3_EVE2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_VIP3_EVE2_MASK                           (1 << 7)

/* Used by PM_CAM_VIP3_WKDEP */
#define DRA7XX_WKUPDEP_VIP3_EVE3_SHIFT                          8
#define DRA7XX_WKUPDEP_VIP3_EVE3_WIDTH                          0x1
#define DRA7XX_WKUPDEP_VIP3_EVE3_MASK                           (1 << 8)

/* Used by PM_CAM_VIP3_WKDEP */
#define DRA7XX_WKUPDEP_VIP3_EVE4_SHIFT                          9
#define DRA7XX_WKUPDEP_VIP3_EVE4_WIDTH                          0x1
#define DRA7XX_WKUPDEP_VIP3_EVE4_MASK                           (1 << 9)

/* Used by PM_CAM_VIP3_WKDEP */
#define DRA7XX_WKUPDEP_VIP3_IPU1_SHIFT                          4
#define DRA7XX_WKUPDEP_VIP3_IPU1_WIDTH                          0x1
#define DRA7XX_WKUPDEP_VIP3_IPU1_MASK                           (1 << 4)

/* Used by PM_CAM_VIP3_WKDEP */
#define DRA7XX_WKUPDEP_VIP3_IPU2_SHIFT                          1
#define DRA7XX_WKUPDEP_VIP3_IPU2_WIDTH                          0x1
#define DRA7XX_WKUPDEP_VIP3_IPU2_MASK                           (1 << 1)

/* Used by PM_CAM_VIP3_WKDEP */
#define DRA7XX_WKUPDEP_VIP3_MPU_SHIFT                           0
#define DRA7XX_WKUPDEP_VIP3_MPU_WIDTH                           0x1
#define DRA7XX_WKUPDEP_VIP3_MPU_MASK                            (1 << 0)

/* Used by PM_VPE_VPE_WKDEP */
#define DRA7XX_WKUPDEP_VPE_DSP1_SHIFT                           2
#define DRA7XX_WKUPDEP_VPE_DSP1_WIDTH                           0x1
#define DRA7XX_WKUPDEP_VPE_DSP1_MASK                            (1 << 2)

/* Used by PM_VPE_VPE_WKDEP */
#define DRA7XX_WKUPDEP_VPE_DSP2_SHIFT                           5
#define DRA7XX_WKUPDEP_VPE_DSP2_WIDTH                           0x1
#define DRA7XX_WKUPDEP_VPE_DSP2_MASK                            (1 << 5)

/* Used by PM_VPE_VPE_WKDEP */
#define DRA7XX_WKUPDEP_VPE_EVE1_SHIFT                           6
#define DRA7XX_WKUPDEP_VPE_EVE1_WIDTH                           0x1
#define DRA7XX_WKUPDEP_VPE_EVE1_MASK                            (1 << 6)

/* Used by PM_VPE_VPE_WKDEP */
#define DRA7XX_WKUPDEP_VPE_EVE2_SHIFT                           7
#define DRA7XX_WKUPDEP_VPE_EVE2_WIDTH                           0x1
#define DRA7XX_WKUPDEP_VPE_EVE2_MASK                            (1 << 7)

/* Used by PM_VPE_VPE_WKDEP */
#define DRA7XX_WKUPDEP_VPE_EVE3_SHIFT                           8
#define DRA7XX_WKUPDEP_VPE_EVE3_WIDTH                           0x1
#define DRA7XX_WKUPDEP_VPE_EVE3_MASK                            (1 << 8)

/* Used by PM_VPE_VPE_WKDEP */
#define DRA7XX_WKUPDEP_VPE_EVE4_SHIFT                           9
#define DRA7XX_WKUPDEP_VPE_EVE4_WIDTH                           0x1
#define DRA7XX_WKUPDEP_VPE_EVE4_MASK                            (1 << 9)

/* Used by PM_VPE_VPE_WKDEP */
#define DRA7XX_WKUPDEP_VPE_IPU1_SHIFT                           4
#define DRA7XX_WKUPDEP_VPE_IPU1_WIDTH                           0x1
#define DRA7XX_WKUPDEP_VPE_IPU1_MASK                            (1 << 4)

/* Used by PM_VPE_VPE_WKDEP */
#define DRA7XX_WKUPDEP_VPE_IPU2_SHIFT                           1
#define DRA7XX_WKUPDEP_VPE_IPU2_WIDTH                           0x1
#define DRA7XX_WKUPDEP_VPE_IPU2_MASK                            (1 << 1)

/* Used by PM_VPE_VPE_WKDEP */
#define DRA7XX_WKUPDEP_VPE_MPU_SHIFT                            0
#define DRA7XX_WKUPDEP_VPE_MPU_WIDTH                            0x1
#define DRA7XX_WKUPDEP_VPE_MPU_MASK                             (1 << 0)

/* Used by PM_WKUPAON_WD_TIMER1_WKDEP */
#define DRA7XX_WKUPDEP_WD_TIMER1_DSP1_SHIFT                     2
#define DRA7XX_WKUPDEP_WD_TIMER1_DSP1_WIDTH                     0x1
#define DRA7XX_WKUPDEP_WD_TIMER1_DSP1_MASK                      (1 << 2)

/* Used by PM_WKUPAON_WD_TIMER1_WKDEP */
#define DRA7XX_WKUPDEP_WD_TIMER1_DSP2_SHIFT                     5
#define DRA7XX_WKUPDEP_WD_TIMER1_DSP2_WIDTH                     0x1
#define DRA7XX_WKUPDEP_WD_TIMER1_DSP2_MASK                      (1 << 5)

/* Used by PM_WKUPAON_WD_TIMER1_WKDEP */
#define DRA7XX_WKUPDEP_WD_TIMER1_EVE1_SHIFT                     6
#define DRA7XX_WKUPDEP_WD_TIMER1_EVE1_WIDTH                     0x1
#define DRA7XX_WKUPDEP_WD_TIMER1_EVE1_MASK                      (1 << 6)

/* Used by PM_WKUPAON_WD_TIMER1_WKDEP */
#define DRA7XX_WKUPDEP_WD_TIMER1_EVE2_SHIFT                     7
#define DRA7XX_WKUPDEP_WD_TIMER1_EVE2_WIDTH                     0x1
#define DRA7XX_WKUPDEP_WD_TIMER1_EVE2_MASK                      (1 << 7)

/* Used by PM_WKUPAON_WD_TIMER1_WKDEP */
#define DRA7XX_WKUPDEP_WD_TIMER1_EVE3_SHIFT                     8
#define DRA7XX_WKUPDEP_WD_TIMER1_EVE3_WIDTH                     0x1
#define DRA7XX_WKUPDEP_WD_TIMER1_EVE3_MASK                      (1 << 8)

/* Used by PM_WKUPAON_WD_TIMER1_WKDEP */
#define DRA7XX_WKUPDEP_WD_TIMER1_EVE4_SHIFT                     9
#define DRA7XX_WKUPDEP_WD_TIMER1_EVE4_WIDTH                     0x1
#define DRA7XX_WKUPDEP_WD_TIMER1_EVE4_MASK                      (1 << 9)

/* Used by PM_WKUPAON_WD_TIMER1_WKDEP */
#define DRA7XX_WKUPDEP_WD_TIMER1_IPU1_SHIFT                     4
#define DRA7XX_WKUPDEP_WD_TIMER1_IPU1_WIDTH                     0x1
#define DRA7XX_WKUPDEP_WD_TIMER1_IPU1_MASK                      (1 << 4)

/* Used by PM_WKUPAON_WD_TIMER1_WKDEP */
#define DRA7XX_WKUPDEP_WD_TIMER1_IPU2_SHIFT                     1
#define DRA7XX_WKUPDEP_WD_TIMER1_IPU2_WIDTH                     0x1
#define DRA7XX_WKUPDEP_WD_TIMER1_IPU2_MASK                      (1 << 1)

/* Used by PM_WKUPAON_WD_TIMER1_WKDEP */
#define DRA7XX_WKUPDEP_WD_TIMER1_MPU_SHIFT                      0
#define DRA7XX_WKUPDEP_WD_TIMER1_MPU_WIDTH                      0x1
#define DRA7XX_WKUPDEP_WD_TIMER1_MPU_MASK                       (1 << 0)

/* Used by PM_WKUPAON_WD_TIMER2_WKDEP */
#define DRA7XX_WKUPDEP_WD_TIMER2_DSP1_SHIFT                     2
#define DRA7XX_WKUPDEP_WD_TIMER2_DSP1_WIDTH                     0x1
#define DRA7XX_WKUPDEP_WD_TIMER2_DSP1_MASK                      (1 << 2)

/* Used by PM_WKUPAON_WD_TIMER2_WKDEP */
#define DRA7XX_WKUPDEP_WD_TIMER2_DSP2_SHIFT                     5
#define DRA7XX_WKUPDEP_WD_TIMER2_DSP2_WIDTH                     0x1
#define DRA7XX_WKUPDEP_WD_TIMER2_DSP2_MASK                      (1 << 5)

/* Used by PM_WKUPAON_WD_TIMER2_WKDEP */
#define DRA7XX_WKUPDEP_WD_TIMER2_EVE1_SHIFT                     6
#define DRA7XX_WKUPDEP_WD_TIMER2_EVE1_WIDTH                     0x1
#define DRA7XX_WKUPDEP_WD_TIMER2_EVE1_MASK                      (1 << 6)

/* Used by PM_WKUPAON_WD_TIMER2_WKDEP */
#define DRA7XX_WKUPDEP_WD_TIMER2_EVE2_SHIFT                     7
#define DRA7XX_WKUPDEP_WD_TIMER2_EVE2_WIDTH                     0x1
#define DRA7XX_WKUPDEP_WD_TIMER2_EVE2_MASK                      (1 << 7)

/* Used by PM_WKUPAON_WD_TIMER2_WKDEP */
#define DRA7XX_WKUPDEP_WD_TIMER2_EVE3_SHIFT                     8
#define DRA7XX_WKUPDEP_WD_TIMER2_EVE3_WIDTH                     0x1
#define DRA7XX_WKUPDEP_WD_TIMER2_EVE3_MASK                      (1 << 8)

/* Used by PM_WKUPAON_WD_TIMER2_WKDEP */
#define DRA7XX_WKUPDEP_WD_TIMER2_EVE4_SHIFT                     9
#define DRA7XX_WKUPDEP_WD_TIMER2_EVE4_WIDTH                     0x1
#define DRA7XX_WKUPDEP_WD_TIMER2_EVE4_MASK                      (1 << 9)

/* Used by PM_WKUPAON_WD_TIMER2_WKDEP */
#define DRA7XX_WKUPDEP_WD_TIMER2_IPU1_SHIFT                     4
#define DRA7XX_WKUPDEP_WD_TIMER2_IPU1_WIDTH                     0x1
#define DRA7XX_WKUPDEP_WD_TIMER2_IPU1_MASK                      (1 << 4)

/* Used by PM_WKUPAON_WD_TIMER2_WKDEP */
#define DRA7XX_WKUPDEP_WD_TIMER2_IPU2_SHIFT                     1
#define DRA7XX_WKUPDEP_WD_TIMER2_IPU2_WIDTH                     0x1
#define DRA7XX_WKUPDEP_WD_TIMER2_IPU2_MASK                      (1 << 1)

/* Used by PM_WKUPAON_WD_TIMER2_WKDEP */
#define DRA7XX_WKUPDEP_WD_TIMER2_MPU_SHIFT                      0
#define DRA7XX_WKUPDEP_WD_TIMER2_MPU_WIDTH                      0x1
#define DRA7XX_WKUPDEP_WD_TIMER2_MPU_MASK                       (1 << 0)

/* Used by PRM_IO_PMCTRL */
#define DRA7XX_WUCLK_CTRL_SHIFT                                 8
#define DRA7XX_WUCLK_CTRL_WIDTH                                 0x1
#define DRA7XX_WUCLK_CTRL_MASK                                  (1 << 8)

/* Used by PRM_IO_PMCTRL */
#define DRA7XX_WUCLK_STATUS_SHIFT                               9
#define DRA7XX_WUCLK_STATUS_WIDTH                               0x1
#define DRA7XX_WUCLK_STATUS_MASK                                (1 << 9)

/* Used by REVISION_PRM */
#define DRA7XX_X_MAJOR_SHIFT                                    8
#define DRA7XX_X_MAJOR_WIDTH                                    0x3
#define DRA7XX_X_MAJOR_MASK                                     (0x7 << 8)

/* Used by REVISION_PRM */
#define DRA7XX_Y_MINOR_SHIFT                                    0
#define DRA7XX_Y_MINOR_WIDTH                                    0x6
#define DRA7XX_Y_MINOR_MASK                                     (0x3f << 0)
#endif