1 /**
2 * sata.c - The ahci sata device init functions
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com
5 * Author: Keshava Munegowda <keshava_mgowda@ti.com>
6 *
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 of
9 * the License as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <linux/io.h>
20 #include <linux/kernel.h>
21 #include <linux/device.h>
22 #include <linux/platform_device.h>
23 #include <linux/platform_data/omap_ocp2scp.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/ahci_platform.h>
27 #include <linux/clk.h>
28 #include <plat/sata.h>
30 #include "omap_device.h"
31 #include "soc.h"
33 #define OMAP_SATA_HWMODNAME "sata"
34 #define OMAP_OCP2SCP3_HWMODNAME "ocp2scp3"
35 #define AHCI_PLAT_DEVNAME "ahci"
37 #define OMAP_SATA_PLL_CONTROL 0x00
38 #define OMAP_SATA_PLL_STATUS 0x04
39 #define OMAP_SATA_PLL_STATUS_LOCK_SHIFT 1
40 #define OMAP_SATA_PLL_STATUS_LOCK 1
41 #define OMAP_SATA_PLL_STATUS_RESET_DONE 1
42 #define OMAP_SATA_PLL_STATUS_LDOPWDN_SHIFT 15
43 #define OMAP_SATA_PLL_STATUS_TICOPWDN_SHIFT 16
45 #define OMAP_SATA_PLL_GO 0x08
47 #define OMAP_SATA_PLL_CFG1 0x0c
48 #define OMAP_SATA_PLL_CFG1_M 625
49 #define OMAP_SATA_PLL_CFG1_M_MASK 0xfff
50 #define OMAP_SATA_PLL_CFG1_M_SHIFT 9
52 #define OMAP_SATA_PLL_CFG1_N 7
53 #define OMAP_SATA_PLL_CFG1_N_MASK 0xff
54 #define OMAP_SATA_PLL_CFG1_N_SHIFT 1
56 #define OMAP_SATA_PLL_CFG2 0x10
57 #define OMAP_SATA_PLL_CFG2_SELFREQDCO 4
58 #define OMAP_SATA_PLL_CFG2_SELFREQDCO_MASK 7
59 #define OMAP_SATA_PLL_CFG2_SELFREQDCO_SHIFT 1
60 #define OMAP_SATA_PLL_CFG2_REFSEL 0
61 #define OMAP_SATA_PLL_CFG2_REFSEL_MASK 3
62 #define OMAP_SATA_PLL_CFG2_REFSEL_SHIFT 21
63 #define OMAP_SATA_PLL_CFG2_LOCKSEL 1
64 #define OMAP_SATA_PLL_CFG2_LOCKSEL_MASK 3
65 #define OMAP_SATA_PLL_CFG2_LOCKSEL_SHIFT 9
66 #define OMAP_SATA_PLL_CFG2_IDLE 1
67 #define OMAP_SATA_PLL_CFG2_IDLE_MASK 1
69 #define OMAP_SATA_PLL_CFG3 0x14
71 #define OMAP_SATA_PLL_CFG3_SD 6
72 #define OMAP_SATA_PLL_CFG3_SD_MASK 0xff
73 #define OMAP_SATA_PLL_CFG3_SD_SHIF 10
75 #define OMAP_SATA_PLL_CFG4 0x20
76 #define OMAP_SATA_PLL_CFG4_REGM_F 0
77 #define OMAP_SATA_PLL_CFG4_REGM_F_MASK 0x3ffff
78 #define OMAP_SATA_PLL_CFG4_REGM2 1
79 #define OMAP_SATA_PLL_CFG4_REGM2_MASK 0x1fc
80 #define OMAP_SATA_PLL_CFG4_REGM2_SHIFT 18
82 #define OMAP_OCP2SCP3_SYSCONFIG 0x10
83 #define OMAP_OCP2SCP3_SYSCONFIG_RESET_MASK 1
84 #define OMAP_OCP2SCP3_SYSCONFIG_RESET_SHIFT 1
85 #define OMAP_OCP2SCP3_SYSCONFIG_RESET 1
87 #define OMAP_OCP2SCP3_SYSSTATUS 0x14
88 #define OMAP_OCP2SCP3_SYSSTATUS_RESETDONE 1
90 #define OMAP_OCP2SCP3_TIMING 0x18
91 #define OMAP_OCP2SCP3_TIMING_DIV_MASK 0x7
92 #define OMAP_OCP2SCP3_TIMING_DIV_SHIFT 7
93 #define OMAP_OCP2SCP3_TIMING_DIV 1
94 #define OMAP_OCP2SCP3_TIMING_SYNC1_MASK 0x7
95 #define OMAP_OCP2SCP3_TIMING_SYNC1_SHIFT 4
96 #define OMAP_OCP2SCP3_TIMING_SYNC1 0
97 #define OMAP_OCP2SCP3_TIMING_SYNC2_MASK 0xF
98 #define OMAP_OCP2SCP3_TIMING_SYNC2 0xF
100 #define SATAPHYRX_IO_A2D_OVRIDES_REG1 0x44
101 #define SATAPHYRX_IO_A2D_OVRIDES_REG1_MEMCDR_LOS_SRC_MASK 3
102 #define SATAPHYRX_IO_A2D_OVRIDES_REG1_MEMCDR_LOS_SRC_SHIFT 9
104 #define OMAP_CTRL_MODULE_CORE 0x4a002000
105 #define OMAP_CTRL_MODULE_CORE_SIZE 2048
107 #define OMAP_CTRL_SATA_PHY_POWER 0x374
108 #define SATA_PWRCTL_CLK_FREQ_SHIFT 22
109 #define SATA_PWRCTL_CLK_CMD_SHIFT 14
111 #define OMAP_CTRL_SATA_EXT_MODE 0x3ac
113 /* Enable the 19.2 Mhz frequency */
114 #define SATA_PWRCTL_CLK_FREQ 19
116 /* Enable Tx and Rx phys */
117 #define SATA_PWRCTL_CLK_CMD 3
119 struct omap_sata_platdata {
120 void __iomem *ocp2scp3, *phyrx, *pll;
121 struct omap_ocp2scp_dev *dev_attr;
122 struct clk *ref_clk;
123 };
125 static struct omap_sata_platdata omap_sata_data;
126 static struct ahci_platform_data sata_pdata;
127 static u64 sata_dmamask = DMA_BIT_MASK(32);
130 static void __iomem *sataphy_pwr;
132 static struct omap_device_pm_latency omap_sata_latency[] = {
133 {
134 .deactivate_func = omap_device_idle_hwmods,
135 .activate_func = omap_device_enable_hwmods,
136 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
137 },
138 };
140 static inline void omap_sata_writel(void __iomem *base, u32 reg, u32 val)
141 {
142 __raw_writel(val, base + reg);
143 }
145 static inline u32 omap_sata_readl(void __iomem *base, u32 reg)
146 {
147 return __raw_readl(base + reg);
148 }
150 static void sataphy_pwr_init(void)
151 {
152 sataphy_pwr = ioremap(OMAP_CTRL_MODULE_CORE,
153 OMAP_CTRL_MODULE_CORE_SIZE);
154 if (!sataphy_pwr)
155 pr_err("%s: ioremap of 0x%X failed\n", __func__,
156 OMAP_CTRL_MODULE_CORE);
157 }
159 static void sataphy_pwr_on(void)
160 {
161 if (!sataphy_pwr) {
162 pr_err("%s: 0x%X not accessible\n", __func__,
163 OMAP_CTRL_MODULE_CORE);
164 return;
165 }
167 omap_sata_writel(sataphy_pwr, OMAP_CTRL_SATA_PHY_POWER,
168 ((SATA_PWRCTL_CLK_FREQ << SATA_PWRCTL_CLK_FREQ_SHIFT)|
169 (SATA_PWRCTL_CLK_CMD << SATA_PWRCTL_CLK_CMD_SHIFT)));
170 omap_sata_writel(sataphy_pwr, OMAP_CTRL_SATA_EXT_MODE, 1);
171 }
173 static void sataphy_pwr_off(void)
174 {
175 u32 reg;
177 if (!sataphy_pwr) {
178 pr_err("%s: 0x%X not accessible\n", __func__,
179 OMAP_CTRL_MODULE_CORE);
180 return;
181 }
183 reg = omap_sata_readl(sataphy_pwr, OMAP_CTRL_SATA_PHY_POWER);
184 reg &= ~(SATA_PWRCTL_CLK_CMD << SATA_PWRCTL_CLK_CMD_SHIFT);
185 omap_sata_writel(sataphy_pwr, OMAP_CTRL_SATA_PHY_POWER, reg);
186 }
188 static void sataphy_pwr_deinit(void)
189 {
190 iounmap(sataphy_pwr);
191 }
194 static void omap_sataphyrx_init(struct device *dev, void __iomem *base)
195 {
196 u32 reg;
198 reg = omap_sata_readl(base, SATAPHYRX_IO_A2D_OVRIDES_REG1);
199 reg &= ~(SATAPHYRX_IO_A2D_OVRIDES_REG1_MEMCDR_LOS_SRC_MASK <<
200 SATAPHYRX_IO_A2D_OVRIDES_REG1_MEMCDR_LOS_SRC_SHIFT);
201 omap_sata_writel(base, SATAPHYRX_IO_A2D_OVRIDES_REG1, reg);
202 }
204 static void omap_ocp2scp_init(struct device *dev, void __iomem *base)
205 {
206 unsigned long timeout;
207 u32 reg;
209 /* config the bridge timing */
210 reg = omap_sata_readl(base, OMAP_OCP2SCP3_TIMING);
211 reg &= (~(OMAP_OCP2SCP3_TIMING_DIV_MASK <<
212 OMAP_OCP2SCP3_TIMING_DIV_SHIFT) |
213 ~(OMAP_OCP2SCP3_TIMING_SYNC1_MASK <<
214 OMAP_OCP2SCP3_TIMING_SYNC1_SHIFT) |
215 ~(OMAP_OCP2SCP3_TIMING_SYNC2_MASK));
217 reg |= ((OMAP_OCP2SCP3_TIMING_DIV <<
218 OMAP_OCP2SCP3_TIMING_DIV_SHIFT) |
219 (OMAP_OCP2SCP3_TIMING_SYNC1 <<
220 OMAP_OCP2SCP3_TIMING_SYNC1_SHIFT) |
221 (OMAP_OCP2SCP3_TIMING_SYNC2));
222 omap_sata_writel(base, OMAP_OCP2SCP3_TIMING, reg);
224 /* do the soft reset of ocp2scp3 */
225 reg = omap_sata_readl(base, OMAP_OCP2SCP3_SYSCONFIG);
226 reg &= ~(OMAP_OCP2SCP3_SYSCONFIG_RESET_MASK <<
227 OMAP_OCP2SCP3_SYSCONFIG_RESET_SHIFT);
228 reg |= (OMAP_OCP2SCP3_SYSCONFIG_RESET <<
229 OMAP_OCP2SCP3_SYSCONFIG_RESET_SHIFT);
230 omap_sata_writel(base, OMAP_OCP2SCP3_SYSCONFIG, reg);
232 /* wait for the reset to complete */
233 timeout = jiffies + msecs_to_jiffies(10000);
234 do {
235 cpu_relax();
236 reg = omap_sata_readl(base, OMAP_OCP2SCP3_SYSSTATUS) &
237 OMAP_OCP2SCP3_SYSSTATUS_RESETDONE;
238 if (time_after(jiffies, timeout) && !reg) {
239 dev_err(dev, "OCP2SCP RESET[0x%08x] timed out\n", reg);
240 break;
241 }
242 } while (!reg);
243 }
245 static int sata_dpll_wait_lock(struct device *dev, void __iomem *base)
246 {
247 unsigned long timeout;
249 /* Poll for the PLL lock */
250 timeout = jiffies + msecs_to_jiffies(10000);
251 while (!(omap_sata_readl(base, OMAP_SATA_PLL_STATUS) &
252 (OMAP_SATA_PLL_STATUS_LOCK <<
253 OMAP_SATA_PLL_STATUS_LOCK_SHIFT))) {
254 cpu_relax();
256 if (time_after(jiffies, timeout)) {
257 dev_err(dev, "sata phy pll lock timed out\n");
258 return -1;
259 }
260 }
261 return 0;
262 }
264 static int sata_dpll_config(struct device *dev, void __iomem *base)
265 {
266 u32 reg;
267 unsigned long timeout;
269 /* Make sure ADPLLLJM is out of reset before configuring it */
270 timeout = jiffies + msecs_to_jiffies(10000);
271 while (!(omap_sata_readl(base, OMAP_SATA_PLL_STATUS) &
272 OMAP_SATA_PLL_STATUS_RESET_DONE)) {
273 cpu_relax();
275 if (time_after(jiffies, timeout)) {
276 dev_err(dev, "SATA PLL RESET - timed out\n");
277 return -1;
278 }
279 }
280 reg = omap_sata_readl(base, OMAP_SATA_PLL_CFG1);
281 reg &= ~((OMAP_SATA_PLL_CFG1_M_MASK << OMAP_SATA_PLL_CFG1_M_SHIFT) |
282 (OMAP_SATA_PLL_CFG1_N_MASK << OMAP_SATA_PLL_CFG1_N_SHIFT));
283 reg |= ((OMAP_SATA_PLL_CFG1_M << OMAP_SATA_PLL_CFG1_M_SHIFT) |
284 (OMAP_SATA_PLL_CFG1_N << OMAP_SATA_PLL_CFG1_N_SHIFT));
285 omap_sata_writel(base, OMAP_SATA_PLL_CFG1, reg);
287 reg = omap_sata_readl(base, OMAP_SATA_PLL_CFG2);
288 reg &= (~(OMAP_SATA_PLL_CFG2_SELFREQDCO_MASK <<
289 OMAP_SATA_PLL_CFG2_SELFREQDCO_SHIFT) |
290 ~(OMAP_SATA_PLL_CFG2_REFSEL_MASK <<
291 OMAP_SATA_PLL_CFG2_REFSEL_SHIFT) |
292 ~(OMAP_SATA_PLL_CFG2_LOCKSEL_MASK <<
293 OMAP_SATA_PLL_CFG2_LOCKSEL_SHIFT));
295 reg |= ((OMAP_SATA_PLL_CFG2_SELFREQDCO <<
296 OMAP_SATA_PLL_CFG2_SELFREQDCO_SHIFT) |
297 (OMAP_SATA_PLL_CFG2_REFSEL <<
298 OMAP_SATA_PLL_CFG2_REFSEL_SHIFT) |
299 (OMAP_SATA_PLL_CFG2_LOCKSEL <<
300 OMAP_SATA_PLL_CFG2_LOCKSEL_SHIFT));
301 omap_sata_writel(base, OMAP_SATA_PLL_CFG2, reg);
303 reg = omap_sata_readl(base, OMAP_SATA_PLL_CFG3);
304 reg &= ~(OMAP_SATA_PLL_CFG3_SD_MASK << OMAP_SATA_PLL_CFG3_SD_SHIF);
305 reg |= (OMAP_SATA_PLL_CFG3_SD << OMAP_SATA_PLL_CFG3_SD_SHIF);
306 omap_sata_writel(base, OMAP_SATA_PLL_CFG3, reg);
308 reg = omap_sata_readl(base, OMAP_SATA_PLL_CFG4);
309 reg &= (~(OMAP_SATA_PLL_CFG4_REGM_F_MASK) |
310 ~(OMAP_SATA_PLL_CFG4_REGM2_MASK <<
311 OMAP_SATA_PLL_CFG4_REGM2_SHIFT));
312 reg |= ((OMAP_SATA_PLL_CFG4_REGM_F) |
313 (OMAP_SATA_PLL_CFG4_REGM2 <<
314 OMAP_SATA_PLL_CFG4_REGM2_SHIFT));
315 omap_sata_writel(base, OMAP_SATA_PLL_CFG4, reg);
316 omap_sata_writel(base, OMAP_SATA_PLL_GO, 1);
318 return sata_dpll_wait_lock(dev, base);
319 }
322 static struct resource *ocp2scp_get_resource_bynme(struct omap_ocp2scp_dev *dev,
323 unsigned int type,
324 const char *name)
325 {
326 struct resource *res = dev->res;
328 while (dev && res && res->start != res->end) {
329 if (type == resource_type(res) && !strcmp(res->name, name))
330 return res;
331 res++;
332 }
333 return NULL;
334 }
336 static int sata_phy_init(struct device *dev)
337 {
338 struct resource *res;
339 struct platform_device *pdev;
340 struct ahci_platform_data *pdata;
341 struct omap_sata_platdata *spdata;
342 struct omap_ocp2scp_dev *ocp2scpdev;
343 int ret;
345 pdev = container_of(dev, struct platform_device, dev);
346 pdata = dev->platform_data;
348 if (!pdata || !pdata->priv) {
349 dev_err(dev, "No platform data\n");
350 return -ENODEV;
351 }
352 spdata = pdata->priv;
353 ocp2scpdev = spdata->dev_attr;
354 spdata->ref_clk = clk_get(dev, "sata_ref_clk");
355 if (IS_ERR(spdata->ref_clk)) {
356 ret = PTR_ERR(spdata->ref_clk);
357 dev_err(dev, "sata_ref_clk failed:%d\n", ret);
358 return ret;
359 }
361 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ocp2scp3");
362 if (!res) {
363 dev_err(dev, "ocp2scp3 get resource failed\n");
364 return -ENXIO;
365 }
367 spdata->ocp2scp3 = ioremap(res->start, resource_size(res));
368 if (!spdata->ocp2scp3) {
369 dev_err(dev, "can't map ocp2scp3 0x%X\n", res->start);
370 return -ENOMEM;
371 }
373 res = ocp2scp_get_resource_bynme(ocp2scpdev, IORESOURCE_MEM,
374 "sata_pll");
375 if (!res) {
376 dev_err(dev, "sata_pll get resource failed\n");
377 ret = -ENXIO;
378 goto pll_err_end;
379 }
381 spdata->pll = ioremap(res->start, resource_size(res));
382 if (!spdata->pll) {
383 dev_err(dev, "can't map sata_pll 0x%X\n", res->start);
384 ret = -ENOMEM;
385 goto pll_err_end;
386 }
388 res = ocp2scp_get_resource_bynme(ocp2scpdev, IORESOURCE_MEM,
389 "sata_phy_rx");
390 if (!res) {
391 dev_err(dev, "sata_phy_rx get resource failed\n");
392 ret = -ENXIO;
393 goto rx_err_end;
394 }
396 spdata->phyrx = ioremap(res->start, resource_size(res));
397 if (!spdata->phyrx) {
398 dev_err(dev, "can't map sata_phy_rx 0x%X\n", res->start);
399 ret = -ENOMEM;
400 goto rx_err_end;
401 }
403 clk_enable(spdata->ref_clk);
405 omap_ocp2scp_init(dev, spdata->ocp2scp3);
406 sata_dpll_config(dev, spdata->pll);
407 sata_dpll_wait_lock(dev, spdata->pll);
408 omap_sataphyrx_init(dev, spdata->phyrx);
409 sataphy_pwr_init();
410 sataphy_pwr_on();
412 return 0;
414 rx_err_end:
415 iounmap(spdata->pll);
417 pll_err_end:
418 iounmap(spdata->ocp2scp3);
420 return ret;
421 }
423 static void sata_phy_exit(struct device *dev)
424 {
425 struct platform_device *pdev;
426 struct ahci_platform_data *pdata;
427 struct omap_sata_platdata *spdata;
429 pdev = container_of(dev, struct platform_device, dev);
430 pdata = dev->platform_data;
432 if (!pdata || !pdata->priv) {
433 dev_err(dev, "No platform data\n");
434 return;
435 }
436 spdata = pdata->priv;
438 clk_disable(spdata->ref_clk);
439 clk_put(spdata->ref_clk);
441 iounmap(spdata->phyrx);
442 iounmap(spdata->pll);
443 iounmap(spdata->ocp2scp3);
445 sataphy_pwr_off();
446 sataphy_pwr_deinit();
447 }
449 static int omap_ahci_plat_init(struct device *dev, void __iomem *base)
450 {
451 pm_runtime_enable(dev);
452 pm_runtime_get_sync(dev);
453 sata_phy_init(dev);
454 return 0;
455 }
457 static void omap_ahci_plat_exit(struct device *dev)
458 {
459 pm_runtime_put_sync(dev);
460 pm_runtime_disable(dev);
461 sata_phy_exit(dev);
462 }
464 #ifdef CONFIG_PM
466 static int omap_sata_suspend(struct device *dev)
467 {
468 struct ahci_platform_data *pdata;
469 struct omap_sata_platdata *spdata;
470 unsigned long timeout;
471 u32 reg;
473 pdata = dev->platform_data;
474 if (!pdata || !pdata->priv) {
475 dev_err(dev, "No platform data\n");
476 return -ENXIO;
477 }
478 spdata = pdata->priv;
479 if (!spdata->ref_clk || !spdata->pll) {
480 dev_err(dev, "No refclk and pll\n");
481 return -EPERM;
482 }
484 reg = omap_sata_readl(spdata->pll, OMAP_SATA_PLL_CFG2);
485 reg &= ~OMAP_SATA_PLL_CFG2_IDLE_MASK;
486 reg |= OMAP_SATA_PLL_CFG2_IDLE;
487 omap_sata_writel(spdata->pll, OMAP_SATA_PLL_CFG2, reg);
489 /* wait for internal LDO and internal oscilator power down */
490 timeout = jiffies + msecs_to_jiffies(10000);
491 do {
492 cpu_relax();
493 reg = omap_sata_readl(spdata->pll, OMAP_SATA_PLL_STATUS);
494 reg = (reg >> OMAP_SATA_PLL_STATUS_LDOPWDN_SHIFT) &
495 (reg >> OMAP_SATA_PLL_STATUS_TICOPWDN_SHIFT);
496 if (time_after(jiffies, timeout) & !reg) {
497 dev_err(dev, "ADPLLLJM IDLE[0x%08x] - timed out\n",
498 reg);
499 return -EIO;
500 }
501 } while (!reg);
503 #ifdef OMAP_SATA_PHY_PWR
504 sataphy_pwr_off();
505 #endif
507 clk_disable(spdata->ref_clk);
508 return 0;
509 }
512 static int omap_sata_resume(struct device *dev)
513 {
514 struct ahci_platform_data *pdata;
515 struct omap_sata_platdata *spdata;
516 u32 reg;
518 pdata = dev->platform_data;
519 if (!pdata || !pdata->priv) {
520 dev_err(dev, "No platform data\n");
521 return -ENXIO;
522 }
523 spdata = pdata->priv;
524 if (!spdata->ref_clk || !spdata->pll ||
525 !spdata->ocp2scp3 || !spdata->phyrx) {
526 dev_err(dev, "No refclk , pll and ocp2scp3\n");
527 return -EPERM;
528 }
530 clk_enable(spdata->ref_clk);
531 omap_ocp2scp_init(dev, spdata->ocp2scp3);
532 reg = omap_sata_readl(spdata->pll, OMAP_SATA_PLL_CFG2);
533 if (reg & OMAP_SATA_PLL_CFG2_IDLE_MASK) {
534 dev_err(dev, "sata pll in idle\n");
535 reg &= ~OMAP_SATA_PLL_CFG2_IDLE_MASK;
536 omap_sata_writel(spdata->pll, OMAP_SATA_PLL_CFG2, reg);
537 } else {
538 dev_err(dev, "sata pll not in idle, so reconfigure pll\n");
539 omap_sataphyrx_init(dev, spdata->phyrx);
540 sata_dpll_config(dev, spdata->pll);
541 }
542 sata_dpll_wait_lock(dev, spdata->pll);
544 #ifdef OMAP_SATA_PHY_PWR
545 sataphy_pwr_on();
546 #endif
548 return 0;
549 }
551 #else
552 static int omap_sata_suspend(struct device *dev)
553 {
554 return -EPERM;
555 }
557 static int omap_sata_resume(struct device *dev)
558 {
559 return -EPERM;
560 }
562 #endif
564 void __init omap_sata_init(void)
565 {
566 struct omap_hwmod *hwmod[2];
567 struct platform_device *pdev;
568 struct device *dev;
569 int oh_cnt = 1;
571 /* For now sata init works only for omap5 */
572 if (!soc_is_omap54xx())
573 return;
575 sata_pdata.init = omap_ahci_plat_init;
576 sata_pdata.exit = omap_ahci_plat_exit;
577 sata_pdata.suspend = omap_sata_suspend;
578 sata_pdata.resume = omap_sata_resume;
580 hwmod[0] = omap_hwmod_lookup(OMAP_SATA_HWMODNAME);
581 if (!hwmod[0]) {
582 pr_err("Could not look up %s\n", OMAP_SATA_HWMODNAME);
583 return;
584 }
586 hwmod[1] = omap_hwmod_lookup(OMAP_OCP2SCP3_HWMODNAME);
587 if (hwmod[1]) {
588 oh_cnt++;
589 } else {
590 pr_err("Could not look up %s\n", OMAP_OCP2SCP3_HWMODNAME);
591 return;
592 }
594 omap_sata_data.dev_attr = (struct omap_ocp2scp_dev *)hwmod[1]->dev_attr;
595 sata_pdata.priv = &omap_sata_data;
597 pdev = omap_device_build_ss(AHCI_PLAT_DEVNAME, PLATFORM_DEVID_AUTO, hwmod, oh_cnt,
598 (void *)&sata_pdata, sizeof(sata_pdata),
599 omap_sata_latency,
600 ARRAY_SIZE(omap_sata_latency), false);
601 if (IS_ERR(pdev)) {
602 pr_err("Could not build hwmod device %s\n",
603 OMAP_SATA_HWMODNAME);
604 return;
605 }
606 dev = &pdev->dev;
607 get_device(dev);
608 dev->dma_mask = &sata_dmamask;
609 dev->coherent_dma_mask = DMA_BIT_MASK(32);
610 put_device(dev);
611 }