1 /*
2 * arch/arm/mach-tegra/tegra30_clocks.c
3 *
4 * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
18 *
19 */
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/list.h>
24 #include <linux/spinlock.h>
25 #include <linux/delay.h>
26 #include <linux/err.h>
27 #include <linux/io.h>
28 #include <linux/clk.h>
29 #include <linux/cpufreq.h>
30 #include <linux/syscore_ops.h>
32 #include <asm/clkdev.h>
34 #include <mach/powergate.h>
36 #include "clock.h"
37 #include "fuse.h"
38 #include "iomap.h"
39 #include "tegra_cpu_car.h"
41 #define USE_PLL_LOCK_BITS 0
43 #define RST_DEVICES_L 0x004
44 #define RST_DEVICES_H 0x008
45 #define RST_DEVICES_U 0x00C
46 #define RST_DEVICES_V 0x358
47 #define RST_DEVICES_W 0x35C
48 #define RST_DEVICES_SET_L 0x300
49 #define RST_DEVICES_CLR_L 0x304
50 #define RST_DEVICES_SET_V 0x430
51 #define RST_DEVICES_CLR_V 0x434
52 #define RST_DEVICES_NUM 5
54 #define CLK_OUT_ENB_L 0x010
55 #define CLK_OUT_ENB_H 0x014
56 #define CLK_OUT_ENB_U 0x018
57 #define CLK_OUT_ENB_V 0x360
58 #define CLK_OUT_ENB_W 0x364
59 #define CLK_OUT_ENB_SET_L 0x320
60 #define CLK_OUT_ENB_CLR_L 0x324
61 #define CLK_OUT_ENB_SET_V 0x440
62 #define CLK_OUT_ENB_CLR_V 0x444
63 #define CLK_OUT_ENB_NUM 5
65 #define RST_DEVICES_V_SWR_CPULP_RST_DIS (0x1 << 1)
66 #define CLK_OUT_ENB_V_CLK_ENB_CPULP_EN (0x1 << 1)
68 #define PERIPH_CLK_TO_BIT(c) (1 << (c->u.periph.clk_num % 32))
69 #define PERIPH_CLK_TO_RST_REG(c) \
70 periph_clk_to_reg((c), RST_DEVICES_L, RST_DEVICES_V, 4)
71 #define PERIPH_CLK_TO_RST_SET_REG(c) \
72 periph_clk_to_reg((c), RST_DEVICES_SET_L, RST_DEVICES_SET_V, 8)
73 #define PERIPH_CLK_TO_RST_CLR_REG(c) \
74 periph_clk_to_reg((c), RST_DEVICES_CLR_L, RST_DEVICES_CLR_V, 8)
76 #define PERIPH_CLK_TO_ENB_REG(c) \
77 periph_clk_to_reg((c), CLK_OUT_ENB_L, CLK_OUT_ENB_V, 4)
78 #define PERIPH_CLK_TO_ENB_SET_REG(c) \
79 periph_clk_to_reg((c), CLK_OUT_ENB_SET_L, CLK_OUT_ENB_SET_V, 8)
80 #define PERIPH_CLK_TO_ENB_CLR_REG(c) \
81 periph_clk_to_reg((c), CLK_OUT_ENB_CLR_L, CLK_OUT_ENB_CLR_V, 8)
83 #define CLK_MASK_ARM 0x44
84 #define MISC_CLK_ENB 0x48
86 #define OSC_CTRL 0x50
87 #define OSC_CTRL_OSC_FREQ_MASK (0xF<<28)
88 #define OSC_CTRL_OSC_FREQ_13MHZ (0x0<<28)
89 #define OSC_CTRL_OSC_FREQ_19_2MHZ (0x4<<28)
90 #define OSC_CTRL_OSC_FREQ_12MHZ (0x8<<28)
91 #define OSC_CTRL_OSC_FREQ_26MHZ (0xC<<28)
92 #define OSC_CTRL_OSC_FREQ_16_8MHZ (0x1<<28)
93 #define OSC_CTRL_OSC_FREQ_38_4MHZ (0x5<<28)
94 #define OSC_CTRL_OSC_FREQ_48MHZ (0x9<<28)
95 #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
97 #define OSC_CTRL_PLL_REF_DIV_MASK (3<<26)
98 #define OSC_CTRL_PLL_REF_DIV_1 (0<<26)
99 #define OSC_CTRL_PLL_REF_DIV_2 (1<<26)
100 #define OSC_CTRL_PLL_REF_DIV_4 (2<<26)
102 #define OSC_FREQ_DET 0x58
103 #define OSC_FREQ_DET_TRIG (1<<31)
105 #define OSC_FREQ_DET_STATUS 0x5C
106 #define OSC_FREQ_DET_BUSY (1<<31)
107 #define OSC_FREQ_DET_CNT_MASK 0xFFFF
109 #define PERIPH_CLK_SOURCE_I2S1 0x100
110 #define PERIPH_CLK_SOURCE_EMC 0x19c
111 #define PERIPH_CLK_SOURCE_OSC 0x1fc
112 #define PERIPH_CLK_SOURCE_NUM1 \
113 ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
115 #define PERIPH_CLK_SOURCE_G3D2 0x3b0
116 #define PERIPH_CLK_SOURCE_SE 0x42c
117 #define PERIPH_CLK_SOURCE_NUM2 \
118 ((PERIPH_CLK_SOURCE_SE - PERIPH_CLK_SOURCE_G3D2) / 4 + 1)
120 #define AUDIO_DLY_CLK 0x49c
121 #define AUDIO_SYNC_CLK_SPDIF 0x4b4
122 #define PERIPH_CLK_SOURCE_NUM3 \
123 ((AUDIO_SYNC_CLK_SPDIF - AUDIO_DLY_CLK) / 4 + 1)
125 #define PERIPH_CLK_SOURCE_NUM (PERIPH_CLK_SOURCE_NUM1 + \
126 PERIPH_CLK_SOURCE_NUM2 + \
127 PERIPH_CLK_SOURCE_NUM3)
129 #define CPU_SOFTRST_CTRL 0x380
131 #define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF
132 #define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF
133 #define PERIPH_CLK_SOURCE_DIV_SHIFT 0
134 #define PERIPH_CLK_SOURCE_DIVIDLE_SHIFT 8
135 #define PERIPH_CLK_SOURCE_DIVIDLE_VAL 50
136 #define PERIPH_CLK_UART_DIV_ENB (1<<24)
137 #define PERIPH_CLK_VI_SEL_EX_SHIFT 24
138 #define PERIPH_CLK_VI_SEL_EX_MASK (0x3<<PERIPH_CLK_VI_SEL_EX_SHIFT)
139 #define PERIPH_CLK_NAND_DIV_EX_ENB (1<<8)
140 #define PERIPH_CLK_DTV_POLARITY_INV (1<<25)
142 #define AUDIO_SYNC_SOURCE_MASK 0x0F
143 #define AUDIO_SYNC_DISABLE_BIT 0x10
144 #define AUDIO_SYNC_TAP_NIBBLE_SHIFT(c) ((c->reg_shift - 24) * 4)
146 #define PLL_BASE 0x0
147 #define PLL_BASE_BYPASS (1<<31)
148 #define PLL_BASE_ENABLE (1<<30)
149 #define PLL_BASE_REF_ENABLE (1<<29)
150 #define PLL_BASE_OVERRIDE (1<<28)
151 #define PLL_BASE_LOCK (1<<27)
152 #define PLL_BASE_DIVP_MASK (0x7<<20)
153 #define PLL_BASE_DIVP_SHIFT 20
154 #define PLL_BASE_DIVN_MASK (0x3FF<<8)
155 #define PLL_BASE_DIVN_SHIFT 8
156 #define PLL_BASE_DIVM_MASK (0x1F)
157 #define PLL_BASE_DIVM_SHIFT 0
159 #define PLL_OUT_RATIO_MASK (0xFF<<8)
160 #define PLL_OUT_RATIO_SHIFT 8
161 #define PLL_OUT_OVERRIDE (1<<2)
162 #define PLL_OUT_CLKEN (1<<1)
163 #define PLL_OUT_RESET_DISABLE (1<<0)
165 #define PLL_MISC(c) \
166 (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
167 #define PLL_MISC_LOCK_ENABLE(c) \
168 (((c)->flags & (PLLU | PLLD)) ? (1<<22) : (1<<18))
170 #define PLL_MISC_DCCON_SHIFT 20
171 #define PLL_MISC_CPCON_SHIFT 8
172 #define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT)
173 #define PLL_MISC_LFCON_SHIFT 4
174 #define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT)
175 #define PLL_MISC_VCOCON_SHIFT 0
176 #define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT)
177 #define PLLD_MISC_CLKENABLE (1<<30)
179 #define PLLU_BASE_POST_DIV (1<<20)
181 #define PLLD_BASE_DSIB_MUX_SHIFT 25
182 #define PLLD_BASE_DSIB_MUX_MASK (1<<PLLD_BASE_DSIB_MUX_SHIFT)
183 #define PLLD_BASE_CSI_CLKENABLE (1<<26)
184 #define PLLD_MISC_DSI_CLKENABLE (1<<30)
185 #define PLLD_MISC_DIV_RST (1<<23)
186 #define PLLD_MISC_DCCON_SHIFT 12
188 #define PLLDU_LFCON_SET_DIVN 600
190 /* FIXME: OUT_OF_TABLE_CPCON per pll */
191 #define OUT_OF_TABLE_CPCON 0x8
193 #define SUPER_CLK_MUX 0x00
194 #define SUPER_STATE_SHIFT 28
195 #define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT)
196 #define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT)
197 #define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT)
198 #define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT)
199 #define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT)
200 #define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT)
201 #define SUPER_LP_DIV2_BYPASS (0x1 << 16)
202 #define SUPER_SOURCE_MASK 0xF
203 #define SUPER_FIQ_SOURCE_SHIFT 12
204 #define SUPER_IRQ_SOURCE_SHIFT 8
205 #define SUPER_RUN_SOURCE_SHIFT 4
206 #define SUPER_IDLE_SOURCE_SHIFT 0
208 #define SUPER_CLK_DIVIDER 0x04
209 #define SUPER_CLOCK_DIV_U71_SHIFT 16
210 #define SUPER_CLOCK_DIV_U71_MASK (0xff << SUPER_CLOCK_DIV_U71_SHIFT)
211 /* guarantees safe cpu backup */
212 #define SUPER_CLOCK_DIV_U71_MIN 0x2
214 #define BUS_CLK_DISABLE (1<<3)
215 #define BUS_CLK_DIV_MASK 0x3
217 #define PMC_CTRL 0x0
218 #define PMC_CTRL_BLINK_ENB (1 << 7)
220 #define PMC_DPD_PADS_ORIDE 0x1c
221 #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20)
223 #define PMC_BLINK_TIMER_DATA_ON_SHIFT 0
224 #define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff
225 #define PMC_BLINK_TIMER_ENB (1 << 15)
226 #define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16
227 #define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff
229 #define PMC_PLLP_WB0_OVERRIDE 0xf8
230 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE (1 << 12)
232 #define UTMIP_PLL_CFG2 0x488
233 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
234 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
235 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN (1 << 0)
236 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN (1 << 2)
237 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN (1 << 4)
239 #define UTMIP_PLL_CFG1 0x484
240 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
241 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
242 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN (1 << 14)
243 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN (1 << 12)
244 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN (1 << 16)
246 #define PLLE_BASE_CML_ENABLE (1<<31)
247 #define PLLE_BASE_ENABLE (1<<30)
248 #define PLLE_BASE_DIVCML_SHIFT 24
249 #define PLLE_BASE_DIVCML_MASK (0xf<<PLLE_BASE_DIVCML_SHIFT)
250 #define PLLE_BASE_DIVP_SHIFT 16
251 #define PLLE_BASE_DIVP_MASK (0x3f<<PLLE_BASE_DIVP_SHIFT)
252 #define PLLE_BASE_DIVN_SHIFT 8
253 #define PLLE_BASE_DIVN_MASK (0xFF<<PLLE_BASE_DIVN_SHIFT)
254 #define PLLE_BASE_DIVM_SHIFT 0
255 #define PLLE_BASE_DIVM_MASK (0xFF<<PLLE_BASE_DIVM_SHIFT)
256 #define PLLE_BASE_DIV_MASK \
257 (PLLE_BASE_DIVCML_MASK | PLLE_BASE_DIVP_MASK | \
258 PLLE_BASE_DIVN_MASK | PLLE_BASE_DIVM_MASK)
259 #define PLLE_BASE_DIV(m, n, p, cml) \
260 (((cml)<<PLLE_BASE_DIVCML_SHIFT) | ((p)<<PLLE_BASE_DIVP_SHIFT) | \
261 ((n)<<PLLE_BASE_DIVN_SHIFT) | ((m)<<PLLE_BASE_DIVM_SHIFT))
263 #define PLLE_MISC_SETUP_BASE_SHIFT 16
264 #define PLLE_MISC_SETUP_BASE_MASK (0xFFFF<<PLLE_MISC_SETUP_BASE_SHIFT)
265 #define PLLE_MISC_READY (1<<15)
266 #define PLLE_MISC_LOCK (1<<11)
267 #define PLLE_MISC_LOCK_ENABLE (1<<9)
268 #define PLLE_MISC_SETUP_EX_SHIFT 2
269 #define PLLE_MISC_SETUP_EX_MASK (0x3<<PLLE_MISC_SETUP_EX_SHIFT)
270 #define PLLE_MISC_SETUP_MASK \
271 (PLLE_MISC_SETUP_BASE_MASK | PLLE_MISC_SETUP_EX_MASK)
272 #define PLLE_MISC_SETUP_VALUE \
273 ((0x7<<PLLE_MISC_SETUP_BASE_SHIFT) | (0x0<<PLLE_MISC_SETUP_EX_SHIFT))
275 #define PLLE_SS_CTRL 0x68
276 #define PLLE_SS_INCINTRV_SHIFT 24
277 #define PLLE_SS_INCINTRV_MASK (0x3f<<PLLE_SS_INCINTRV_SHIFT)
278 #define PLLE_SS_INC_SHIFT 16
279 #define PLLE_SS_INC_MASK (0xff<<PLLE_SS_INC_SHIFT)
280 #define PLLE_SS_MAX_SHIFT 0
281 #define PLLE_SS_MAX_MASK (0x1ff<<PLLE_SS_MAX_SHIFT)
282 #define PLLE_SS_COEFFICIENTS_MASK \
283 (PLLE_SS_INCINTRV_MASK | PLLE_SS_INC_MASK | PLLE_SS_MAX_MASK)
284 #define PLLE_SS_COEFFICIENTS_12MHZ \
285 ((0x18<<PLLE_SS_INCINTRV_SHIFT) | (0x1<<PLLE_SS_INC_SHIFT) | \
286 (0x24<<PLLE_SS_MAX_SHIFT))
287 #define PLLE_SS_DISABLE ((1<<12) | (1<<11) | (1<<10))
289 #define PLLE_AUX 0x48c
290 #define PLLE_AUX_PLLP_SEL (1<<2)
291 #define PLLE_AUX_CML_SATA_ENABLE (1<<1)
292 #define PLLE_AUX_CML_PCIE_ENABLE (1<<0)
294 #define PMC_SATA_PWRGT 0x1ac
295 #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE (1<<5)
296 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1<<4)
298 #define ROUND_DIVIDER_UP 0
299 #define ROUND_DIVIDER_DOWN 1
301 /* FIXME: recommended safety delay after lock is detected */
302 #define PLL_POST_LOCK_DELAY 100
304 /* Tegra CPU clock and reset control regs */
305 #define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c
306 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340
307 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344
308 #define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c
309 #define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
311 #define CPU_CLOCK(cpu) (0x1 << (8 + cpu))
312 #define CPU_RESET(cpu) (0x1111ul << (cpu))
314 #define CLK_RESET_CCLK_BURST 0x20
315 #define CLK_RESET_CCLK_DIVIDER 0x24
316 #define CLK_RESET_PLLX_BASE 0xe0
317 #define CLK_RESET_PLLX_MISC 0xe4
319 #define CLK_RESET_SOURCE_CSITE 0x1d4
321 #define CLK_RESET_CCLK_BURST_POLICY_SHIFT 28
322 #define CLK_RESET_CCLK_RUN_POLICY_SHIFT 4
323 #define CLK_RESET_CCLK_IDLE_POLICY_SHIFT 0
324 #define CLK_RESET_CCLK_IDLE_POLICY 1
325 #define CLK_RESET_CCLK_RUN_POLICY 2
326 #define CLK_RESET_CCLK_BURST_POLICY_PLLX 8
328 #ifdef CONFIG_PM_SLEEP
329 static struct cpu_clk_suspend_context {
330 u32 pllx_misc;
331 u32 pllx_base;
333 u32 cpu_burst;
334 u32 clk_csite_src;
335 u32 cclk_divider;
336 } tegra30_cpu_clk_sctx;
337 #endif
339 /**
340 * Structure defining the fields for USB UTMI clocks Parameters.
341 */
342 struct utmi_clk_param {
343 /* Oscillator Frequency in KHz */
344 u32 osc_frequency;
345 /* UTMIP PLL Enable Delay Count */
346 u8 enable_delay_count;
347 /* UTMIP PLL Stable count */
348 u8 stable_count;
349 /* UTMIP PLL Active delay count */
350 u8 active_delay_count;
351 /* UTMIP PLL Xtal frequency count */
352 u8 xtal_freq_count;
353 };
355 static const struct utmi_clk_param utmi_parameters[] = {
356 {
357 .osc_frequency = 13000000,
358 .enable_delay_count = 0x02,
359 .stable_count = 0x33,
360 .active_delay_count = 0x05,
361 .xtal_freq_count = 0x7F
362 },
363 {
364 .osc_frequency = 19200000,
365 .enable_delay_count = 0x03,
366 .stable_count = 0x4B,
367 .active_delay_count = 0x06,
368 .xtal_freq_count = 0xBB},
369 {
370 .osc_frequency = 12000000,
371 .enable_delay_count = 0x02,
372 .stable_count = 0x2F,
373 .active_delay_count = 0x04,
374 .xtal_freq_count = 0x76
375 },
376 {
377 .osc_frequency = 26000000,
378 .enable_delay_count = 0x04,
379 .stable_count = 0x66,
380 .active_delay_count = 0x09,
381 .xtal_freq_count = 0xFE
382 },
383 {
384 .osc_frequency = 16800000,
385 .enable_delay_count = 0x03,
386 .stable_count = 0x41,
387 .active_delay_count = 0x0A,
388 .xtal_freq_count = 0xA4
389 },
390 };
392 static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
393 static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
394 static void __iomem *misc_gp_hidrev_base = IO_ADDRESS(TEGRA_APB_MISC_BASE);
396 #define MISC_GP_HIDREV 0x804
398 /*
399 * Some peripheral clocks share an enable bit, so refcount the enable bits
400 * in registers CLK_ENABLE_L, ... CLK_ENABLE_W
401 */
402 static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32];
404 #define clk_writel(value, reg) \
405 __raw_writel(value, reg_clk_base + (reg))
406 #define clk_readl(reg) \
407 __raw_readl(reg_clk_base + (reg))
408 #define pmc_writel(value, reg) \
409 __raw_writel(value, reg_pmc_base + (reg))
410 #define pmc_readl(reg) \
411 __raw_readl(reg_pmc_base + (reg))
412 #define chipid_readl() \
413 __raw_readl(misc_gp_hidrev_base + MISC_GP_HIDREV)
415 #define clk_writel_delay(value, reg) \
416 do { \
417 __raw_writel((value), reg_clk_base + (reg)); \
418 udelay(2); \
419 } while (0)
421 static inline int clk_set_div(struct clk_tegra *c, u32 n)
422 {
423 struct clk *clk = c->hw.clk;
425 return clk_set_rate(clk,
426 (__clk_get_rate(__clk_get_parent(clk)) + n - 1) / n);
427 }
429 static inline u32 periph_clk_to_reg(
430 struct clk_tegra *c, u32 reg_L, u32 reg_V, int offs)
431 {
432 u32 reg = c->u.periph.clk_num / 32;
433 BUG_ON(reg >= RST_DEVICES_NUM);
434 if (reg < 3)
435 reg = reg_L + (reg * offs);
436 else
437 reg = reg_V + ((reg - 3) * offs);
438 return reg;
439 }
441 static unsigned long clk_measure_input_freq(void)
442 {
443 u32 clock_autodetect;
444 clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
445 do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY);
446 clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS);
447 if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) {
448 return 12000000;
449 } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) {
450 return 13000000;
451 } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) {
452 return 19200000;
453 } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) {
454 return 26000000;
455 } else if (clock_autodetect >= 1025 - 3 && clock_autodetect <= 1025 + 3) {
456 return 16800000;
457 } else if (clock_autodetect >= 2344 - 3 && clock_autodetect <= 2344 + 3) {
458 return 38400000;
459 } else if (clock_autodetect >= 2928 - 3 && clock_autodetect <= 2928 + 3) {
460 return 48000000;
461 } else {
462 pr_err("%s: Unexpected clock autodetect value %d", __func__,
463 clock_autodetect);
464 BUG();
465 return 0;
466 }
467 }
469 static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate,
470 u32 flags, u32 round_mode)
471 {
472 s64 divider_u71 = parent_rate;
473 if (!rate)
474 return -EINVAL;
476 if (!(flags & DIV_U71_INT))
477 divider_u71 *= 2;
478 if (round_mode == ROUND_DIVIDER_UP)
479 divider_u71 += rate - 1;
480 do_div(divider_u71, rate);
481 if (flags & DIV_U71_INT)
482 divider_u71 *= 2;
484 if (divider_u71 - 2 < 0)
485 return 0;
487 if (divider_u71 - 2 > 255)
488 return -EINVAL;
490 return divider_u71 - 2;
491 }
493 static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
494 {
495 s64 divider_u16;
497 divider_u16 = parent_rate;
498 if (!rate)
499 return -EINVAL;
500 divider_u16 += rate - 1;
501 do_div(divider_u16, rate);
503 if (divider_u16 - 1 < 0)
504 return 0;
506 if (divider_u16 - 1 > 0xFFFF)
507 return -EINVAL;
509 return divider_u16 - 1;
510 }
512 static unsigned long tegra30_clk_fixed_recalc_rate(struct clk_hw *hw,
513 unsigned long parent_rate)
514 {
515 return to_clk_tegra(hw)->fixed_rate;
516 }
518 struct clk_ops tegra30_clk_32k_ops = {
519 .recalc_rate = tegra30_clk_fixed_recalc_rate,
520 };
522 /* clk_m functions */
523 static unsigned long tegra30_clk_m_recalc_rate(struct clk_hw *hw,
524 unsigned long parent_rate)
525 {
526 if (!to_clk_tegra(hw)->fixed_rate)
527 to_clk_tegra(hw)->fixed_rate = clk_measure_input_freq();
528 return to_clk_tegra(hw)->fixed_rate;
529 }
531 static void tegra30_clk_m_init(struct clk_hw *hw)
532 {
533 u32 osc_ctrl = clk_readl(OSC_CTRL);
534 u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK;
535 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
537 switch (to_clk_tegra(hw)->fixed_rate) {
538 case 12000000:
539 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
540 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
541 break;
542 case 13000000:
543 auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
544 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
545 break;
546 case 19200000:
547 auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
548 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
549 break;
550 case 26000000:
551 auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
552 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
553 break;
554 case 16800000:
555 auto_clock_control |= OSC_CTRL_OSC_FREQ_16_8MHZ;
556 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
557 break;
558 case 38400000:
559 auto_clock_control |= OSC_CTRL_OSC_FREQ_38_4MHZ;
560 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_2);
561 break;
562 case 48000000:
563 auto_clock_control |= OSC_CTRL_OSC_FREQ_48MHZ;
564 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4);
565 break;
566 default:
567 pr_err("%s: Unexpected clock rate %ld", __func__,
568 to_clk_tegra(hw)->fixed_rate);
569 BUG();
570 }
571 clk_writel(auto_clock_control, OSC_CTRL);
572 }
574 struct clk_ops tegra30_clk_m_ops = {
575 .init = tegra30_clk_m_init,
576 .recalc_rate = tegra30_clk_m_recalc_rate,
577 };
579 static unsigned long tegra30_clk_m_div_recalc_rate(struct clk_hw *hw,
580 unsigned long parent_rate)
581 {
582 struct clk_tegra *c = to_clk_tegra(hw);
583 u64 rate = parent_rate;
585 if (c->mul != 0 && c->div != 0) {
586 rate *= c->mul;
587 rate += c->div - 1; /* round up */
588 do_div(rate, c->div);
589 }
591 return rate;
592 }
594 struct clk_ops tegra_clk_m_div_ops = {
595 .recalc_rate = tegra30_clk_m_div_recalc_rate,
596 };
598 /* PLL reference divider functions */
599 static unsigned long tegra30_pll_ref_recalc_rate(struct clk_hw *hw,
600 unsigned long parent_rate)
601 {
602 struct clk_tegra *c = to_clk_tegra(hw);
603 unsigned long rate = parent_rate;
604 u32 pll_ref_div = clk_readl(OSC_CTRL) & OSC_CTRL_PLL_REF_DIV_MASK;
606 switch (pll_ref_div) {
607 case OSC_CTRL_PLL_REF_DIV_1:
608 c->div = 1;
609 break;
610 case OSC_CTRL_PLL_REF_DIV_2:
611 c->div = 2;
612 break;
613 case OSC_CTRL_PLL_REF_DIV_4:
614 c->div = 4;
615 break;
616 default:
617 pr_err("%s: Invalid pll ref divider %d", __func__, pll_ref_div);
618 BUG();
619 }
620 c->mul = 1;
622 if (c->mul != 0 && c->div != 0) {
623 rate *= c->mul;
624 rate += c->div - 1; /* round up */
625 do_div(rate, c->div);
626 }
628 return rate;
629 }
631 struct clk_ops tegra_pll_ref_ops = {
632 .recalc_rate = tegra30_pll_ref_recalc_rate,
633 };
635 /* super clock functions */
636 /* "super clocks" on tegra30 have two-stage muxes, fractional 7.1 divider and
637 * clock skipping super divider. We will ignore the clock skipping divider,
638 * since we can't lower the voltage when using the clock skip, but we can if
639 * we lower the PLL frequency. We will use 7.1 divider for CPU super-clock
640 * only when its parent is a fixed rate PLL, since we can't change PLL rate
641 * in this case.
642 */
643 static void tegra30_super_clk_init(struct clk_hw *hw)
644 {
645 struct clk_tegra *c = to_clk_tegra(hw);
646 struct clk_tegra *p =
647 to_clk_tegra(__clk_get_hw(__clk_get_parent(hw->clk)));
649 c->state = ON;
650 if (c->flags & DIV_U71) {
651 /* Init safe 7.1 divider value (does not affect PLLX path) */
652 clk_writel(SUPER_CLOCK_DIV_U71_MIN << SUPER_CLOCK_DIV_U71_SHIFT,
653 c->reg + SUPER_CLK_DIVIDER);
654 c->mul = 2;
655 c->div = 2;
656 if (!(p->flags & PLLX))
657 c->div += SUPER_CLOCK_DIV_U71_MIN;
658 } else
659 clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
660 }
662 static u8 tegra30_super_clk_get_parent(struct clk_hw *hw)
663 {
664 struct clk_tegra *c = to_clk_tegra(hw);
665 u32 val;
666 int source;
667 int shift;
669 val = clk_readl(c->reg + SUPER_CLK_MUX);
670 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
671 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
672 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
673 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
674 source = (val >> shift) & SUPER_SOURCE_MASK;
675 if (c->flags & DIV_2)
676 source |= val & SUPER_LP_DIV2_BYPASS;
678 return source;
679 }
681 static int tegra30_super_clk_set_parent(struct clk_hw *hw, u8 index)
682 {
683 struct clk_tegra *c = to_clk_tegra(hw);
684 struct clk_tegra *p =
685 to_clk_tegra(__clk_get_hw(clk_get_parent(hw->clk)));
686 u32 val;
687 int shift;
689 val = clk_readl(c->reg + SUPER_CLK_MUX);
690 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
691 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
692 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
693 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
695 /* For LP mode super-clock switch between PLLX direct
696 and divided-by-2 outputs is allowed only when other
697 than PLLX clock source is current parent */
698 if ((c->flags & DIV_2) && (p->flags & PLLX) &&
699 ((index ^ val) & SUPER_LP_DIV2_BYPASS)) {
700 if (p->flags & PLLX)
701 return -EINVAL;
702 val ^= SUPER_LP_DIV2_BYPASS;
703 clk_writel_delay(val, c->reg);
704 }
705 val &= ~(SUPER_SOURCE_MASK << shift);
706 val |= (index & SUPER_SOURCE_MASK) << shift;
708 /* 7.1 divider for CPU super-clock does not affect
709 PLLX path */
710 if (c->flags & DIV_U71) {
711 u32 div = 0;
712 if (!(p->flags & PLLX)) {
713 div = clk_readl(c->reg +
714 SUPER_CLK_DIVIDER);
715 div &= SUPER_CLOCK_DIV_U71_MASK;
716 div >>= SUPER_CLOCK_DIV_U71_SHIFT;
717 }
718 c->div = div + 2;
719 c->mul = 2;
720 }
721 clk_writel_delay(val, c->reg);
723 return 0;
724 }
726 /*
727 * Do not use super clocks "skippers", since dividing using a clock skipper
728 * does not allow the voltage to be scaled down. Instead adjust the rate of
729 * the parent clock. This requires that the parent of a super clock have no
730 * other children, otherwise the rate will change underneath the other
731 * children. Special case: if fixed rate PLL is CPU super clock parent the
732 * rate of this PLL can't be changed, and it has many other children. In
733 * this case use 7.1 fractional divider to adjust the super clock rate.
734 */
735 static int tegra30_super_clk_set_rate(struct clk_hw *hw, unsigned long rate,
736 unsigned long parent_rate)
737 {
738 struct clk_tegra *c = to_clk_tegra(hw);
739 struct clk *parent = __clk_get_parent(hw->clk);
740 struct clk_tegra *cparent = to_clk_tegra(__clk_get_hw(parent));
742 if ((c->flags & DIV_U71) && (cparent->flags & PLL_FIXED)) {
743 int div = clk_div71_get_divider(parent_rate,
744 rate, c->flags, ROUND_DIVIDER_DOWN);
745 div = max(div, SUPER_CLOCK_DIV_U71_MIN);
747 clk_writel(div << SUPER_CLOCK_DIV_U71_SHIFT,
748 c->reg + SUPER_CLK_DIVIDER);
749 c->div = div + 2;
750 c->mul = 2;
751 return 0;
752 }
753 return 0;
754 }
756 static unsigned long tegra30_super_clk_recalc_rate(struct clk_hw *hw,
757 unsigned long parent_rate)
758 {
759 struct clk_tegra *c = to_clk_tegra(hw);
760 u64 rate = parent_rate;
762 if (c->mul != 0 && c->div != 0) {
763 rate *= c->mul;
764 rate += c->div - 1; /* round up */
765 do_div(rate, c->div);
766 }
768 return rate;
769 }
771 static long tegra30_super_clk_round_rate(struct clk_hw *hw, unsigned long rate,
772 unsigned long *prate)
773 {
774 struct clk_tegra *c = to_clk_tegra(hw);
775 struct clk *parent = __clk_get_parent(hw->clk);
776 struct clk_tegra *cparent = to_clk_tegra(__clk_get_hw(parent));
777 int mul = 2;
778 int div;
780 if ((c->flags & DIV_U71) && (cparent->flags & PLL_FIXED)) {
781 div = clk_div71_get_divider(*prate,
782 rate, c->flags, ROUND_DIVIDER_DOWN);
783 div = max(div, SUPER_CLOCK_DIV_U71_MIN) + 2;
784 rate = *prate * mul;
785 rate += div - 1; /* round up */
786 do_div(rate, c->div);
788 return rate;
789 }
790 return *prate;
791 }
793 struct clk_ops tegra30_super_ops = {
794 .init = tegra30_super_clk_init,
795 .set_parent = tegra30_super_clk_set_parent,
796 .get_parent = tegra30_super_clk_get_parent,
797 .recalc_rate = tegra30_super_clk_recalc_rate,
798 .round_rate = tegra30_super_clk_round_rate,
799 .set_rate = tegra30_super_clk_set_rate,
800 };
802 static unsigned long tegra30_twd_clk_recalc_rate(struct clk_hw *hw,
803 unsigned long parent_rate)
804 {
805 struct clk_tegra *c = to_clk_tegra(hw);
806 u64 rate = parent_rate;
808 if (c->mul != 0 && c->div != 0) {
809 rate *= c->mul;
810 rate += c->div - 1; /* round up */
811 do_div(rate, c->div);
812 }
814 return rate;
815 }
817 struct clk_ops tegra30_twd_ops = {
818 .recalc_rate = tegra30_twd_clk_recalc_rate,
819 };
821 /* bus clock functions */
822 static int tegra30_bus_clk_is_enabled(struct clk_hw *hw)
823 {
824 struct clk_tegra *c = to_clk_tegra(hw);
825 u32 val = clk_readl(c->reg);
827 c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
828 return c->state;
829 }
831 static int tegra30_bus_clk_enable(struct clk_hw *hw)
832 {
833 struct clk_tegra *c = to_clk_tegra(hw);
834 u32 val;
836 val = clk_readl(c->reg);
837 val &= ~(BUS_CLK_DISABLE << c->reg_shift);
838 clk_writel(val, c->reg);
840 return 0;
841 }
843 static void tegra30_bus_clk_disable(struct clk_hw *hw)
844 {
845 struct clk_tegra *c = to_clk_tegra(hw);
846 u32 val;
848 val = clk_readl(c->reg);
849 val |= BUS_CLK_DISABLE << c->reg_shift;
850 clk_writel(val, c->reg);
851 }
853 static unsigned long tegra30_bus_clk_recalc_rate(struct clk_hw *hw,
854 unsigned long prate)
855 {
856 struct clk_tegra *c = to_clk_tegra(hw);
857 u32 val = clk_readl(c->reg);
858 u64 rate = prate;
860 c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
861 c->mul = 1;
863 if (c->mul != 0 && c->div != 0) {
864 rate *= c->mul;
865 rate += c->div - 1; /* round up */
866 do_div(rate, c->div);
867 }
868 return rate;
869 }
871 static int tegra30_bus_clk_set_rate(struct clk_hw *hw, unsigned long rate,
872 unsigned long parent_rate)
873 {
874 struct clk_tegra *c = to_clk_tegra(hw);
875 int ret = -EINVAL;
876 u32 val;
877 int i;
879 val = clk_readl(c->reg);
880 for (i = 1; i <= 4; i++) {
881 if (rate == parent_rate / i) {
882 val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
883 val |= (i - 1) << c->reg_shift;
884 clk_writel(val, c->reg);
885 c->div = i;
886 c->mul = 1;
887 ret = 0;
888 break;
889 }
890 }
892 return ret;
893 }
895 static long tegra30_bus_clk_round_rate(struct clk_hw *hw, unsigned long rate,
896 unsigned long *prate)
897 {
898 unsigned long parent_rate = *prate;
899 s64 divider;
901 if (rate >= parent_rate)
902 return parent_rate;
904 divider = parent_rate;
905 divider += rate - 1;
906 do_div(divider, rate);
908 if (divider < 0)
909 return divider;
911 if (divider > 4)
912 divider = 4;
913 do_div(parent_rate, divider);
915 return parent_rate;
916 }
918 struct clk_ops tegra30_bus_ops = {
919 .is_enabled = tegra30_bus_clk_is_enabled,
920 .enable = tegra30_bus_clk_enable,
921 .disable = tegra30_bus_clk_disable,
922 .set_rate = tegra30_bus_clk_set_rate,
923 .round_rate = tegra30_bus_clk_round_rate,
924 .recalc_rate = tegra30_bus_clk_recalc_rate,
925 };
927 /* Blink output functions */
928 static int tegra30_blink_clk_is_enabled(struct clk_hw *hw)
929 {
930 struct clk_tegra *c = to_clk_tegra(hw);
931 u32 val;
933 val = pmc_readl(PMC_CTRL);
934 c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
935 return c->state;
936 }
938 static int tegra30_blink_clk_enable(struct clk_hw *hw)
939 {
940 u32 val;
942 val = pmc_readl(PMC_DPD_PADS_ORIDE);
943 pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
945 val = pmc_readl(PMC_CTRL);
946 pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL);
948 return 0;
949 }
951 static void tegra30_blink_clk_disable(struct clk_hw *hw)
952 {
953 u32 val;
955 val = pmc_readl(PMC_CTRL);
956 pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL);
958 val = pmc_readl(PMC_DPD_PADS_ORIDE);
959 pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
960 }
962 static int tegra30_blink_clk_set_rate(struct clk_hw *hw, unsigned long rate,
963 unsigned long parent_rate)
964 {
965 struct clk_tegra *c = to_clk_tegra(hw);
967 if (rate >= parent_rate) {
968 c->div = 1;
969 pmc_writel(0, c->reg);
970 } else {
971 unsigned int on_off;
972 u32 val;
974 on_off = DIV_ROUND_UP(parent_rate / 8, rate);
975 c->div = on_off * 8;
977 val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) <<
978 PMC_BLINK_TIMER_DATA_ON_SHIFT;
979 on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK;
980 on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
981 val |= on_off;
982 val |= PMC_BLINK_TIMER_ENB;
983 pmc_writel(val, c->reg);
984 }
986 return 0;
987 }
989 static unsigned long tegra30_blink_clk_recalc_rate(struct clk_hw *hw,
990 unsigned long parent_rate)
991 {
992 struct clk_tegra *c = to_clk_tegra(hw);
993 u64 rate = parent_rate;
994 u32 val;
995 u32 mul;
996 u32 div;
997 u32 on_off;
999 mul = 1;
1000 val = pmc_readl(c->reg);
1002 if (val & PMC_BLINK_TIMER_ENB) {
1003 on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
1004 PMC_BLINK_TIMER_DATA_ON_MASK;
1005 val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
1006 val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
1007 on_off += val;
1008 /* each tick in the blink timer is 4 32KHz clocks */
1009 div = on_off * 4;
1010 } else {
1011 div = 1;
1012 }
1014 if (mul != 0 && div != 0) {
1015 rate *= mul;
1016 rate += div - 1; /* round up */
1017 do_div(rate, div);
1018 }
1019 return rate;
1020 }
1022 static long tegra30_blink_clk_round_rate(struct clk_hw *hw, unsigned long rate,
1023 unsigned long *prate)
1024 {
1025 int div;
1026 int mul;
1027 long round_rate = *prate;
1029 mul = 1;
1031 if (rate >= *prate) {
1032 div = 1;
1033 } else {
1034 div = DIV_ROUND_UP(*prate / 8, rate);
1035 div *= 8;
1036 }
1038 round_rate *= mul;
1039 round_rate += div - 1;
1040 do_div(round_rate, div);
1042 return round_rate;
1043 }
1045 struct clk_ops tegra30_blink_clk_ops = {
1046 .is_enabled = tegra30_blink_clk_is_enabled,
1047 .enable = tegra30_blink_clk_enable,
1048 .disable = tegra30_blink_clk_disable,
1049 .recalc_rate = tegra30_blink_clk_recalc_rate,
1050 .round_rate = tegra30_blink_clk_round_rate,
1051 .set_rate = tegra30_blink_clk_set_rate,
1052 };
1054 static void tegra30_utmi_param_configure(struct clk_hw *hw)
1055 {
1056 unsigned long main_rate =
1057 __clk_get_rate(__clk_get_parent(__clk_get_parent(hw->clk)));
1058 u32 reg;
1059 int i;
1061 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1062 if (main_rate == utmi_parameters[i].osc_frequency)
1063 break;
1064 }
1066 if (i >= ARRAY_SIZE(utmi_parameters)) {
1067 pr_err("%s: Unexpected main rate %lu\n", __func__, main_rate);
1068 return;
1069 }
1071 reg = clk_readl(UTMIP_PLL_CFG2);
1073 /* Program UTMIP PLL stable and active counts */
1074 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
1075 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1076 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(
1077 utmi_parameters[i].stable_count);
1079 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1081 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(
1082 utmi_parameters[i].active_delay_count);
1084 /* Remove power downs from UTMIP PLL control bits */
1085 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1086 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1087 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1089 clk_writel(reg, UTMIP_PLL_CFG2);
1091 /* Program UTMIP PLL delay and oscillator frequency counts */
1092 reg = clk_readl(UTMIP_PLL_CFG1);
1093 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1095 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(
1096 utmi_parameters[i].enable_delay_count);
1098 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1099 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(
1100 utmi_parameters[i].xtal_freq_count);
1102 /* Remove power downs from UTMIP PLL control bits */
1103 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1104 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1105 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1107 clk_writel(reg, UTMIP_PLL_CFG1);
1108 }
1110 /* PLL Functions */
1111 static int tegra30_pll_clk_wait_for_lock(struct clk_tegra *c, u32 lock_reg,
1112 u32 lock_bit)
1113 {
1114 int ret = 0;
1116 #if USE_PLL_LOCK_BITS
1117 int i;
1118 for (i = 0; i < c->u.pll.lock_delay; i++) {
1119 if (clk_readl(lock_reg) & lock_bit) {
1120 udelay(PLL_POST_LOCK_DELAY);
1121 return 0;
1122 }
1123 udelay(2); /* timeout = 2 * lock time */
1124 }
1125 pr_err("Timed out waiting for lock bit on pll %s",
1126 __clk_get_name(hw->clk));
1127 ret = -1;
1128 #else
1129 udelay(c->u.pll.lock_delay);
1130 #endif
1131 return ret;
1132 }
1134 static int tegra30_pll_clk_is_enabled(struct clk_hw *hw)
1135 {
1136 struct clk_tegra *c = to_clk_tegra(hw);
1137 u32 val = clk_readl(c->reg + PLL_BASE);
1139 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
1140 return c->state;
1141 }
1143 static void tegra30_pll_clk_init(struct clk_hw *hw)
1144 {
1145 struct clk_tegra *c = to_clk_tegra(hw);
1147 if (c->flags & PLLU)
1148 tegra30_utmi_param_configure(hw);
1149 }
1151 static int tegra30_pll_clk_enable(struct clk_hw *hw)
1152 {
1153 struct clk_tegra *c = to_clk_tegra(hw);
1154 u32 val;
1155 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
1157 #if USE_PLL_LOCK_BITS
1158 val = clk_readl(c->reg + PLL_MISC(c));
1159 val |= PLL_MISC_LOCK_ENABLE(c);
1160 clk_writel(val, c->reg + PLL_MISC(c));
1161 #endif
1162 val = clk_readl(c->reg + PLL_BASE);
1163 val &= ~PLL_BASE_BYPASS;
1164 val |= PLL_BASE_ENABLE;
1165 clk_writel(val, c->reg + PLL_BASE);
1167 if (c->flags & PLLM) {
1168 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
1169 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
1170 pmc_writel(val, PMC_PLLP_WB0_OVERRIDE);
1171 }
1173 tegra30_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, PLL_BASE_LOCK);
1175 return 0;
1176 }
1178 static void tegra30_pll_clk_disable(struct clk_hw *hw)
1179 {
1180 struct clk_tegra *c = to_clk_tegra(hw);
1181 u32 val;
1182 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
1184 val = clk_readl(c->reg);
1185 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
1186 clk_writel(val, c->reg);
1188 if (c->flags & PLLM) {
1189 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
1190 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
1191 pmc_writel(val, PMC_PLLP_WB0_OVERRIDE);
1192 }
1193 }
1195 static int tegra30_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1196 unsigned long parent_rate)
1197 {
1198 struct clk_tegra *c = to_clk_tegra(hw);
1199 u32 val, p_div, old_base;
1200 unsigned long input_rate;
1201 const struct clk_pll_freq_table *sel;
1202 struct clk_pll_freq_table cfg;
1204 if (c->flags & PLL_FIXED) {
1205 int ret = 0;
1206 if (rate != c->u.pll.fixed_rate) {
1207 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
1208 __func__, __clk_get_name(hw->clk),
1209 c->u.pll.fixed_rate, rate);
1210 ret = -EINVAL;
1211 }
1212 return ret;
1213 }
1215 if (c->flags & PLLM) {
1216 if (rate != __clk_get_rate(hw->clk)) {
1217 pr_err("%s: Can not change memory %s rate in flight\n",
1218 __func__, __clk_get_name(hw->clk));
1219 return -EINVAL;
1220 }
1221 }
1223 p_div = 0;
1224 input_rate = parent_rate;
1226 /* Check if the target rate is tabulated */
1227 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
1228 if (sel->input_rate == input_rate && sel->output_rate == rate) {
1229 if (c->flags & PLLU) {
1230 BUG_ON(sel->p < 1 || sel->p > 2);
1231 if (sel->p == 1)
1232 p_div = PLLU_BASE_POST_DIV;
1233 } else {
1234 BUG_ON(sel->p < 1);
1235 for (val = sel->p; val > 1; val >>= 1)
1236 p_div++;
1237 p_div <<= PLL_BASE_DIVP_SHIFT;
1238 }
1239 break;
1240 }
1241 }
1243 /* Configure out-of-table rate */
1244 if (sel->input_rate == 0) {
1245 unsigned long cfreq;
1246 BUG_ON(c->flags & PLLU);
1247 sel = &cfg;
1249 switch (input_rate) {
1250 case 12000000:
1251 case 26000000:
1252 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
1253 break;
1254 case 13000000:
1255 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
1256 break;
1257 case 16800000:
1258 case 19200000:
1259 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
1260 break;
1261 default:
1262 pr_err("%s: Unexpected reference rate %lu\n",
1263 __func__, input_rate);
1264 BUG();
1265 }
1267 /* Raise VCO to guarantee 0.5% accuracy */
1268 for (cfg.output_rate = rate; cfg.output_rate < 200 * cfreq;
1269 cfg.output_rate <<= 1)
1270 p_div++;
1272 cfg.p = 0x1 << p_div;
1273 cfg.m = input_rate / cfreq;
1274 cfg.n = cfg.output_rate / cfreq;
1275 cfg.cpcon = OUT_OF_TABLE_CPCON;
1277 if ((cfg.m > (PLL_BASE_DIVM_MASK >> PLL_BASE_DIVM_SHIFT)) ||
1278 (cfg.n > (PLL_BASE_DIVN_MASK >> PLL_BASE_DIVN_SHIFT)) ||
1279 (p_div > (PLL_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT)) ||
1280 (cfg.output_rate > c->u.pll.vco_max)) {
1281 pr_err("%s: Failed to set %s out-of-table rate %lu\n",
1282 __func__, __clk_get_name(hw->clk), rate);
1283 return -EINVAL;
1284 }
1285 p_div <<= PLL_BASE_DIVP_SHIFT;
1286 }
1288 c->mul = sel->n;
1289 c->div = sel->m * sel->p;
1291 old_base = val = clk_readl(c->reg + PLL_BASE);
1292 val &= ~(PLL_BASE_DIVM_MASK | PLL_BASE_DIVN_MASK |
1293 ((c->flags & PLLU) ? PLLU_BASE_POST_DIV : PLL_BASE_DIVP_MASK));
1294 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
1295 (sel->n << PLL_BASE_DIVN_SHIFT) | p_div;
1296 if (val == old_base)
1297 return 0;
1299 if (c->state == ON) {
1300 tegra30_pll_clk_disable(hw);
1301 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
1302 }
1303 clk_writel(val, c->reg + PLL_BASE);
1305 if (c->flags & PLL_HAS_CPCON) {
1306 val = clk_readl(c->reg + PLL_MISC(c));
1307 val &= ~PLL_MISC_CPCON_MASK;
1308 val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
1309 if (c->flags & (PLLU | PLLD)) {
1310 val &= ~PLL_MISC_LFCON_MASK;
1311 if (sel->n >= PLLDU_LFCON_SET_DIVN)
1312 val |= 0x1 << PLL_MISC_LFCON_SHIFT;
1313 } else if (c->flags & (PLLX | PLLM)) {
1314 val &= ~(0x1 << PLL_MISC_DCCON_SHIFT);
1315 if (rate >= (c->u.pll.vco_max >> 1))
1316 val |= 0x1 << PLL_MISC_DCCON_SHIFT;
1317 }
1318 clk_writel(val, c->reg + PLL_MISC(c));
1319 }
1321 if (c->state == ON)
1322 tegra30_pll_clk_enable(hw);
1324 c->u.pll.fixed_rate = rate;
1326 return 0;
1327 }
1329 static long tegra30_pll_round_rate(struct clk_hw *hw, unsigned long rate,
1330 unsigned long *prate)
1331 {
1332 struct clk_tegra *c = to_clk_tegra(hw);
1333 unsigned long input_rate = *prate;
1334 u64 output_rate = *prate;
1335 const struct clk_pll_freq_table *sel;
1336 struct clk_pll_freq_table cfg;
1337 int mul;
1338 int div;
1339 u32 p_div;
1340 u32 val;
1342 if (c->flags & PLL_FIXED)
1343 return c->u.pll.fixed_rate;
1345 if (c->flags & PLLM)
1346 return __clk_get_rate(hw->clk);
1348 p_div = 0;
1349 /* Check if the target rate is tabulated */
1350 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
1351 if (sel->input_rate == input_rate && sel->output_rate == rate) {
1352 if (c->flags & PLLU) {
1353 BUG_ON(sel->p < 1 || sel->p > 2);
1354 if (sel->p == 1)
1355 p_div = PLLU_BASE_POST_DIV;
1356 } else {
1357 BUG_ON(sel->p < 1);
1358 for (val = sel->p; val > 1; val >>= 1)
1359 p_div++;
1360 p_div <<= PLL_BASE_DIVP_SHIFT;
1361 }
1362 break;
1363 }
1364 }
1366 if (sel->input_rate == 0) {
1367 unsigned long cfreq;
1368 BUG_ON(c->flags & PLLU);
1369 sel = &cfg;
1371 switch (input_rate) {
1372 case 12000000:
1373 case 26000000:
1374 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
1375 break;
1376 case 13000000:
1377 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
1378 break;
1379 case 16800000:
1380 case 19200000:
1381 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
1382 break;
1383 default:
1384 pr_err("%s: Unexpected reference rate %lu\n",
1385 __func__, input_rate);
1386 BUG();
1387 }
1389 /* Raise VCO to guarantee 0.5% accuracy */
1390 for (cfg.output_rate = rate; cfg.output_rate < 200 * cfreq;
1391 cfg.output_rate <<= 1)
1392 p_div++;
1394 cfg.p = 0x1 << p_div;
1395 cfg.m = input_rate / cfreq;
1396 cfg.n = cfg.output_rate / cfreq;
1397 }
1399 mul = sel->n;
1400 div = sel->m * sel->p;
1402 output_rate *= mul;
1403 output_rate += div - 1; /* round up */
1404 do_div(output_rate, div);
1406 return output_rate;
1407 }
1409 static unsigned long tegra30_pll_recalc_rate(struct clk_hw *hw,
1410 unsigned long parent_rate)
1411 {
1412 struct clk_tegra *c = to_clk_tegra(hw);
1413 u64 rate = parent_rate;
1414 u32 val = clk_readl(c->reg + PLL_BASE);
1416 if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
1417 const struct clk_pll_freq_table *sel;
1418 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
1419 if (sel->input_rate == parent_rate &&
1420 sel->output_rate == c->u.pll.fixed_rate) {
1421 c->mul = sel->n;
1422 c->div = sel->m * sel->p;
1423 break;
1424 }
1425 }
1426 pr_err("Clock %s has unknown fixed frequency\n",
1427 __clk_get_name(hw->clk));
1428 BUG();
1429 } else if (val & PLL_BASE_BYPASS) {
1430 c->mul = 1;
1431 c->div = 1;
1432 } else {
1433 c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
1434 c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
1435 if (c->flags & PLLU)
1436 c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
1437 else
1438 c->div *= (0x1 << ((val & PLL_BASE_DIVP_MASK) >>
1439 PLL_BASE_DIVP_SHIFT));
1440 }
1442 if (c->mul != 0 && c->div != 0) {
1443 rate *= c->mul;
1444 rate += c->div - 1; /* round up */
1445 do_div(rate, c->div);
1446 }
1448 return rate;
1449 }
1451 struct clk_ops tegra30_pll_ops = {
1452 .is_enabled = tegra30_pll_clk_is_enabled,
1453 .init = tegra30_pll_clk_init,
1454 .enable = tegra30_pll_clk_enable,
1455 .disable = tegra30_pll_clk_disable,
1456 .recalc_rate = tegra30_pll_recalc_rate,
1457 .round_rate = tegra30_pll_round_rate,
1458 .set_rate = tegra30_pll_clk_set_rate,
1459 };
1461 int tegra30_plld_clk_cfg_ex(struct clk_hw *hw,
1462 enum tegra_clk_ex_param p, u32 setting)
1463 {
1464 struct clk_tegra *c = to_clk_tegra(hw);
1465 u32 val, mask, reg;
1467 switch (p) {
1468 case TEGRA_CLK_PLLD_CSI_OUT_ENB:
1469 mask = PLLD_BASE_CSI_CLKENABLE;
1470 reg = c->reg + PLL_BASE;
1471 break;
1472 case TEGRA_CLK_PLLD_DSI_OUT_ENB:
1473 mask = PLLD_MISC_DSI_CLKENABLE;
1474 reg = c->reg + PLL_MISC(c);
1475 break;
1476 case TEGRA_CLK_PLLD_MIPI_MUX_SEL:
1477 if (!(c->flags & PLL_ALT_MISC_REG)) {
1478 mask = PLLD_BASE_DSIB_MUX_MASK;
1479 reg = c->reg + PLL_BASE;
1480 break;
1481 }
1482 /* fall through - error since PLLD2 does not have MUX_SEL control */
1483 default:
1484 return -EINVAL;
1485 }
1487 val = clk_readl(reg);
1488 if (setting)
1489 val |= mask;
1490 else
1491 val &= ~mask;
1492 clk_writel(val, reg);
1493 return 0;
1494 }
1496 static int tegra30_plle_clk_is_enabled(struct clk_hw *hw)
1497 {
1498 struct clk_tegra *c = to_clk_tegra(hw);
1499 u32 val;
1501 val = clk_readl(c->reg + PLL_BASE);
1502 c->state = (val & PLLE_BASE_ENABLE) ? ON : OFF;
1503 return c->state;
1504 }
1506 static void tegra30_plle_clk_disable(struct clk_hw *hw)
1507 {
1508 struct clk_tegra *c = to_clk_tegra(hw);
1509 u32 val;
1511 val = clk_readl(c->reg + PLL_BASE);
1512 val &= ~(PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE);
1513 clk_writel(val, c->reg + PLL_BASE);
1514 }
1516 static void tegra30_plle_training(struct clk_tegra *c)
1517 {
1518 u32 val;
1520 /* PLLE is already disabled, and setup cleared;
1521 * create falling edge on PLLE IDDQ input */
1522 val = pmc_readl(PMC_SATA_PWRGT);
1523 val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
1524 pmc_writel(val, PMC_SATA_PWRGT);
1526 val = pmc_readl(PMC_SATA_PWRGT);
1527 val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
1528 pmc_writel(val, PMC_SATA_PWRGT);
1530 val = pmc_readl(PMC_SATA_PWRGT);
1531 val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
1532 pmc_writel(val, PMC_SATA_PWRGT);
1534 do {
1535 val = clk_readl(c->reg + PLL_MISC(c));
1536 } while (!(val & PLLE_MISC_READY));
1537 }
1539 static int tegra30_plle_configure(struct clk_hw *hw, bool force_training)
1540 {
1541 struct clk_tegra *c = to_clk_tegra(hw);
1542 struct clk *parent = __clk_get_parent(hw->clk);
1543 const struct clk_pll_freq_table *sel;
1544 u32 val;
1546 unsigned long rate = c->u.pll.fixed_rate;
1547 unsigned long input_rate = __clk_get_rate(parent);
1549 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
1550 if (sel->input_rate == input_rate && sel->output_rate == rate)
1551 break;
1552 }
1554 if (sel->input_rate == 0)
1555 return -ENOSYS;
1557 /* disable PLLE, clear setup fiels */
1558 tegra30_plle_clk_disable(hw);
1560 val = clk_readl(c->reg + PLL_MISC(c));
1561 val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
1562 clk_writel(val, c->reg + PLL_MISC(c));
1564 /* training */
1565 val = clk_readl(c->reg + PLL_MISC(c));
1566 if (force_training || (!(val & PLLE_MISC_READY)))
1567 tegra30_plle_training(c);
1569 /* configure dividers, setup, disable SS */
1570 val = clk_readl(c->reg + PLL_BASE);
1571 val &= ~PLLE_BASE_DIV_MASK;
1572 val |= PLLE_BASE_DIV(sel->m, sel->n, sel->p, sel->cpcon);
1573 clk_writel(val, c->reg + PLL_BASE);
1574 c->mul = sel->n;
1575 c->div = sel->m * sel->p;
1577 val = clk_readl(c->reg + PLL_MISC(c));
1578 val |= PLLE_MISC_SETUP_VALUE;
1579 val |= PLLE_MISC_LOCK_ENABLE;
1580 clk_writel(val, c->reg + PLL_MISC(c));
1582 val = clk_readl(PLLE_SS_CTRL);
1583 val |= PLLE_SS_DISABLE;
1584 clk_writel(val, PLLE_SS_CTRL);
1586 /* enable and lock PLLE*/
1587 val = clk_readl(c->reg + PLL_BASE);
1588 val |= (PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE);
1589 clk_writel(val, c->reg + PLL_BASE);
1591 tegra30_pll_clk_wait_for_lock(c, c->reg + PLL_MISC(c), PLLE_MISC_LOCK);
1593 return 0;
1594 }
1596 static int tegra30_plle_clk_enable(struct clk_hw *hw)
1597 {
1598 struct clk_tegra *c = to_clk_tegra(hw);
1600 return tegra30_plle_configure(hw, !c->set);
1601 }
1603 static unsigned long tegra30_plle_clk_recalc_rate(struct clk_hw *hw,
1604 unsigned long parent_rate)
1605 {
1606 struct clk_tegra *c = to_clk_tegra(hw);
1607 unsigned long rate = parent_rate;
1608 u32 val;
1610 val = clk_readl(c->reg + PLL_BASE);
1611 c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLLE_BASE_DIVN_SHIFT;
1612 c->div = (val & PLLE_BASE_DIVM_MASK) >> PLLE_BASE_DIVM_SHIFT;
1613 c->div *= (val & PLLE_BASE_DIVP_MASK) >> PLLE_BASE_DIVP_SHIFT;
1615 if (c->mul != 0 && c->div != 0) {
1616 rate *= c->mul;
1617 rate += c->div - 1; /* round up */
1618 do_div(rate, c->div);
1619 }
1620 return rate;
1621 }
1623 struct clk_ops tegra30_plle_ops = {
1624 .is_enabled = tegra30_plle_clk_is_enabled,
1625 .enable = tegra30_plle_clk_enable,
1626 .disable = tegra30_plle_clk_disable,
1627 .recalc_rate = tegra30_plle_clk_recalc_rate,
1628 };
1630 /* Clock divider ops */
1631 static int tegra30_pll_div_clk_is_enabled(struct clk_hw *hw)
1632 {
1633 struct clk_tegra *c = to_clk_tegra(hw);
1635 if (c->flags & DIV_U71) {
1636 u32 val = clk_readl(c->reg);
1637 val >>= c->reg_shift;
1638 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
1639 if (!(val & PLL_OUT_RESET_DISABLE))
1640 c->state = OFF;
1641 } else {
1642 c->state = ON;
1643 }
1644 return c->state;
1645 }
1647 static int tegra30_pll_div_clk_enable(struct clk_hw *hw)
1648 {
1649 struct clk_tegra *c = to_clk_tegra(hw);
1650 u32 val;
1651 u32 new_val;
1653 pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
1654 if (c->flags & DIV_U71) {
1655 val = clk_readl(c->reg);
1656 new_val = val >> c->reg_shift;
1657 new_val &= 0xFFFF;
1659 new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
1661 val &= ~(0xFFFF << c->reg_shift);
1662 val |= new_val << c->reg_shift;
1663 clk_writel_delay(val, c->reg);
1664 return 0;
1665 } else if (c->flags & DIV_2) {
1666 return 0;
1667 }
1668 return -EINVAL;
1669 }
1671 static void tegra30_pll_div_clk_disable(struct clk_hw *hw)
1672 {
1673 struct clk_tegra *c = to_clk_tegra(hw);
1674 u32 val;
1675 u32 new_val;
1677 pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
1678 if (c->flags & DIV_U71) {
1679 val = clk_readl(c->reg);
1680 new_val = val >> c->reg_shift;
1681 new_val &= 0xFFFF;
1683 new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
1685 val &= ~(0xFFFF << c->reg_shift);
1686 val |= new_val << c->reg_shift;
1687 clk_writel_delay(val, c->reg);
1688 }
1689 }
1691 static int tegra30_pll_div_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1692 unsigned long parent_rate)
1693 {
1694 struct clk_tegra *c = to_clk_tegra(hw);
1695 u32 val;
1696 u32 new_val;
1697 int divider_u71;
1699 if (c->flags & DIV_U71) {
1700 divider_u71 = clk_div71_get_divider(
1701 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
1702 if (divider_u71 >= 0) {
1703 val = clk_readl(c->reg);
1704 new_val = val >> c->reg_shift;
1705 new_val &= 0xFFFF;
1706 if (c->flags & DIV_U71_FIXED)
1707 new_val |= PLL_OUT_OVERRIDE;
1708 new_val &= ~PLL_OUT_RATIO_MASK;
1709 new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
1711 val &= ~(0xFFFF << c->reg_shift);
1712 val |= new_val << c->reg_shift;
1713 clk_writel_delay(val, c->reg);
1714 c->div = divider_u71 + 2;
1715 c->mul = 2;
1716 c->fixed_rate = rate;
1717 return 0;
1718 }
1719 } else if (c->flags & DIV_2) {
1720 c->fixed_rate = rate;
1721 return 0;
1722 }
1724 return -EINVAL;
1725 }
1727 static unsigned long tegra30_pll_div_clk_recalc_rate(struct clk_hw *hw,
1728 unsigned long parent_rate)
1729 {
1730 struct clk_tegra *c = to_clk_tegra(hw);
1731 u64 rate = parent_rate;
1733 if (c->flags & DIV_U71) {
1734 u32 divu71;
1735 u32 val = clk_readl(c->reg);
1736 val >>= c->reg_shift;
1738 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
1739 c->div = (divu71 + 2);
1740 c->mul = 2;
1741 } else if (c->flags & DIV_2) {
1742 if (c->flags & (PLLD | PLLX)) {
1743 c->div = 2;
1744 c->mul = 1;
1745 } else
1746 BUG();
1747 } else {
1748 c->div = 1;
1749 c->mul = 1;
1750 }
1751 if (c->mul != 0 && c->div != 0) {
1752 rate *= c->mul;
1753 rate += c->div - 1; /* round up */
1754 do_div(rate, c->div);
1755 }
1757 return rate;
1758 }
1760 static long tegra30_pll_div_clk_round_rate(struct clk_hw *hw,
1761 unsigned long rate, unsigned long *prate)
1762 {
1763 struct clk_tegra *c = to_clk_tegra(hw);
1764 unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
1765 int divider;
1767 if (prate)
1768 parent_rate = *prate;
1770 if (c->flags & DIV_U71) {
1771 divider = clk_div71_get_divider(
1772 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
1773 if (divider < 0)
1774 return divider;
1775 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
1776 } else if (c->flags & DIV_2) {
1777 *prate = rate * 2;
1778 return rate;
1779 }
1781 return -EINVAL;
1782 }
1784 struct clk_ops tegra30_pll_div_ops = {
1785 .is_enabled = tegra30_pll_div_clk_is_enabled,
1786 .enable = tegra30_pll_div_clk_enable,
1787 .disable = tegra30_pll_div_clk_disable,
1788 .set_rate = tegra30_pll_div_clk_set_rate,
1789 .recalc_rate = tegra30_pll_div_clk_recalc_rate,
1790 .round_rate = tegra30_pll_div_clk_round_rate,
1791 };
1793 /* Periph clk ops */
1794 static inline u32 periph_clk_source_mask(struct clk_tegra *c)
1795 {
1796 if (c->flags & MUX8)
1797 return 7 << 29;
1798 else if (c->flags & MUX_PWM)
1799 return 3 << 28;
1800 else if (c->flags & MUX_CLK_OUT)
1801 return 3 << (c->u.periph.clk_num + 4);
1802 else if (c->flags & PLLD)
1803 return PLLD_BASE_DSIB_MUX_MASK;
1804 else
1805 return 3 << 30;
1806 }
1808 static inline u32 periph_clk_source_shift(struct clk_tegra *c)
1809 {
1810 if (c->flags & MUX8)
1811 return 29;
1812 else if (c->flags & MUX_PWM)
1813 return 28;
1814 else if (c->flags & MUX_CLK_OUT)
1815 return c->u.periph.clk_num + 4;
1816 else if (c->flags & PLLD)
1817 return PLLD_BASE_DSIB_MUX_SHIFT;
1818 else
1819 return 30;
1820 }
1822 static int tegra30_periph_clk_is_enabled(struct clk_hw *hw)
1823 {
1824 struct clk_tegra *c = to_clk_tegra(hw);
1826 c->state = ON;
1827 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
1828 c->state = OFF;
1829 if (!(c->flags & PERIPH_NO_RESET))
1830 if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c))
1831 c->state = OFF;
1832 return c->state;
1833 }
1835 static int tegra30_periph_clk_enable(struct clk_hw *hw)
1836 {
1837 struct clk_tegra *c = to_clk_tegra(hw);
1839 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
1840 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1)
1841 return 0;
1843 clk_writel_delay(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_SET_REG(c));
1844 if (!(c->flags & PERIPH_NO_RESET) &&
1845 !(c->flags & PERIPH_MANUAL_RESET)) {
1846 if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) &
1847 PERIPH_CLK_TO_BIT(c)) {
1848 udelay(5); /* reset propagation delay */
1849 clk_writel(PERIPH_CLK_TO_BIT(c),
1850 PERIPH_CLK_TO_RST_CLR_REG(c));
1851 }
1852 }
1853 return 0;
1854 }
1856 static void tegra30_periph_clk_disable(struct clk_hw *hw)
1857 {
1858 struct clk_tegra *c = to_clk_tegra(hw);
1859 unsigned long val;
1861 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
1863 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 0)
1864 return;
1866 /* If peripheral is in the APB bus then read the APB bus to
1867 * flush the write operation in apb bus. This will avoid the
1868 * peripheral access after disabling clock*/
1869 if (c->flags & PERIPH_ON_APB)
1870 val = chipid_readl();
1872 clk_writel_delay(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c));
1873 }
1875 void tegra30_periph_clk_reset(struct clk_hw *hw, bool assert)
1876 {
1877 struct clk_tegra *c = to_clk_tegra(hw);
1878 unsigned long val;
1880 if (!(c->flags & PERIPH_NO_RESET)) {
1881 if (assert) {
1882 /* If peripheral is in the APB bus then read the APB
1883 * bus to flush the write operation in apb bus. This
1884 * will avoid the peripheral access after disabling
1885 * clock */
1886 if (c->flags & PERIPH_ON_APB)
1887 val = chipid_readl();
1889 clk_writel(PERIPH_CLK_TO_BIT(c),
1890 PERIPH_CLK_TO_RST_SET_REG(c));
1891 } else
1892 clk_writel(PERIPH_CLK_TO_BIT(c),
1893 PERIPH_CLK_TO_RST_CLR_REG(c));
1894 }
1895 }
1897 static int tegra30_periph_clk_set_parent(struct clk_hw *hw, u8 index)
1898 {
1899 struct clk_tegra *c = to_clk_tegra(hw);
1900 u32 val;
1902 if (!(c->flags & MUX))
1903 return (index == 0) ? 0 : (-EINVAL);
1905 val = clk_readl(c->reg);
1906 val &= ~periph_clk_source_mask(c);
1907 val |= (index << periph_clk_source_shift(c));
1908 clk_writel_delay(val, c->reg);
1909 return 0;
1910 }
1912 static u8 tegra30_periph_clk_get_parent(struct clk_hw *hw)
1913 {
1914 struct clk_tegra *c = to_clk_tegra(hw);
1915 u32 val = clk_readl(c->reg);
1916 int source = (val & periph_clk_source_mask(c)) >>
1917 periph_clk_source_shift(c);
1919 if (!(c->flags & MUX))
1920 return 0;
1922 return source;
1923 }
1925 static int tegra30_periph_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1926 unsigned long parent_rate)
1927 {
1928 struct clk_tegra *c = to_clk_tegra(hw);
1929 u32 val;
1930 int divider;
1932 if (c->flags & DIV_U71) {
1933 divider = clk_div71_get_divider(
1934 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
1935 if (divider >= 0) {
1936 val = clk_readl(c->reg);
1937 val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
1938 val |= divider;
1939 if (c->flags & DIV_U71_UART) {
1940 if (divider)
1941 val |= PERIPH_CLK_UART_DIV_ENB;
1942 else
1943 val &= ~PERIPH_CLK_UART_DIV_ENB;
1944 }
1945 clk_writel_delay(val, c->reg);
1946 c->div = divider + 2;
1947 c->mul = 2;
1948 return 0;
1949 }
1950 } else if (c->flags & DIV_U16) {
1951 divider = clk_div16_get_divider(parent_rate, rate);
1952 if (divider >= 0) {
1953 val = clk_readl(c->reg);
1954 val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
1955 val |= divider;
1956 clk_writel_delay(val, c->reg);
1957 c->div = divider + 1;
1958 c->mul = 1;
1959 return 0;
1960 }
1961 } else if (parent_rate <= rate) {
1962 c->div = 1;
1963 c->mul = 1;
1964 return 0;
1965 }
1966 return -EINVAL;
1967 }
1969 static long tegra30_periph_clk_round_rate(struct clk_hw *hw, unsigned long rate,
1970 unsigned long *prate)
1971 {
1972 struct clk_tegra *c = to_clk_tegra(hw);
1973 unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
1974 int divider;
1976 if (prate)
1977 parent_rate = *prate;
1979 if (c->flags & DIV_U71) {
1980 divider = clk_div71_get_divider(
1981 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
1982 if (divider < 0)
1983 return divider;
1985 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
1986 } else if (c->flags & DIV_U16) {
1987 divider = clk_div16_get_divider(parent_rate, rate);
1988 if (divider < 0)
1989 return divider;
1990 return DIV_ROUND_UP(parent_rate, divider + 1);
1991 }
1992 return -EINVAL;
1993 }
1995 static unsigned long tegra30_periph_clk_recalc_rate(struct clk_hw *hw,
1996 unsigned long parent_rate)
1997 {
1998 struct clk_tegra *c = to_clk_tegra(hw);
1999 u64 rate = parent_rate;
2000 u32 val = clk_readl(c->reg);
2002 if (c->flags & DIV_U71) {
2003 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
2004 if ((c->flags & DIV_U71_UART) &&
2005 (!(val & PERIPH_CLK_UART_DIV_ENB))) {
2006 divu71 = 0;
2007 }
2008 if (c->flags & DIV_U71_IDLE) {
2009 val &= ~(PERIPH_CLK_SOURCE_DIVU71_MASK <<
2010 PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
2011 val |= (PERIPH_CLK_SOURCE_DIVIDLE_VAL <<
2012 PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
2013 clk_writel(val, c->reg);
2014 }
2015 c->div = divu71 + 2;
2016 c->mul = 2;
2017 } else if (c->flags & DIV_U16) {
2018 u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
2019 c->div = divu16 + 1;
2020 c->mul = 1;
2021 } else {
2022 c->div = 1;
2023 c->mul = 1;
2024 }
2026 if (c->mul != 0 && c->div != 0) {
2027 rate *= c->mul;
2028 rate += c->div - 1; /* round up */
2029 do_div(rate, c->div);
2030 }
2031 return rate;
2032 }
2034 struct clk_ops tegra30_periph_clk_ops = {
2035 .is_enabled = tegra30_periph_clk_is_enabled,
2036 .enable = tegra30_periph_clk_enable,
2037 .disable = tegra30_periph_clk_disable,
2038 .set_parent = tegra30_periph_clk_set_parent,
2039 .get_parent = tegra30_periph_clk_get_parent,
2040 .set_rate = tegra30_periph_clk_set_rate,
2041 .round_rate = tegra30_periph_clk_round_rate,
2042 .recalc_rate = tegra30_periph_clk_recalc_rate,
2043 };
2045 static int tegra30_dsib_clk_set_parent(struct clk_hw *hw, u8 index)
2046 {
2047 struct clk *d = clk_get_sys(NULL, "pll_d");
2048 /* The DSIB parent selection bit is in PLLD base register */
2049 tegra_clk_cfg_ex(
2050 d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, index);
2052 return 0;
2053 }
2055 struct clk_ops tegra30_dsib_clk_ops = {
2056 .is_enabled = tegra30_periph_clk_is_enabled,
2057 .enable = &tegra30_periph_clk_enable,
2058 .disable = &tegra30_periph_clk_disable,
2059 .set_parent = &tegra30_dsib_clk_set_parent,
2060 .get_parent = &tegra30_periph_clk_get_parent,
2061 .set_rate = &tegra30_periph_clk_set_rate,
2062 .round_rate = &tegra30_periph_clk_round_rate,
2063 .recalc_rate = &tegra30_periph_clk_recalc_rate,
2064 };
2066 /* Periph extended clock configuration ops */
2067 int tegra30_vi_clk_cfg_ex(struct clk_hw *hw,
2068 enum tegra_clk_ex_param p, u32 setting)
2069 {
2070 struct clk_tegra *c = to_clk_tegra(hw);
2072 if (p == TEGRA_CLK_VI_INP_SEL) {
2073 u32 val = clk_readl(c->reg);
2074 val &= ~PERIPH_CLK_VI_SEL_EX_MASK;
2075 val |= (setting << PERIPH_CLK_VI_SEL_EX_SHIFT) &
2076 PERIPH_CLK_VI_SEL_EX_MASK;
2077 clk_writel(val, c->reg);
2078 return 0;
2079 }
2080 return -EINVAL;
2081 }
2083 int tegra30_nand_clk_cfg_ex(struct clk_hw *hw,
2084 enum tegra_clk_ex_param p, u32 setting)
2085 {
2086 struct clk_tegra *c = to_clk_tegra(hw);
2088 if (p == TEGRA_CLK_NAND_PAD_DIV2_ENB) {
2089 u32 val = clk_readl(c->reg);
2090 if (setting)
2091 val |= PERIPH_CLK_NAND_DIV_EX_ENB;
2092 else
2093 val &= ~PERIPH_CLK_NAND_DIV_EX_ENB;
2094 clk_writel(val, c->reg);
2095 return 0;
2096 }
2097 return -EINVAL;
2098 }
2100 int tegra30_dtv_clk_cfg_ex(struct clk_hw *hw,
2101 enum tegra_clk_ex_param p, u32 setting)
2102 {
2103 struct clk_tegra *c = to_clk_tegra(hw);
2105 if (p == TEGRA_CLK_DTV_INVERT) {
2106 u32 val = clk_readl(c->reg);
2107 if (setting)
2108 val |= PERIPH_CLK_DTV_POLARITY_INV;
2109 else
2110 val &= ~PERIPH_CLK_DTV_POLARITY_INV;
2111 clk_writel(val, c->reg);
2112 return 0;
2113 }
2114 return -EINVAL;
2115 }
2117 /* Output clock ops */
2119 static DEFINE_SPINLOCK(clk_out_lock);
2121 static int tegra30_clk_out_is_enabled(struct clk_hw *hw)
2122 {
2123 struct clk_tegra *c = to_clk_tegra(hw);
2124 u32 val = pmc_readl(c->reg);
2126 c->state = (val & (0x1 << c->u.periph.clk_num)) ? ON : OFF;
2127 c->mul = 1;
2128 c->div = 1;
2129 return c->state;
2130 }
2132 static int tegra30_clk_out_enable(struct clk_hw *hw)
2133 {
2134 struct clk_tegra *c = to_clk_tegra(hw);
2135 u32 val;
2136 unsigned long flags;
2138 spin_lock_irqsave(&clk_out_lock, flags);
2139 val = pmc_readl(c->reg);
2140 val |= (0x1 << c->u.periph.clk_num);
2141 pmc_writel(val, c->reg);
2142 spin_unlock_irqrestore(&clk_out_lock, flags);
2144 return 0;
2145 }
2147 static void tegra30_clk_out_disable(struct clk_hw *hw)
2148 {
2149 struct clk_tegra *c = to_clk_tegra(hw);
2150 u32 val;
2151 unsigned long flags;
2153 spin_lock_irqsave(&clk_out_lock, flags);
2154 val = pmc_readl(c->reg);
2155 val &= ~(0x1 << c->u.periph.clk_num);
2156 pmc_writel(val, c->reg);
2157 spin_unlock_irqrestore(&clk_out_lock, flags);
2158 }
2160 static int tegra30_clk_out_set_parent(struct clk_hw *hw, u8 index)
2161 {
2162 struct clk_tegra *c = to_clk_tegra(hw);
2163 u32 val;
2164 unsigned long flags;
2166 spin_lock_irqsave(&clk_out_lock, flags);
2167 val = pmc_readl(c->reg);
2168 val &= ~periph_clk_source_mask(c);
2169 val |= (index << periph_clk_source_shift(c));
2170 pmc_writel(val, c->reg);
2171 spin_unlock_irqrestore(&clk_out_lock, flags);
2173 return 0;
2174 }
2176 static u8 tegra30_clk_out_get_parent(struct clk_hw *hw)
2177 {
2178 struct clk_tegra *c = to_clk_tegra(hw);
2179 u32 val = pmc_readl(c->reg);
2180 int source;
2182 source = (val & periph_clk_source_mask(c)) >>
2183 periph_clk_source_shift(c);
2184 return source;
2185 }
2187 struct clk_ops tegra_clk_out_ops = {
2188 .is_enabled = tegra30_clk_out_is_enabled,
2189 .enable = tegra30_clk_out_enable,
2190 .disable = tegra30_clk_out_disable,
2191 .set_parent = tegra30_clk_out_set_parent,
2192 .get_parent = tegra30_clk_out_get_parent,
2193 .recalc_rate = tegra30_clk_fixed_recalc_rate,
2194 };
2196 /* Clock doubler ops */
2197 static int tegra30_clk_double_is_enabled(struct clk_hw *hw)
2198 {
2199 struct clk_tegra *c = to_clk_tegra(hw);
2201 c->state = ON;
2202 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
2203 c->state = OFF;
2204 return c->state;
2205 };
2207 static int tegra30_clk_double_set_rate(struct clk_hw *hw, unsigned long rate,
2208 unsigned long parent_rate)
2209 {
2210 struct clk_tegra *c = to_clk_tegra(hw);
2211 u32 val;
2213 if (rate == parent_rate) {
2214 val = clk_readl(c->reg) | (0x1 << c->reg_shift);
2215 clk_writel(val, c->reg);
2216 c->mul = 1;
2217 c->div = 1;
2218 return 0;
2219 } else if (rate == 2 * parent_rate) {
2220 val = clk_readl(c->reg) & (~(0x1 << c->reg_shift));
2221 clk_writel(val, c->reg);
2222 c->mul = 2;
2223 c->div = 1;
2224 return 0;
2225 }
2226 return -EINVAL;
2227 }
2229 static unsigned long tegra30_clk_double_recalc_rate(struct clk_hw *hw,
2230 unsigned long parent_rate)
2231 {
2232 struct clk_tegra *c = to_clk_tegra(hw);
2233 u64 rate = parent_rate;
2235 u32 val = clk_readl(c->reg);
2236 c->mul = val & (0x1 << c->reg_shift) ? 1 : 2;
2237 c->div = 1;
2239 if (c->mul != 0 && c->div != 0) {
2240 rate *= c->mul;
2241 rate += c->div - 1; /* round up */
2242 do_div(rate, c->div);
2243 }
2245 return rate;
2246 }
2248 static long tegra30_clk_double_round_rate(struct clk_hw *hw, unsigned long rate,
2249 unsigned long *prate)
2250 {
2251 unsigned long output_rate = *prate;
2253 do_div(output_rate, 2);
2254 return output_rate;
2255 }
2257 struct clk_ops tegra30_clk_double_ops = {
2258 .is_enabled = tegra30_clk_double_is_enabled,
2259 .enable = tegra30_periph_clk_enable,
2260 .disable = tegra30_periph_clk_disable,
2261 .recalc_rate = tegra30_clk_double_recalc_rate,
2262 .round_rate = tegra30_clk_double_round_rate,
2263 .set_rate = tegra30_clk_double_set_rate,
2264 };
2266 /* Audio sync clock ops */
2267 struct clk_ops tegra_sync_source_ops = {
2268 .recalc_rate = tegra30_clk_fixed_recalc_rate,
2269 };
2271 static int tegra30_audio_sync_clk_is_enabled(struct clk_hw *hw)
2272 {
2273 struct clk_tegra *c = to_clk_tegra(hw);
2274 u32 val = clk_readl(c->reg);
2275 c->state = (val & AUDIO_SYNC_DISABLE_BIT) ? OFF : ON;
2276 return c->state;
2277 }
2279 static int tegra30_audio_sync_clk_enable(struct clk_hw *hw)
2280 {
2281 struct clk_tegra *c = to_clk_tegra(hw);
2282 u32 val = clk_readl(c->reg);
2283 clk_writel((val & (~AUDIO_SYNC_DISABLE_BIT)), c->reg);
2284 return 0;
2285 }
2287 static void tegra30_audio_sync_clk_disable(struct clk_hw *hw)
2288 {
2289 struct clk_tegra *c = to_clk_tegra(hw);
2290 u32 val = clk_readl(c->reg);
2291 clk_writel((val | AUDIO_SYNC_DISABLE_BIT), c->reg);
2292 }
2294 static int tegra30_audio_sync_clk_set_parent(struct clk_hw *hw, u8 index)
2295 {
2296 struct clk_tegra *c = to_clk_tegra(hw);
2297 u32 val;
2299 val = clk_readl(c->reg);
2300 val &= ~AUDIO_SYNC_SOURCE_MASK;
2301 val |= index;
2303 clk_writel(val, c->reg);
2304 return 0;
2305 }
2307 static u8 tegra30_audio_sync_clk_get_parent(struct clk_hw *hw)
2308 {
2309 struct clk_tegra *c = to_clk_tegra(hw);
2310 u32 val = clk_readl(c->reg);
2311 int source;
2313 source = val & AUDIO_SYNC_SOURCE_MASK;
2314 return source;
2315 }
2317 struct clk_ops tegra30_audio_sync_clk_ops = {
2318 .is_enabled = tegra30_audio_sync_clk_is_enabled,
2319 .enable = tegra30_audio_sync_clk_enable,
2320 .disable = tegra30_audio_sync_clk_disable,
2321 .set_parent = tegra30_audio_sync_clk_set_parent,
2322 .get_parent = tegra30_audio_sync_clk_get_parent,
2323 .recalc_rate = tegra30_clk_fixed_recalc_rate,
2324 };
2326 /* cml0 (pcie), and cml1 (sata) clock ops */
2327 static int tegra30_cml_clk_is_enabled(struct clk_hw *hw)
2328 {
2329 struct clk_tegra *c = to_clk_tegra(hw);
2330 u32 val = clk_readl(c->reg);
2331 c->state = val & (0x1 << c->u.periph.clk_num) ? ON : OFF;
2332 return c->state;
2333 }
2335 static int tegra30_cml_clk_enable(struct clk_hw *hw)
2336 {
2337 struct clk_tegra *c = to_clk_tegra(hw);
2339 u32 val = clk_readl(c->reg);
2340 val |= (0x1 << c->u.periph.clk_num);
2341 clk_writel(val, c->reg);
2343 return 0;
2344 }
2346 static void tegra30_cml_clk_disable(struct clk_hw *hw)
2347 {
2348 struct clk_tegra *c = to_clk_tegra(hw);
2350 u32 val = clk_readl(c->reg);
2351 val &= ~(0x1 << c->u.periph.clk_num);
2352 clk_writel(val, c->reg);
2353 }
2355 struct clk_ops tegra_cml_clk_ops = {
2356 .is_enabled = tegra30_cml_clk_is_enabled,
2357 .enable = tegra30_cml_clk_enable,
2358 .disable = tegra30_cml_clk_disable,
2359 .recalc_rate = tegra30_clk_fixed_recalc_rate,
2360 };
2362 struct clk_ops tegra_pciex_clk_ops = {
2363 .recalc_rate = tegra30_clk_fixed_recalc_rate,
2364 };
2366 /* Tegra30 CPU clock and reset control functions */
2367 static void tegra30_wait_cpu_in_reset(u32 cpu)
2368 {
2369 unsigned int reg;
2371 do {
2372 reg = readl(reg_clk_base +
2373 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
2374 cpu_relax();
2375 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
2377 return;
2378 }
2380 static void tegra30_put_cpu_in_reset(u32 cpu)
2381 {
2382 writel(CPU_RESET(cpu),
2383 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
2384 dmb();
2385 }
2387 static void tegra30_cpu_out_of_reset(u32 cpu)
2388 {
2389 writel(CPU_RESET(cpu),
2390 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
2391 wmb();
2392 }
2394 static void tegra30_enable_cpu_clock(u32 cpu)
2395 {
2396 unsigned int reg;
2398 writel(CPU_CLOCK(cpu),
2399 reg_clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
2400 reg = readl(reg_clk_base +
2401 TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
2402 }
2404 static void tegra30_disable_cpu_clock(u32 cpu)
2405 {
2407 unsigned int reg;
2409 reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
2410 writel(reg | CPU_CLOCK(cpu),
2411 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
2412 }
2414 #ifdef CONFIG_PM_SLEEP
2415 static bool tegra30_cpu_rail_off_ready(void)
2416 {
2417 unsigned int cpu_rst_status;
2418 int cpu_pwr_status;
2420 cpu_rst_status = readl(reg_clk_base +
2421 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
2422 cpu_pwr_status = tegra_powergate_is_powered(TEGRA_POWERGATE_CPU1) ||
2423 tegra_powergate_is_powered(TEGRA_POWERGATE_CPU2) ||
2424 tegra_powergate_is_powered(TEGRA_POWERGATE_CPU3);
2426 if (((cpu_rst_status & 0xE) != 0xE) || cpu_pwr_status)
2427 return false;
2429 return true;
2430 }
2432 static void tegra30_cpu_clock_suspend(void)
2433 {
2434 /* switch coresite to clk_m, save off original source */
2435 tegra30_cpu_clk_sctx.clk_csite_src =
2436 readl(reg_clk_base + CLK_RESET_SOURCE_CSITE);
2437 writel(3<<30, reg_clk_base + CLK_RESET_SOURCE_CSITE);
2439 tegra30_cpu_clk_sctx.cpu_burst =
2440 readl(reg_clk_base + CLK_RESET_CCLK_BURST);
2441 tegra30_cpu_clk_sctx.pllx_base =
2442 readl(reg_clk_base + CLK_RESET_PLLX_BASE);
2443 tegra30_cpu_clk_sctx.pllx_misc =
2444 readl(reg_clk_base + CLK_RESET_PLLX_MISC);
2445 tegra30_cpu_clk_sctx.cclk_divider =
2446 readl(reg_clk_base + CLK_RESET_CCLK_DIVIDER);
2447 }
2449 static void tegra30_cpu_clock_resume(void)
2450 {
2451 unsigned int reg, policy;
2453 /* Is CPU complex already running on PLLX? */
2454 reg = readl(reg_clk_base + CLK_RESET_CCLK_BURST);
2455 policy = (reg >> CLK_RESET_CCLK_BURST_POLICY_SHIFT) & 0xF;
2457 if (policy == CLK_RESET_CCLK_IDLE_POLICY)
2458 reg = (reg >> CLK_RESET_CCLK_IDLE_POLICY_SHIFT) & 0xF;
2459 else if (policy == CLK_RESET_CCLK_RUN_POLICY)
2460 reg = (reg >> CLK_RESET_CCLK_RUN_POLICY_SHIFT) & 0xF;
2461 else
2462 BUG();
2464 if (reg != CLK_RESET_CCLK_BURST_POLICY_PLLX) {
2465 /* restore PLLX settings if CPU is on different PLL */
2466 writel(tegra30_cpu_clk_sctx.pllx_misc,
2467 reg_clk_base + CLK_RESET_PLLX_MISC);
2468 writel(tegra30_cpu_clk_sctx.pllx_base,
2469 reg_clk_base + CLK_RESET_PLLX_BASE);
2471 /* wait for PLL stabilization if PLLX was enabled */
2472 if (tegra30_cpu_clk_sctx.pllx_base & (1 << 30))
2473 udelay(300);
2474 }
2476 /*
2477 * Restore original burst policy setting for calls resulting from CPU
2478 * LP2 in idle or system suspend.
2479 */
2480 writel(tegra30_cpu_clk_sctx.cclk_divider,
2481 reg_clk_base + CLK_RESET_CCLK_DIVIDER);
2482 writel(tegra30_cpu_clk_sctx.cpu_burst,
2483 reg_clk_base + CLK_RESET_CCLK_BURST);
2485 writel(tegra30_cpu_clk_sctx.clk_csite_src,
2486 reg_clk_base + CLK_RESET_SOURCE_CSITE);
2487 }
2488 #endif
2490 static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
2491 .wait_for_reset = tegra30_wait_cpu_in_reset,
2492 .put_in_reset = tegra30_put_cpu_in_reset,
2493 .out_of_reset = tegra30_cpu_out_of_reset,
2494 .enable_clock = tegra30_enable_cpu_clock,
2495 .disable_clock = tegra30_disable_cpu_clock,
2496 #ifdef CONFIG_PM_SLEEP
2497 .rail_off_ready = tegra30_cpu_rail_off_ready,
2498 .suspend = tegra30_cpu_clock_suspend,
2499 .resume = tegra30_cpu_clock_resume,
2500 #endif
2501 };
2503 void __init tegra30_cpu_car_ops_init(void)
2504 {
2505 tegra_cpu_car_ops = &tegra30_cpu_car_ops;
2506 }