1 /*
2 * OMAP DPLL clock support
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * Tero Kristo <t-kristo@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
18 #include <linux/clk-provider.h>
19 #include <linux/slab.h>
20 #include <linux/err.h>
21 #include <linux/of.h>
22 #include <linux/of_address.h>
23 #include <linux/clk/ti.h>
25 #undef pr_fmt
26 #define pr_fmt(fmt) "%s: " fmt, __func__
28 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
29 defined(CONFIG_SOC_DRA7XX)
30 static const struct clk_ops dpll_m4xen_ck_ops = {
31 .enable = &omap3_noncore_dpll_enable,
32 .disable = &omap3_noncore_dpll_disable,
33 .recalc_rate = &omap4_dpll_regm4xen_recalc,
34 .round_rate = &omap4_dpll_regm4xen_round_rate,
35 .set_rate = &omap3_noncore_dpll_set_rate,
36 .get_parent = &omap2_init_dpll_parent,
37 .save_context = &omap3_core_dpll_save_context,
38 .restore_context = &omap3_core_dpll_restore_context,
39 };
40 #else
41 static const struct clk_ops dpll_m4xen_ck_ops = {};
42 #endif
44 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) || \
45 defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) || \
46 defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
47 static const struct clk_ops dpll_core_ck_ops = {
48 .recalc_rate = &omap3_dpll_recalc,
49 .get_parent = &omap2_init_dpll_parent,
50 };
52 static const struct clk_ops dpll_ck_ops = {
53 .enable = &omap3_noncore_dpll_enable,
54 .disable = &omap3_noncore_dpll_disable,
55 .recalc_rate = &omap3_dpll_recalc,
56 .round_rate = &omap2_dpll_round_rate,
57 .set_rate = &omap3_noncore_dpll_set_rate,
58 .get_parent = &omap2_init_dpll_parent,
59 .save_context = &omap3_noncore_dpll_save_context,
60 .restore_context = &omap3_noncore_dpll_restore_context,
61 };
63 static const struct clk_ops dpll_no_gate_ck_ops = {
64 .recalc_rate = &omap3_dpll_recalc,
65 .get_parent = &omap2_init_dpll_parent,
66 .round_rate = &omap2_dpll_round_rate,
67 .set_rate = &omap3_noncore_dpll_set_rate,
68 .save_context = &omap3_noncore_dpll_save_context,
69 .restore_context = &omap3_noncore_dpll_restore_context
70 };
71 #else
72 static const struct clk_ops dpll_core_ck_ops = {};
73 static const struct clk_ops dpll_ck_ops = {};
74 static const struct clk_ops dpll_no_gate_ck_ops = {};
75 const struct clk_hw_omap_ops clkhwops_omap3_dpll = {};
76 #endif
78 #ifdef CONFIG_ARCH_OMAP2
79 static const struct clk_ops omap2_dpll_core_ck_ops = {
80 .get_parent = &omap2_init_dpll_parent,
81 .recalc_rate = &omap2_dpllcore_recalc,
82 .round_rate = &omap2_dpll_round_rate,
83 .set_rate = &omap2_reprogram_dpllcore,
84 };
85 #else
86 static const struct clk_ops omap2_dpll_core_ck_ops = {};
87 #endif
89 #ifdef CONFIG_ARCH_OMAP3
90 static const struct clk_ops omap3_dpll_core_ck_ops = {
91 .get_parent = &omap2_init_dpll_parent,
92 .recalc_rate = &omap3_dpll_recalc,
93 .round_rate = &omap2_dpll_round_rate,
94 };
95 #else
96 static const struct clk_ops omap3_dpll_core_ck_ops = {};
97 #endif
99 #ifdef CONFIG_ARCH_OMAP3
100 static const struct clk_ops omap3_dpll_ck_ops = {
101 .enable = &omap3_noncore_dpll_enable,
102 .disable = &omap3_noncore_dpll_disable,
103 .get_parent = &omap2_init_dpll_parent,
104 .recalc_rate = &omap3_dpll_recalc,
105 .set_rate = &omap3_noncore_dpll_set_rate,
106 .round_rate = &omap2_dpll_round_rate,
107 };
109 static const struct clk_ops omap3_dpll_per_ck_ops = {
110 .enable = &omap3_noncore_dpll_enable,
111 .disable = &omap3_noncore_dpll_disable,
112 .get_parent = &omap2_init_dpll_parent,
113 .recalc_rate = &omap3_dpll_recalc,
114 .set_rate = &omap3_dpll4_set_rate,
115 .round_rate = &omap2_dpll_round_rate,
116 };
117 #endif
119 static const struct clk_ops dpll_x2_ck_ops = {
120 .recalc_rate = &omap3_clkoutx2_recalc,
121 };
123 /**
124 * ti_clk_register_dpll - low level registration of a DPLL clock
125 * @hw: hardware clock definition for the clock
126 * @node: device node for the clock
127 *
128 * Finalizes DPLL registration process. In case a failure (clk-ref or
129 * clk-bypass is missing), the clock is added to retry list and
130 * the initialization is retried on later stage.
131 */
132 static void __init ti_clk_register_dpll(struct clk_hw *hw,
133 struct device_node *node)
134 {
135 struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
136 struct dpll_data *dd = clk_hw->dpll_data;
137 struct clk *clk;
139 dd->clk_ref = of_clk_get(node, 0);
140 dd->clk_bypass = of_clk_get(node, 1);
142 if (IS_ERR(dd->clk_ref) || IS_ERR(dd->clk_bypass)) {
143 pr_debug("clk-ref or clk-bypass missing for %s, retry later\n",
144 node->name);
145 if (!ti_clk_retry_init(node, hw, ti_clk_register_dpll))
146 return;
148 goto cleanup;
149 }
151 /* register the clock */
152 clk = clk_register(NULL, &clk_hw->hw);
154 if (!IS_ERR(clk)) {
155 omap2_init_clk_hw_omap_clocks(clk);
156 of_clk_add_provider(node, of_clk_src_simple_get, clk);
157 kfree(clk_hw->hw.init->parent_names);
158 kfree(clk_hw->hw.init);
159 return;
160 }
162 cleanup:
163 kfree(clk_hw->dpll_data);
164 kfree(clk_hw->hw.init->parent_names);
165 kfree(clk_hw->hw.init);
166 kfree(clk_hw);
167 }
169 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
170 defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX) || \
171 defined(CONFIG_SOC_AM43XX)
172 /**
173 * ti_clk_register_dpll_x2 - Registers a DPLLx2 clock
174 * @node: device node for this clock
175 * @ops: clk_ops for this clock
176 * @hw_ops: clk_hw_ops for this clock
177 *
178 * Initializes a DPLL x 2 clock from device tree data.
179 */
180 static void ti_clk_register_dpll_x2(struct device_node *node,
181 const struct clk_ops *ops,
182 const struct clk_hw_omap_ops *hw_ops)
183 {
184 struct clk *clk;
185 struct clk_init_data init = { NULL };
186 struct clk_hw_omap *clk_hw;
187 const char *name = node->name;
188 const char *parent_name;
190 parent_name = of_clk_get_parent_name(node, 0);
191 if (!parent_name) {
192 pr_err("%s must have parent\n", node->name);
193 return;
194 }
196 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
197 if (!clk_hw)
198 return;
200 clk_hw->ops = hw_ops;
201 clk_hw->hw.init = &init;
203 init.name = name;
204 init.ops = ops;
205 init.parent_names = &parent_name;
206 init.num_parents = 1;
208 /* register the clock */
209 clk = clk_register(NULL, &clk_hw->hw);
211 if (IS_ERR(clk)) {
212 kfree(clk_hw);
213 } else {
214 omap2_init_clk_hw_omap_clocks(clk);
215 of_clk_add_provider(node, of_clk_src_simple_get, clk);
216 }
217 }
218 #endif
220 /**
221 * of_ti_dpll_setup - Setup function for OMAP DPLL clocks
222 * @node: device node containing the DPLL info
223 * @ops: ops for the DPLL
224 * @ddt: DPLL data template to use
225 *
226 * Initializes a DPLL clock from device tree data.
227 */
228 static void __init of_ti_dpll_setup(struct device_node *node,
229 const struct clk_ops *ops,
230 const struct dpll_data *ddt)
231 {
232 struct clk_hw_omap *clk_hw = NULL;
233 struct clk_init_data *init = NULL;
234 const char **parent_names = NULL;
235 struct dpll_data *dd = NULL;
236 int i;
237 u8 dpll_mode = 0;
239 dd = kzalloc(sizeof(*dd), GFP_KERNEL);
240 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
241 init = kzalloc(sizeof(*init), GFP_KERNEL);
242 if (!dd || !clk_hw || !init)
243 goto cleanup;
245 memcpy(dd, ddt, sizeof(*dd));
247 clk_hw->dpll_data = dd;
248 clk_hw->ops = &clkhwops_omap3_dpll;
249 clk_hw->hw.init = init;
250 clk_hw->flags = MEMMAP_ADDRESSING;
252 init->name = node->name;
253 init->ops = ops;
255 init->num_parents = of_clk_get_parent_count(node);
256 if (init->num_parents < 1) {
257 pr_err("%s must have parent(s)\n", node->name);
258 goto cleanup;
259 }
261 parent_names = kzalloc(sizeof(char *) * init->num_parents, GFP_KERNEL);
262 if (!parent_names)
263 goto cleanup;
265 for (i = 0; i < init->num_parents; i++)
266 parent_names[i] = of_clk_get_parent_name(node, i);
268 init->parent_names = parent_names;
270 dd->control_reg = ti_clk_get_reg_addr(node, 0);
272 /*
273 * Special case for OMAP2 DPLL, register order is different due to
274 * missing idlest_reg, also clkhwops is different. Detected from
275 * missing idlest_mask.
276 */
277 if (!dd->idlest_mask) {
278 dd->mult_div1_reg = ti_clk_get_reg_addr(node, 1);
279 #ifdef CONFIG_ARCH_OMAP2
280 clk_hw->ops = &clkhwops_omap2xxx_dpll;
281 omap2xxx_clkt_dpllcore_init(&clk_hw->hw);
282 #endif
283 } else {
284 dd->idlest_reg = ti_clk_get_reg_addr(node, 1);
285 if (!dd->idlest_reg)
286 goto cleanup;
288 dd->mult_div1_reg = ti_clk_get_reg_addr(node, 2);
289 }
291 if (!dd->control_reg || !dd->mult_div1_reg)
292 goto cleanup;
294 if (dd->autoidle_mask) {
295 dd->autoidle_reg = ti_clk_get_reg_addr(node, 3);
296 if (!dd->autoidle_reg)
297 goto cleanup;
298 }
300 if (of_property_read_bool(node, "ti,low-power-stop"))
301 dpll_mode |= 1 << DPLL_LOW_POWER_STOP;
303 if (of_property_read_bool(node, "ti,low-power-bypass"))
304 dpll_mode |= 1 << DPLL_LOW_POWER_BYPASS;
306 if (of_property_read_bool(node, "ti,lock"))
307 dpll_mode |= 1 << DPLL_LOCKED;
309 if (dpll_mode)
310 dd->modes = dpll_mode;
312 ti_clk_register_dpll(&clk_hw->hw, node);
313 return;
315 cleanup:
316 kfree(dd);
317 kfree(parent_names);
318 kfree(init);
319 kfree(clk_hw);
320 }
322 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
323 defined(CONFIG_SOC_DRA7XX)
324 static void __init of_ti_omap4_dpll_x2_setup(struct device_node *node)
325 {
326 ti_clk_register_dpll_x2(node, &dpll_x2_ck_ops, &clkhwops_omap4_dpllmx);
327 }
328 CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock",
329 of_ti_omap4_dpll_x2_setup);
330 #endif
332 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
333 static void __init of_ti_am3_dpll_x2_setup(struct device_node *node)
334 {
335 ti_clk_register_dpll_x2(node, &dpll_x2_ck_ops, NULL);
336 }
337 CLK_OF_DECLARE(ti_am3_dpll_x2_clock, "ti,am3-dpll-x2-clock",
338 of_ti_am3_dpll_x2_setup);
339 #endif
341 #ifdef CONFIG_ARCH_OMAP3
342 static void __init of_ti_omap3_dpll_setup(struct device_node *node)
343 {
344 const struct dpll_data dd = {
345 .idlest_mask = 0x1,
346 .enable_mask = 0x7,
347 .autoidle_mask = 0x7,
348 .mult_mask = 0x7ff << 8,
349 .div1_mask = 0x7f,
350 .max_multiplier = 2047,
351 .max_divider = 128,
352 .min_divider = 1,
353 .freqsel_mask = 0xf0,
354 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
355 };
357 of_ti_dpll_setup(node, &omap3_dpll_ck_ops, &dd);
358 }
359 CLK_OF_DECLARE(ti_omap3_dpll_clock, "ti,omap3-dpll-clock",
360 of_ti_omap3_dpll_setup);
362 static void __init of_ti_omap3_core_dpll_setup(struct device_node *node)
363 {
364 const struct dpll_data dd = {
365 .idlest_mask = 0x1,
366 .enable_mask = 0x7,
367 .autoidle_mask = 0x7,
368 .mult_mask = 0x7ff << 16,
369 .div1_mask = 0x7f << 8,
370 .max_multiplier = 2047,
371 .max_divider = 128,
372 .min_divider = 1,
373 .freqsel_mask = 0xf0,
374 };
376 of_ti_dpll_setup(node, &omap3_dpll_core_ck_ops, &dd);
377 }
378 CLK_OF_DECLARE(ti_omap3_core_dpll_clock, "ti,omap3-dpll-core-clock",
379 of_ti_omap3_core_dpll_setup);
381 static void __init of_ti_omap3_per_dpll_setup(struct device_node *node)
382 {
383 const struct dpll_data dd = {
384 .idlest_mask = 0x1 << 1,
385 .enable_mask = 0x7 << 16,
386 .autoidle_mask = 0x7 << 3,
387 .mult_mask = 0x7ff << 8,
388 .div1_mask = 0x7f,
389 .max_multiplier = 2047,
390 .max_divider = 128,
391 .min_divider = 1,
392 .freqsel_mask = 0xf00000,
393 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
394 };
396 of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd);
397 }
398 CLK_OF_DECLARE(ti_omap3_per_dpll_clock, "ti,omap3-dpll-per-clock",
399 of_ti_omap3_per_dpll_setup);
401 static void __init of_ti_omap3_per_jtype_dpll_setup(struct device_node *node)
402 {
403 const struct dpll_data dd = {
404 .idlest_mask = 0x1 << 1,
405 .enable_mask = 0x7 << 16,
406 .autoidle_mask = 0x7 << 3,
407 .mult_mask = 0xfff << 8,
408 .div1_mask = 0x7f,
409 .max_multiplier = 4095,
410 .max_divider = 128,
411 .min_divider = 1,
412 .sddiv_mask = 0xff << 24,
413 .dco_mask = 0xe << 20,
414 .flags = DPLL_J_TYPE,
415 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
416 };
418 of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd);
419 }
420 CLK_OF_DECLARE(ti_omap3_per_jtype_dpll_clock, "ti,omap3-dpll-per-j-type-clock",
421 of_ti_omap3_per_jtype_dpll_setup);
422 #endif
424 static void __init of_ti_omap4_dpll_setup(struct device_node *node)
425 {
426 const struct dpll_data dd = {
427 .idlest_mask = 0x1,
428 .enable_mask = 0x7,
429 .autoidle_mask = 0x7,
430 .mult_mask = 0x7ff << 8,
431 .div1_mask = 0x7f,
432 .max_multiplier = 2047,
433 .max_divider = 128,
434 .min_divider = 1,
435 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
436 };
438 of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
439 }
440 CLK_OF_DECLARE(ti_omap4_dpll_clock, "ti,omap4-dpll-clock",
441 of_ti_omap4_dpll_setup);
443 static void __init of_ti_omap5_mpu_dpll_setup(struct device_node *node)
444 {
445 const struct dpll_data dd = {
446 .idlest_mask = 0x1,
447 .enable_mask = 0x7,
448 .autoidle_mask = 0x7,
449 .mult_mask = 0x7ff << 8,
450 .div1_mask = 0x7f,
451 .max_multiplier = 2047,
452 .max_divider = 128,
453 .dcc_mask = BIT(22),
454 .dcc_rate = 1400000000, /* DCC beyond 1.4GHz */
455 .min_divider = 1,
456 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
457 };
459 of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
460 }
461 CLK_OF_DECLARE(of_ti_omap5_mpu_dpll_clock, "ti,omap5-mpu-dpll-clock",
462 of_ti_omap5_mpu_dpll_setup);
464 static void __init of_ti_omap4_core_dpll_setup(struct device_node *node)
465 {
466 const struct dpll_data dd = {
467 .idlest_mask = 0x1,
468 .enable_mask = 0x7,
469 .autoidle_mask = 0x7,
470 .mult_mask = 0x7ff << 8,
471 .div1_mask = 0x7f,
472 .max_multiplier = 2047,
473 .max_divider = 128,
474 .min_divider = 1,
475 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
476 };
478 of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd);
479 }
480 CLK_OF_DECLARE(ti_omap4_core_dpll_clock, "ti,omap4-dpll-core-clock",
481 of_ti_omap4_core_dpll_setup);
483 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
484 defined(CONFIG_SOC_DRA7XX)
485 static void __init of_ti_omap4_m4xen_dpll_setup(struct device_node *node)
486 {
487 const struct dpll_data dd = {
488 .idlest_mask = 0x1,
489 .enable_mask = 0x7,
490 .autoidle_mask = 0x7,
491 .mult_mask = 0x7ff << 8,
492 .div1_mask = 0x7f,
493 .max_multiplier = 2047,
494 .max_divider = 128,
495 .min_divider = 1,
496 .m4xen_mask = 0x800,
497 .lpmode_mask = 1 << 10,
498 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
499 };
501 of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd);
502 }
503 CLK_OF_DECLARE(ti_omap4_m4xen_dpll_clock, "ti,omap4-dpll-m4xen-clock",
504 of_ti_omap4_m4xen_dpll_setup);
506 static void __init of_ti_omap4_jtype_dpll_setup(struct device_node *node)
507 {
508 const struct dpll_data dd = {
509 .idlest_mask = 0x1,
510 .enable_mask = 0x7,
511 .autoidle_mask = 0x7,
512 .mult_mask = 0xfff << 8,
513 .div1_mask = 0xff,
514 .max_multiplier = 4095,
515 .max_divider = 256,
516 .min_divider = 1,
517 .sddiv_mask = 0xff << 24,
518 .flags = DPLL_J_TYPE,
519 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
520 };
522 of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd);
523 }
524 CLK_OF_DECLARE(ti_omap4_jtype_dpll_clock, "ti,omap4-dpll-j-type-clock",
525 of_ti_omap4_jtype_dpll_setup);
526 #endif
528 static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node)
529 {
530 const struct dpll_data dd = {
531 .idlest_mask = 0x1,
532 .enable_mask = 0x7,
533 .mult_mask = 0x7ff << 8,
534 .div1_mask = 0x7f,
535 .max_multiplier = 2047,
536 .max_divider = 128,
537 .min_divider = 1,
538 .max_rate = 1000000000,
539 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
540 };
542 of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd);
543 }
544 CLK_OF_DECLARE(ti_am3_no_gate_dpll_clock, "ti,am3-dpll-no-gate-clock",
545 of_ti_am3_no_gate_dpll_setup);
547 static void __init of_ti_am3_jtype_dpll_setup(struct device_node *node)
548 {
549 const struct dpll_data dd = {
550 .idlest_mask = 0x1,
551 .enable_mask = 0x7,
552 .mult_mask = 0x7ff << 8,
553 .div1_mask = 0x7f,
554 .max_multiplier = 4095,
555 .max_divider = 256,
556 .min_divider = 2,
557 .flags = DPLL_J_TYPE,
558 .max_rate = 2000000000,
559 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
560 };
562 of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
563 }
564 CLK_OF_DECLARE(ti_am3_jtype_dpll_clock, "ti,am3-dpll-j-type-clock",
565 of_ti_am3_jtype_dpll_setup);
567 static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node)
568 {
569 const struct dpll_data dd = {
570 .idlest_mask = 0x1,
571 .enable_mask = 0x7,
572 .mult_mask = 0x7ff << 8,
573 .div1_mask = 0x7f,
574 .max_multiplier = 2047,
575 .max_divider = 128,
576 .min_divider = 1,
577 .max_rate = 2000000000,
578 .flags = DPLL_J_TYPE,
579 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
580 };
582 of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd);
583 }
584 CLK_OF_DECLARE(ti_am3_no_gate_jtype_dpll_clock,
585 "ti,am3-dpll-no-gate-j-type-clock",
586 of_ti_am3_no_gate_jtype_dpll_setup);
588 static void __init of_ti_am3_dpll_setup(struct device_node *node)
589 {
590 const struct dpll_data dd = {
591 .idlest_mask = 0x1,
592 .enable_mask = 0x7,
593 .mult_mask = 0x7ff << 8,
594 .div1_mask = 0x7f,
595 .max_multiplier = 2047,
596 .max_divider = 128,
597 .min_divider = 1,
598 .max_rate = 1000000000,
599 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
600 };
602 of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
603 }
604 CLK_OF_DECLARE(ti_am3_dpll_clock, "ti,am3-dpll-clock", of_ti_am3_dpll_setup);
606 static void __init of_ti_am3_core_dpll_setup(struct device_node *node)
607 {
608 const struct dpll_data dd = {
609 .idlest_mask = 0x1,
610 .enable_mask = 0x7,
611 .mult_mask = 0x7ff << 8,
612 .div1_mask = 0x7f,
613 .max_multiplier = 2047,
614 .max_divider = 128,
615 .min_divider = 1,
616 .max_rate = 1000000000,
617 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
618 };
620 of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd);
621 }
622 CLK_OF_DECLARE(ti_am3_core_dpll_clock, "ti,am3-dpll-core-clock",
623 of_ti_am3_core_dpll_setup);
625 static void __init of_ti_omap2_core_dpll_setup(struct device_node *node)
626 {
627 const struct dpll_data dd = {
628 .enable_mask = 0x3,
629 .mult_mask = 0x3ff << 12,
630 .div1_mask = 0xf << 8,
631 .max_divider = 16,
632 .min_divider = 1,
633 };
635 of_ti_dpll_setup(node, &omap2_dpll_core_ck_ops, &dd);
636 }
637 CLK_OF_DECLARE(ti_omap2_core_dpll_clock, "ti,omap2-dpll-core-clock",
638 of_ti_omap2_core_dpll_setup);