1 /*
2 * This file is part of wlcore
3 *
4 * Copyright (C) 2011 Texas Instruments Inc.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
22 #ifndef __WLCORE_H__
23 #define __WLCORE_H__
25 #include <linux/platform_device.h>
27 #include "wlcore_i.h"
28 #include "event.h"
29 #include "boot.h"
31 /* The maximum number of Tx descriptors in all chip families */
32 #define WLCORE_MAX_TX_DESCRIPTORS 32
34 /*
35 * We always allocate this number of mac addresses. If we don't
36 * have enough allocated addresses, the LAA bit is used
37 */
38 #define WLCORE_NUM_MAC_ADDRESSES 3
40 /* forward declaration */
41 struct wl1271_tx_hw_descr;
42 enum wl_rx_buf_align;
43 struct wl1271_rx_descriptor;
45 struct wlcore_ops {
46 int (*setup)(struct wl1271 *wl);
47 int (*identify_chip)(struct wl1271 *wl);
48 int (*identify_fw)(struct wl1271 *wl);
49 int (*boot)(struct wl1271 *wl);
50 int (*plt_init)(struct wl1271 *wl);
51 int (*trigger_cmd)(struct wl1271 *wl, int cmd_box_addr,
52 void *buf, size_t len);
53 int (*ack_event)(struct wl1271 *wl);
54 u32 (*calc_tx_blocks)(struct wl1271 *wl, u32 len, u32 spare_blks);
55 void (*set_tx_desc_blocks)(struct wl1271 *wl,
56 struct wl1271_tx_hw_descr *desc,
57 u32 blks, u32 spare_blks);
58 void (*set_tx_desc_data_len)(struct wl1271 *wl,
59 struct wl1271_tx_hw_descr *desc,
60 struct sk_buff *skb);
61 enum wl_rx_buf_align (*get_rx_buf_align)(struct wl1271 *wl,
62 u32 rx_desc);
63 int (*prepare_read)(struct wl1271 *wl, u32 rx_desc, u32 len);
64 u32 (*get_rx_packet_len)(struct wl1271 *wl, void *rx_data,
65 u32 data_len);
66 int (*tx_delayed_compl)(struct wl1271 *wl);
67 void (*tx_immediate_compl)(struct wl1271 *wl);
68 int (*hw_init)(struct wl1271 *wl);
69 int (*init_vif)(struct wl1271 *wl, struct wl12xx_vif *wlvif);
70 u32 (*sta_get_ap_rate_mask)(struct wl1271 *wl,
71 struct wl12xx_vif *wlvif);
72 int (*get_pg_ver)(struct wl1271 *wl, s8 *ver);
73 int (*get_mac)(struct wl1271 *wl);
74 void (*set_tx_desc_csum)(struct wl1271 *wl,
75 struct wl1271_tx_hw_descr *desc,
76 struct sk_buff *skb);
77 void (*set_rx_csum)(struct wl1271 *wl,
78 struct wl1271_rx_descriptor *desc,
79 struct sk_buff *skb);
80 u32 (*ap_get_mimo_wide_rate_mask)(struct wl1271 *wl,
81 struct wl12xx_vif *wlvif);
82 int (*debugfs_init)(struct wl1271 *wl, struct dentry *rootdir);
83 int (*handle_static_data)(struct wl1271 *wl,
84 struct wl1271_static_data *static_data);
85 int (*get_spare_blocks)(struct wl1271 *wl, bool is_gem);
86 int (*set_key)(struct wl1271 *wl, enum set_key_cmd cmd,
87 struct ieee80211_vif *vif,
88 struct ieee80211_sta *sta,
89 struct ieee80211_key_conf *key_conf);
90 u32 (*pre_pkt_send)(struct wl1271 *wl, u32 buf_offset, u32 last_len);
91 };
93 enum wlcore_partitions {
94 PART_DOWN,
95 PART_WORK,
96 PART_BOOT,
97 PART_DRPW,
98 PART_TOP_PRCM_ELP_SOC,
99 PART_PHY_INIT,
101 PART_TABLE_LEN,
102 };
104 struct wlcore_partition {
105 u32 size;
106 u32 start;
107 };
109 struct wlcore_partition_set {
110 struct wlcore_partition mem;
111 struct wlcore_partition reg;
112 struct wlcore_partition mem2;
113 struct wlcore_partition mem3;
114 };
116 enum wlcore_registers {
117 /* register addresses, used with partition translation */
118 REG_ECPU_CONTROL,
119 REG_INTERRUPT_NO_CLEAR,
120 REG_INTERRUPT_ACK,
121 REG_COMMAND_MAILBOX_PTR,
122 REG_EVENT_MAILBOX_PTR,
123 REG_INTERRUPT_TRIG,
124 REG_INTERRUPT_MASK,
125 REG_PC_ON_RECOVERY,
126 REG_CHIP_ID_B,
127 REG_CMD_MBOX_ADDRESS,
129 /* data access memory addresses, used with partition translation */
130 REG_SLV_MEM_DATA,
131 REG_SLV_REG_DATA,
133 /* raw data access memory addresses */
134 REG_RAW_FW_STATUS_ADDR,
136 REG_TABLE_LEN,
137 };
139 struct wl1271_stats {
140 void *fw_stats;
141 unsigned long fw_stats_update;
142 size_t fw_stats_len;
144 unsigned int retry_count;
145 unsigned int excessive_retries;
146 };
148 struct wl1271 {
149 bool initialized;
150 struct ieee80211_hw *hw;
151 bool mac80211_registered;
153 struct device *dev;
154 struct platform_device *pdev;
156 void *if_priv;
158 struct wl1271_if_operations *if_ops;
160 void (*set_power)(bool enable);
161 int irq;
163 spinlock_t wl_lock;
165 enum wlcore_state state;
166 enum wl12xx_fw_type fw_type;
167 bool plt;
168 enum plt_mode plt_mode;
169 u8 fem_manuf;
170 u8 last_vif_count;
171 struct mutex mutex;
173 unsigned long flags;
175 struct wlcore_partition_set curr_part;
177 struct wl1271_chip chip;
179 int cmd_box_addr;
181 u8 *fw;
182 size_t fw_len;
183 void *nvs;
184 size_t nvs_len;
186 s8 hw_pg_ver;
188 /* address read from the fuse ROM */
189 u32 fuse_oui_addr;
190 u32 fuse_nic_addr;
192 /* we have up to 2 MAC addresses */
193 struct mac_address addresses[WLCORE_NUM_MAC_ADDRESSES];
194 int channel;
195 u8 system_hlid;
197 unsigned long links_map[BITS_TO_LONGS(WL12XX_MAX_LINKS)];
198 unsigned long roles_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
199 unsigned long roc_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
200 unsigned long rate_policies_map[
201 BITS_TO_LONGS(WL12XX_MAX_RATE_POLICIES)];
202 unsigned long klv_templates_map[
203 BITS_TO_LONGS(WLCORE_MAX_KLV_TEMPLATES)];
205 struct list_head wlvif_list;
207 u8 sta_count;
208 u8 ap_count;
210 struct wl1271_acx_mem_map *target_mem_map;
212 /* Accounting for allocated / available TX blocks on HW */
213 u32 tx_blocks_freed;
214 u32 tx_blocks_available;
215 u32 tx_allocated_blocks;
216 u32 tx_results_count;
218 /* Accounting for allocated / available Tx packets in HW */
219 u32 tx_pkts_freed[NUM_TX_QUEUES];
220 u32 tx_allocated_pkts[NUM_TX_QUEUES];
222 /* Transmitted TX packets counter for chipset interface */
223 u32 tx_packets_count;
225 /* Time-offset between host and chipset clocks */
226 s64 time_offset;
228 /* Frames scheduled for transmission, not handled yet */
229 int tx_queue_count[NUM_TX_QUEUES];
230 unsigned long queue_stop_reasons[NUM_TX_QUEUES];
232 /* Frames received, not handled yet by mac80211 */
233 struct sk_buff_head deferred_rx_queue;
235 /* Frames sent, not returned yet to mac80211 */
236 struct sk_buff_head deferred_tx_queue;
238 struct work_struct tx_work;
239 struct workqueue_struct *freezable_wq;
241 /* Pending TX frames */
242 unsigned long tx_frames_map[BITS_TO_LONGS(WLCORE_MAX_TX_DESCRIPTORS)];
243 struct sk_buff *tx_frames[WLCORE_MAX_TX_DESCRIPTORS];
244 int tx_frames_cnt;
246 /* FW Rx counter */
247 u32 rx_counter;
249 /* Intermediate buffer, used for packet aggregation */
250 u8 *aggr_buf;
251 u32 aggr_buf_size;
253 /* Reusable dummy packet template */
254 struct sk_buff *dummy_packet;
256 /* Network stack work */
257 struct work_struct netstack_work;
259 /* FW log buffer */
260 u8 *fwlog;
262 /* Number of valid bytes in the FW log buffer */
263 ssize_t fwlog_size;
265 /* Sysfs FW log entry readers wait queue */
266 wait_queue_head_t fwlog_waitq;
268 /* Hardware recovery work */
269 struct work_struct recovery_work;
270 bool watchdog_recovery;
272 /* Pointer that holds DMA-friendly block for the mailbox */
273 struct event_mailbox *mbox;
275 /* The mbox event mask */
276 u32 event_mask;
278 /* Mailbox pointers */
279 u32 mbox_ptr[2];
281 /* Are we currently scanning */
282 struct ieee80211_vif *scan_vif;
283 struct wl1271_scan scan;
284 struct delayed_work scan_complete_work;
286 /* Connection loss work */
287 struct delayed_work connection_loss_work;
289 bool sched_scanning;
291 /* The current band */
292 enum ieee80211_band band;
294 struct completion *elp_compl;
295 struct delayed_work elp_work;
297 /* in dBm */
298 int power_level;
300 struct wl1271_stats stats;
302 __le32 buffer_32;
303 u32 buffer_cmd;
304 u32 buffer_busyword[WL1271_BUSY_WORD_CNT];
306 struct wl_fw_status_1 *fw_status_1;
307 struct wl_fw_status_2 *fw_status_2;
308 struct wl1271_tx_hw_res_if *tx_res_if;
310 /* Current chipset configuration */
311 struct wlcore_conf conf;
313 bool sg_enabled;
315 bool enable_11a;
317 /* Most recently reported noise in dBm */
318 s8 noise;
320 /* bands supported by this instance of wl12xx */
321 struct ieee80211_supported_band bands[WLCORE_NUM_BANDS];
323 /*
324 * wowlan trigger was configured during suspend.
325 * (currently, only "ANY" trigger is supported)
326 */
327 bool wow_enabled;
328 bool irq_wake_enabled;
330 /*
331 * AP-mode - links indexed by HLID. The global and broadcast links
332 * are always active.
333 */
334 struct wl1271_link links[WL12XX_MAX_LINKS];
336 /* AP-mode - a bitmap of links currently in PS mode according to FW */
337 u32 ap_fw_ps_map;
339 /* AP-mode - a bitmap of links currently in PS mode in mac80211 */
340 unsigned long ap_ps_map;
342 /* Quirks of specific hardware revisions */
343 unsigned int quirks;
345 /* Platform limitations */
346 unsigned int platform_quirks;
348 /* number of currently active RX BA sessions */
349 int ba_rx_session_count;
351 /* AP-mode - number of currently connected stations */
352 int active_sta_count;
354 /* last wlvif we transmitted from */
355 struct wl12xx_vif *last_wlvif;
357 /* work to fire when Tx is stuck */
358 struct delayed_work tx_watchdog_work;
360 struct wlcore_ops *ops;
361 /* pointer to the lower driver partition table */
362 const struct wlcore_partition_set *ptable;
363 /* pointer to the lower driver register table */
364 const int *rtable;
365 /* name of the firmwares to load - for PLT, single role, multi-role */
366 const char *plt_fw_name;
367 const char *sr_fw_name;
368 const char *mr_fw_name;
370 /* per-chip-family private structure */
371 void *priv;
373 /* number of TX descriptors the HW supports. */
374 u32 num_tx_desc;
375 /* number of RX descriptors the HW supports. */
376 u32 num_rx_desc;
378 /* translate HW Tx rates to standard rate-indices */
379 const u8 **band_rate_to_idx;
381 /* size of table for HW rates that can be received from chip */
382 u8 hw_tx_rate_tbl_size;
384 /* this HW rate and below are considered HT rates for this chip */
385 u8 hw_min_ht_rate;
387 /* HW HT (11n) capabilities */
388 struct ieee80211_sta_ht_cap ht_cap[WLCORE_NUM_BANDS];
390 /* size of the private FW status data */
391 size_t fw_status_priv_len;
393 /* RX Data filter rule state - enabled/disabled */
394 bool rx_filter_enabled[WL1271_MAX_RX_FILTERS];
396 /* size of the private static data */
397 size_t static_data_priv_len;
399 /* the current channel type */
400 enum nl80211_channel_type channel_type;
402 /* mutex for protecting the tx_flush function */
403 struct mutex flush_mutex;
405 /* sleep auth value currently configured to FW */
406 int sleep_auth;
408 /* the number of allocated MAC addresses in this chip */
409 int num_mac_addr;
411 /* the minimum FW version required for the driver to work */
412 unsigned int min_fw_ver[NUM_FW_VER];
414 struct completion nvs_loading_complete;
415 };
417 int wlcore_probe(struct wl1271 *wl, struct platform_device *pdev);
418 int wlcore_remove(struct platform_device *pdev);
419 struct ieee80211_hw *wlcore_alloc_hw(size_t priv_size, u32 aggr_buf_size);
420 int wlcore_free_hw(struct wl1271 *wl);
421 int wlcore_set_key(struct wl1271 *wl, enum set_key_cmd cmd,
422 struct ieee80211_vif *vif,
423 struct ieee80211_sta *sta,
424 struct ieee80211_key_conf *key_conf);
426 static inline void
427 wlcore_set_ht_cap(struct wl1271 *wl, enum ieee80211_band band,
428 struct ieee80211_sta_ht_cap *ht_cap)
429 {
430 memcpy(&wl->ht_cap[band], ht_cap, sizeof(*ht_cap));
431 }
433 static inline void
434 wlcore_set_min_fw_ver(struct wl1271 *wl, unsigned int chip,
435 unsigned int iftype, unsigned int major,
436 unsigned int subtype, unsigned int minor)
437 {
438 wl->min_fw_ver[FW_VER_CHIP] = chip;
439 wl->min_fw_ver[FW_VER_IF_TYPE] = iftype;
440 wl->min_fw_ver[FW_VER_MAJOR] = major;
441 wl->min_fw_ver[FW_VER_SUBTYPE] = subtype;
442 wl->min_fw_ver[FW_VER_MINOR] = minor;
443 }
445 /* Firmware image load chunk size */
446 #define CHUNK_SIZE 16384
448 /* Quirks */
450 /* Each RX/TX transaction requires an end-of-transaction transfer */
451 #define WLCORE_QUIRK_END_OF_TRANSACTION BIT(0)
453 /* wl127x and SPI don't support SDIO block size alignment */
454 #define WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN BIT(2)
456 /* means aggregated Rx packets are aligned to a SDIO block */
457 #define WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN BIT(3)
459 /* Older firmwares did not implement the FW logger over bus feature */
460 #define WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED BIT(4)
462 /* Older firmwares use an old NVS format */
463 #define WLCORE_QUIRK_LEGACY_NVS BIT(5)
465 /* Some firmwares may not support ELP */
466 #define WLCORE_QUIRK_NO_ELP BIT(6)
468 /* pad only the last frame in the aggregate buffer */
469 #define WLCORE_QUIRK_TX_PAD_LAST_FRAME BIT(7)
471 /* extra header space is required for TKIP */
472 #define WLCORE_QUIRK_TKIP_HEADER_SPACE BIT(8)
474 /* Some firmwares not support sched scans while connected */
475 #define WLCORE_QUIRK_NO_SCHED_SCAN_WHILE_CONN BIT(9)
477 /* separate probe response templates for one-shot and sched scans */
478 #define WLCORE_QUIRK_DUAL_PROBE_TMPL BIT(10)
480 /* TODO: move to the lower drivers when all usages are abstracted */
481 #define CHIP_ID_1271_PG10 (0x4030101)
482 #define CHIP_ID_1271_PG20 (0x4030111)
483 #define CHIP_ID_1283_PG10 (0x05030101)
484 #define CHIP_ID_1283_PG20 (0x05030111)
486 /* TODO: move all these common registers and values elsewhere */
487 #define HW_ACCESS_ELP_CTRL_REG 0x1FFFC
489 /* ELP register commands */
490 #define ELPCTRL_WAKE_UP 0x1
491 #define ELPCTRL_WAKE_UP_WLAN_READY 0x5
492 #define ELPCTRL_SLEEP 0x0
493 /* ELP WLAN_READY bit */
494 #define ELPCTRL_WLAN_READY 0x2
496 /*************************************************************************
498 Interrupt Trigger Register (Host -> WiLink)
500 **************************************************************************/
502 /* Hardware to Embedded CPU Interrupts - first 32-bit register set */
504 /*
505 * The host sets this bit to inform the Wlan
506 * FW that a TX packet is in the XFER
507 * Buffer #0.
508 */
509 #define INTR_TRIG_TX_PROC0 BIT(2)
511 /*
512 * The host sets this bit to inform the FW
513 * that it read a packet from RX XFER
514 * Buffer #0.
515 */
516 #define INTR_TRIG_RX_PROC0 BIT(3)
518 #define INTR_TRIG_DEBUG_ACK BIT(4)
520 #define INTR_TRIG_STATE_CHANGED BIT(5)
522 /* Hardware to Embedded CPU Interrupts - second 32-bit register set */
524 /*
525 * The host sets this bit to inform the FW
526 * that it read a packet from RX XFER
527 * Buffer #1.
528 */
529 #define INTR_TRIG_RX_PROC1 BIT(17)
531 /*
532 * The host sets this bit to inform the Wlan
533 * hardware that a TX packet is in the XFER
534 * Buffer #1.
535 */
536 #define INTR_TRIG_TX_PROC1 BIT(18)
538 #define ACX_SLV_SOFT_RESET_BIT BIT(1)
539 #define SOFT_RESET_MAX_TIME 1000000
540 #define SOFT_RESET_STALL_TIME 1000
542 #define ECPU_CONTROL_HALT 0x00000101
544 #define WELP_ARM_COMMAND_VAL 0x4
546 #endif /* __WLCORE_H__ */