Revert "usb: dwc3: debugfs: dual role switch through debugfs entries"
[android-sdk/kernel-video.git] / drivers / usb / dwc3 / dwc3-omap.c
1 /**
2  * dwc3-omap.c - OMAP Specific Glue layer
3  *
4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5  *
6  * Authors: Felipe Balbi <balbi@ti.com>,
7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8  *
9  * This program is free software: you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2  of
11  * the License as published by the Free Software Foundation.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  */
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/slab.h>
22 #include <linux/interrupt.h>
23 #include <linux/platform_device.h>
24 #include <linux/platform_data/dwc3-omap.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/ioport.h>
28 #include <linux/io.h>
29 #include <linux/of.h>
30 #include <linux/of_platform.h>
31 #include <linux/extcon.h>
32 #include <linux/regulator/consumer.h>
34 #include <linux/usb/otg.h>
36 /*
37  * All these registers belong to OMAP's Wrapper around the
38  * DesignWare USB3 Core.
39  */
41 #define USBOTGSS_REVISION                       0x0000
42 #define USBOTGSS_SYSCONFIG                      0x0010
43 #define USBOTGSS_IRQ_EOI                        0x0020
44 #define USBOTGSS_EOI_OFFSET                     0x0008
45 #define USBOTGSS_IRQSTATUS_RAW_0                0x0024
46 #define USBOTGSS_IRQSTATUS_0                    0x0028
47 #define USBOTGSS_IRQENABLE_SET_0                0x002c
48 #define USBOTGSS_IRQENABLE_CLR_0                0x0030
49 #define USBOTGSS_IRQ0_OFFSET                    0x0004
50 #define USBOTGSS_IRQSTATUS_RAW_1                0x0030
51 #define USBOTGSS_IRQSTATUS_1                    0x0034
52 #define USBOTGSS_IRQENABLE_SET_1                0x0038
53 #define USBOTGSS_IRQENABLE_CLR_1                0x003c
54 #define USBOTGSS_IRQSTATUS_RAW_2                0x0040
55 #define USBOTGSS_IRQSTATUS_2                    0x0044
56 #define USBOTGSS_IRQENABLE_SET_2                0x0048
57 #define USBOTGSS_IRQENABLE_CLR_2                0x004c
58 #define USBOTGSS_IRQSTATUS_RAW_3                0x0050
59 #define USBOTGSS_IRQSTATUS_3                    0x0054
60 #define USBOTGSS_IRQENABLE_SET_3                0x0058
61 #define USBOTGSS_IRQENABLE_CLR_3                0x005c
62 #define USBOTGSS_IRQSTATUS_EOI_MISC             0x0030
63 #define USBOTGSS_IRQSTATUS_RAW_MISC             0x0034
64 #define USBOTGSS_IRQSTATUS_MISC                 0x0038
65 #define USBOTGSS_IRQENABLE_SET_MISC             0x003c
66 #define USBOTGSS_IRQENABLE_CLR_MISC             0x0040
67 #define USBOTGSS_IRQMISC_OFFSET                 0x03fc
68 #define USBOTGSS_UTMI_OTG_CTRL                  0x0080
69 #define USBOTGSS_UTMI_OTG_STATUS                0x0084
70 #define USBOTGSS_UTMI_OTG_OFFSET                0x0480
71 #define USBOTGSS_TXFIFO_DEPTH                   0x0508
72 #define USBOTGSS_RXFIFO_DEPTH                   0x050c
73 #define USBOTGSS_MMRAM_OFFSET                   0x0100
74 #define USBOTGSS_FLADJ                          0x0104
75 #define USBOTGSS_DEBUG_CFG                      0x0108
76 #define USBOTGSS_DEBUG_DATA                     0x010c
77 #define USBOTGSS_DEV_EBC_EN                     0x0110
78 #define USBOTGSS_DEBUG_OFFSET                   0x0600
80 /* SYSCONFIG REGISTER */
81 #define USBOTGSS_SYSCONFIG_DMADISABLE           (1 << 16)
83 /* IRQ_EOI REGISTER */
84 #define USBOTGSS_IRQ_EOI_LINE_NUMBER            (1 << 0)
86 /* IRQS0 BITS */
87 #define USBOTGSS_IRQO_COREIRQ_ST                (1 << 0)
89 /* IRQMISC BITS */
90 #define USBOTGSS_IRQMISC_DMADISABLECLR          (1 << 17)
91 #define USBOTGSS_IRQMISC_OEVT                   (1 << 16)
92 #define USBOTGSS_IRQMISC_DRVVBUS_RISE           (1 << 13)
93 #define USBOTGSS_IRQMISC_CHRGVBUS_RISE          (1 << 12)
94 #define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE       (1 << 11)
95 #define USBOTGSS_IRQMISC_IDPULLUP_RISE          (1 << 8)
96 #define USBOTGSS_IRQMISC_DRVVBUS_FALL           (1 << 5)
97 #define USBOTGSS_IRQMISC_CHRGVBUS_FALL          (1 << 4)
98 #define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL               (1 << 3)
99 #define USBOTGSS_IRQMISC_IDPULLUP_FALL          (1 << 0)
101 /* UTMI_OTG_CTRL REGISTER */
102 #define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS          (1 << 5)
103 #define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS         (1 << 4)
104 #define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS      (1 << 3)
105 #define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP         (1 << 0)
107 /* UTMI_OTG_STATUS REGISTER */
108 #define USBOTGSS_UTMI_OTG_STATUS_SW_MODE        (1 << 31)
109 #define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT   (1 << 9)
110 #define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8)
111 #define USBOTGSS_UTMI_OTG_STATUS_IDDIG          (1 << 4)
112 #define USBOTGSS_UTMI_OTG_STATUS_SESSEND        (1 << 3)
113 #define USBOTGSS_UTMI_OTG_STATUS_SESSVALID      (1 << 2)
114 #define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID      (1 << 1)
116 struct dwc3_omap {
117         struct device           *dev;
119         int                     irq;
120         void __iomem            *base;
122         u32                     utmi_otg_status;
123         u32                     utmi_otg_offset;
124         u32                     irqmisc_offset;
125         u32                     irq_eoi_offset;
126         u32                     debug_offset;
127         u32                     irq0_offset;
129         u32                     dma_status:1;
130         u32                     id_detect_only:1;
132         struct extcon_specific_cable_nb extcon_vbus_dev;
133         struct extcon_specific_cable_nb extcon_id_dev;
134         struct notifier_block   vbus_nb;
135         struct notifier_block   id_nb;
137         struct regulator        *vbus_reg;
138 };
140 enum omap_dwc3_vbus_id_status {
141         OMAP_DWC3_ID_FLOAT,
142         OMAP_DWC3_ID_GROUND,
143         OMAP_DWC3_VBUS_OFF,
144         OMAP_DWC3_VBUS_VALID,
145 };
147 static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset)
149         return readl(base + offset);
152 static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
154         writel(value, base + offset);
157 static u32 dwc3_omap_read_utmi_status(struct dwc3_omap *omap)
159         return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS +
160                                                         omap->utmi_otg_offset);
163 static void dwc3_omap_write_utmi_status(struct dwc3_omap *omap, u32 value)
165         dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS +
166                                         omap->utmi_otg_offset, value);
170 static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap)
172         return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0 -
173                                                 omap->irq0_offset);
176 static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value)
178         dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 -
179                                                 omap->irq0_offset, value);
183 static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap)
185         return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_MISC +
186                                                 omap->irqmisc_offset);
189 static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value)
191         dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC +
192                                         omap->irqmisc_offset, value);
196 static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value)
198         dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC +
199                                                 omap->irqmisc_offset, value);
203 static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value)
205         dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 -
206                                                 omap->irq0_offset, value);
209 static void dwc3_omap_write_irqmisc_clr(struct dwc3_omap *omap, u32 value)
211         dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_MISC +
212                                                 omap->irqmisc_offset, value);
215 static void dwc3_omap_write_irq0_clr(struct dwc3_omap *omap, u32 value)
217         dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_0 -
218                                                 omap->irq0_offset, value);
221 static void dwc3_omap_set_mailbox(struct dwc3_omap *omap,
222         enum omap_dwc3_vbus_id_status status)
224         int     ret;
225         u32     val;
227         switch (status) {
228         case OMAP_DWC3_ID_GROUND:
229                 dev_dbg(omap->dev, "ID GND\n");
231                 if (omap->vbus_reg) {
232                         ret = regulator_enable(omap->vbus_reg);
233                         if (ret) {
234                                 dev_dbg(omap->dev, "regulator enable failed\n");
235                                 return;
236                         }
237                 }
239                 val = dwc3_omap_read_utmi_status(omap);
240                 val &= ~(USBOTGSS_UTMI_OTG_STATUS_IDDIG
241                                 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
242                                 | USBOTGSS_UTMI_OTG_STATUS_SESSEND);
243                 val |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID
244                                 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
245                 dwc3_omap_write_utmi_status(omap, val);
246                 break;
248         case OMAP_DWC3_VBUS_VALID:
249                 dev_dbg(omap->dev, "VBUS Connect\n");
251                 val = dwc3_omap_read_utmi_status(omap);
252                 val &= ~USBOTGSS_UTMI_OTG_STATUS_SESSEND;
253                 val |= USBOTGSS_UTMI_OTG_STATUS_IDDIG
254                                 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
255                                 | USBOTGSS_UTMI_OTG_STATUS_SESSVALID
256                                 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
257                 dwc3_omap_write_utmi_status(omap, val);
258                 break;
260         case OMAP_DWC3_ID_FLOAT:
261                 if (omap->vbus_reg)
262                         regulator_disable(omap->vbus_reg);
264         case OMAP_DWC3_VBUS_OFF:
265                 dev_dbg(omap->dev, "VBUS Disconnect\n");
267                 val = dwc3_omap_read_utmi_status(omap);
268                 val &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSVALID
269                                 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
270                                 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT);
271                 val |= USBOTGSS_UTMI_OTG_STATUS_SESSEND
272                                 | USBOTGSS_UTMI_OTG_STATUS_IDDIG;
273                 dwc3_omap_write_utmi_status(omap, val);
274                 break;
276         default:
277                 dev_dbg(omap->dev, "invalid state\n");
278         }
281 static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
283         struct dwc3_omap        *omap = _omap;
284         u32                     reg;
286         reg = dwc3_omap_read_irqmisc_status(omap);
288         if (reg & USBOTGSS_IRQMISC_DMADISABLECLR) {
289                 dev_dbg(omap->dev, "DMA Disable was Cleared\n");
290                 omap->dma_status = false;
291         }
293         if (reg & USBOTGSS_IRQMISC_OEVT)
294                 dev_dbg(omap->dev, "OTG Event\n");
296         if (reg & USBOTGSS_IRQMISC_DRVVBUS_RISE)
297                 dev_dbg(omap->dev, "DRVVBUS Rise\n");
299         if (reg & USBOTGSS_IRQMISC_CHRGVBUS_RISE)
300                 dev_dbg(omap->dev, "CHRGVBUS Rise\n");
302         if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_RISE)
303                 dev_dbg(omap->dev, "DISCHRGVBUS Rise\n");
305         if (reg & USBOTGSS_IRQMISC_IDPULLUP_RISE)
306                 dev_dbg(omap->dev, "IDPULLUP Rise\n");
308         if (reg & USBOTGSS_IRQMISC_DRVVBUS_FALL)
309                 dev_dbg(omap->dev, "DRVVBUS Fall\n");
311         if (reg & USBOTGSS_IRQMISC_CHRGVBUS_FALL)
312                 dev_dbg(omap->dev, "CHRGVBUS Fall\n");
314         if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_FALL)
315                 dev_dbg(omap->dev, "DISCHRGVBUS Fall\n");
317         if (reg & USBOTGSS_IRQMISC_IDPULLUP_FALL)
318                 dev_dbg(omap->dev, "IDPULLUP Fall\n");
320         dwc3_omap_write_irqmisc_status(omap, reg);
322         reg = dwc3_omap_read_irq0_status(omap);
324         dwc3_omap_write_irq0_status(omap, reg);
326         return IRQ_HANDLED;
329 static int dwc3_omap_remove_core(struct device *dev, void *c)
331         struct platform_device *pdev = to_platform_device(dev);
333         of_device_unregister(pdev);
335         return 0;
338 static void dwc3_omap_enable_irqs(struct dwc3_omap *omap)
340         u32                     reg;
342         /* enable all IRQs */
343         reg = USBOTGSS_IRQO_COREIRQ_ST;
344         dwc3_omap_write_irq0_set(omap, reg);
346         reg = (USBOTGSS_IRQMISC_OEVT |
347                         USBOTGSS_IRQMISC_DRVVBUS_RISE |
348                         USBOTGSS_IRQMISC_CHRGVBUS_RISE |
349                         USBOTGSS_IRQMISC_DISCHRGVBUS_RISE |
350                         USBOTGSS_IRQMISC_IDPULLUP_RISE |
351                         USBOTGSS_IRQMISC_DRVVBUS_FALL |
352                         USBOTGSS_IRQMISC_CHRGVBUS_FALL |
353                         USBOTGSS_IRQMISC_DISCHRGVBUS_FALL |
354                         USBOTGSS_IRQMISC_IDPULLUP_FALL);
356         dwc3_omap_write_irqmisc_set(omap, reg);
359 static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)
361         u32                     reg;
363         /* disable all IRQs */
364         reg = USBOTGSS_IRQO_COREIRQ_ST;
365         dwc3_omap_write_irq0_clr(omap, reg);
367         reg = (USBOTGSS_IRQMISC_OEVT |
368                         USBOTGSS_IRQMISC_DRVVBUS_RISE |
369                         USBOTGSS_IRQMISC_CHRGVBUS_RISE |
370                         USBOTGSS_IRQMISC_DISCHRGVBUS_RISE |
371                         USBOTGSS_IRQMISC_IDPULLUP_RISE |
372                         USBOTGSS_IRQMISC_DRVVBUS_FALL |
373                         USBOTGSS_IRQMISC_CHRGVBUS_FALL |
374                         USBOTGSS_IRQMISC_DISCHRGVBUS_FALL |
375                         USBOTGSS_IRQMISC_IDPULLUP_FALL);
377         dwc3_omap_write_irqmisc_clr(omap, reg);
380 static u64 dwc3_omap_dma_mask = DMA_BIT_MASK(32);
382 static int dwc3_omap_id_notifier(struct notifier_block *nb,
383         unsigned long event, void *ptr)
385         struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, id_nb);
387         if (event) {
388                 if (omap->id_detect_only)
389                         dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF);
390                 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
391         } else {
392                 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT);
393                 if (omap->id_detect_only)
394                         dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
395         }
397         return NOTIFY_DONE;
400 static int dwc3_omap_vbus_notifier(struct notifier_block *nb,
401         unsigned long event, void *ptr)
403         struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, vbus_nb);
405         if (event)
406                 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
407         else
408                 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF);
410         return NOTIFY_DONE;
413 static void dwc3_omap_map_offset(struct dwc3_omap *omap)
415         struct device_node      *node = omap->dev->of_node;
417         /* Differentiate between OMAP5 and AM437x.
418          * For OMAP5(ES2.0) and AM437x wrapper revision is same  even
419          * though there are changes in wrapper register offsets.
420          * Using dt compatible to differentiate  AM437x.
421          */
423         if (of_device_is_compatible(node, "ti,am437x-dwc3")) {
424                 omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET;
425                 omap->irq0_offset = USBOTGSS_IRQ0_OFFSET;
426                 omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET;
427                 omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET;
428                 omap->debug_offset = USBOTGSS_DEBUG_OFFSET;
429         }
432 static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap)
434         u32                     reg;
435         struct device_node      *node = omap->dev->of_node;
436         int                     utmi_mode = 0;
438         reg = dwc3_omap_read_utmi_status(omap);
440         of_property_read_u32(node, "utmi-mode", &utmi_mode);
442         switch (utmi_mode) {
443         case DWC3_OMAP_UTMI_MODE_SW:
444                 reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
445                 break;
446         case DWC3_OMAP_UTMI_MODE_HW:
447                 reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
448                 break;
449         default:
450                 dev_dbg(omap->dev, "UNKNOWN utmi mode %d\n", utmi_mode);
451         }
453         dwc3_omap_write_utmi_status(omap, reg);
456 static int dwc3_omap_extcon_register(struct dwc3_omap *omap)
458         int                     ret;
459         struct device_node      *node = omap->dev->of_node;
460         struct extcon_dev       *edev;
462         if (of_property_read_bool(node, "extcon")) {
463                 edev = extcon_get_edev_by_phandle(omap->dev, 0);
464                 if (IS_ERR(edev)) {
465                         dev_vdbg(omap->dev, "couldn't get extcon device\n");
466                         return -EPROBE_DEFER;
467                 }
469                 omap->vbus_nb.notifier_call = dwc3_omap_vbus_notifier;
470                 ret = extcon_register_interest(&omap->extcon_vbus_dev,
471                                                edev->name, "USB",
472                                                &omap->vbus_nb);
473                 if (ret < 0) {
474                         omap->id_detect_only = 1;
475                         dev_vdbg(omap->dev, "failed to register notifier for USB\n");
476                 }
478                 omap->id_nb.notifier_call = dwc3_omap_id_notifier;
479                 ret = extcon_register_interest(&omap->extcon_id_dev,
480                                                edev->name, "USB-HOST",
481                                                &omap->id_nb);
482                 if (ret < 0)
483                         dev_vdbg(omap->dev, "failed to register notifier for USB-HOST\n");
486                 if (extcon_get_cable_state(edev, "USB") == true)
487                         dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
488                 if (extcon_get_cable_state(edev, "USB-HOST") == true)
489                         dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
490                 else if (omap->id_detect_only)
491                         dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
492         }
494         return 0;
497 static int dwc3_omap_probe(struct platform_device *pdev)
499         struct device_node      *node = pdev->dev.of_node;
501         struct dwc3_omap        *omap;
502         struct resource         *res;
503         struct device           *dev = &pdev->dev;
504         struct regulator        *vbus_reg = NULL;
506         int                     ret;
507         int                     irq;
509         u32                     reg;
511         void __iomem            *base;
513         if (!node) {
514                 dev_err(dev, "device node not found\n");
515                 return -EINVAL;
516         }
518         omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
519         if (!omap) {
520                 dev_err(dev, "not enough memory\n");
521                 return -ENOMEM;
522         }
524         platform_set_drvdata(pdev, omap);
526         irq = platform_get_irq(pdev, 0);
527         if (irq < 0) {
528                 dev_err(dev, "missing IRQ resource\n");
529                 return -EINVAL;
530         }
532         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
533         base = devm_ioremap_resource(dev, res);
534         if (IS_ERR(base))
535                 return PTR_ERR(base);
537         if (of_property_read_bool(node, "vbus-supply")) {
538                 vbus_reg = devm_regulator_get(dev, "vbus");
539                 if (IS_ERR(vbus_reg)) {
540                         dev_err(dev, "vbus init failed\n");
541                         return PTR_ERR(vbus_reg);
542                 }
543         }
545         omap->dev       = dev;
546         omap->irq       = irq;
547         omap->base      = base;
548         omap->vbus_reg  = vbus_reg;
549         dev->dma_mask   = &dwc3_omap_dma_mask;
551         pm_runtime_enable(dev);
552         ret = pm_runtime_get_sync(dev);
553         if (ret < 0) {
554                 dev_err(dev, "get_sync failed with err %d\n", ret);
555                 goto err0;
556         }
558         dwc3_omap_map_offset(omap);
559         dwc3_omap_set_utmi_mode(omap);
561         /* check the DMA Status */
562         reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);
563         omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);
565         ret = devm_request_irq(dev, omap->irq, dwc3_omap_interrupt, IRQF_SHARED,
566                                "dwc3-omap", omap);
567         if (ret) {
568                 dev_err(dev, "failed to request IRQ #%d --> %d\n",
569                                 omap->irq, ret);
570                 goto err1;
571         }
573         dwc3_omap_enable_irqs(omap);
575         ret = dwc3_omap_extcon_register(omap);
576         if (ret < 0)
577                 goto err2;
579         ret = of_platform_populate(node, NULL, NULL, dev);
580         if (ret) {
581                 dev_err(&pdev->dev, "failed to create dwc3 core\n");
582                 goto err3;
583         }
585         return 0;
587 err3:
588         if (omap->extcon_vbus_dev.edev)
589                 extcon_unregister_interest(&omap->extcon_vbus_dev);
590         if (omap->extcon_id_dev.edev)
591                 extcon_unregister_interest(&omap->extcon_id_dev);
593 err2:
594         dwc3_omap_disable_irqs(omap);
596 err1:
597         pm_runtime_put_sync(dev);
599 err0:
600         pm_runtime_disable(dev);
602         return ret;
605 static int dwc3_omap_remove(struct platform_device *pdev)
607         struct dwc3_omap        *omap = platform_get_drvdata(pdev);
609         if (omap->extcon_vbus_dev.edev)
610                 extcon_unregister_interest(&omap->extcon_vbus_dev);
611         if (omap->extcon_id_dev.edev)
612                 extcon_unregister_interest(&omap->extcon_id_dev);
613         dwc3_omap_disable_irqs(omap);
614         device_for_each_child(&pdev->dev, NULL, dwc3_omap_remove_core);
615         pm_runtime_put_sync(&pdev->dev);
616         pm_runtime_disable(&pdev->dev);
618         return 0;
621 static const struct of_device_id of_dwc3_match[] = {
622         {
623                 .compatible =   "ti,dwc3"
624         },
625         {
626                 .compatible =   "ti,am437x-dwc3"
627         },
628         { },
629 };
630 MODULE_DEVICE_TABLE(of, of_dwc3_match);
632 #ifdef CONFIG_PM_SLEEP
633 static int dwc3_omap_suspend(struct device *dev)
635         struct dwc3_omap        *omap = dev_get_drvdata(dev);
637         omap->utmi_otg_status = dwc3_omap_read_utmi_status(omap);
638         dwc3_omap_disable_irqs(omap);
640         pinctrl_pm_select_sleep_state(dev);
641         return 0;
644 static int dwc3_omap_resume(struct device *dev)
646         struct dwc3_omap        *omap = dev_get_drvdata(dev);
648         pinctrl_pm_select_default_state(dev);
650         pm_runtime_disable(dev);
651         pm_runtime_set_active(dev);
652         pm_runtime_enable(dev);
654         dwc3_omap_write_utmi_status(omap, omap->utmi_otg_status);
655         dwc3_omap_enable_irqs(omap);
656         return 0;
659 static const struct dev_pm_ops dwc3_omap_dev_pm_ops = {
660         SET_SYSTEM_SLEEP_PM_OPS(dwc3_omap_suspend, dwc3_omap_resume)
661 };
663 #define DEV_PM_OPS      (&dwc3_omap_dev_pm_ops)
664 #else
665 #define DEV_PM_OPS      NULL
666 #endif /* CONFIG_PM_SLEEP */
668 static struct platform_driver dwc3_omap_driver = {
669         .probe          = dwc3_omap_probe,
670         .remove         = dwc3_omap_remove,
671         .driver         = {
672                 .name   = "omap-dwc3",
673                 .of_match_table = of_dwc3_match,
674                 .pm     = DEV_PM_OPS,
675         },
676 };
678 module_platform_driver(dwc3_omap_driver);
680 MODULE_ALIAS("platform:omap-dwc3");
681 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
682 MODULE_LICENSE("GPL v2");
683 MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");