96b4c46cbbd2925063b6b71c42ca00e7742f4d7b
[android-sdk/kernel-video.git] / drivers / usb / dwc3 / dwc3-omap.c
1 /**
2  * dwc3-omap.c - OMAP Specific Glue layer
3  *
4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5  *
6  * Authors: Felipe Balbi <balbi@ti.com>,
7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8  *
9  * This program is free software: you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2  of
11  * the License as published by the Free Software Foundation.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  */
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/slab.h>
22 #include <linux/interrupt.h>
23 #include <linux/platform_device.h>
24 #include <linux/platform_data/dwc3-omap.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/ioport.h>
28 #include <linux/io.h>
29 #include <linux/of.h>
30 #include <linux/of_platform.h>
31 #include <linux/extcon.h>
32 #include <linux/regulator/consumer.h>
34 #include <linux/usb/otg.h>
35 #include <linux/usb/drd.h>
37 /*
38  * All these registers belong to OMAP's Wrapper around the
39  * DesignWare USB3 Core.
40  */
42 #define USBOTGSS_REVISION                       0x0000
43 #define USBOTGSS_SYSCONFIG                      0x0010
44 #define USBOTGSS_IRQ_EOI                        0x0020
45 #define USBOTGSS_EOI_OFFSET                     0x0008
46 #define USBOTGSS_IRQSTATUS_RAW_0                0x0024
47 #define USBOTGSS_IRQSTATUS_0                    0x0028
48 #define USBOTGSS_IRQENABLE_SET_0                0x002c
49 #define USBOTGSS_IRQENABLE_CLR_0                0x0030
50 #define USBOTGSS_IRQ0_OFFSET                    0x0004
51 #define USBOTGSS_IRQSTATUS_RAW_1                0x0030
52 #define USBOTGSS_IRQSTATUS_1                    0x0034
53 #define USBOTGSS_IRQENABLE_SET_1                0x0038
54 #define USBOTGSS_IRQENABLE_CLR_1                0x003c
55 #define USBOTGSS_IRQSTATUS_RAW_2                0x0040
56 #define USBOTGSS_IRQSTATUS_2                    0x0044
57 #define USBOTGSS_IRQENABLE_SET_2                0x0048
58 #define USBOTGSS_IRQENABLE_CLR_2                0x004c
59 #define USBOTGSS_IRQSTATUS_RAW_3                0x0050
60 #define USBOTGSS_IRQSTATUS_3                    0x0054
61 #define USBOTGSS_IRQENABLE_SET_3                0x0058
62 #define USBOTGSS_IRQENABLE_CLR_3                0x005c
63 #define USBOTGSS_IRQSTATUS_EOI_MISC             0x0030
64 #define USBOTGSS_IRQSTATUS_RAW_MISC             0x0034
65 #define USBOTGSS_IRQSTATUS_MISC                 0x0038
66 #define USBOTGSS_IRQENABLE_SET_MISC             0x003c
67 #define USBOTGSS_IRQENABLE_CLR_MISC             0x0040
68 #define USBOTGSS_IRQMISC_OFFSET                 0x03fc
69 #define USBOTGSS_UTMI_OTG_CTRL                  0x0080
70 #define USBOTGSS_UTMI_OTG_STATUS                0x0084
71 #define USBOTGSS_UTMI_OTG_OFFSET                0x0480
72 #define USBOTGSS_TXFIFO_DEPTH                   0x0508
73 #define USBOTGSS_RXFIFO_DEPTH                   0x050c
74 #define USBOTGSS_MMRAM_OFFSET                   0x0100
75 #define USBOTGSS_FLADJ                          0x0104
76 #define USBOTGSS_DEBUG_CFG                      0x0108
77 #define USBOTGSS_DEBUG_DATA                     0x010c
78 #define USBOTGSS_DEV_EBC_EN                     0x0110
79 #define USBOTGSS_DEBUG_OFFSET                   0x0600
81 /* SYSCONFIG REGISTER */
82 #define USBOTGSS_SYSCONFIG_DMADISABLE           (1 << 16)
84 /* IRQ_EOI REGISTER */
85 #define USBOTGSS_IRQ_EOI_LINE_NUMBER            (1 << 0)
87 /* IRQS0 BITS */
88 #define USBOTGSS_IRQO_COREIRQ_ST                (1 << 0)
90 /* IRQMISC BITS */
91 #define USBOTGSS_IRQMISC_DMADISABLECLR          (1 << 17)
92 #define USBOTGSS_IRQMISC_OEVT                   (1 << 16)
93 #define USBOTGSS_IRQMISC_DRVVBUS_RISE           (1 << 13)
94 #define USBOTGSS_IRQMISC_CHRGVBUS_RISE          (1 << 12)
95 #define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE       (1 << 11)
96 #define USBOTGSS_IRQMISC_IDPULLUP_RISE          (1 << 8)
97 #define USBOTGSS_IRQMISC_DRVVBUS_FALL           (1 << 5)
98 #define USBOTGSS_IRQMISC_CHRGVBUS_FALL          (1 << 4)
99 #define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL               (1 << 3)
100 #define USBOTGSS_IRQMISC_IDPULLUP_FALL          (1 << 0)
102 /* UTMI_OTG_CTRL REGISTER */
103 #define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS          (1 << 5)
104 #define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS         (1 << 4)
105 #define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS      (1 << 3)
106 #define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP         (1 << 0)
108 /* UTMI_OTG_STATUS REGISTER */
109 #define USBOTGSS_UTMI_OTG_STATUS_SW_MODE        (1 << 31)
110 #define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT   (1 << 9)
111 #define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8)
112 #define USBOTGSS_UTMI_OTG_STATUS_IDDIG          (1 << 4)
113 #define USBOTGSS_UTMI_OTG_STATUS_SESSEND        (1 << 3)
114 #define USBOTGSS_UTMI_OTG_STATUS_SESSVALID      (1 << 2)
115 #define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID      (1 << 1)
117 struct dwc3_omap {
118         struct device           *dev;
120         int                     irq;
121         void __iomem            *base;
123         u32                     utmi_otg_status;
124         u32                     utmi_otg_offset;
125         u32                     irqmisc_offset;
126         u32                     irq_eoi_offset;
127         u32                     debug_offset;
128         u32                     irq0_offset;
130         u32                     dma_status:1;
131         u32                     id_detect_only:1;
133         struct extcon_specific_cable_nb extcon_vbus_dev;
134         struct extcon_specific_cable_nb extcon_id_dev;
135         struct notifier_block   vbus_nb;
136         struct notifier_block   id_nb;
138         struct regulator        *vbus_reg;
139 };
141 static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset)
143         return readl(base + offset);
146 static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
148         writel(value, base + offset);
151 static u32 dwc3_omap_read_utmi_status(struct dwc3_omap *omap)
153         return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS +
154                                                         omap->utmi_otg_offset);
157 static void dwc3_omap_write_utmi_status(struct dwc3_omap *omap, u32 value)
159         dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS +
160                                         omap->utmi_otg_offset, value);
164 static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap)
166         return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0 -
167                                                 omap->irq0_offset);
170 static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value)
172         dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 -
173                                                 omap->irq0_offset, value);
177 static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap)
179         return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_MISC +
180                                                 omap->irqmisc_offset);
183 static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value)
185         dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC +
186                                         omap->irqmisc_offset, value);
190 static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value)
192         dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC +
193                                                 omap->irqmisc_offset, value);
197 static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value)
199         dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 -
200                                                 omap->irq0_offset, value);
203 static void dwc3_omap_write_irqmisc_clr(struct dwc3_omap *omap, u32 value)
205         dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_MISC +
206                                                 omap->irqmisc_offset, value);
209 static void dwc3_omap_write_irq0_clr(struct dwc3_omap *omap, u32 value)
211         dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_0 -
212                                                 omap->irq0_offset, value);
215 static void dwc3_omap_set_mailbox(struct dwc3_omap *omap,
216         enum omap_dwc3_vbus_id_status status)
218         int     ret;
219         u32     val;
221         switch (status) {
222         case OMAP_DWC3_ID_GROUND:
223                 dev_dbg(omap->dev, "ID GND\n");
225                 if (omap->vbus_reg) {
226                         ret = regulator_enable(omap->vbus_reg);
227                         if (ret) {
228                                 dev_dbg(omap->dev, "regulator enable failed\n");
229                                 return;
230                         }
231                 }
233                 val = dwc3_omap_read_utmi_status(omap);
234                 val &= ~(USBOTGSS_UTMI_OTG_STATUS_IDDIG
235                                 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
236                                 | USBOTGSS_UTMI_OTG_STATUS_SESSEND);
237                 val |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID
238                                 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
239                 dwc3_omap_write_utmi_status(omap, val);
240                 break;
242         case OMAP_DWC3_VBUS_VALID:
243                 dev_dbg(omap->dev, "VBUS Connect\n");
245                 val = dwc3_omap_read_utmi_status(omap);
246                 val &= ~USBOTGSS_UTMI_OTG_STATUS_SESSEND;
247                 val |= USBOTGSS_UTMI_OTG_STATUS_IDDIG
248                                 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
249                                 | USBOTGSS_UTMI_OTG_STATUS_SESSVALID
250                                 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
251                 dwc3_omap_write_utmi_status(omap, val);
252                 break;
254         case OMAP_DWC3_ID_FLOAT:
255                 if (omap->vbus_reg)
256                         regulator_disable(omap->vbus_reg);
258         case OMAP_DWC3_VBUS_OFF:
259                 dev_dbg(omap->dev, "VBUS Disconnect\n");
261                 val = dwc3_omap_read_utmi_status(omap);
262                 val &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSVALID
263                                 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
264                                 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT);
265                 val |= USBOTGSS_UTMI_OTG_STATUS_SESSEND
266                                 | USBOTGSS_UTMI_OTG_STATUS_IDDIG;
267                 dwc3_omap_write_utmi_status(omap, val);
268                 break;
270         default:
271                 dev_dbg(omap->dev, "invalid state\n");
272         }
275 int dwc3_omap_usbvbus_id_handler(struct device *dev,
276         enum omap_dwc3_vbus_id_status status)
278         struct dwc3_omap        *omap;
279         struct platform_device  *pdev;
281         if (!dev)
282                 return -ENODEV;
284         dev_dbg(omap->dev, "VBUS Connect\n");
286         pdev = to_platform_device(dev);
287         omap =  platform_get_drvdata(pdev);
288         if (!omap)
289                 return -ENODEV;
291         dwc3_omap_set_mailbox(omap, status);
293         return 0;
295 EXPORT_SYMBOL(dwc3_omap_usbvbus_id_handler);
297 static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
299         struct dwc3_omap        *omap = _omap;
300         u32                     reg;
302         reg = dwc3_omap_read_irqmisc_status(omap);
304         if (reg & USBOTGSS_IRQMISC_DMADISABLECLR) {
305                 dev_dbg(omap->dev, "DMA Disable was Cleared\n");
306                 omap->dma_status = false;
307         }
309         if (reg & USBOTGSS_IRQMISC_OEVT)
310                 dev_dbg(omap->dev, "OTG Event\n");
312         if (reg & USBOTGSS_IRQMISC_DRVVBUS_RISE)
313                 dev_dbg(omap->dev, "DRVVBUS Rise\n");
315         if (reg & USBOTGSS_IRQMISC_CHRGVBUS_RISE)
316                 dev_dbg(omap->dev, "CHRGVBUS Rise\n");
318         if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_RISE)
319                 dev_dbg(omap->dev, "DISCHRGVBUS Rise\n");
321         if (reg & USBOTGSS_IRQMISC_IDPULLUP_RISE)
322                 dev_dbg(omap->dev, "IDPULLUP Rise\n");
324         if (reg & USBOTGSS_IRQMISC_DRVVBUS_FALL)
325                 dev_dbg(omap->dev, "DRVVBUS Fall\n");
327         if (reg & USBOTGSS_IRQMISC_CHRGVBUS_FALL)
328                 dev_dbg(omap->dev, "CHRGVBUS Fall\n");
330         if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_FALL)
331                 dev_dbg(omap->dev, "DISCHRGVBUS Fall\n");
333         if (reg & USBOTGSS_IRQMISC_IDPULLUP_FALL)
334                 dev_dbg(omap->dev, "IDPULLUP Fall\n");
336         dwc3_omap_write_irqmisc_status(omap, reg);
338         reg = dwc3_omap_read_irq0_status(omap);
340         dwc3_omap_write_irq0_status(omap, reg);
342         return IRQ_HANDLED;
345 static int dwc3_omap_remove_core(struct device *dev, void *c)
347         struct platform_device *pdev = to_platform_device(dev);
349         of_device_unregister(pdev);
351         return 0;
354 static void dwc3_omap_enable_irqs(struct dwc3_omap *omap)
356         u32                     reg;
358         /* enable all IRQs */
359         reg = USBOTGSS_IRQO_COREIRQ_ST;
360         dwc3_omap_write_irq0_set(omap, reg);
362         reg = (USBOTGSS_IRQMISC_OEVT |
363                         USBOTGSS_IRQMISC_DRVVBUS_RISE |
364                         USBOTGSS_IRQMISC_CHRGVBUS_RISE |
365                         USBOTGSS_IRQMISC_DISCHRGVBUS_RISE |
366                         USBOTGSS_IRQMISC_IDPULLUP_RISE |
367                         USBOTGSS_IRQMISC_DRVVBUS_FALL |
368                         USBOTGSS_IRQMISC_CHRGVBUS_FALL |
369                         USBOTGSS_IRQMISC_DISCHRGVBUS_FALL |
370                         USBOTGSS_IRQMISC_IDPULLUP_FALL);
372         dwc3_omap_write_irqmisc_set(omap, reg);
375 static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)
377         u32                     reg;
379         /* disable all IRQs */
380         reg = USBOTGSS_IRQO_COREIRQ_ST;
381         dwc3_omap_write_irq0_clr(omap, reg);
383         reg = (USBOTGSS_IRQMISC_OEVT |
384                         USBOTGSS_IRQMISC_DRVVBUS_RISE |
385                         USBOTGSS_IRQMISC_CHRGVBUS_RISE |
386                         USBOTGSS_IRQMISC_DISCHRGVBUS_RISE |
387                         USBOTGSS_IRQMISC_IDPULLUP_RISE |
388                         USBOTGSS_IRQMISC_DRVVBUS_FALL |
389                         USBOTGSS_IRQMISC_CHRGVBUS_FALL |
390                         USBOTGSS_IRQMISC_DISCHRGVBUS_FALL |
391                         USBOTGSS_IRQMISC_IDPULLUP_FALL);
393         dwc3_omap_write_irqmisc_clr(omap, reg);
396 static u64 dwc3_omap_dma_mask = DMA_BIT_MASK(32);
398 static int dwc3_omap_id_notifier(struct notifier_block *nb,
399         unsigned long event, void *ptr)
401         struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, id_nb);
403         if (event) {
404                 if (omap->id_detect_only)
405                         dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF);
406                 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
407         } else {
408                 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT);
409                 if (omap->id_detect_only)
410                         dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
411         }
413         return NOTIFY_DONE;
416 static int dwc3_omap_vbus_notifier(struct notifier_block *nb,
417         unsigned long event, void *ptr)
419         struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, vbus_nb);
421         if (event)
422                 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
423         else
424                 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF);
426         return NOTIFY_DONE;
429 static void dwc3_omap_map_offset(struct dwc3_omap *omap)
431         struct device_node      *node = omap->dev->of_node;
433         /* Differentiate between OMAP5 and AM437x.
434          * For OMAP5(ES2.0) and AM437x wrapper revision is same  even
435          * though there are changes in wrapper register offsets.
436          * Using dt compatible to differentiate  AM437x.
437          */
439         if (of_device_is_compatible(node, "ti,am437x-dwc3")) {
440                 omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET;
441                 omap->irq0_offset = USBOTGSS_IRQ0_OFFSET;
442                 omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET;
443                 omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET;
444                 omap->debug_offset = USBOTGSS_DEBUG_OFFSET;
445         }
448 static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap)
450         u32                     reg;
451         struct device_node      *node = omap->dev->of_node;
452         int                     utmi_mode = 0;
454         reg = dwc3_omap_read_utmi_status(omap);
456         of_property_read_u32(node, "utmi-mode", &utmi_mode);
458         switch (utmi_mode) {
459         case DWC3_OMAP_UTMI_MODE_SW:
460                 reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
461                 break;
462         case DWC3_OMAP_UTMI_MODE_HW:
463                 reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
464                 break;
465         default:
466                 dev_dbg(omap->dev, "UNKNOWN utmi mode %d\n", utmi_mode);
467         }
469         dwc3_omap_write_utmi_status(omap, reg);
472 static int dwc3_omap_extcon_register(struct dwc3_omap *omap)
474         int                     ret;
475         struct device_node      *node = omap->dev->of_node;
476         struct extcon_dev       *edev;
478         if (of_property_read_bool(node, "extcon")) {
479                 edev = extcon_get_edev_by_phandle(omap->dev, 0);
480                 if (IS_ERR(edev)) {
481                         dev_vdbg(omap->dev, "couldn't get extcon device\n");
482                         return -EPROBE_DEFER;
483                 }
485                 omap->vbus_nb.notifier_call = dwc3_omap_vbus_notifier;
486                 ret = extcon_register_interest(&omap->extcon_vbus_dev,
487                                                edev->name, "USB",
488                                                &omap->vbus_nb);
489                 if (ret < 0) {
490                         omap->id_detect_only = 1;
491                         dev_vdbg(omap->dev, "failed to register notifier for USB\n");
492                 }
494                 omap->id_nb.notifier_call = dwc3_omap_id_notifier;
495                 ret = extcon_register_interest(&omap->extcon_id_dev,
496                                                edev->name, "USB-HOST",
497                                                &omap->id_nb);
498                 if (ret < 0)
499                         dev_vdbg(omap->dev, "failed to register notifier for USB-HOST\n");
502                 if (extcon_get_cable_state(edev, "USB") == true)
503                         dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
504                 if (extcon_get_cable_state(edev, "USB-HOST") == true)
505                         dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
506                 else if (omap->id_detect_only)
507                         dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
508         }
510         return 0;
513 static int dwc3_omap_probe(struct platform_device *pdev)
515         struct device_node      *node = pdev->dev.of_node;
517         struct dwc3_omap        *omap;
518         struct resource         *res;
519         struct device           *dev = &pdev->dev;
520         struct regulator        *vbus_reg = NULL;
522         int                     ret;
523         int                     irq;
525         u32                     reg;
527         void __iomem            *base;
529         if (!node) {
530                 dev_err(dev, "device node not found\n");
531                 return -EINVAL;
532         }
534         omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
535         if (!omap) {
536                 dev_err(dev, "not enough memory\n");
537                 return -ENOMEM;
538         }
540         platform_set_drvdata(pdev, omap);
542         irq = platform_get_irq(pdev, 0);
543         if (irq < 0) {
544                 dev_err(dev, "missing IRQ resource\n");
545                 return -EINVAL;
546         }
548         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
549         base = devm_ioremap_resource(dev, res);
550         if (IS_ERR(base))
551                 return PTR_ERR(base);
553         if (of_property_read_bool(node, "vbus-supply")) {
554                 vbus_reg = devm_regulator_get(dev, "vbus");
555                 if (IS_ERR(vbus_reg)) {
556                         dev_err(dev, "vbus init failed\n");
557                         return PTR_ERR(vbus_reg);
558                 }
559         }
561         omap->dev       = dev;
562         omap->irq       = irq;
563         omap->base      = base;
564         omap->vbus_reg  = vbus_reg;
565         dev->dma_mask   = &dwc3_omap_dma_mask;
567         pm_runtime_enable(dev);
568         ret = pm_runtime_get_sync(dev);
569         if (ret < 0) {
570                 dev_err(dev, "get_sync failed with err %d\n", ret);
571                 goto err0;
572         }
574         dwc3_omap_map_offset(omap);
575         dwc3_omap_set_utmi_mode(omap);
577         /* check the DMA Status */
578         reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);
579         omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);
581         ret = devm_request_irq(dev, omap->irq, dwc3_omap_interrupt, IRQF_SHARED,
582                                "dwc3-omap", omap);
583         if (ret) {
584                 dev_err(dev, "failed to request IRQ #%d --> %d\n",
585                                 omap->irq, ret);
586                 goto err1;
587         }
589         dwc3_omap_enable_irqs(omap);
591         ret = dwc3_omap_extcon_register(omap);
592         if (ret < 0)
593                 goto err2;
595         ret = of_platform_populate(node, NULL, NULL, dev);
596         if (ret) {
597                 dev_err(&pdev->dev, "failed to create dwc3 core\n");
598                 goto err3;
599         }
601         return 0;
603 err3:
604         if (omap->extcon_vbus_dev.edev)
605                 extcon_unregister_interest(&omap->extcon_vbus_dev);
606         if (omap->extcon_id_dev.edev)
607                 extcon_unregister_interest(&omap->extcon_id_dev);
609 err2:
610         dwc3_omap_disable_irqs(omap);
612 err1:
613         pm_runtime_put_sync(dev);
615 err0:
616         pm_runtime_disable(dev);
618         return ret;
621 static int dwc3_omap_remove(struct platform_device *pdev)
623         struct dwc3_omap        *omap = platform_get_drvdata(pdev);
625         if (omap->extcon_vbus_dev.edev)
626                 extcon_unregister_interest(&omap->extcon_vbus_dev);
627         if (omap->extcon_id_dev.edev)
628                 extcon_unregister_interest(&omap->extcon_id_dev);
629         dwc3_omap_disable_irqs(omap);
630         device_for_each_child(&pdev->dev, NULL, dwc3_omap_remove_core);
631         pm_runtime_put_sync(&pdev->dev);
632         pm_runtime_disable(&pdev->dev);
634         return 0;
637 static const struct of_device_id of_dwc3_match[] = {
638         {
639                 .compatible =   "ti,dwc3"
640         },
641         {
642                 .compatible =   "ti,am437x-dwc3"
643         },
644         { },
645 };
646 MODULE_DEVICE_TABLE(of, of_dwc3_match);
648 #ifdef CONFIG_PM_SLEEP
649 static int dwc3_omap_suspend(struct device *dev)
651         struct dwc3_omap        *omap = dev_get_drvdata(dev);
653         omap->utmi_otg_status = dwc3_omap_read_utmi_status(omap);
654         dwc3_omap_disable_irqs(omap);
656         pinctrl_pm_select_sleep_state(dev);
657         return 0;
660 static int dwc3_omap_resume(struct device *dev)
662         struct dwc3_omap        *omap = dev_get_drvdata(dev);
664         pinctrl_pm_select_default_state(dev);
666         pm_runtime_disable(dev);
667         pm_runtime_set_active(dev);
668         pm_runtime_enable(dev);
670         dwc3_omap_write_utmi_status(omap, omap->utmi_otg_status);
671         dwc3_omap_enable_irqs(omap);
672         return 0;
675 static const struct dev_pm_ops dwc3_omap_dev_pm_ops = {
676         SET_SYSTEM_SLEEP_PM_OPS(dwc3_omap_suspend, dwc3_omap_resume)
677 };
679 #define DEV_PM_OPS      (&dwc3_omap_dev_pm_ops)
680 #else
681 #define DEV_PM_OPS      NULL
682 #endif /* CONFIG_PM_SLEEP */
684 static struct platform_driver dwc3_omap_driver = {
685         .probe          = dwc3_omap_probe,
686         .remove         = dwc3_omap_remove,
687         .driver         = {
688                 .name   = "omap-dwc3",
689                 .of_match_table = of_dwc3_match,
690                 .pm     = DEV_PM_OPS,
691         },
692 };
694 module_platform_driver(dwc3_omap_driver);
696 MODULE_ALIAS("platform:omap-dwc3");
697 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
698 MODULE_LICENSE("GPL v2");
699 MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");