1 /*
2 * Copyright (C) 2011 Texas Instruments
3 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
18 #define DSS_SUBSYS_NAME "APPLY"
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/slab.h>
23 #include <linux/spinlock.h>
24 #include <linux/jiffies.h>
26 #include <video/omapdss.h>
28 #include "dss.h"
29 #include "dss_features.h"
30 #include "dispc-compat.h"
32 /*
33 * We have 4 levels of cache for the dispc settings. First two are in SW and
34 * the latter two in HW.
35 *
36 * set_info()
37 * v
38 * +--------------------+
39 * | user_info |
40 * +--------------------+
41 * v
42 * apply()
43 * v
44 * +--------------------+
45 * | info |
46 * +--------------------+
47 * v
48 * write_regs()
49 * v
50 * +--------------------+
51 * | shadow registers |
52 * +--------------------+
53 * v
54 * VFP or lcd/digit_enable
55 * v
56 * +--------------------+
57 * | registers |
58 * +--------------------+
59 */
61 struct ovl_priv_data {
63 bool user_info_dirty;
64 struct omap_overlay_info user_info;
66 bool info_dirty;
67 struct omap_overlay_info info;
69 bool shadow_info_dirty;
71 bool extra_info_dirty;
72 bool shadow_extra_info_dirty;
74 bool enabled;
75 u32 fifo_low, fifo_high;
77 /*
78 * True if overlay is to be enabled. Used to check and calculate configs
79 * for the overlay before it is enabled in the HW.
80 */
81 bool enabling;
82 };
84 struct mgr_priv_data {
86 bool user_info_dirty;
87 struct omap_overlay_manager_info user_info;
89 bool info_dirty;
90 struct omap_overlay_manager_info info;
92 bool shadow_info_dirty;
94 /* If true, GO bit is up and shadow registers cannot be written.
95 * Never true for manual update displays */
96 bool busy;
98 /* If true, dispc output is enabled */
99 bool updating;
101 /* If true, a display is enabled using this manager */
102 bool enabled;
104 bool extra_info_dirty;
105 bool shadow_extra_info_dirty;
107 struct omap_video_timings timings;
108 struct dss_lcd_mgr_config lcd_config;
110 void (*framedone_handler)(void *);
111 void *framedone_handler_data;
112 };
114 static struct {
115 struct ovl_priv_data ovl_priv_data_array[MAX_DSS_OVERLAYS];
116 struct mgr_priv_data mgr_priv_data_array[MAX_DSS_MANAGERS];
118 bool irq_enabled;
119 } dss_data;
121 /* protects dss_data */
122 static spinlock_t data_lock;
123 /* lock for blocking functions */
124 static DEFINE_MUTEX(apply_lock);
125 static DECLARE_COMPLETION(extra_updated_completion);
127 static void dss_register_vsync_isr(void);
129 static struct ovl_priv_data *get_ovl_priv(struct omap_overlay *ovl)
130 {
131 return &dss_data.ovl_priv_data_array[ovl->id];
132 }
134 static struct mgr_priv_data *get_mgr_priv(struct omap_overlay_manager *mgr)
135 {
136 return &dss_data.mgr_priv_data_array[mgr->id];
137 }
139 static void apply_init_priv(void)
140 {
141 const int num_ovls = dss_feat_get_num_ovls();
142 struct mgr_priv_data *mp;
143 int i;
145 spin_lock_init(&data_lock);
147 for (i = 0; i < num_ovls; ++i) {
148 struct ovl_priv_data *op;
150 op = &dss_data.ovl_priv_data_array[i];
152 op->info.color_mode = OMAP_DSS_COLOR_RGB16;
153 op->info.rotation_type = OMAP_DSS_ROT_DMA;
155 op->info.global_alpha = 255;
157 switch (i) {
158 case 0:
159 op->info.zorder = 0;
160 break;
161 case 1:
162 op->info.zorder =
163 dss_has_feature(FEAT_ALPHA_FREE_ZORDER) ? 3 : 0;
164 break;
165 case 2:
166 op->info.zorder =
167 dss_has_feature(FEAT_ALPHA_FREE_ZORDER) ? 2 : 0;
168 break;
169 case 3:
170 op->info.zorder =
171 dss_has_feature(FEAT_ALPHA_FREE_ZORDER) ? 1 : 0;
172 break;
173 }
175 op->user_info = op->info;
176 }
178 /*
179 * Initialize some of the lcd_config fields for TV manager, this lets
180 * us prevent checking if the manager is LCD or TV at some places
181 */
182 mp = &dss_data.mgr_priv_data_array[OMAP_DSS_CHANNEL_DIGIT];
184 mp->lcd_config.video_port_width = 24;
185 mp->lcd_config.clock_info.lck_div = 1;
186 mp->lcd_config.clock_info.pck_div = 1;
187 }
189 /*
190 * A LCD manager's stallmode decides whether it is in manual or auto update. TV
191 * manager is always auto update, stallmode field for TV manager is false by
192 * default
193 */
194 static bool ovl_manual_update(struct omap_overlay *ovl)
195 {
196 struct mgr_priv_data *mp = get_mgr_priv(ovl->manager);
198 return mp->lcd_config.stallmode;
199 }
201 static bool mgr_manual_update(struct omap_overlay_manager *mgr)
202 {
203 struct mgr_priv_data *mp = get_mgr_priv(mgr);
205 return mp->lcd_config.stallmode;
206 }
208 static int dss_check_settings_low(struct omap_overlay_manager *mgr,
209 bool applying)
210 {
211 struct omap_overlay_info *oi;
212 struct omap_overlay_manager_info *mi;
213 struct omap_overlay *ovl;
214 struct omap_overlay_info *ois[MAX_DSS_OVERLAYS];
215 struct ovl_priv_data *op;
216 struct mgr_priv_data *mp;
218 mp = get_mgr_priv(mgr);
220 if (!mp->enabled)
221 return 0;
223 if (applying && mp->user_info_dirty)
224 mi = &mp->user_info;
225 else
226 mi = &mp->info;
228 /* collect the infos to be tested into the array */
229 list_for_each_entry(ovl, &mgr->overlays, list) {
230 op = get_ovl_priv(ovl);
232 if (!op->enabled && !op->enabling)
233 oi = NULL;
234 else if (applying && op->user_info_dirty)
235 oi = &op->user_info;
236 else
237 oi = &op->info;
239 ois[ovl->id] = oi;
240 }
242 return dss_mgr_check(mgr, mi, &mp->timings, &mp->lcd_config, ois);
243 }
245 /*
246 * check manager and overlay settings using overlay_info from data->info
247 */
248 static int dss_check_settings(struct omap_overlay_manager *mgr)
249 {
250 return dss_check_settings_low(mgr, false);
251 }
253 /*
254 * check manager and overlay settings using overlay_info from ovl->info if
255 * dirty and from data->info otherwise
256 */
257 static int dss_check_settings_apply(struct omap_overlay_manager *mgr)
258 {
259 return dss_check_settings_low(mgr, true);
260 }
262 static bool need_isr(void)
263 {
264 const int num_mgrs = dss_feat_get_num_mgrs();
265 int i;
267 for (i = 0; i < num_mgrs; ++i) {
268 struct omap_overlay_manager *mgr;
269 struct mgr_priv_data *mp;
270 struct omap_overlay *ovl;
272 mgr = omap_dss_get_overlay_manager(i);
273 mp = get_mgr_priv(mgr);
275 if (!mp->enabled)
276 continue;
278 if (mgr_manual_update(mgr)) {
279 /* to catch FRAMEDONE */
280 if (mp->updating)
281 return true;
282 } else {
283 /* to catch GO bit going down */
284 if (mp->busy)
285 return true;
287 /* to write new values to registers */
288 if (mp->info_dirty)
289 return true;
291 /* to set GO bit */
292 if (mp->shadow_info_dirty)
293 return true;
295 /*
296 * NOTE: we don't check extra_info flags for disabled
297 * managers, once the manager is enabled, the extra_info
298 * related manager changes will be taken in by HW.
299 */
301 /* to write new values to registers */
302 if (mp->extra_info_dirty)
303 return true;
305 /* to set GO bit */
306 if (mp->shadow_extra_info_dirty)
307 return true;
309 list_for_each_entry(ovl, &mgr->overlays, list) {
310 struct ovl_priv_data *op;
312 op = get_ovl_priv(ovl);
314 /*
315 * NOTE: we check extra_info flags even for
316 * disabled overlays, as extra_infos need to be
317 * always written.
318 */
320 /* to write new values to registers */
321 if (op->extra_info_dirty)
322 return true;
324 /* to set GO bit */
325 if (op->shadow_extra_info_dirty)
326 return true;
328 if (!op->enabled)
329 continue;
331 /* to write new values to registers */
332 if (op->info_dirty)
333 return true;
335 /* to set GO bit */
336 if (op->shadow_info_dirty)
337 return true;
338 }
339 }
340 }
342 return false;
343 }
345 static bool need_go(struct omap_overlay_manager *mgr)
346 {
347 struct omap_overlay *ovl;
348 struct mgr_priv_data *mp;
349 struct ovl_priv_data *op;
351 mp = get_mgr_priv(mgr);
353 if (mp->shadow_info_dirty || mp->shadow_extra_info_dirty)
354 return true;
356 list_for_each_entry(ovl, &mgr->overlays, list) {
357 op = get_ovl_priv(ovl);
358 if (op->shadow_info_dirty || op->shadow_extra_info_dirty)
359 return true;
360 }
362 return false;
363 }
365 /* returns true if an extra_info field is currently being updated */
366 static bool extra_info_update_ongoing(void)
367 {
368 const int num_mgrs = dss_feat_get_num_mgrs();
369 int i;
371 for (i = 0; i < num_mgrs; ++i) {
372 struct omap_overlay_manager *mgr;
373 struct omap_overlay *ovl;
374 struct mgr_priv_data *mp;
376 mgr = omap_dss_get_overlay_manager(i);
377 mp = get_mgr_priv(mgr);
379 if (!mp->enabled)
380 continue;
382 if (!mp->updating)
383 continue;
385 if (mp->extra_info_dirty || mp->shadow_extra_info_dirty)
386 return true;
388 list_for_each_entry(ovl, &mgr->overlays, list) {
389 struct ovl_priv_data *op = get_ovl_priv(ovl);
391 if (op->extra_info_dirty || op->shadow_extra_info_dirty)
392 return true;
393 }
394 }
396 return false;
397 }
399 /* wait until no extra_info updates are pending */
400 static void wait_pending_extra_info_updates(void)
401 {
402 bool updating;
403 unsigned long flags;
404 unsigned long t;
405 int r;
407 spin_lock_irqsave(&data_lock, flags);
409 updating = extra_info_update_ongoing();
411 if (!updating) {
412 spin_unlock_irqrestore(&data_lock, flags);
413 return;
414 }
416 init_completion(&extra_updated_completion);
418 spin_unlock_irqrestore(&data_lock, flags);
420 t = msecs_to_jiffies(500);
421 r = wait_for_completion_timeout(&extra_updated_completion, t);
422 if (r == 0)
423 DSSWARN("timeout in wait_pending_extra_info_updates\n");
424 }
426 static struct omap_dss_device *dss_mgr_get_device(struct omap_overlay_manager *mgr)
427 {
428 struct omap_dss_device *dssdev;
430 dssdev = mgr->output;
431 if (dssdev == NULL)
432 return NULL;
434 while (dssdev->dst)
435 dssdev = dssdev->dst;
437 if (dssdev->driver)
438 return dssdev;
439 else
440 return NULL;
441 }
443 static struct omap_dss_device *dss_ovl_get_device(struct omap_overlay *ovl)
444 {
445 return ovl->manager ? dss_mgr_get_device(ovl->manager) : NULL;
446 }
448 static int dss_mgr_wait_for_vsync(struct omap_overlay_manager *mgr)
449 {
450 unsigned long timeout = msecs_to_jiffies(500);
451 u32 irq;
452 int r;
454 if (mgr->output == NULL)
455 return -ENODEV;
457 r = dispc_runtime_get();
458 if (r)
459 return r;
461 switch (mgr->output->id) {
462 case OMAP_DSS_OUTPUT_VENC:
463 irq = DISPC_IRQ_EVSYNC_ODD;
464 break;
465 case OMAP_DSS_OUTPUT_HDMI:
466 irq = DISPC_IRQ_EVSYNC_EVEN;
467 break;
468 default:
469 irq = dispc_mgr_get_vsync_irq(mgr->id);
470 break;
471 }
473 r = omap_dispc_wait_for_irq_interruptible_timeout(irq, timeout);
475 dispc_runtime_put();
477 return r;
478 }
480 static int dss_mgr_wait_for_go(struct omap_overlay_manager *mgr)
481 {
482 unsigned long timeout = msecs_to_jiffies(500);
483 struct mgr_priv_data *mp = get_mgr_priv(mgr);
484 u32 irq;
485 unsigned long flags;
486 int r;
487 int i;
489 spin_lock_irqsave(&data_lock, flags);
491 if (mgr_manual_update(mgr)) {
492 spin_unlock_irqrestore(&data_lock, flags);
493 return 0;
494 }
496 if (!mp->enabled) {
497 spin_unlock_irqrestore(&data_lock, flags);
498 return 0;
499 }
501 spin_unlock_irqrestore(&data_lock, flags);
503 r = dispc_runtime_get();
504 if (r)
505 return r;
507 irq = dispc_mgr_get_vsync_irq(mgr->id);
509 i = 0;
510 while (1) {
511 bool shadow_dirty, dirty;
513 spin_lock_irqsave(&data_lock, flags);
514 dirty = mp->info_dirty;
515 shadow_dirty = mp->shadow_info_dirty;
516 spin_unlock_irqrestore(&data_lock, flags);
518 if (!dirty && !shadow_dirty) {
519 r = 0;
520 break;
521 }
523 /* 4 iterations is the worst case:
524 * 1 - initial iteration, dirty = true (between VFP and VSYNC)
525 * 2 - first VSYNC, dirty = true
526 * 3 - dirty = false, shadow_dirty = true
527 * 4 - shadow_dirty = false */
528 if (i++ == 3) {
529 DSSERR("mgr(%d)->wait_for_go() not finishing\n",
530 mgr->id);
531 r = 0;
532 break;
533 }
535 r = omap_dispc_wait_for_irq_interruptible_timeout(irq, timeout);
536 if (r == -ERESTARTSYS)
537 break;
539 if (r) {
540 DSSERR("mgr(%d)->wait_for_go() timeout\n", mgr->id);
541 break;
542 }
543 }
545 dispc_runtime_put();
547 return r;
548 }
550 static int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl)
551 {
552 unsigned long timeout = msecs_to_jiffies(500);
553 struct ovl_priv_data *op;
554 struct mgr_priv_data *mp;
555 u32 irq;
556 unsigned long flags;
557 int r;
558 int i;
560 if (!ovl->manager)
561 return 0;
563 mp = get_mgr_priv(ovl->manager);
565 spin_lock_irqsave(&data_lock, flags);
567 if (ovl_manual_update(ovl)) {
568 spin_unlock_irqrestore(&data_lock, flags);
569 return 0;
570 }
572 if (!mp->enabled) {
573 spin_unlock_irqrestore(&data_lock, flags);
574 return 0;
575 }
577 spin_unlock_irqrestore(&data_lock, flags);
579 r = dispc_runtime_get();
580 if (r)
581 return r;
583 irq = dispc_mgr_get_vsync_irq(ovl->manager->id);
585 op = get_ovl_priv(ovl);
586 i = 0;
587 while (1) {
588 bool shadow_dirty, dirty;
590 spin_lock_irqsave(&data_lock, flags);
591 dirty = op->info_dirty;
592 shadow_dirty = op->shadow_info_dirty;
593 spin_unlock_irqrestore(&data_lock, flags);
595 if (!dirty && !shadow_dirty) {
596 r = 0;
597 break;
598 }
600 /* 4 iterations is the worst case:
601 * 1 - initial iteration, dirty = true (between VFP and VSYNC)
602 * 2 - first VSYNC, dirty = true
603 * 3 - dirty = false, shadow_dirty = true
604 * 4 - shadow_dirty = false */
605 if (i++ == 3) {
606 DSSERR("ovl(%d)->wait_for_go() not finishing\n",
607 ovl->id);
608 r = 0;
609 break;
610 }
612 r = omap_dispc_wait_for_irq_interruptible_timeout(irq, timeout);
613 if (r == -ERESTARTSYS)
614 break;
616 if (r) {
617 DSSERR("ovl(%d)->wait_for_go() timeout\n", ovl->id);
618 break;
619 }
620 }
622 dispc_runtime_put();
624 return r;
625 }
627 static void dss_ovl_write_regs(struct omap_overlay *ovl)
628 {
629 struct ovl_priv_data *op = get_ovl_priv(ovl);
630 struct omap_overlay_info *oi;
631 bool replication;
632 struct mgr_priv_data *mp;
633 int r;
635 DSSDBG("writing ovl %d regs\n", ovl->id);
637 if (!op->enabled || !op->info_dirty)
638 return;
640 oi = &op->info;
642 mp = get_mgr_priv(ovl->manager);
644 replication = dss_ovl_use_replication(mp->lcd_config, oi->color_mode);
646 r = dispc_ovl_setup(ovl->id, oi, replication, &mp->timings, false);
647 if (r) {
648 /*
649 * We can't do much here, as this function can be called from
650 * vsync interrupt.
651 */
652 DSSERR("dispc_ovl_setup failed for ovl %d\n", ovl->id);
654 /* This will leave fifo configurations in a nonoptimal state */
655 op->enabled = false;
656 dispc_ovl_enable(ovl->id, false);
657 return;
658 }
660 op->info_dirty = false;
661 if (mp->updating)
662 op->shadow_info_dirty = true;
663 }
665 static void dss_ovl_write_regs_extra(struct omap_overlay *ovl)
666 {
667 struct ovl_priv_data *op = get_ovl_priv(ovl);
668 struct mgr_priv_data *mp;
670 DSSDBG("writing ovl %d regs extra\n", ovl->id);
672 if (!op->extra_info_dirty)
673 return;
675 /* note: write also when op->enabled == false, so that the ovl gets
676 * disabled */
678 dispc_ovl_enable(ovl->id, op->enabled);
679 dispc_ovl_set_fifo_threshold(ovl->id, op->fifo_low, op->fifo_high);
681 mp = get_mgr_priv(ovl->manager);
683 op->extra_info_dirty = false;
684 if (mp->updating)
685 op->shadow_extra_info_dirty = true;
686 }
688 static void dss_mgr_write_regs(struct omap_overlay_manager *mgr)
689 {
690 struct mgr_priv_data *mp = get_mgr_priv(mgr);
691 struct omap_overlay *ovl;
693 DSSDBG("writing mgr %d regs\n", mgr->id);
695 if (!mp->enabled)
696 return;
698 WARN_ON(mp->busy);
700 /* Commit overlay settings */
701 list_for_each_entry(ovl, &mgr->overlays, list) {
702 dss_ovl_write_regs(ovl);
703 dss_ovl_write_regs_extra(ovl);
704 }
706 if (mp->info_dirty) {
707 dispc_mgr_setup(mgr->id, &mp->info);
709 mp->info_dirty = false;
710 if (mp->updating)
711 mp->shadow_info_dirty = true;
712 }
713 }
715 static void dss_mgr_write_regs_extra(struct omap_overlay_manager *mgr)
716 {
717 struct mgr_priv_data *mp = get_mgr_priv(mgr);
719 DSSDBG("writing mgr %d regs extra\n", mgr->id);
721 if (!mp->extra_info_dirty)
722 return;
724 if (!omapdss_skipinit() || mgr->id != OMAP_DSS_CHANNEL_LCD) {
725 dispc_mgr_set_timings(mgr->id, &mp->timings);
727 /* lcd_config parameters */
728 if (dss_mgr_is_lcd(mgr->id))
729 dispc_mgr_set_lcd_config(mgr->id, &mp->lcd_config);
730 }
732 mp->extra_info_dirty = false;
733 if (mp->updating)
734 mp->shadow_extra_info_dirty = true;
735 }
737 static void dss_write_regs(void)
738 {
739 const int num_mgrs = omap_dss_get_num_overlay_managers();
740 int i;
742 for (i = 0; i < num_mgrs; ++i) {
743 struct omap_overlay_manager *mgr;
744 struct mgr_priv_data *mp;
745 int r;
747 mgr = omap_dss_get_overlay_manager(i);
748 mp = get_mgr_priv(mgr);
750 if (!mp->enabled || mgr_manual_update(mgr) || mp->busy)
751 continue;
753 r = dss_check_settings(mgr);
754 if (r) {
755 DSSERR("cannot write registers for manager %s: "
756 "illegal configuration\n", mgr->name);
757 continue;
758 }
760 dss_mgr_write_regs(mgr);
761 dss_mgr_write_regs_extra(mgr);
762 }
763 }
765 static void dss_set_go_bits(void)
766 {
767 const int num_mgrs = omap_dss_get_num_overlay_managers();
768 int i;
770 for (i = 0; i < num_mgrs; ++i) {
771 struct omap_overlay_manager *mgr;
772 struct mgr_priv_data *mp;
774 mgr = omap_dss_get_overlay_manager(i);
775 mp = get_mgr_priv(mgr);
777 if (!mp->enabled || mgr_manual_update(mgr) || mp->busy)
778 continue;
780 if (!need_go(mgr))
781 continue;
783 mp->busy = true;
785 if (!dss_data.irq_enabled && need_isr())
786 dss_register_vsync_isr();
788 dispc_mgr_go(mgr->id);
789 }
791 }
793 static void mgr_clear_shadow_dirty(struct omap_overlay_manager *mgr)
794 {
795 struct omap_overlay *ovl;
796 struct mgr_priv_data *mp;
797 struct ovl_priv_data *op;
799 mp = get_mgr_priv(mgr);
800 mp->shadow_info_dirty = false;
801 mp->shadow_extra_info_dirty = false;
803 list_for_each_entry(ovl, &mgr->overlays, list) {
804 op = get_ovl_priv(ovl);
805 op->shadow_info_dirty = false;
806 op->shadow_extra_info_dirty = false;
807 }
808 }
810 static int dss_mgr_connect_compat(struct omap_overlay_manager *mgr,
811 struct omap_dss_device *dst)
812 {
813 return mgr->set_output(mgr, dst);
814 }
816 static void dss_mgr_disconnect_compat(struct omap_overlay_manager *mgr,
817 struct omap_dss_device *dst)
818 {
819 mgr->unset_output(mgr);
820 }
822 static void dss_mgr_start_update_compat(struct omap_overlay_manager *mgr)
823 {
824 struct mgr_priv_data *mp = get_mgr_priv(mgr);
825 unsigned long flags;
826 int r;
828 spin_lock_irqsave(&data_lock, flags);
830 WARN_ON(mp->updating);
832 r = dss_check_settings(mgr);
833 if (r) {
834 DSSERR("cannot start manual update: illegal configuration\n");
835 spin_unlock_irqrestore(&data_lock, flags);
836 return;
837 }
839 dss_mgr_write_regs(mgr);
840 dss_mgr_write_regs_extra(mgr);
842 mp->updating = true;
844 if (!dss_data.irq_enabled && need_isr())
845 dss_register_vsync_isr();
847 dispc_mgr_enable_sync(mgr->id);
849 spin_unlock_irqrestore(&data_lock, flags);
850 }
852 static void dss_apply_irq_handler(void *data, u32 mask);
854 static void dss_register_vsync_isr(void)
855 {
856 const int num_mgrs = dss_feat_get_num_mgrs();
857 u32 mask;
858 int r, i;
860 mask = 0;
861 for (i = 0; i < num_mgrs; ++i)
862 mask |= dispc_mgr_get_vsync_irq(i);
864 for (i = 0; i < num_mgrs; ++i)
865 mask |= dispc_mgr_get_framedone_irq(i);
867 r = omap_dispc_register_isr(dss_apply_irq_handler, NULL, mask);
868 WARN_ON(r);
870 dss_data.irq_enabled = true;
871 }
873 static void dss_unregister_vsync_isr(void)
874 {
875 const int num_mgrs = dss_feat_get_num_mgrs();
876 u32 mask;
877 int r, i;
879 mask = 0;
880 for (i = 0; i < num_mgrs; ++i)
881 mask |= dispc_mgr_get_vsync_irq(i);
883 for (i = 0; i < num_mgrs; ++i)
884 mask |= dispc_mgr_get_framedone_irq(i);
886 r = omap_dispc_unregister_isr(dss_apply_irq_handler, NULL, mask);
887 WARN_ON(r);
889 dss_data.irq_enabled = false;
890 }
892 static void dss_apply_irq_handler(void *data, u32 mask)
893 {
894 const int num_mgrs = dss_feat_get_num_mgrs();
895 int i;
896 bool extra_updating;
898 spin_lock(&data_lock);
900 /* clear busy, updating flags, shadow_dirty flags */
901 for (i = 0; i < num_mgrs; i++) {
902 struct omap_overlay_manager *mgr;
903 struct mgr_priv_data *mp;
905 mgr = omap_dss_get_overlay_manager(i);
906 mp = get_mgr_priv(mgr);
908 if (!mp->enabled)
909 continue;
911 mp->updating = dispc_mgr_is_enabled(i);
913 if (!mgr_manual_update(mgr)) {
914 bool was_busy = mp->busy;
915 mp->busy = dispc_mgr_go_busy(i);
917 if (was_busy && !mp->busy)
918 mgr_clear_shadow_dirty(mgr);
919 }
920 }
922 dss_write_regs();
923 dss_set_go_bits();
925 extra_updating = extra_info_update_ongoing();
926 if (!extra_updating)
927 complete_all(&extra_updated_completion);
929 /* call framedone handlers for manual update displays */
930 for (i = 0; i < num_mgrs; i++) {
931 struct omap_overlay_manager *mgr;
932 struct mgr_priv_data *mp;
934 mgr = omap_dss_get_overlay_manager(i);
935 mp = get_mgr_priv(mgr);
937 if (!mgr_manual_update(mgr) || !mp->framedone_handler)
938 continue;
940 if (mask & dispc_mgr_get_framedone_irq(i))
941 mp->framedone_handler(mp->framedone_handler_data);
942 }
944 if (!need_isr())
945 dss_unregister_vsync_isr();
947 spin_unlock(&data_lock);
948 }
950 static void omap_dss_mgr_apply_ovl(struct omap_overlay *ovl)
951 {
952 struct ovl_priv_data *op;
954 op = get_ovl_priv(ovl);
956 if (!op->user_info_dirty)
957 return;
959 op->user_info_dirty = false;
960 op->info_dirty = true;
961 op->info = op->user_info;
962 }
964 static void omap_dss_mgr_apply_mgr(struct omap_overlay_manager *mgr)
965 {
966 struct mgr_priv_data *mp;
968 mp = get_mgr_priv(mgr);
970 if (!mp->user_info_dirty)
971 return;
973 mp->user_info_dirty = false;
974 mp->info_dirty = true;
975 mp->info = mp->user_info;
976 }
978 static int omap_dss_mgr_apply(struct omap_overlay_manager *mgr)
979 {
980 unsigned long flags;
981 struct omap_overlay *ovl;
982 int r;
984 DSSDBG("omap_dss_mgr_apply(%s)\n", mgr->name);
986 spin_lock_irqsave(&data_lock, flags);
988 r = dss_check_settings_apply(mgr);
989 if (r) {
990 spin_unlock_irqrestore(&data_lock, flags);
991 DSSERR("failed to apply settings: illegal configuration.\n");
992 return r;
993 }
995 /* Configure overlays */
996 list_for_each_entry(ovl, &mgr->overlays, list)
997 omap_dss_mgr_apply_ovl(ovl);
999 /* Configure manager */
1000 omap_dss_mgr_apply_mgr(mgr);
1002 dss_write_regs();
1003 dss_set_go_bits();
1005 spin_unlock_irqrestore(&data_lock, flags);
1007 return 0;
1008 }
1010 static void dss_apply_ovl_enable(struct omap_overlay *ovl, bool enable)
1011 {
1012 struct ovl_priv_data *op;
1014 op = get_ovl_priv(ovl);
1016 if (op->enabled == enable)
1017 return;
1019 op->enabled = enable;
1020 op->extra_info_dirty = true;
1021 }
1023 static void dss_apply_ovl_fifo_thresholds(struct omap_overlay *ovl,
1024 u32 fifo_low, u32 fifo_high)
1025 {
1026 struct ovl_priv_data *op = get_ovl_priv(ovl);
1028 if (op->fifo_low == fifo_low && op->fifo_high == fifo_high)
1029 return;
1031 op->fifo_low = fifo_low;
1032 op->fifo_high = fifo_high;
1033 op->extra_info_dirty = true;
1034 }
1036 static void dss_ovl_setup_fifo(struct omap_overlay *ovl)
1037 {
1038 struct ovl_priv_data *op = get_ovl_priv(ovl);
1039 u32 fifo_low, fifo_high;
1040 bool use_fifo_merge = false;
1042 if (!op->enabled && !op->enabling)
1043 return;
1045 dispc_ovl_compute_fifo_thresholds(ovl->id, &fifo_low, &fifo_high,
1046 use_fifo_merge, ovl_manual_update(ovl));
1048 dss_apply_ovl_fifo_thresholds(ovl, fifo_low, fifo_high);
1049 }
1051 static void dss_mgr_setup_fifos(struct omap_overlay_manager *mgr)
1052 {
1053 struct omap_overlay *ovl;
1054 struct mgr_priv_data *mp;
1056 mp = get_mgr_priv(mgr);
1058 if (!mp->enabled)
1059 return;
1061 list_for_each_entry(ovl, &mgr->overlays, list)
1062 dss_ovl_setup_fifo(ovl);
1063 }
1065 static void dss_setup_fifos(void)
1066 {
1067 const int num_mgrs = omap_dss_get_num_overlay_managers();
1068 struct omap_overlay_manager *mgr;
1069 int i;
1071 for (i = 0; i < num_mgrs; ++i) {
1072 mgr = omap_dss_get_overlay_manager(i);
1073 dss_mgr_setup_fifos(mgr);
1074 }
1075 }
1077 static int dss_mgr_enable_compat(struct omap_overlay_manager *mgr)
1078 {
1079 struct mgr_priv_data *mp = get_mgr_priv(mgr);
1080 unsigned long flags;
1081 int r;
1083 mutex_lock(&apply_lock);
1085 if (mp->enabled)
1086 goto out;
1088 spin_lock_irqsave(&data_lock, flags);
1090 mp->enabled = true;
1092 r = dss_check_settings(mgr);
1093 if (r) {
1094 DSSERR("failed to enable manager %d: check_settings failed\n",
1095 mgr->id);
1096 goto err;
1097 }
1099 dss_setup_fifos();
1101 dss_write_regs();
1102 dss_set_go_bits();
1104 if (!mgr_manual_update(mgr))
1105 mp->updating = true;
1107 if (!dss_data.irq_enabled && need_isr())
1108 dss_register_vsync_isr();
1110 spin_unlock_irqrestore(&data_lock, flags);
1112 if (!mgr_manual_update(mgr))
1113 dispc_mgr_enable_sync(mgr->id);
1115 out:
1116 mutex_unlock(&apply_lock);
1118 return 0;
1120 err:
1121 mp->enabled = false;
1122 spin_unlock_irqrestore(&data_lock, flags);
1123 mutex_unlock(&apply_lock);
1124 return r;
1125 }
1127 static void dss_mgr_disable_compat(struct omap_overlay_manager *mgr)
1128 {
1129 struct mgr_priv_data *mp = get_mgr_priv(mgr);
1130 unsigned long flags;
1132 mutex_lock(&apply_lock);
1134 if (!mp->enabled)
1135 goto out;
1137 if (!mgr_manual_update(mgr))
1138 dispc_mgr_disable_sync(mgr->id);
1140 spin_lock_irqsave(&data_lock, flags);
1142 mp->updating = false;
1143 mp->enabled = false;
1145 spin_unlock_irqrestore(&data_lock, flags);
1147 out:
1148 mutex_unlock(&apply_lock);
1149 }
1151 static int dss_mgr_set_info(struct omap_overlay_manager *mgr,
1152 struct omap_overlay_manager_info *info)
1153 {
1154 struct mgr_priv_data *mp = get_mgr_priv(mgr);
1155 unsigned long flags;
1156 int r;
1158 r = dss_mgr_simple_check(mgr, info);
1159 if (r)
1160 return r;
1162 spin_lock_irqsave(&data_lock, flags);
1164 mp->user_info = *info;
1165 mp->user_info_dirty = true;
1167 spin_unlock_irqrestore(&data_lock, flags);
1169 return 0;
1170 }
1172 static void dss_mgr_get_info(struct omap_overlay_manager *mgr,
1173 struct omap_overlay_manager_info *info)
1174 {
1175 struct mgr_priv_data *mp = get_mgr_priv(mgr);
1176 unsigned long flags;
1178 spin_lock_irqsave(&data_lock, flags);
1180 *info = mp->user_info;
1182 spin_unlock_irqrestore(&data_lock, flags);
1183 }
1185 static int dss_mgr_set_output(struct omap_overlay_manager *mgr,
1186 struct omap_dss_device *output)
1187 {
1188 int r;
1190 mutex_lock(&apply_lock);
1192 if (mgr->output) {
1193 DSSERR("manager %s is already connected to an output\n",
1194 mgr->name);
1195 r = -EINVAL;
1196 goto err;
1197 }
1199 if ((mgr->supported_outputs & output->id) == 0) {
1200 DSSERR("output does not support manager %s\n",
1201 mgr->name);
1202 r = -EINVAL;
1203 goto err;
1204 }
1206 output->manager = mgr;
1207 mgr->output = output;
1209 mutex_unlock(&apply_lock);
1211 return 0;
1212 err:
1213 mutex_unlock(&apply_lock);
1214 return r;
1215 }
1217 static int dss_mgr_unset_output(struct omap_overlay_manager *mgr)
1218 {
1219 int r;
1220 struct mgr_priv_data *mp = get_mgr_priv(mgr);
1221 unsigned long flags;
1223 mutex_lock(&apply_lock);
1225 if (!mgr->output) {
1226 DSSERR("failed to unset output, output not set\n");
1227 r = -EINVAL;
1228 goto err;
1229 }
1231 spin_lock_irqsave(&data_lock, flags);
1233 if (mp->enabled) {
1234 DSSERR("output can't be unset when manager is enabled\n");
1235 r = -EINVAL;
1236 goto err1;
1237 }
1239 spin_unlock_irqrestore(&data_lock, flags);
1241 mgr->output->manager = NULL;
1242 mgr->output = NULL;
1244 mutex_unlock(&apply_lock);
1246 return 0;
1247 err1:
1248 spin_unlock_irqrestore(&data_lock, flags);
1249 err:
1250 mutex_unlock(&apply_lock);
1252 return r;
1253 }
1255 static void dss_apply_mgr_timings(struct omap_overlay_manager *mgr,
1256 const struct omap_video_timings *timings)
1257 {
1258 struct mgr_priv_data *mp = get_mgr_priv(mgr);
1260 mp->timings = *timings;
1261 mp->extra_info_dirty = true;
1262 }
1264 static void dss_mgr_set_timings_compat(struct omap_overlay_manager *mgr,
1265 const struct omap_video_timings *timings)
1266 {
1267 unsigned long flags;
1268 struct mgr_priv_data *mp = get_mgr_priv(mgr);
1270 spin_lock_irqsave(&data_lock, flags);
1272 if (mp->updating) {
1273 DSSERR("cannot set timings for %s: manager needs to be disabled\n",
1274 mgr->name);
1275 goto out;
1276 }
1278 dss_apply_mgr_timings(mgr, timings);
1279 out:
1280 spin_unlock_irqrestore(&data_lock, flags);
1281 }
1283 static void dss_apply_mgr_lcd_config(struct omap_overlay_manager *mgr,
1284 const struct dss_lcd_mgr_config *config)
1285 {
1286 struct mgr_priv_data *mp = get_mgr_priv(mgr);
1288 mp->lcd_config = *config;
1289 mp->extra_info_dirty = true;
1290 }
1292 static void dss_mgr_set_lcd_config_compat(struct omap_overlay_manager *mgr,
1293 const struct dss_lcd_mgr_config *config)
1294 {
1295 unsigned long flags;
1296 struct mgr_priv_data *mp = get_mgr_priv(mgr);
1298 spin_lock_irqsave(&data_lock, flags);
1300 if (mp->enabled) {
1301 DSSERR("cannot apply lcd config for %s: manager needs to be disabled\n",
1302 mgr->name);
1303 goto out;
1304 }
1306 dss_apply_mgr_lcd_config(mgr, config);
1307 out:
1308 spin_unlock_irqrestore(&data_lock, flags);
1309 }
1311 static int dss_ovl_set_info(struct omap_overlay *ovl,
1312 struct omap_overlay_info *info)
1313 {
1314 struct ovl_priv_data *op = get_ovl_priv(ovl);
1315 unsigned long flags;
1316 int r;
1318 r = dss_ovl_simple_check(ovl, info);
1319 if (r)
1320 return r;
1322 spin_lock_irqsave(&data_lock, flags);
1324 op->user_info = *info;
1325 op->user_info_dirty = true;
1327 spin_unlock_irqrestore(&data_lock, flags);
1329 return 0;
1330 }
1332 static void dss_ovl_get_info(struct omap_overlay *ovl,
1333 struct omap_overlay_info *info)
1334 {
1335 struct ovl_priv_data *op = get_ovl_priv(ovl);
1336 unsigned long flags;
1338 spin_lock_irqsave(&data_lock, flags);
1340 *info = op->user_info;
1342 spin_unlock_irqrestore(&data_lock, flags);
1343 }
1345 static int dss_ovl_set_manager(struct omap_overlay *ovl,
1346 struct omap_overlay_manager *mgr)
1347 {
1348 struct ovl_priv_data *op = get_ovl_priv(ovl);
1349 unsigned long flags;
1350 int r;
1352 if (!mgr)
1353 return -EINVAL;
1355 mutex_lock(&apply_lock);
1357 if (ovl->manager) {
1358 DSSERR("overlay '%s' already has a manager '%s'\n",
1359 ovl->name, ovl->manager->name);
1360 r = -EINVAL;
1361 goto err;
1362 }
1364 r = dispc_runtime_get();
1365 if (r)
1366 goto err;
1368 spin_lock_irqsave(&data_lock, flags);
1370 if (op->enabled) {
1371 spin_unlock_irqrestore(&data_lock, flags);
1372 DSSERR("overlay has to be disabled to change the manager\n");
1373 r = -EINVAL;
1374 goto err1;
1375 }
1377 dispc_ovl_set_channel_out(ovl->id, mgr->id);
1379 ovl->manager = mgr;
1380 list_add_tail(&ovl->list, &mgr->overlays);
1382 spin_unlock_irqrestore(&data_lock, flags);
1384 dispc_runtime_put();
1386 mutex_unlock(&apply_lock);
1388 return 0;
1390 err1:
1391 dispc_runtime_put();
1392 err:
1393 mutex_unlock(&apply_lock);
1394 return r;
1395 }
1397 static int dss_ovl_unset_manager(struct omap_overlay *ovl)
1398 {
1399 struct ovl_priv_data *op = get_ovl_priv(ovl);
1400 unsigned long flags;
1401 int r;
1403 mutex_lock(&apply_lock);
1405 if (!ovl->manager) {
1406 DSSERR("failed to detach overlay: manager not set\n");
1407 r = -EINVAL;
1408 goto err;
1409 }
1411 spin_lock_irqsave(&data_lock, flags);
1413 if (op->enabled) {
1414 spin_unlock_irqrestore(&data_lock, flags);
1415 DSSERR("overlay has to be disabled to unset the manager\n");
1416 r = -EINVAL;
1417 goto err;
1418 }
1420 spin_unlock_irqrestore(&data_lock, flags);
1422 /* wait for pending extra_info updates to ensure the ovl is disabled */
1423 wait_pending_extra_info_updates();
1425 /*
1426 * For a manual update display, there is no guarantee that the overlay
1427 * is really disabled in HW, we may need an extra update from this
1428 * manager before the configurations can go in. Return an error if the
1429 * overlay needed an update from the manager.
1430 *
1431 * TODO: Instead of returning an error, try to do a dummy manager update
1432 * here to disable the overlay in hardware. Use the *GATED fields in
1433 * the DISPC_CONFIG registers to do a dummy update.
1434 */
1435 spin_lock_irqsave(&data_lock, flags);
1437 if (ovl_manual_update(ovl) && op->extra_info_dirty) {
1438 spin_unlock_irqrestore(&data_lock, flags);
1439 DSSERR("need an update to change the manager\n");
1440 r = -EINVAL;
1441 goto err;
1442 }
1444 ovl->manager = NULL;
1445 list_del(&ovl->list);
1447 spin_unlock_irqrestore(&data_lock, flags);
1449 mutex_unlock(&apply_lock);
1451 return 0;
1452 err:
1453 mutex_unlock(&apply_lock);
1454 return r;
1455 }
1457 static bool dss_ovl_is_enabled(struct omap_overlay *ovl)
1458 {
1459 struct ovl_priv_data *op = get_ovl_priv(ovl);
1460 unsigned long flags;
1461 bool e;
1463 spin_lock_irqsave(&data_lock, flags);
1465 e = op->enabled;
1467 spin_unlock_irqrestore(&data_lock, flags);
1469 return e;
1470 }
1472 static int dss_ovl_enable(struct omap_overlay *ovl)
1473 {
1474 struct ovl_priv_data *op = get_ovl_priv(ovl);
1475 unsigned long flags;
1476 int r;
1478 mutex_lock(&apply_lock);
1480 if (op->enabled) {
1481 r = 0;
1482 goto err1;
1483 }
1485 if (ovl->manager == NULL || ovl->manager->output == NULL) {
1486 r = -EINVAL;
1487 goto err1;
1488 }
1490 spin_lock_irqsave(&data_lock, flags);
1492 op->enabling = true;
1494 r = dss_check_settings(ovl->manager);
1495 if (r) {
1496 DSSERR("failed to enable overlay %d: check_settings failed\n",
1497 ovl->id);
1498 goto err2;
1499 }
1501 dss_setup_fifos();
1503 op->enabling = false;
1504 dss_apply_ovl_enable(ovl, true);
1506 dss_write_regs();
1507 dss_set_go_bits();
1509 spin_unlock_irqrestore(&data_lock, flags);
1511 mutex_unlock(&apply_lock);
1513 return 0;
1514 err2:
1515 op->enabling = false;
1516 spin_unlock_irqrestore(&data_lock, flags);
1517 err1:
1518 mutex_unlock(&apply_lock);
1519 return r;
1520 }
1522 static int dss_ovl_disable(struct omap_overlay *ovl)
1523 {
1524 struct ovl_priv_data *op = get_ovl_priv(ovl);
1525 unsigned long flags;
1526 int r;
1528 mutex_lock(&apply_lock);
1530 if (!op->enabled) {
1531 r = 0;
1532 goto err;
1533 }
1535 if (ovl->manager == NULL || ovl->manager->output == NULL) {
1536 r = -EINVAL;
1537 goto err;
1538 }
1540 spin_lock_irqsave(&data_lock, flags);
1542 dss_apply_ovl_enable(ovl, false);
1543 dss_write_regs();
1544 dss_set_go_bits();
1546 spin_unlock_irqrestore(&data_lock, flags);
1548 mutex_unlock(&apply_lock);
1550 return 0;
1552 err:
1553 mutex_unlock(&apply_lock);
1554 return r;
1555 }
1557 static int dss_mgr_register_framedone_handler_compat(struct omap_overlay_manager *mgr,
1558 void (*handler)(void *), void *data)
1559 {
1560 struct mgr_priv_data *mp = get_mgr_priv(mgr);
1562 if (mp->framedone_handler)
1563 return -EBUSY;
1565 mp->framedone_handler = handler;
1566 mp->framedone_handler_data = data;
1568 return 0;
1569 }
1571 static void dss_mgr_unregister_framedone_handler_compat(struct omap_overlay_manager *mgr,
1572 void (*handler)(void *), void *data)
1573 {
1574 struct mgr_priv_data *mp = get_mgr_priv(mgr);
1576 WARN_ON(mp->framedone_handler != handler ||
1577 mp->framedone_handler_data != data);
1579 mp->framedone_handler = NULL;
1580 mp->framedone_handler_data = NULL;
1581 }
1583 static const struct dss_mgr_ops apply_mgr_ops = {
1584 .connect = dss_mgr_connect_compat,
1585 .disconnect = dss_mgr_disconnect_compat,
1586 .start_update = dss_mgr_start_update_compat,
1587 .enable = dss_mgr_enable_compat,
1588 .disable = dss_mgr_disable_compat,
1589 .set_timings = dss_mgr_set_timings_compat,
1590 .set_lcd_config = dss_mgr_set_lcd_config_compat,
1591 .register_framedone_handler = dss_mgr_register_framedone_handler_compat,
1592 .unregister_framedone_handler = dss_mgr_unregister_framedone_handler_compat,
1593 };
1595 static int compat_refcnt;
1596 static DEFINE_MUTEX(compat_init_lock);
1598 int omapdss_compat_init(void)
1599 {
1600 struct platform_device *pdev = dss_get_core_pdev();
1601 int i, r;
1603 mutex_lock(&compat_init_lock);
1605 if (compat_refcnt++ > 0)
1606 goto out;
1608 apply_init_priv();
1610 dss_init_overlay_managers_sysfs(pdev);
1611 dss_init_overlays(pdev);
1613 for (i = 0; i < omap_dss_get_num_overlay_managers(); i++) {
1614 struct omap_overlay_manager *mgr;
1616 mgr = omap_dss_get_overlay_manager(i);
1618 mgr->set_output = &dss_mgr_set_output;
1619 mgr->unset_output = &dss_mgr_unset_output;
1620 mgr->apply = &omap_dss_mgr_apply;
1621 mgr->set_manager_info = &dss_mgr_set_info;
1622 mgr->get_manager_info = &dss_mgr_get_info;
1623 mgr->wait_for_go = &dss_mgr_wait_for_go;
1624 mgr->wait_for_vsync = &dss_mgr_wait_for_vsync;
1625 mgr->get_device = &dss_mgr_get_device;
1626 }
1628 for (i = 0; i < omap_dss_get_num_overlays(); i++) {
1629 struct omap_overlay *ovl = omap_dss_get_overlay(i);
1631 ovl->is_enabled = &dss_ovl_is_enabled;
1632 ovl->enable = &dss_ovl_enable;
1633 ovl->disable = &dss_ovl_disable;
1634 ovl->set_manager = &dss_ovl_set_manager;
1635 ovl->unset_manager = &dss_ovl_unset_manager;
1636 ovl->set_overlay_info = &dss_ovl_set_info;
1637 ovl->get_overlay_info = &dss_ovl_get_info;
1638 ovl->wait_for_go = &dss_mgr_wait_for_go_ovl;
1639 ovl->get_device = &dss_ovl_get_device;
1640 }
1642 r = dss_install_mgr_ops(&apply_mgr_ops);
1643 if (r)
1644 goto err_mgr_ops;
1646 r = display_init_sysfs(pdev);
1647 if (r)
1648 goto err_disp_sysfs;
1650 dispc_runtime_get();
1652 r = dss_dispc_initialize_irq();
1653 if (r)
1654 goto err_init_irq;
1656 dispc_runtime_put();
1658 out:
1659 mutex_unlock(&compat_init_lock);
1661 return 0;
1663 err_init_irq:
1664 dispc_runtime_put();
1665 display_uninit_sysfs(pdev);
1667 err_disp_sysfs:
1668 dss_uninstall_mgr_ops();
1670 err_mgr_ops:
1671 dss_uninit_overlay_managers_sysfs(pdev);
1672 dss_uninit_overlays(pdev);
1674 compat_refcnt--;
1676 mutex_unlock(&compat_init_lock);
1678 return r;
1679 }
1680 EXPORT_SYMBOL(omapdss_compat_init);
1682 void omapdss_compat_uninit(void)
1683 {
1684 struct platform_device *pdev = dss_get_core_pdev();
1686 mutex_lock(&compat_init_lock);
1688 if (--compat_refcnt > 0)
1689 goto out;
1691 dss_dispc_uninitialize_irq();
1693 display_uninit_sysfs(pdev);
1695 dss_uninstall_mgr_ops();
1697 dss_uninit_overlay_managers_sysfs(pdev);
1698 dss_uninit_overlays(pdev);
1699 out:
1700 mutex_unlock(&compat_init_lock);
1701 }
1702 EXPORT_SYMBOL(omapdss_compat_uninit);