1 /*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
23 #define DSS_SUBSYS_NAME "DISPC"
25 #include <linux/kernel.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/vmalloc.h>
28 #include <linux/export.h>
29 #include <linux/clk.h>
30 #include <linux/io.h>
31 #include <linux/jiffies.h>
32 #include <linux/seq_file.h>
33 #include <linux/delay.h>
34 #include <linux/workqueue.h>
35 #include <linux/hardirq.h>
36 #include <linux/platform_device.h>
37 #include <linux/pm_runtime.h>
38 #include <linux/sizes.h>
39 #include <linux/mfd/syscon.h>
40 #include <linux/regmap.h>
42 #include <video/omapdss.h>
44 #include "dss.h"
45 #include "dss_features.h"
46 #include "dispc.h"
48 #define CTRL_CORE_SMA_SW_1 0x534
50 /* DISPC */
51 #define DISPC_SZ_REGS SZ_4K
53 enum omap_burst_size {
54 BURST_SIZE_X2 = 0,
55 BURST_SIZE_X4 = 1,
56 BURST_SIZE_X8 = 2,
57 };
59 #define REG_GET(idx, start, end) \
60 FLD_GET(dispc_read_reg(idx), start, end)
62 #define REG_FLD_MOD(idx, val, start, end) \
63 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
65 struct dispc_features {
66 u8 sw_start;
67 u8 fp_start;
68 u8 bp_start;
69 u16 sw_max;
70 u16 vp_max;
71 u16 hp_max;
72 u8 mgr_width_start;
73 u8 mgr_height_start;
74 u16 mgr_width_max;
75 u16 mgr_height_max;
76 unsigned long max_lcd_pclk;
77 unsigned long max_tv_pclk;
78 int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
79 const struct omap_video_timings *mgr_timings,
80 u16 width, u16 height, u16 out_width, u16 out_height,
81 enum omap_color_mode color_mode, bool *five_taps,
82 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
83 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
84 unsigned long (*calc_core_clk) (unsigned long pclk,
85 u16 width, u16 height, u16 out_width, u16 out_height,
86 bool mem_to_mem);
87 u8 num_fifos;
89 /* swap GFX & WB fifos */
90 bool gfx_fifo_workaround:1;
92 /* no DISPC_IRQ_FRAMEDONETV on this SoC */
93 bool no_framedone_tv:1;
95 /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
96 bool mstandby_workaround:1;
98 bool set_max_preload:1;
100 /* alternate pixel clock source is DSI PLL, or VIDEO PLL */
101 bool alt_clk_dsi_pll:1;
103 /* polarities must be programmed to CTRL_CORE_SMA_SW_1 also */
104 bool has_ctrl_core_sma_sw_1:1;
106 /* PIXEL_INC is not added to the last pixel of a line */
107 bool last_pixel_inc_missing:1;
108 };
110 #define DISPC_MAX_NR_FIFOS 5
112 static struct {
113 struct platform_device *pdev;
114 void __iomem *base;
116 int irq;
117 irq_handler_t user_handler;
118 void *user_data;
120 unsigned long core_clk_rate;
121 unsigned long tv_pclk_rate;
123 u32 fifo_size[DISPC_MAX_NR_FIFOS];
124 /* maps which plane is using a fifo. fifo-id -> plane-id */
125 int fifo_assignment[DISPC_MAX_NR_FIFOS];
127 bool ctx_valid;
128 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
130 const struct dispc_features *feat;
132 bool is_enabled;
134 struct regmap *syscon;
136 /* DISPC_CONTROL & DISPC_CONFIG lock*/
137 spinlock_t control_lock;
138 } dispc;
140 enum omap_color_component {
141 /* used for all color formats for OMAP3 and earlier
142 * and for RGB and Y color component on OMAP4
143 */
144 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
145 /* used for UV component for
146 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
147 * color formats on OMAP4
148 */
149 DISPC_COLOR_COMPONENT_UV = 1 << 1,
150 };
152 enum mgr_reg_fields {
153 DISPC_MGR_FLD_ENABLE,
154 DISPC_MGR_FLD_STNTFT,
155 DISPC_MGR_FLD_GO,
156 DISPC_MGR_FLD_TFTDATALINES,
157 DISPC_MGR_FLD_STALLMODE,
158 DISPC_MGR_FLD_TCKENABLE,
159 DISPC_MGR_FLD_TCKSELECTION,
160 DISPC_MGR_FLD_CPR,
161 DISPC_MGR_FLD_FIFOHANDCHECK,
162 /* used to maintain a count of the above fields */
163 DISPC_MGR_FLD_NUM,
164 };
166 struct dispc_reg_field {
167 u16 reg;
168 u8 high;
169 u8 low;
170 };
172 static const struct {
173 const char *name;
174 u32 vsync_irq;
175 u32 framedone_irq;
176 u32 sync_lost_irq;
177 struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM];
178 } mgr_desc[] = {
179 [OMAP_DSS_CHANNEL_LCD] = {
180 .name = "LCD",
181 .vsync_irq = DISPC_IRQ_VSYNC,
182 .framedone_irq = DISPC_IRQ_FRAMEDONE,
183 .sync_lost_irq = DISPC_IRQ_SYNC_LOST,
184 .reg_desc = {
185 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
186 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
187 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
188 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
189 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
190 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
191 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
192 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
193 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
194 },
195 },
196 [OMAP_DSS_CHANNEL_DIGIT] = {
197 .name = "DIGIT",
198 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
199 .framedone_irq = DISPC_IRQ_FRAMEDONETV,
200 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
201 .reg_desc = {
202 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
203 [DISPC_MGR_FLD_STNTFT] = { },
204 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
205 [DISPC_MGR_FLD_TFTDATALINES] = { },
206 [DISPC_MGR_FLD_STALLMODE] = { },
207 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
208 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
209 [DISPC_MGR_FLD_CPR] = { },
210 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
211 },
212 },
213 [OMAP_DSS_CHANNEL_LCD2] = {
214 .name = "LCD2",
215 .vsync_irq = DISPC_IRQ_VSYNC2,
216 .framedone_irq = DISPC_IRQ_FRAMEDONE2,
217 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
218 .reg_desc = {
219 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
220 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
221 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
222 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
223 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
224 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
225 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
226 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
227 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
228 },
229 },
230 [OMAP_DSS_CHANNEL_LCD3] = {
231 .name = "LCD3",
232 .vsync_irq = DISPC_IRQ_VSYNC3,
233 .framedone_irq = DISPC_IRQ_FRAMEDONE3,
234 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3,
235 .reg_desc = {
236 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 },
237 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 },
238 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
239 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 },
240 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 },
241 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 },
242 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 },
243 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 },
244 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 },
245 },
246 },
247 };
249 struct color_conv_coef {
250 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
251 int full_range;
252 };
254 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
255 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
257 static inline void dispc_write_reg(const u16 idx, u32 val)
258 {
259 __raw_writel(val, dispc.base + idx);
260 }
262 static inline u32 dispc_read_reg(const u16 idx)
263 {
264 return __raw_readl(dispc.base + idx);
265 }
267 static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
268 {
269 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
270 return REG_GET(rfld.reg, rfld.high, rfld.low);
271 }
273 static void mgr_fld_write(enum omap_channel channel,
274 enum mgr_reg_fields regfld, int val) {
275 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
276 const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG;
277 unsigned long flags;
279 if (need_lock)
280 spin_lock_irqsave(&dispc.control_lock, flags);
282 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
284 if (need_lock)
285 spin_unlock_irqrestore(&dispc.control_lock, flags);
286 }
288 #define SR(reg) \
289 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
290 #define RR(reg) \
291 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
293 static void dispc_save_context(void)
294 {
295 int i, j;
297 DSSDBG("dispc_save_context\n");
299 SR(IRQENABLE);
300 SR(CONTROL);
301 SR(CONFIG);
302 SR(LINE_NUMBER);
303 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
304 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
305 SR(GLOBAL_ALPHA);
306 if (dss_has_feature(FEAT_MGR_LCD2)) {
307 SR(CONTROL2);
308 SR(CONFIG2);
309 }
310 if (dss_has_feature(FEAT_MGR_LCD3)) {
311 SR(CONTROL3);
312 SR(CONFIG3);
313 }
315 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
316 SR(DEFAULT_COLOR(i));
317 SR(TRANS_COLOR(i));
318 SR(SIZE_MGR(i));
319 if (i == OMAP_DSS_CHANNEL_DIGIT)
320 continue;
321 SR(TIMING_H(i));
322 SR(TIMING_V(i));
323 SR(POL_FREQ(i));
324 SR(DIVISORo(i));
326 SR(DATA_CYCLE1(i));
327 SR(DATA_CYCLE2(i));
328 SR(DATA_CYCLE3(i));
330 if (dss_has_feature(FEAT_CPR)) {
331 SR(CPR_COEF_R(i));
332 SR(CPR_COEF_G(i));
333 SR(CPR_COEF_B(i));
334 }
335 }
337 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
338 SR(OVL_BA0(i));
339 SR(OVL_BA1(i));
340 SR(OVL_POSITION(i));
341 SR(OVL_SIZE(i));
342 SR(OVL_ATTRIBUTES(i));
343 SR(OVL_FIFO_THRESHOLD(i));
344 SR(OVL_ROW_INC(i));
345 SR(OVL_PIXEL_INC(i));
346 if (dss_has_feature(FEAT_PRELOAD))
347 SR(OVL_PRELOAD(i));
348 if (i == OMAP_DSS_GFX) {
349 SR(OVL_WINDOW_SKIP(i));
350 SR(OVL_TABLE_BA(i));
351 continue;
352 }
353 SR(OVL_FIR(i));
354 SR(OVL_PICTURE_SIZE(i));
355 SR(OVL_ACCU0(i));
356 SR(OVL_ACCU1(i));
358 for (j = 0; j < 8; j++)
359 SR(OVL_FIR_COEF_H(i, j));
361 for (j = 0; j < 8; j++)
362 SR(OVL_FIR_COEF_HV(i, j));
364 for (j = 0; j < 5; j++)
365 SR(OVL_CONV_COEF(i, j));
367 if (dss_has_feature(FEAT_FIR_COEF_V)) {
368 for (j = 0; j < 8; j++)
369 SR(OVL_FIR_COEF_V(i, j));
370 }
372 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
373 SR(OVL_BA0_UV(i));
374 SR(OVL_BA1_UV(i));
375 SR(OVL_FIR2(i));
376 SR(OVL_ACCU2_0(i));
377 SR(OVL_ACCU2_1(i));
379 for (j = 0; j < 8; j++)
380 SR(OVL_FIR_COEF_H2(i, j));
382 for (j = 0; j < 8; j++)
383 SR(OVL_FIR_COEF_HV2(i, j));
385 for (j = 0; j < 8; j++)
386 SR(OVL_FIR_COEF_V2(i, j));
387 }
388 if (dss_has_feature(FEAT_ATTR2))
389 SR(OVL_ATTRIBUTES2(i));
390 }
392 if (dss_has_feature(FEAT_CORE_CLK_DIV))
393 SR(DIVISOR);
395 dispc.ctx_valid = true;
397 DSSDBG("context saved\n");
398 }
400 static void dispc_restore_context(void)
401 {
402 int i, j;
404 DSSDBG("dispc_restore_context\n");
406 if (!dispc.ctx_valid)
407 return;
409 /*RR(IRQENABLE);*/
410 /*RR(CONTROL);*/
411 RR(CONFIG);
412 RR(LINE_NUMBER);
413 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
414 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
415 RR(GLOBAL_ALPHA);
416 if (dss_has_feature(FEAT_MGR_LCD2))
417 RR(CONFIG2);
418 if (dss_has_feature(FEAT_MGR_LCD3))
419 RR(CONFIG3);
421 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
422 RR(DEFAULT_COLOR(i));
423 RR(TRANS_COLOR(i));
424 RR(SIZE_MGR(i));
425 if (i == OMAP_DSS_CHANNEL_DIGIT)
426 continue;
427 RR(TIMING_H(i));
428 RR(TIMING_V(i));
429 RR(POL_FREQ(i));
430 RR(DIVISORo(i));
432 RR(DATA_CYCLE1(i));
433 RR(DATA_CYCLE2(i));
434 RR(DATA_CYCLE3(i));
436 if (dss_has_feature(FEAT_CPR)) {
437 RR(CPR_COEF_R(i));
438 RR(CPR_COEF_G(i));
439 RR(CPR_COEF_B(i));
440 }
441 }
443 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
444 RR(OVL_BA0(i));
445 RR(OVL_BA1(i));
446 RR(OVL_POSITION(i));
447 RR(OVL_SIZE(i));
448 RR(OVL_ATTRIBUTES(i));
449 RR(OVL_FIFO_THRESHOLD(i));
450 RR(OVL_ROW_INC(i));
451 RR(OVL_PIXEL_INC(i));
452 if (dss_has_feature(FEAT_PRELOAD))
453 RR(OVL_PRELOAD(i));
454 if (i == OMAP_DSS_GFX) {
455 RR(OVL_WINDOW_SKIP(i));
456 RR(OVL_TABLE_BA(i));
457 continue;
458 }
459 RR(OVL_FIR(i));
460 RR(OVL_PICTURE_SIZE(i));
461 RR(OVL_ACCU0(i));
462 RR(OVL_ACCU1(i));
464 for (j = 0; j < 8; j++)
465 RR(OVL_FIR_COEF_H(i, j));
467 for (j = 0; j < 8; j++)
468 RR(OVL_FIR_COEF_HV(i, j));
470 for (j = 0; j < 5; j++)
471 RR(OVL_CONV_COEF(i, j));
473 if (dss_has_feature(FEAT_FIR_COEF_V)) {
474 for (j = 0; j < 8; j++)
475 RR(OVL_FIR_COEF_V(i, j));
476 }
478 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
479 RR(OVL_BA0_UV(i));
480 RR(OVL_BA1_UV(i));
481 RR(OVL_FIR2(i));
482 RR(OVL_ACCU2_0(i));
483 RR(OVL_ACCU2_1(i));
485 for (j = 0; j < 8; j++)
486 RR(OVL_FIR_COEF_H2(i, j));
488 for (j = 0; j < 8; j++)
489 RR(OVL_FIR_COEF_HV2(i, j));
491 for (j = 0; j < 8; j++)
492 RR(OVL_FIR_COEF_V2(i, j));
493 }
494 if (dss_has_feature(FEAT_ATTR2))
495 RR(OVL_ATTRIBUTES2(i));
496 }
498 if (dss_has_feature(FEAT_CORE_CLK_DIV))
499 RR(DIVISOR);
501 /* enable last, because LCD & DIGIT enable are here */
502 RR(CONTROL);
503 if (dss_has_feature(FEAT_MGR_LCD2))
504 RR(CONTROL2);
505 if (dss_has_feature(FEAT_MGR_LCD3))
506 RR(CONTROL3);
507 /* clear spurious SYNC_LOST_DIGIT interrupts */
508 dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
510 /*
511 * enable last so IRQs won't trigger before
512 * the context is fully restored
513 */
514 RR(IRQENABLE);
516 DSSDBG("context restored\n");
517 }
519 #undef SR
520 #undef RR
522 int dispc_runtime_get(void)
523 {
524 int r;
526 DSSDBG("dispc_runtime_get\n");
528 r = pm_runtime_get_sync(&dispc.pdev->dev);
529 WARN_ON(r < 0);
530 return r < 0 ? r : 0;
531 }
532 EXPORT_SYMBOL(dispc_runtime_get);
534 void dispc_runtime_put(void)
535 {
536 int r;
538 DSSDBG("dispc_runtime_put\n");
540 r = pm_runtime_put_sync(&dispc.pdev->dev);
541 WARN_ON(r < 0 && r != -ENOSYS);
542 }
543 EXPORT_SYMBOL(dispc_runtime_put);
545 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
546 {
547 return mgr_desc[channel].vsync_irq;
548 }
549 EXPORT_SYMBOL(dispc_mgr_get_vsync_irq);
551 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
552 {
553 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
554 return 0;
556 return mgr_desc[channel].framedone_irq;
557 }
558 EXPORT_SYMBOL(dispc_mgr_get_framedone_irq);
560 u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
561 {
562 return mgr_desc[channel].sync_lost_irq;
563 }
564 EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq);
566 u32 dispc_wb_get_framedone_irq(void)
567 {
568 return DISPC_IRQ_FRAMEDONEWB;
569 }
571 bool dispc_mgr_go_busy(enum omap_channel channel)
572 {
573 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
574 }
575 EXPORT_SYMBOL(dispc_mgr_go_busy);
577 void dispc_mgr_go(enum omap_channel channel)
578 {
579 WARN_ON(dispc_mgr_is_enabled(channel) == false);
581 if (omapdss_display_share())
582 /* In case of display share use case, the remote core
583 * will be setting GO bit independently. Hence we might see the
584 * channel as busy on kernel side. Ignore this and proceed
585 * further */
586 WARN_ON(dispc_mgr_go_busy(channel));
588 DSSDBG("GO %s\n", mgr_desc[channel].name);
590 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
591 }
592 EXPORT_SYMBOL(dispc_mgr_go);
594 bool dispc_wb_go_busy(void)
595 {
596 return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
597 }
599 void dispc_wb_go(void)
600 {
601 enum omap_plane plane = OMAP_DSS_WB;
602 bool enable, go;
604 enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
606 if (!enable)
607 return;
609 go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
610 if (go) {
611 DSSERR("GO bit not down for WB\n");
612 return;
613 }
615 REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
616 }
618 static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
619 {
620 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
621 }
623 static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
624 {
625 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
626 }
628 static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
629 {
630 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
631 }
633 static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
634 {
635 BUG_ON(plane == OMAP_DSS_GFX);
637 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
638 }
640 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
641 u32 value)
642 {
643 BUG_ON(plane == OMAP_DSS_GFX);
645 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
646 }
648 static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
649 {
650 BUG_ON(plane == OMAP_DSS_GFX);
652 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
653 }
655 static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
656 int fir_vinc, int five_taps,
657 enum omap_color_component color_comp)
658 {
659 const struct dispc_coef *h_coef, *v_coef;
660 int i;
662 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
663 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
665 for (i = 0; i < 8; i++) {
666 u32 h, hv;
668 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
669 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
670 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
671 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
672 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
673 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
674 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
675 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
677 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
678 dispc_ovl_write_firh_reg(plane, i, h);
679 dispc_ovl_write_firhv_reg(plane, i, hv);
680 } else {
681 dispc_ovl_write_firh2_reg(plane, i, h);
682 dispc_ovl_write_firhv2_reg(plane, i, hv);
683 }
685 }
687 if (five_taps) {
688 for (i = 0; i < 8; i++) {
689 u32 v;
690 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
691 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
692 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
693 dispc_ovl_write_firv_reg(plane, i, v);
694 else
695 dispc_ovl_write_firv2_reg(plane, i, v);
696 }
697 }
698 }
701 static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
702 const struct color_conv_coef *ct)
703 {
704 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
706 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
707 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb));
708 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
709 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
710 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
712 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
714 #undef CVAL
715 }
717 static void dispc_setup_color_conv_coef(void)
718 {
719 int i;
720 int num_ovl = dss_feat_get_num_ovls();
721 int num_wb = dss_feat_get_num_wbs();
722 const struct color_conv_coef ctbl_bt601_5_ovl = {
723 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
724 };
725 const struct color_conv_coef ctbl_bt601_5_wb = {
726 66, 112, -38, 129, -94, -74, 25, -18, 112, 0,
727 };
729 for (i = 1; i < num_ovl; i++)
730 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
732 for (; i < num_wb; i++)
733 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_wb);
734 }
736 static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
737 {
738 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
739 }
741 static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
742 {
743 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
744 }
746 static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
747 {
748 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
749 }
751 static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
752 {
753 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
754 }
756 static void dispc_ovl_set_pos(enum omap_plane plane,
757 enum omap_overlay_caps caps, int x, int y)
758 {
759 u32 val;
761 if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
762 return;
764 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
766 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
767 }
769 static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
770 int height)
771 {
772 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
774 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
775 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
776 else
777 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
778 }
780 static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
781 int height)
782 {
783 u32 val;
785 BUG_ON(plane == OMAP_DSS_GFX);
787 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
789 if (plane == OMAP_DSS_WB)
790 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
791 else
792 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
793 }
795 static void dispc_ovl_set_zorder(enum omap_plane plane,
796 enum omap_overlay_caps caps, u8 zorder)
797 {
798 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
799 return;
801 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
802 }
804 static void dispc_ovl_enable_zorder_planes(void)
805 {
806 int i;
808 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
809 return;
811 for (i = 0; i < dss_feat_get_num_ovls(); i++)
812 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
813 }
815 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
816 enum omap_overlay_caps caps, bool enable)
817 {
818 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
819 return;
821 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
822 }
824 static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
825 enum omap_overlay_caps caps, u8 global_alpha)
826 {
827 static const unsigned shifts[] = { 0, 8, 16, 24, };
828 int shift;
830 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
831 return;
833 shift = shifts[plane];
834 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
835 }
837 static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
838 {
839 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
840 }
842 static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
843 {
844 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
845 }
847 static void dispc_ovl_set_color_mode(enum omap_plane plane,
848 enum omap_color_mode color_mode)
849 {
850 u32 m = 0;
851 if (plane != OMAP_DSS_GFX) {
852 switch (color_mode) {
853 case OMAP_DSS_COLOR_NV12:
854 m = 0x0; break;
855 case OMAP_DSS_COLOR_RGBX16:
856 m = 0x1; break;
857 case OMAP_DSS_COLOR_RGBA16:
858 m = 0x2; break;
859 case OMAP_DSS_COLOR_RGB12U:
860 m = 0x4; break;
861 case OMAP_DSS_COLOR_ARGB16:
862 m = 0x5; break;
863 case OMAP_DSS_COLOR_RGB16:
864 m = 0x6; break;
865 case OMAP_DSS_COLOR_ARGB16_1555:
866 m = 0x7; break;
867 case OMAP_DSS_COLOR_RGB24U:
868 m = 0x8; break;
869 case OMAP_DSS_COLOR_RGB24P:
870 m = 0x9; break;
871 case OMAP_DSS_COLOR_YUV2:
872 m = 0xa; break;
873 case OMAP_DSS_COLOR_UYVY:
874 m = 0xb; break;
875 case OMAP_DSS_COLOR_ARGB32:
876 m = 0xc; break;
877 case OMAP_DSS_COLOR_RGBA32:
878 m = 0xd; break;
879 case OMAP_DSS_COLOR_RGBX32:
880 m = 0xe; break;
881 case OMAP_DSS_COLOR_XRGB16_1555:
882 m = 0xf; break;
883 default:
884 BUG(); return;
885 }
886 } else {
887 switch (color_mode) {
888 case OMAP_DSS_COLOR_CLUT1:
889 m = 0x0; break;
890 case OMAP_DSS_COLOR_CLUT2:
891 m = 0x1; break;
892 case OMAP_DSS_COLOR_CLUT4:
893 m = 0x2; break;
894 case OMAP_DSS_COLOR_CLUT8:
895 m = 0x3; break;
896 case OMAP_DSS_COLOR_RGB12U:
897 m = 0x4; break;
898 case OMAP_DSS_COLOR_ARGB16:
899 m = 0x5; break;
900 case OMAP_DSS_COLOR_RGB16:
901 m = 0x6; break;
902 case OMAP_DSS_COLOR_ARGB16_1555:
903 m = 0x7; break;
904 case OMAP_DSS_COLOR_RGB24U:
905 m = 0x8; break;
906 case OMAP_DSS_COLOR_RGB24P:
907 m = 0x9; break;
908 case OMAP_DSS_COLOR_RGBX16:
909 m = 0xa; break;
910 case OMAP_DSS_COLOR_RGBA16:
911 m = 0xb; break;
912 case OMAP_DSS_COLOR_ARGB32:
913 m = 0xc; break;
914 case OMAP_DSS_COLOR_RGBA32:
915 m = 0xd; break;
916 case OMAP_DSS_COLOR_RGBX32:
917 m = 0xe; break;
918 case OMAP_DSS_COLOR_XRGB16_1555:
919 m = 0xf; break;
920 default:
921 BUG(); return;
922 }
923 }
925 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
926 }
928 static void dispc_ovl_configure_burst_type(enum omap_plane plane,
929 enum omap_dss_rotation_type rotation_type)
930 {
931 if (dss_has_feature(FEAT_BURST_2D) == 0)
932 return;
934 if (rotation_type == OMAP_DSS_ROT_TILER)
935 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
936 else
937 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
938 }
940 void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
941 {
942 int shift;
943 u32 val;
944 int chan = 0, chan2 = 0;
946 switch (plane) {
947 case OMAP_DSS_GFX:
948 shift = 8;
949 break;
950 case OMAP_DSS_VIDEO1:
951 case OMAP_DSS_VIDEO2:
952 case OMAP_DSS_VIDEO3:
953 shift = 16;
954 break;
955 default:
956 BUG();
957 return;
958 }
960 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
961 if (dss_has_feature(FEAT_MGR_LCD2)) {
962 switch (channel) {
963 case OMAP_DSS_CHANNEL_LCD:
964 chan = 0;
965 chan2 = 0;
966 break;
967 case OMAP_DSS_CHANNEL_DIGIT:
968 chan = 1;
969 chan2 = 0;
970 break;
971 case OMAP_DSS_CHANNEL_LCD2:
972 chan = 0;
973 chan2 = 1;
974 break;
975 case OMAP_DSS_CHANNEL_LCD3:
976 if (dss_has_feature(FEAT_MGR_LCD3)) {
977 chan = 0;
978 chan2 = 2;
979 } else {
980 BUG();
981 return;
982 }
983 break;
984 default:
985 BUG();
986 return;
987 }
989 val = FLD_MOD(val, chan, shift, shift);
990 val = FLD_MOD(val, chan2, 31, 30);
991 } else {
992 val = FLD_MOD(val, channel, shift, shift);
993 }
994 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
995 }
996 EXPORT_SYMBOL(dispc_ovl_set_channel_out);
998 static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
999 {
1000 int shift;
1001 u32 val;
1002 enum omap_channel channel;
1004 switch (plane) {
1005 case OMAP_DSS_GFX:
1006 shift = 8;
1007 break;
1008 case OMAP_DSS_VIDEO1:
1009 case OMAP_DSS_VIDEO2:
1010 case OMAP_DSS_VIDEO3:
1011 shift = 16;
1012 break;
1013 default:
1014 BUG();
1015 return 0;
1016 }
1018 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1020 if (dss_has_feature(FEAT_MGR_LCD3)) {
1021 if (FLD_GET(val, 31, 30) == 0)
1022 channel = FLD_GET(val, shift, shift);
1023 else if (FLD_GET(val, 31, 30) == 1)
1024 channel = OMAP_DSS_CHANNEL_LCD2;
1025 else
1026 channel = OMAP_DSS_CHANNEL_LCD3;
1027 } else if (dss_has_feature(FEAT_MGR_LCD2)) {
1028 if (FLD_GET(val, 31, 30) == 0)
1029 channel = FLD_GET(val, shift, shift);
1030 else
1031 channel = OMAP_DSS_CHANNEL_LCD2;
1032 } else {
1033 channel = FLD_GET(val, shift, shift);
1034 }
1036 return channel;
1037 }
1039 void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
1040 {
1041 enum omap_plane plane = OMAP_DSS_WB;
1043 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
1044 }
1046 static void dispc_ovl_set_burst_size(enum omap_plane plane,
1047 enum omap_burst_size burst_size)
1048 {
1049 static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
1050 int shift;
1052 shift = shifts[plane];
1053 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
1054 }
1056 static void dispc_configure_burst_sizes(void)
1057 {
1058 int i;
1059 const int burst_size = BURST_SIZE_X8;
1061 /* Configure burst size always to maximum size */
1062 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1063 dispc_ovl_set_burst_size(i, burst_size);
1064 }
1066 static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
1067 {
1068 unsigned unit = dss_feat_get_burst_size_unit();
1069 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1070 return unit * 8;
1071 }
1073 void dispc_enable_gamma_table(bool enable)
1074 {
1075 /*
1076 * This is partially implemented to support only disabling of
1077 * the gamma table.
1078 */
1079 if (enable) {
1080 DSSWARN("Gamma table enabling for TV not yet supported");
1081 return;
1082 }
1084 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1085 }
1087 static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
1088 {
1089 if (channel == OMAP_DSS_CHANNEL_DIGIT)
1090 return;
1092 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
1093 }
1095 static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
1096 const struct omap_dss_cpr_coefs *coefs)
1097 {
1098 u32 coef_r, coef_g, coef_b;
1100 if (!dss_mgr_is_lcd(channel))
1101 return;
1103 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1104 FLD_VAL(coefs->rb, 9, 0);
1105 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1106 FLD_VAL(coefs->gb, 9, 0);
1107 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1108 FLD_VAL(coefs->bb, 9, 0);
1110 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1111 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1112 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1113 }
1115 static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
1116 {
1117 u32 val;
1119 BUG_ON(plane == OMAP_DSS_GFX);
1121 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1122 val = FLD_MOD(val, enable, 9, 9);
1123 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1124 }
1126 static void dispc_ovl_enable_replication(enum omap_plane plane,
1127 enum omap_overlay_caps caps, bool enable)
1128 {
1129 static const unsigned shifts[] = { 5, 10, 10, 10 };
1130 int shift;
1132 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1133 return;
1135 shift = shifts[plane];
1136 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1137 }
1139 static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
1140 u16 height)
1141 {
1142 u32 val;
1144 val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
1145 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
1147 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
1148 }
1150 static void dispc_init_fifos(void)
1151 {
1152 u32 size;
1153 int fifo;
1154 u8 start, end;
1155 u32 unit;
1156 int i;
1158 unit = dss_feat_get_buffer_size_unit();
1160 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1162 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1163 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
1164 size *= unit;
1165 dispc.fifo_size[fifo] = size;
1167 /*
1168 * By default fifos are mapped directly to overlays, fifo 0 to
1169 * ovl 0, fifo 1 to ovl 1, etc.
1170 */
1171 dispc.fifo_assignment[fifo] = fifo;
1172 }
1174 /*
1175 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1176 * causes problems with certain use cases, like using the tiler in 2D
1177 * mode. The below hack swaps the fifos of GFX and WB planes, thus
1178 * giving GFX plane a larger fifo. WB but should work fine with a
1179 * smaller fifo.
1180 */
1181 if (dispc.feat->gfx_fifo_workaround) {
1182 u32 v;
1184 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1186 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1187 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1188 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1189 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1191 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1193 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1194 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1195 }
1197 /*
1198 * Setup default fifo thresholds.
1199 */
1200 for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1201 u32 low, high;
1202 const bool use_fifomerge = false;
1203 const bool manual_update = false;
1205 dispc_ovl_compute_fifo_thresholds(i, &low, &high,
1206 use_fifomerge, manual_update);
1208 dispc_ovl_set_fifo_threshold(i, low, high);
1209 }
1210 }
1212 static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1213 {
1214 int fifo;
1215 u32 size = 0;
1217 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1218 if (dispc.fifo_assignment[fifo] == plane)
1219 size += dispc.fifo_size[fifo];
1220 }
1222 return size;
1223 }
1225 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
1226 {
1227 u8 hi_start, hi_end, lo_start, lo_end;
1228 u32 unit;
1230 unit = dss_feat_get_buffer_size_unit();
1232 WARN_ON(low % unit != 0);
1233 WARN_ON(high % unit != 0);
1235 low /= unit;
1236 high /= unit;
1238 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1239 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1241 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
1242 plane,
1243 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1244 lo_start, lo_end) * unit,
1245 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1246 hi_start, hi_end) * unit,
1247 low * unit, high * unit);
1249 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1250 FLD_VAL(high, hi_start, hi_end) |
1251 FLD_VAL(low, lo_start, lo_end));
1253 /*
1254 * configure the preload to the pipeline's high threhold, if HT it's too
1255 * large for the preload field, set the threshold to the maximum value
1256 * that can be held by the preload register
1257 */
1258 if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload &&
1259 plane != OMAP_DSS_WB)
1260 dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu));
1261 }
1262 EXPORT_SYMBOL(dispc_ovl_set_fifo_threshold);
1264 void dispc_enable_fifomerge(bool enable)
1265 {
1266 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1267 WARN_ON(enable);
1268 return;
1269 }
1271 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1272 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1273 }
1275 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
1276 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1277 bool manual_update)
1278 {
1279 /*
1280 * All sizes are in bytes. Both the buffer and burst are made of
1281 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1282 */
1284 unsigned buf_unit = dss_feat_get_buffer_size_unit();
1285 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1286 int i;
1288 burst_size = dispc_ovl_get_burst_size(plane);
1289 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
1291 if (use_fifomerge) {
1292 total_fifo_size = 0;
1293 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1294 total_fifo_size += dispc_ovl_get_fifo_size(i);
1295 } else {
1296 total_fifo_size = ovl_fifo_size;
1297 }
1299 /*
1300 * We use the same low threshold for both fifomerge and non-fifomerge
1301 * cases, but for fifomerge we calculate the high threshold using the
1302 * combined fifo size
1303 */
1305 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
1306 *fifo_low = ovl_fifo_size - burst_size * 2;
1307 *fifo_high = total_fifo_size - burst_size;
1308 } else if (plane == OMAP_DSS_WB) {
1309 /*
1310 * Most optimal configuration for writeback is to push out data
1311 * to the interconnect the moment writeback pushes enough pixels
1312 * in the FIFO to form a burst
1313 */
1314 *fifo_low = 0;
1315 *fifo_high = burst_size;
1316 } else {
1317 *fifo_low = ovl_fifo_size - burst_size;
1318 *fifo_high = total_fifo_size - buf_unit;
1319 }
1320 }
1321 EXPORT_SYMBOL(dispc_ovl_compute_fifo_thresholds);
1323 static void dispc_ovl_set_mflag(enum omap_plane plane, bool enable)
1324 {
1325 int bit;
1327 if (plane == OMAP_DSS_GFX)
1328 bit = 14;
1329 else
1330 bit = 23;
1332 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
1333 }
1335 static void dispc_ovl_set_mflag_threshold(enum omap_plane plane,
1336 int low, int high)
1337 {
1338 dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane),
1339 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0));
1340 }
1342 static void dispc_init_mflag(void)
1343 {
1344 int i;
1346 /*
1347 * HACK: NV12 color format and MFLAG seem to have problems working
1348 * together: using two displays, and having an NV12 overlay on one of
1349 * the displays will cause underflows/synclosts when MFLAG_CTRL=2.
1350 * Changing MFLAG thresholds and PRELOAD to certain values seem to
1351 * remove the errors, but there doesn't seem to be a clear logic on
1352 * which values work and which not.
1353 *
1354 * As a work-around, set force MFLAG to always on.
1355 */
1356 dispc_write_reg(DISPC_GLOBAL_MFLAG_ATTRIBUTE,
1357 (1 << 0) | /* MFLAG_CTRL = force always on */
1358 (0 << 2)); /* MFLAG_START = disable */
1360 for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1361 u32 size = dispc_ovl_get_fifo_size(i);
1362 u32 unit = dss_feat_get_buffer_size_unit();
1363 u32 low, high;
1365 dispc_ovl_set_mflag(i, true);
1367 /*
1368 * Simulation team suggests below thesholds:
1369 * HT = fifosize * 5 / 8;
1370 * LT = fifosize * 4 / 8;
1371 */
1373 low = size * 4 / 8 / unit;
1374 high = size * 5 / 8 / unit;
1376 dispc_ovl_set_mflag_threshold(i, low, high);
1377 }
1378 }
1380 static void dispc_ovl_set_fir(enum omap_plane plane,
1381 int hinc, int vinc,
1382 enum omap_color_component color_comp)
1383 {
1384 u32 val;
1386 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1387 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1389 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1390 &hinc_start, &hinc_end);
1391 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1392 &vinc_start, &vinc_end);
1393 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1394 FLD_VAL(hinc, hinc_start, hinc_end);
1396 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1397 } else {
1398 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1399 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1400 }
1401 }
1403 static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1404 {
1405 u32 val;
1406 u8 hor_start, hor_end, vert_start, vert_end;
1408 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1409 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1411 val = FLD_VAL(vaccu, vert_start, vert_end) |
1412 FLD_VAL(haccu, hor_start, hor_end);
1414 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1415 }
1417 static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1418 {
1419 u32 val;
1420 u8 hor_start, hor_end, vert_start, vert_end;
1422 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1423 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1425 val = FLD_VAL(vaccu, vert_start, vert_end) |
1426 FLD_VAL(haccu, hor_start, hor_end);
1428 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1429 }
1431 static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1432 int vaccu)
1433 {
1434 u32 val;
1436 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1437 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1438 }
1440 static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1441 int vaccu)
1442 {
1443 u32 val;
1445 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1446 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1447 }
1449 static void dispc_ovl_set_scale_param(enum omap_plane plane,
1450 u16 orig_width, u16 orig_height,
1451 u16 out_width, u16 out_height,
1452 bool five_taps, u8 rotation,
1453 enum omap_color_component color_comp)
1454 {
1455 int fir_hinc, fir_vinc;
1457 fir_hinc = 1024 * orig_width / out_width;
1458 fir_vinc = 1024 * orig_height / out_height;
1460 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1461 color_comp);
1462 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1463 }
1465 static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1466 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1467 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1468 {
1469 int h_accu2_0, h_accu2_1;
1470 int v_accu2_0, v_accu2_1;
1471 int chroma_hinc, chroma_vinc;
1472 int idx;
1474 struct accu {
1475 s8 h0_m, h0_n;
1476 s8 h1_m, h1_n;
1477 s8 v0_m, v0_n;
1478 s8 v1_m, v1_n;
1479 };
1481 const struct accu *accu_table;
1482 const struct accu *accu_val;
1484 static const struct accu accu_nv12[4] = {
1485 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1486 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1487 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1488 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1489 };
1491 static const struct accu accu_nv12_ilace[4] = {
1492 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1493 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1494 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1495 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1496 };
1498 static const struct accu accu_yuv[4] = {
1499 { 0, 1, 0, 1, 0, 1, 0, 1 },
1500 { 0, 1, 0, 1, 0, 1, 0, 1 },
1501 { -1, 1, 0, 1, 0, 1, 0, 1 },
1502 { 0, 1, 0, 1, -1, 1, 0, 1 },
1503 };
1505 switch (rotation) {
1506 case OMAP_DSS_ROT_0:
1507 idx = 0;
1508 break;
1509 case OMAP_DSS_ROT_90:
1510 idx = 1;
1511 break;
1512 case OMAP_DSS_ROT_180:
1513 idx = 2;
1514 break;
1515 case OMAP_DSS_ROT_270:
1516 idx = 3;
1517 break;
1518 default:
1519 BUG();
1520 return;
1521 }
1523 switch (color_mode) {
1524 case OMAP_DSS_COLOR_NV12:
1525 if (ilace)
1526 accu_table = accu_nv12_ilace;
1527 else
1528 accu_table = accu_nv12;
1529 break;
1530 case OMAP_DSS_COLOR_YUV2:
1531 case OMAP_DSS_COLOR_UYVY:
1532 accu_table = accu_yuv;
1533 break;
1534 default:
1535 BUG();
1536 return;
1537 }
1539 accu_val = &accu_table[idx];
1541 chroma_hinc = 1024 * orig_width / out_width;
1542 chroma_vinc = 1024 * orig_height / out_height;
1544 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1545 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1546 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1547 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1549 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1550 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1551 }
1553 static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1554 u16 orig_width, u16 orig_height,
1555 u16 out_width, u16 out_height,
1556 bool ilace, bool five_taps,
1557 bool fieldmode, enum omap_color_mode color_mode,
1558 u8 rotation)
1559 {
1560 int accu0 = 0;
1561 int accu1 = 0;
1562 u32 l;
1564 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1565 out_width, out_height, five_taps,
1566 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1567 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1569 /* RESIZEENABLE and VERTICALTAPS */
1570 l &= ~((0x3 << 5) | (0x1 << 21));
1571 l |= (orig_width != out_width) ? (1 << 5) : 0;
1572 l |= (orig_height != out_height) ? (1 << 6) : 0;
1573 l |= five_taps ? (1 << 21) : 0;
1575 /* VRESIZECONF and HRESIZECONF */
1576 if (dss_has_feature(FEAT_RESIZECONF)) {
1577 l &= ~(0x3 << 7);
1578 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1579 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1580 }
1582 /* LINEBUFFERSPLIT */
1583 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1584 l &= ~(0x1 << 22);
1585 l |= five_taps ? (1 << 22) : 0;
1586 }
1588 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1590 /*
1591 * field 0 = even field = bottom field
1592 * field 1 = odd field = top field
1593 */
1594 if (ilace && !fieldmode) {
1595 accu1 = 0;
1596 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1597 if (accu0 >= 1024/2) {
1598 accu1 = 1024/2;
1599 accu0 -= accu1;
1600 }
1601 }
1603 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1604 dispc_ovl_set_vid_accu1(plane, 0, accu1);
1605 }
1607 static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1608 u16 orig_width, u16 orig_height,
1609 u16 out_width, u16 out_height,
1610 bool ilace, bool five_taps,
1611 bool fieldmode, enum omap_color_mode color_mode,
1612 u8 rotation)
1613 {
1614 int scale_x = out_width != orig_width;
1615 int scale_y = out_height != orig_height;
1616 bool chroma_upscale = plane != OMAP_DSS_WB ? true : false;
1618 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1619 return;
1620 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1621 color_mode != OMAP_DSS_COLOR_UYVY &&
1622 color_mode != OMAP_DSS_COLOR_NV12)) {
1623 /* reset chroma resampling for RGB formats */
1624 if (plane != OMAP_DSS_WB)
1625 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1626 return;
1627 }
1629 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1630 out_height, ilace, color_mode, rotation);
1632 switch (color_mode) {
1633 case OMAP_DSS_COLOR_NV12:
1634 if (chroma_upscale) {
1635 /* UV is subsampled by 2 horizontally and vertically */
1636 orig_height >>= 1;
1637 orig_width >>= 1;
1638 } else {
1639 /* UV is downsampled by 2 horizontally and vertically */
1640 orig_height <<= 1;
1641 orig_width <<= 1;
1642 }
1644 break;
1645 case OMAP_DSS_COLOR_YUV2:
1646 case OMAP_DSS_COLOR_UYVY:
1647 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
1648 if (rotation == OMAP_DSS_ROT_0 ||
1649 rotation == OMAP_DSS_ROT_180) {
1650 if (chroma_upscale)
1651 /* UV is subsampled by 2 horizontally */
1652 orig_width >>= 1;
1653 else
1654 /* UV is downsampled by 2 horizontally */
1655 orig_width <<= 1;
1656 }
1658 /* must use FIR for YUV422 if rotated */
1659 if (rotation != OMAP_DSS_ROT_0)
1660 scale_x = scale_y = true;
1662 break;
1663 default:
1664 BUG();
1665 return;
1666 }
1668 if (out_width != orig_width)
1669 scale_x = true;
1670 if (out_height != orig_height)
1671 scale_y = true;
1673 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1674 out_width, out_height, five_taps,
1675 rotation, DISPC_COLOR_COMPONENT_UV);
1677 if (plane != OMAP_DSS_WB)
1678 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1679 (scale_x || scale_y) ? 1 : 0, 8, 8);
1681 /* set H scaling */
1682 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1683 /* set V scaling */
1684 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1685 }
1687 static void dispc_ovl_set_scaling(enum omap_plane plane,
1688 u16 orig_width, u16 orig_height,
1689 u16 out_width, u16 out_height,
1690 bool ilace, bool five_taps,
1691 bool fieldmode, enum omap_color_mode color_mode,
1692 u8 rotation)
1693 {
1694 BUG_ON(plane == OMAP_DSS_GFX);
1696 dispc_ovl_set_scaling_common(plane,
1697 orig_width, orig_height,
1698 out_width, out_height,
1699 ilace, five_taps,
1700 fieldmode, color_mode,
1701 rotation);
1703 dispc_ovl_set_scaling_uv(plane,
1704 orig_width, orig_height,
1705 out_width, out_height,
1706 ilace, five_taps,
1707 fieldmode, color_mode,
1708 rotation);
1709 }
1711 static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1712 enum omap_dss_rotation_type rotation_type,
1713 bool mirroring, enum omap_color_mode color_mode)
1714 {
1715 bool row_repeat = false;
1716 int vidrot = 0;
1718 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1719 color_mode == OMAP_DSS_COLOR_UYVY) {
1721 if (mirroring) {
1722 switch (rotation) {
1723 case OMAP_DSS_ROT_0:
1724 vidrot = 2;
1725 break;
1726 case OMAP_DSS_ROT_90:
1727 vidrot = 1;
1728 break;
1729 case OMAP_DSS_ROT_180:
1730 vidrot = 0;
1731 break;
1732 case OMAP_DSS_ROT_270:
1733 vidrot = 3;
1734 break;
1735 }
1736 } else {
1737 switch (rotation) {
1738 case OMAP_DSS_ROT_0:
1739 vidrot = 0;
1740 break;
1741 case OMAP_DSS_ROT_90:
1742 vidrot = 1;
1743 break;
1744 case OMAP_DSS_ROT_180:
1745 vidrot = 2;
1746 break;
1747 case OMAP_DSS_ROT_270:
1748 vidrot = 3;
1749 break;
1750 }
1751 }
1753 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1754 row_repeat = true;
1755 else
1756 row_repeat = false;
1757 }
1759 /*
1760 * OMAP4/5 Errata i631:
1761 * NV12 in 1D mode must use ROTATION=1. Otherwise DSS will fetch extra
1762 * rows beyond the framebuffer, which may cause OCP error.
1763 */
1764 if (color_mode == OMAP_DSS_COLOR_NV12 &&
1765 rotation_type != OMAP_DSS_ROT_TILER)
1766 vidrot = 1;
1768 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1769 if (dss_has_feature(FEAT_ROWREPEATENABLE))
1770 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1771 row_repeat ? 1 : 0, 18, 18);
1773 if (color_mode == OMAP_DSS_COLOR_NV12) {
1774 bool doublestride = (rotation_type == OMAP_DSS_ROT_TILER) &&
1775 (rotation == OMAP_DSS_ROT_0 ||
1776 rotation == OMAP_DSS_ROT_180);
1777 /* DOUBLESTRIDE */
1778 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22);
1779 }
1781 }
1783 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1784 {
1785 switch (color_mode) {
1786 case OMAP_DSS_COLOR_CLUT1:
1787 return 1;
1788 case OMAP_DSS_COLOR_CLUT2:
1789 return 2;
1790 case OMAP_DSS_COLOR_CLUT4:
1791 return 4;
1792 case OMAP_DSS_COLOR_CLUT8:
1793 case OMAP_DSS_COLOR_NV12:
1794 return 8;
1795 case OMAP_DSS_COLOR_RGB12U:
1796 case OMAP_DSS_COLOR_RGB16:
1797 case OMAP_DSS_COLOR_ARGB16:
1798 case OMAP_DSS_COLOR_YUV2:
1799 case OMAP_DSS_COLOR_UYVY:
1800 case OMAP_DSS_COLOR_RGBA16:
1801 case OMAP_DSS_COLOR_RGBX16:
1802 case OMAP_DSS_COLOR_ARGB16_1555:
1803 case OMAP_DSS_COLOR_XRGB16_1555:
1804 return 16;
1805 case OMAP_DSS_COLOR_RGB24P:
1806 return 24;
1807 case OMAP_DSS_COLOR_RGB24U:
1808 case OMAP_DSS_COLOR_ARGB32:
1809 case OMAP_DSS_COLOR_RGBA32:
1810 case OMAP_DSS_COLOR_RGBX32:
1811 return 32;
1812 default:
1813 BUG();
1814 return 0;
1815 }
1816 }
1818 static s32 pixinc(int pixels, u8 ps)
1819 {
1820 if (pixels == 1)
1821 return 1;
1822 else if (pixels > 1)
1823 return 1 + (pixels - 1) * ps;
1824 else if (pixels < 0)
1825 return 1 - (-pixels + 1) * ps;
1826 else
1827 BUG();
1828 return 0;
1829 }
1831 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1832 u16 screen_width,
1833 u16 width, u16 height,
1834 enum omap_color_mode color_mode, bool fieldmode,
1835 unsigned int field_offset,
1836 unsigned *offset0, unsigned *offset1,
1837 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1838 {
1839 u8 ps;
1841 /* FIXME CLUT formats */
1842 switch (color_mode) {
1843 case OMAP_DSS_COLOR_CLUT1:
1844 case OMAP_DSS_COLOR_CLUT2:
1845 case OMAP_DSS_COLOR_CLUT4:
1846 case OMAP_DSS_COLOR_CLUT8:
1847 BUG();
1848 return;
1849 case OMAP_DSS_COLOR_YUV2:
1850 case OMAP_DSS_COLOR_UYVY:
1851 ps = 4;
1852 break;
1853 default:
1854 ps = color_mode_to_bpp(color_mode) / 8;
1855 break;
1856 }
1858 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1859 width, height);
1861 /*
1862 * field 0 = even field = bottom field
1863 * field 1 = odd field = top field
1864 */
1865 switch (rotation + mirror * 4) {
1866 case OMAP_DSS_ROT_0:
1867 case OMAP_DSS_ROT_180:
1868 /*
1869 * If the pixel format is YUV or UYVY divide the width
1870 * of the image by 2 for 0 and 180 degree rotation.
1871 */
1872 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1873 color_mode == OMAP_DSS_COLOR_UYVY)
1874 width = width >> 1;
1875 case OMAP_DSS_ROT_90:
1876 case OMAP_DSS_ROT_270:
1877 *offset1 = 0;
1878 if (field_offset)
1879 *offset0 = field_offset * screen_width * ps;
1880 else
1881 *offset0 = 0;
1883 *row_inc = pixinc(1 +
1884 (y_predecim * screen_width - x_predecim * width) +
1885 (fieldmode ? screen_width : 0), ps);
1886 *pix_inc = pixinc(x_predecim, ps);
1887 break;
1889 case OMAP_DSS_ROT_0 + 4:
1890 case OMAP_DSS_ROT_180 + 4:
1891 /* If the pixel format is YUV or UYVY divide the width
1892 * of the image by 2 for 0 degree and 180 degree
1893 */
1894 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1895 color_mode == OMAP_DSS_COLOR_UYVY)
1896 width = width >> 1;
1897 case OMAP_DSS_ROT_90 + 4:
1898 case OMAP_DSS_ROT_270 + 4:
1899 *offset1 = 0;
1900 if (field_offset)
1901 *offset0 = field_offset * screen_width * ps;
1902 else
1903 *offset0 = 0;
1904 *row_inc = pixinc(1 -
1905 (y_predecim * screen_width + x_predecim * width) -
1906 (fieldmode ? screen_width : 0), ps);
1907 *pix_inc = pixinc(x_predecim, ps);
1908 break;
1910 default:
1911 BUG();
1912 return;
1913 }
1914 }
1916 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1917 u16 screen_width,
1918 u16 width, u16 height,
1919 enum omap_color_mode color_mode, bool fieldmode,
1920 unsigned int field_offset,
1921 unsigned *offset0, unsigned *offset1,
1922 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1923 {
1924 u8 ps;
1925 u16 fbw, fbh;
1927 /* FIXME CLUT formats */
1928 switch (color_mode) {
1929 case OMAP_DSS_COLOR_CLUT1:
1930 case OMAP_DSS_COLOR_CLUT2:
1931 case OMAP_DSS_COLOR_CLUT4:
1932 case OMAP_DSS_COLOR_CLUT8:
1933 BUG();
1934 return;
1935 default:
1936 ps = color_mode_to_bpp(color_mode) / 8;
1937 break;
1938 }
1940 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1941 width, height);
1943 /* width & height are overlay sizes, convert to fb sizes */
1945 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1946 fbw = width;
1947 fbh = height;
1948 } else {
1949 fbw = height;
1950 fbh = width;
1951 }
1953 /*
1954 * field 0 = even field = bottom field
1955 * field 1 = odd field = top field
1956 */
1957 switch (rotation + mirror * 4) {
1958 case OMAP_DSS_ROT_0:
1959 *offset1 = 0;
1960 if (field_offset)
1961 *offset0 = *offset1 + field_offset * screen_width * ps;
1962 else
1963 *offset0 = *offset1;
1964 *row_inc = pixinc(1 +
1965 (y_predecim * screen_width - fbw * x_predecim) +
1966 (fieldmode ? screen_width : 0), ps);
1967 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1968 color_mode == OMAP_DSS_COLOR_UYVY)
1969 *pix_inc = pixinc(x_predecim, 2 * ps);
1970 else
1971 *pix_inc = pixinc(x_predecim, ps);
1972 break;
1973 case OMAP_DSS_ROT_90:
1974 *offset1 = screen_width * (fbh - 1) * ps;
1975 if (field_offset)
1976 *offset0 = *offset1 + field_offset * ps;
1977 else
1978 *offset0 = *offset1;
1979 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
1980 y_predecim + (fieldmode ? 1 : 0), ps);
1981 *pix_inc = pixinc(-x_predecim * screen_width, ps);
1982 break;
1983 case OMAP_DSS_ROT_180:
1984 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1985 if (field_offset)
1986 *offset0 = *offset1 - field_offset * screen_width * ps;
1987 else
1988 *offset0 = *offset1;
1989 *row_inc = pixinc(-1 -
1990 (y_predecim * screen_width - fbw * x_predecim) -
1991 (fieldmode ? screen_width : 0), ps);
1992 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1993 color_mode == OMAP_DSS_COLOR_UYVY)
1994 *pix_inc = pixinc(-x_predecim, 2 * ps);
1995 else
1996 *pix_inc = pixinc(-x_predecim, ps);
1997 break;
1998 case OMAP_DSS_ROT_270:
1999 *offset1 = (fbw - 1) * ps;
2000 if (field_offset)
2001 *offset0 = *offset1 - field_offset * ps;
2002 else
2003 *offset0 = *offset1;
2004 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
2005 y_predecim - (fieldmode ? 1 : 0), ps);
2006 *pix_inc = pixinc(x_predecim * screen_width, ps);
2007 break;
2009 /* mirroring */
2010 case OMAP_DSS_ROT_0 + 4:
2011 *offset1 = (fbw - 1) * ps;
2012 if (field_offset)
2013 *offset0 = *offset1 + field_offset * screen_width * ps;
2014 else
2015 *offset0 = *offset1;
2016 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
2017 (fieldmode ? screen_width : 0),
2018 ps);
2019 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2020 color_mode == OMAP_DSS_COLOR_UYVY)
2021 *pix_inc = pixinc(-x_predecim, 2 * ps);
2022 else
2023 *pix_inc = pixinc(-x_predecim, ps);
2024 break;
2026 case OMAP_DSS_ROT_90 + 4:
2027 *offset1 = 0;
2028 if (field_offset)
2029 *offset0 = *offset1 + field_offset * ps;
2030 else
2031 *offset0 = *offset1;
2032 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
2033 y_predecim + (fieldmode ? 1 : 0),
2034 ps);
2035 *pix_inc = pixinc(x_predecim * screen_width, ps);
2036 break;
2038 case OMAP_DSS_ROT_180 + 4:
2039 *offset1 = screen_width * (fbh - 1) * ps;
2040 if (field_offset)
2041 *offset0 = *offset1 - field_offset * screen_width * ps;
2042 else
2043 *offset0 = *offset1;
2044 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
2045 (fieldmode ? screen_width : 0),
2046 ps);
2047 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2048 color_mode == OMAP_DSS_COLOR_UYVY)
2049 *pix_inc = pixinc(x_predecim, 2 * ps);
2050 else
2051 *pix_inc = pixinc(x_predecim, ps);
2052 break;
2054 case OMAP_DSS_ROT_270 + 4:
2055 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
2056 if (field_offset)
2057 *offset0 = *offset1 - field_offset * ps;
2058 else
2059 *offset0 = *offset1;
2060 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
2061 y_predecim - (fieldmode ? 1 : 0),
2062 ps);
2063 *pix_inc = pixinc(-x_predecim * screen_width, ps);
2064 break;
2066 default:
2067 BUG();
2068 return;
2069 }
2070 }
2072 static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
2073 enum omap_color_mode color_mode, bool fieldmode,
2074 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
2075 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
2076 {
2077 u8 ps;
2079 switch (color_mode) {
2080 case OMAP_DSS_COLOR_CLUT1:
2081 case OMAP_DSS_COLOR_CLUT2:
2082 case OMAP_DSS_COLOR_CLUT4:
2083 case OMAP_DSS_COLOR_CLUT8:
2084 BUG();
2085 return;
2086 default:
2087 ps = color_mode_to_bpp(color_mode) / 8;
2088 break;
2089 }
2091 DSSDBG("scrw %d, width %d\n", screen_width, width);
2093 /*
2094 * field 0 = even field = bottom field
2095 * field 1 = odd field = top field
2096 */
2097 *offset1 = 0;
2098 if (field_offset)
2099 *offset0 = *offset1 + field_offset * screen_width * ps;
2100 else
2101 *offset0 = *offset1;
2102 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
2103 (fieldmode ? screen_width : 0), ps);
2104 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2105 color_mode == OMAP_DSS_COLOR_UYVY)
2106 *pix_inc = pixinc(x_predecim, 2 * ps);
2107 else
2108 *pix_inc = pixinc(x_predecim, ps);
2109 }
2111 /*
2112 * This function is used to avoid synclosts in OMAP3, because of some
2113 * undocumented horizontal position and timing related limitations.
2114 */
2115 static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
2116 const struct omap_video_timings *t, u16 pos_x,
2117 u16 width, u16 height, u16 out_width, u16 out_height,
2118 bool five_taps)
2119 {
2120 const int ds = DIV_ROUND_UP(height, out_height);
2121 unsigned long nonactive;
2122 static const u8 limits[3] = { 8, 10, 20 };
2123 u64 val, blank;
2124 int i;
2126 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
2128 i = 0;
2129 if (out_height < height)
2130 i++;
2131 if (out_width < width)
2132 i++;
2133 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
2134 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2135 if (blank <= limits[i])
2136 return -EINVAL;
2138 /* FIXME add checks for 3-tap filter once the limitations are known */
2139 if (!five_taps)
2140 return 0;
2142 /*
2143 * Pixel data should be prepared before visible display point starts.
2144 * So, atleast DS-2 lines must have already been fetched by DISPC
2145 * during nonactive - pos_x period.
2146 */
2147 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2148 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
2149 val, max(0, ds - 2) * width);
2150 if (val < max(0, ds - 2) * width)
2151 return -EINVAL;
2153 /*
2154 * All lines need to be refilled during the nonactive period of which
2155 * only one line can be loaded during the active period. So, atleast
2156 * DS - 1 lines should be loaded during nonactive period.
2157 */
2158 val = div_u64((u64)nonactive * lclk, pclk);
2159 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
2160 val, max(0, ds - 1) * width);
2161 if (val < max(0, ds - 1) * width)
2162 return -EINVAL;
2164 return 0;
2165 }
2167 static unsigned long calc_core_clk_five_taps(unsigned long pclk,
2168 const struct omap_video_timings *mgr_timings, u16 width,
2169 u16 height, u16 out_width, u16 out_height,
2170 enum omap_color_mode color_mode)
2171 {
2172 u32 core_clk = 0;
2173 u64 tmp;
2175 if (height <= out_height && width <= out_width)
2176 return (unsigned long) pclk;
2178 if (height > out_height) {
2179 unsigned int ppl = mgr_timings->x_res;
2181 tmp = (u64)pclk * height * out_width;
2182 do_div(tmp, 2 * out_height * ppl);
2183 core_clk = tmp;
2185 if (height > 2 * out_height) {
2186 if (ppl == out_width)
2187 return 0;
2189 tmp = (u64)pclk * (height - 2 * out_height) * out_width;
2190 do_div(tmp, 2 * out_height * (ppl - out_width));
2191 core_clk = max_t(u32, core_clk, tmp);
2192 }
2193 }
2195 if (width > out_width) {
2196 tmp = (u64)pclk * width;
2197 do_div(tmp, out_width);
2198 core_clk = max_t(u32, core_clk, tmp);
2200 if (color_mode == OMAP_DSS_COLOR_RGB24U)
2201 core_clk <<= 1;
2202 }
2204 return core_clk;
2205 }
2207 static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
2208 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2209 {
2210 if (height > out_height && width > out_width)
2211 return pclk * 4;
2212 else
2213 return pclk * 2;
2214 }
2216 static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
2217 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2218 {
2219 unsigned int hf, vf;
2221 /*
2222 * FIXME how to determine the 'A' factor
2223 * for the no downscaling case ?
2224 */
2226 if (width > 3 * out_width)
2227 hf = 4;
2228 else if (width > 2 * out_width)
2229 hf = 3;
2230 else if (width > out_width)
2231 hf = 2;
2232 else
2233 hf = 1;
2234 if (height > out_height)
2235 vf = 2;
2236 else
2237 vf = 1;
2239 return pclk * vf * hf;
2240 }
2242 static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
2243 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2244 {
2245 /*
2246 * If the overlay/writeback is in mem to mem mode, there are no
2247 * downscaling limitations with respect to pixel clock, return 1 as
2248 * required core clock to represent that we have sufficient enough
2249 * core clock to do maximum downscaling
2250 */
2251 if (mem_to_mem)
2252 return 1;
2254 if (width > out_width)
2255 return DIV_ROUND_UP(pclk, out_width) * width;
2256 else
2257 return pclk;
2258 }
2260 static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
2261 const struct omap_video_timings *mgr_timings,
2262 u16 width, u16 height, u16 out_width, u16 out_height,
2263 enum omap_color_mode color_mode, bool *five_taps,
2264 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2265 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2266 {
2267 int error;
2268 u16 in_width, in_height;
2269 int min_factor = min(*decim_x, *decim_y);
2270 const int maxsinglelinewidth =
2271 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2273 *five_taps = false;
2275 do {
2276 in_height = height / *decim_y;
2277 in_width = width / *decim_x;
2278 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2279 in_height, out_width, out_height, mem_to_mem);
2280 error = (in_width > maxsinglelinewidth || !*core_clk ||
2281 *core_clk > dispc_core_clk_rate());
2282 if (error) {
2283 if (*decim_x == *decim_y) {
2284 *decim_x = min_factor;
2285 ++*decim_y;
2286 } else {
2287 swap(*decim_x, *decim_y);
2288 if (*decim_x < *decim_y)
2289 ++*decim_x;
2290 }
2291 }
2292 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2294 if (error) {
2295 DSSERR("failed to find scaling settings\n");
2296 return -EINVAL;
2297 }
2299 if (in_width > maxsinglelinewidth) {
2300 DSSERR("Cannot scale max input width exceeded");
2301 return -EINVAL;
2302 }
2303 return 0;
2304 }
2306 static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
2307 const struct omap_video_timings *mgr_timings,
2308 u16 width, u16 height, u16 out_width, u16 out_height,
2309 enum omap_color_mode color_mode, bool *five_taps,
2310 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2311 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2312 {
2313 int error;
2314 u16 in_width, in_height;
2315 const int maxsinglelinewidth =
2316 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2318 do {
2319 in_height = height / *decim_y;
2320 in_width = width / *decim_x;
2321 *five_taps = in_height > out_height;
2323 if (in_width > maxsinglelinewidth)
2324 if (in_height > out_height &&
2325 in_height < out_height * 2)
2326 *five_taps = false;
2327 again:
2328 if (*five_taps)
2329 *core_clk = calc_core_clk_five_taps(pclk, mgr_timings,
2330 in_width, in_height, out_width,
2331 out_height, color_mode);
2332 else
2333 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2334 in_height, out_width, out_height,
2335 mem_to_mem);
2337 error = check_horiz_timing_omap3(pclk, lclk, mgr_timings,
2338 pos_x, in_width, in_height, out_width,
2339 out_height, *five_taps);
2340 if (error && *five_taps) {
2341 *five_taps = false;
2342 goto again;
2343 }
2345 error = (error || in_width > maxsinglelinewidth * 2 ||
2346 (in_width > maxsinglelinewidth && *five_taps) ||
2347 !*core_clk || *core_clk > dispc_core_clk_rate());
2349 if (!error) {
2350 /* verify that we're inside the limits of scaler */
2351 if (in_width / 4 > out_width)
2352 error = 1;
2354 if (*five_taps) {
2355 if (in_height / 4 > out_height)
2356 error = 1;
2357 } else {
2358 if (in_height / 2 > out_height)
2359 error = 1;
2360 }
2361 }
2363 if (error)
2364 ++*decim_y;
2365 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2367 if (error) {
2368 DSSERR("failed to find scaling settings\n");
2369 return -EINVAL;
2370 }
2372 if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, in_width,
2373 in_height, out_width, out_height, *five_taps)) {
2374 DSSERR("horizontal timing too tight\n");
2375 return -EINVAL;
2376 }
2378 if (in_width > (maxsinglelinewidth * 2)) {
2379 DSSERR("Cannot setup scaling");
2380 DSSERR("width exceeds maximum width possible");
2381 return -EINVAL;
2382 }
2384 if (in_width > maxsinglelinewidth && *five_taps) {
2385 DSSERR("cannot setup scaling with five taps");
2386 return -EINVAL;
2387 }
2388 return 0;
2389 }
2391 static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
2392 const struct omap_video_timings *mgr_timings,
2393 u16 width, u16 height, u16 out_width, u16 out_height,
2394 enum omap_color_mode color_mode, bool *five_taps,
2395 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2396 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2397 {
2398 u16 in_width, in_width_max;
2399 int decim_x_min = *decim_x;
2400 u16 in_height = height / *decim_y;
2401 const int maxsinglelinewidth =
2402 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2403 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2405 if (mem_to_mem) {
2406 in_width_max = out_width * maxdownscale;
2407 } else {
2408 in_width_max = dispc_core_clk_rate() /
2409 DIV_ROUND_UP(pclk, out_width);
2410 }
2412 *decim_x = DIV_ROUND_UP(width, in_width_max);
2414 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2415 if (*decim_x > *x_predecim)
2416 return -EINVAL;
2418 do {
2419 in_width = width / *decim_x;
2420 } while (*decim_x <= *x_predecim &&
2421 in_width > maxsinglelinewidth && ++*decim_x);
2423 if (in_width > maxsinglelinewidth) {
2424 DSSERR("Cannot scale width exceeds max line width");
2425 return -EINVAL;
2426 }
2428 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,
2429 out_width, out_height, mem_to_mem);
2430 return 0;
2431 }
2433 #define DIV_FRAC(dividend, divisor) \
2434 ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100))
2436 static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
2437 enum omap_overlay_caps caps,
2438 const struct omap_video_timings *mgr_timings,
2439 u16 width, u16 height, u16 out_width, u16 out_height,
2440 enum omap_color_mode color_mode, bool *five_taps,
2441 int *x_predecim, int *y_predecim, u16 pos_x,
2442 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
2443 {
2444 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2445 const int max_decim_limit = 16;
2446 unsigned long core_clk = 0;
2447 int decim_x, decim_y, ret;
2449 if (width == out_width && height == out_height)
2450 return 0;
2452 if (pclk == 0 || mgr_timings->pixelclock == 0) {
2453 DSSERR("cannot calculate scaling settings: pclk is zero\n");
2454 return -EINVAL;
2455 }
2457 if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
2458 return -EINVAL;
2460 if (mem_to_mem) {
2461 *x_predecim = *y_predecim = 1;
2462 } else {
2463 *x_predecim = max_decim_limit;
2464 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2465 dss_has_feature(FEAT_BURST_2D)) ?
2466 2 : max_decim_limit;
2467 }
2469 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2470 color_mode == OMAP_DSS_COLOR_CLUT2 ||
2471 color_mode == OMAP_DSS_COLOR_CLUT4 ||
2472 color_mode == OMAP_DSS_COLOR_CLUT8) {
2473 *x_predecim = 1;
2474 *y_predecim = 1;
2475 *five_taps = false;
2476 return 0;
2477 }
2479 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2480 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2482 if (decim_x > *x_predecim || out_width > width * 8)
2483 return -EINVAL;
2485 if (decim_y > *y_predecim || out_height > height * 8)
2486 return -EINVAL;
2488 ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height,
2489 out_width, out_height, color_mode, five_taps,
2490 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2491 mem_to_mem);
2492 if (ret)
2493 return ret;
2495 DSSDBG("%dx%d -> %dx%d (%d.%02d x %d.%02d), decim %dx%d %dx%d (%d.%02d x %d.%02d), taps %d, req clk %lu, cur clk %lu\n",
2496 width, height,
2497 out_width, out_height,
2498 out_width / width, DIV_FRAC(out_width, width),
2499 out_height / height, DIV_FRAC(out_height, height),
2501 decim_x, decim_y,
2502 width / decim_x, height / decim_y,
2503 out_width / (width / decim_x), DIV_FRAC(out_width, width / decim_x),
2504 out_height / (height / decim_y), DIV_FRAC(out_height, height / decim_y),
2506 *five_taps ? 5 : 3,
2507 core_clk, dispc_core_clk_rate());
2509 if (!core_clk || core_clk > dispc_core_clk_rate()) {
2510 DSSERR("failed to set up scaling, "
2511 "required core clk rate = %lu Hz, "
2512 "current core clk rate = %lu Hz\n",
2513 core_clk, dispc_core_clk_rate());
2514 return -EINVAL;
2515 }
2517 *x_predecim = decim_x;
2518 *y_predecim = decim_y;
2519 return 0;
2520 }
2522 int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
2523 const struct omap_overlay_info *oi,
2524 const struct omap_video_timings *timings,
2525 int *x_predecim, int *y_predecim)
2526 {
2527 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2528 bool five_taps = true;
2529 bool fieldmode = false;
2530 u16 in_height = oi->height;
2531 u16 in_width = oi->width;
2532 bool ilace = timings->interlace;
2533 u16 out_width, out_height;
2534 int pos_x = oi->pos_x;
2535 unsigned long pclk = dispc_mgr_pclk_rate(channel);
2536 unsigned long lclk = dispc_mgr_lclk_rate(channel);
2538 out_width = oi->out_width == 0 ? oi->width : oi->out_width;
2539 out_height = oi->out_height == 0 ? oi->height : oi->out_height;
2541 if (ilace && oi->height == out_height)
2542 fieldmode = true;
2544 if (ilace) {
2545 if (fieldmode)
2546 in_height /= 2;
2547 out_height /= 2;
2549 DSSDBG("adjusting for ilace: height %d, out_height %d\n",
2550 in_height, out_height);
2551 }
2553 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
2554 return -EINVAL;
2556 return dispc_ovl_calc_scaling(pclk, lclk, caps, timings, in_width,
2557 in_height, out_width, out_height, oi->color_mode,
2558 &five_taps, x_predecim, y_predecim, pos_x,
2559 oi->rotation_type, false);
2560 }
2561 EXPORT_SYMBOL(dispc_ovl_check);
2563 static int dispc_ovl_setup_common(enum omap_plane plane,
2564 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2565 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2566 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2567 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2568 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
2569 bool replication, const struct omap_video_timings *mgr_timings,
2570 bool mem_to_mem)
2571 {
2572 bool five_taps = true;
2573 bool fieldmode = false;
2574 int r, cconv = 0;
2575 unsigned offset0, offset1;
2576 s32 row_inc;
2577 s32 pix_inc;
2578 u16 frame_width, frame_height;
2579 unsigned int field_offset = 0;
2580 u16 in_height = height;
2581 u16 in_width = width;
2582 int x_predecim = 1, y_predecim = 1;
2583 bool ilace = mgr_timings->interlace;
2584 unsigned long pclk = dispc_plane_pclk_rate(plane);
2585 unsigned long lclk = dispc_plane_lclk_rate(plane);
2587 if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER)
2588 return -EINVAL;
2590 switch (color_mode) {
2591 case OMAP_DSS_COLOR_YUV2:
2592 case OMAP_DSS_COLOR_UYVY:
2593 case OMAP_DSS_COLOR_NV12:
2594 if (in_width & 1) {
2595 DSSERR("input width %d is not even for YUV format\n",
2596 in_width);
2597 return -EINVAL;
2598 }
2599 break;
2601 default:
2602 break;
2603 }
2605 out_width = out_width == 0 ? width : out_width;
2606 out_height = out_height == 0 ? height : out_height;
2608 if (ilace && height == out_height)
2609 fieldmode = true;
2611 if (ilace) {
2612 if (fieldmode)
2613 in_height /= 2;
2614 pos_y /= 2;
2615 out_height /= 2;
2617 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
2618 "out_height %d\n", in_height, pos_y,
2619 out_height);
2620 }
2622 if (!dss_feat_color_mode_supported(plane, color_mode))
2623 return -EINVAL;
2625 r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width,
2626 in_height, out_width, out_height, color_mode,
2627 &five_taps, &x_predecim, &y_predecim, pos_x,
2628 rotation_type, mem_to_mem);
2629 if (r)
2630 return r;
2632 in_width = in_width / x_predecim;
2633 in_height = in_height / y_predecim;
2635 if (x_predecim > 1 || y_predecim > 1)
2636 DSSDBG("predecimation %d x %x, new input size %d x %d\n",
2637 x_predecim, y_predecim, in_width, in_height);
2639 switch (color_mode) {
2640 case OMAP_DSS_COLOR_YUV2:
2641 case OMAP_DSS_COLOR_UYVY:
2642 case OMAP_DSS_COLOR_NV12:
2643 if (in_width & 1) {
2644 DSSDBG("predecimated input width is not even for YUV format\n");
2645 DSSDBG("adjusting input width %d -> %d\n",
2646 in_width, in_width & ~1);
2648 in_width &= ~1;
2649 }
2650 break;
2652 default:
2653 break;
2654 }
2656 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2657 color_mode == OMAP_DSS_COLOR_UYVY ||
2658 color_mode == OMAP_DSS_COLOR_NV12)
2659 cconv = 1;
2661 if (ilace && !fieldmode) {
2662 /*
2663 * when downscaling the bottom field may have to start several
2664 * source lines below the top field. Unfortunately ACCUI
2665 * registers will only hold the fractional part of the offset
2666 * so the integer part must be added to the base address of the
2667 * bottom field.
2668 */
2669 if (!in_height || in_height == out_height)
2670 field_offset = 0;
2671 else
2672 field_offset = in_height / out_height / 2;
2673 }
2675 /* Fields are independent but interleaved in memory. */
2676 if (fieldmode)
2677 field_offset = 1;
2679 offset0 = 0;
2680 offset1 = 0;
2681 row_inc = 0;
2682 pix_inc = 0;
2684 if (plane == OMAP_DSS_WB) {
2685 frame_width = out_width;
2686 frame_height = out_height;
2687 } else {
2688 frame_width = in_width;
2689 frame_height = height;
2690 }
2692 if (rotation_type == OMAP_DSS_ROT_TILER)
2693 calc_tiler_rotation_offset(screen_width, frame_width,
2694 color_mode, fieldmode, field_offset,
2695 &offset0, &offset1, &row_inc, &pix_inc,
2696 x_predecim, y_predecim);
2697 else if (rotation_type == OMAP_DSS_ROT_DMA)
2698 calc_dma_rotation_offset(rotation, mirror, screen_width,
2699 frame_width, frame_height,
2700 color_mode, fieldmode, field_offset,
2701 &offset0, &offset1, &row_inc, &pix_inc,
2702 x_predecim, y_predecim);
2703 else
2704 calc_vrfb_rotation_offset(rotation, mirror,
2705 screen_width, frame_width, frame_height,
2706 color_mode, fieldmode, field_offset,
2707 &offset0, &offset1, &row_inc, &pix_inc,
2708 x_predecim, y_predecim);
2710 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2711 offset0, offset1, row_inc, pix_inc);
2713 dispc_ovl_set_color_mode(plane, color_mode);
2715 dispc_ovl_configure_burst_type(plane, rotation_type);
2717 dispc_ovl_set_ba0(plane, paddr + offset0);
2718 dispc_ovl_set_ba1(plane, paddr + offset1);
2720 if (OMAP_DSS_COLOR_NV12 == color_mode) {
2721 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2722 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
2723 }
2725 if (dispc.feat->last_pixel_inc_missing)
2726 row_inc += pix_inc - 1;
2728 dispc_ovl_set_row_inc(plane, row_inc);
2729 dispc_ovl_set_pix_inc(plane, pix_inc);
2731 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
2732 in_height, out_width, out_height);
2734 dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
2736 dispc_ovl_set_input_size(plane, in_width, in_height);
2738 if (caps & OMAP_DSS_OVL_CAP_SCALE) {
2739 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2740 out_height, ilace, five_taps, fieldmode,
2741 color_mode, rotation);
2742 dispc_ovl_set_output_size(plane, out_width, out_height);
2743 dispc_ovl_set_vid_color_conv(plane, cconv);
2744 }
2746 dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror,
2747 color_mode);
2749 dispc_ovl_set_zorder(plane, caps, zorder);
2750 dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2751 dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
2753 dispc_ovl_enable_replication(plane, caps, replication);
2755 return 0;
2756 }
2758 int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
2759 bool replication, const struct omap_video_timings *mgr_timings,
2760 bool mem_to_mem)
2761 {
2762 int r;
2763 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2764 enum omap_channel channel;
2766 channel = dispc_ovl_get_channel_out(plane);
2768 DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->"
2769 " %dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2770 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x,
2771 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2772 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2774 r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
2775 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2776 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2777 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
2778 oi->rotation_type, replication, mgr_timings, mem_to_mem);
2780 return r;
2781 }
2782 EXPORT_SYMBOL(dispc_ovl_setup);
2784 int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
2785 bool mem_to_mem, const struct omap_video_timings *mgr_timings)
2786 {
2787 int r;
2788 u32 l;
2789 enum omap_plane plane = OMAP_DSS_WB;
2790 const int pos_x = 0, pos_y = 0;
2791 const u8 zorder = 0, global_alpha = 0;
2792 const bool replication = false;
2793 bool truncation;
2794 int in_width = mgr_timings->x_res;
2795 int in_height = mgr_timings->y_res;
2796 enum omap_overlay_caps caps =
2797 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2799 DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2800 "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width,
2801 in_height, wi->width, wi->height, wi->color_mode, wi->rotation,
2802 wi->mirror);
2804 r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
2805 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2806 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
2807 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
2808 replication, mgr_timings, mem_to_mem);
2810 switch (wi->color_mode) {
2811 case OMAP_DSS_COLOR_RGB16:
2812 case OMAP_DSS_COLOR_RGB24P:
2813 case OMAP_DSS_COLOR_ARGB16:
2814 case OMAP_DSS_COLOR_RGBA16:
2815 case OMAP_DSS_COLOR_RGB12U:
2816 case OMAP_DSS_COLOR_ARGB16_1555:
2817 case OMAP_DSS_COLOR_XRGB16_1555:
2818 case OMAP_DSS_COLOR_RGBX16:
2819 truncation = true;
2820 break;
2821 default:
2822 truncation = false;
2823 break;
2824 }
2826 /* setup extra DISPC_WB_ATTRIBUTES */
2827 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2828 l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */
2829 l = FLD_MOD(l, mem_to_mem, 19, 19); /* WRITEBACKMODE */
2830 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
2832 return r;
2833 }
2835 int dispc_ovl_enable(enum omap_plane plane, bool enable)
2836 {
2837 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2839 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
2841 return 0;
2842 }
2843 EXPORT_SYMBOL(dispc_ovl_enable);
2845 bool dispc_ovl_enabled(enum omap_plane plane)
2846 {
2847 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2848 }
2849 EXPORT_SYMBOL(dispc_ovl_enabled);
2851 void dispc_mgr_enable(enum omap_channel channel, bool enable)
2852 {
2853 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2854 /* flush posted write */
2855 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2856 }
2857 EXPORT_SYMBOL(dispc_mgr_enable);
2859 bool dispc_mgr_is_enabled(enum omap_channel channel)
2860 {
2861 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2862 }
2863 EXPORT_SYMBOL(dispc_mgr_is_enabled);
2865 void dispc_wb_enable(bool enable)
2866 {
2867 dispc_ovl_enable(OMAP_DSS_WB, enable);
2868 }
2870 bool dispc_wb_is_enabled(void)
2871 {
2872 return dispc_ovl_enabled(OMAP_DSS_WB);
2873 }
2875 static void dispc_lcd_enable_signal_polarity(bool act_high)
2876 {
2877 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2878 return;
2880 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2881 }
2883 void dispc_lcd_enable_signal(bool enable)
2884 {
2885 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2886 return;
2888 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2889 }
2891 void dispc_pck_free_enable(bool enable)
2892 {
2893 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2894 return;
2896 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2897 }
2899 static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2900 {
2901 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
2902 }
2905 static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
2906 {
2907 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
2908 }
2910 void dispc_set_loadmode(enum omap_dss_load_mode mode)
2911 {
2912 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2913 }
2916 static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
2917 {
2918 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2919 }
2921 static void dispc_mgr_set_trans_key(enum omap_channel ch,
2922 enum omap_dss_trans_key_type type,
2923 u32 trans_key)
2924 {
2925 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
2927 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2928 }
2930 static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2931 {
2932 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
2933 }
2935 static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2936 bool enable)
2937 {
2938 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2939 return;
2941 if (ch == OMAP_DSS_CHANNEL_LCD)
2942 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2943 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2944 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2945 }
2947 void dispc_mgr_setup(enum omap_channel channel,
2948 const struct omap_overlay_manager_info *info)
2949 {
2950 dispc_mgr_set_default_color(channel, info->default_color);
2951 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2952 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2953 dispc_mgr_enable_alpha_fixed_zorder(channel,
2954 info->partial_alpha_enabled);
2955 if (dss_has_feature(FEAT_CPR)) {
2956 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2957 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2958 }
2959 }
2960 EXPORT_SYMBOL(dispc_mgr_setup);
2962 static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2963 {
2964 int code;
2966 switch (data_lines) {
2967 case 12:
2968 code = 0;
2969 break;
2970 case 16:
2971 code = 1;
2972 break;
2973 case 18:
2974 code = 2;
2975 break;
2976 case 24:
2977 code = 3;
2978 break;
2979 default:
2980 BUG();
2981 return;
2982 }
2984 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
2985 }
2987 static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
2988 {
2989 u32 l;
2990 int gpout0, gpout1;
2992 switch (mode) {
2993 case DSS_IO_PAD_MODE_RESET:
2994 gpout0 = 0;
2995 gpout1 = 0;
2996 break;
2997 case DSS_IO_PAD_MODE_RFBI:
2998 gpout0 = 1;
2999 gpout1 = 0;
3000 break;
3001 case DSS_IO_PAD_MODE_BYPASS:
3002 gpout0 = 1;
3003 gpout1 = 1;
3004 break;
3005 default:
3006 BUG();
3007 return;
3008 }
3010 l = dispc_read_reg(DISPC_CONTROL);
3011 l = FLD_MOD(l, gpout0, 15, 15);
3012 l = FLD_MOD(l, gpout1, 16, 16);
3013 dispc_write_reg(DISPC_CONTROL, l);
3014 }
3016 static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
3017 {
3018 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
3019 }
3021 void dispc_mgr_set_lcd_config(enum omap_channel channel,
3022 const struct dss_lcd_mgr_config *config)
3023 {
3024 dispc_mgr_set_io_pad_mode(config->io_pad_mode);
3026 dispc_mgr_enable_stallmode(channel, config->stallmode);
3027 dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
3029 dispc_mgr_set_clock_div(channel, &config->clock_info);
3031 dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
3033 dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
3035 dispc_mgr_set_lcd_type_tft(channel);
3036 }
3037 EXPORT_SYMBOL(dispc_mgr_set_lcd_config);
3039 static bool _dispc_mgr_size_ok(u16 width, u16 height)
3040 {
3041 return width <= dispc.feat->mgr_width_max &&
3042 height <= dispc.feat->mgr_height_max;
3043 }
3045 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
3046 int vsw, int vfp, int vbp)
3047 {
3048 if (hsw < 1 || hsw > dispc.feat->sw_max ||
3049 hfp < 1 || hfp > dispc.feat->hp_max ||
3050 hbp < 1 || hbp > dispc.feat->hp_max ||
3051 vsw < 1 || vsw > dispc.feat->sw_max ||
3052 vfp < 0 || vfp > dispc.feat->vp_max ||
3053 vbp < 0 || vbp > dispc.feat->vp_max)
3054 return false;
3055 return true;
3056 }
3058 static bool _dispc_mgr_pclk_ok(enum omap_channel channel,
3059 unsigned long pclk)
3060 {
3061 if (dss_mgr_is_lcd(channel))
3062 return pclk <= dispc.feat->max_lcd_pclk ? true : false;
3063 else
3064 return pclk <= dispc.feat->max_tv_pclk ? true : false;
3065 }
3067 bool dispc_mgr_timings_ok(enum omap_channel channel,
3068 const struct omap_video_timings *timings)
3069 {
3070 if (!_dispc_mgr_size_ok(timings->x_res, timings->y_res))
3071 return false;
3073 if (!_dispc_mgr_pclk_ok(channel, timings->pixelclock))
3074 return false;
3076 if (dss_mgr_is_lcd(channel)) {
3077 /* TODO: OMAP4+ supports interlace for LCD outputs */
3078 if (timings->interlace)
3079 return false;
3081 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
3082 timings->hbp, timings->vsw, timings->vfp,
3083 timings->vbp))
3084 return false;
3085 }
3087 return true;
3088 }
3090 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
3091 int hfp, int hbp, int vsw, int vfp, int vbp,
3092 enum omap_dss_signal_level vsync_level,
3093 enum omap_dss_signal_level hsync_level,
3094 enum omap_dss_signal_edge data_pclk_edge,
3095 enum omap_dss_signal_level de_level,
3096 enum omap_dss_signal_edge sync_pclk_edge)
3098 {
3099 u32 timing_h, timing_v, l;
3100 bool onoff, rf, ipc, vs, hs, de;
3102 timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
3103 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
3104 FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
3105 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
3106 FLD_VAL(vfp, dispc.feat->fp_start, 8) |
3107 FLD_VAL(vbp, dispc.feat->bp_start, 20);
3109 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
3110 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
3112 switch (vsync_level) {
3113 case OMAPDSS_SIG_ACTIVE_LOW:
3114 vs = true;
3115 break;
3116 case OMAPDSS_SIG_ACTIVE_HIGH:
3117 vs = false;
3118 break;
3119 default:
3120 BUG();
3121 }
3123 switch (hsync_level) {
3124 case OMAPDSS_SIG_ACTIVE_LOW:
3125 hs = true;
3126 break;
3127 case OMAPDSS_SIG_ACTIVE_HIGH:
3128 hs = false;
3129 break;
3130 default:
3131 BUG();
3132 }
3134 switch (de_level) {
3135 case OMAPDSS_SIG_ACTIVE_LOW:
3136 de = true;
3137 break;
3138 case OMAPDSS_SIG_ACTIVE_HIGH:
3139 de = false;
3140 break;
3141 default:
3142 BUG();
3143 }
3145 switch (data_pclk_edge) {
3146 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3147 ipc = false;
3148 break;
3149 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3150 ipc = true;
3151 break;
3152 default:
3153 BUG();
3154 }
3156 /* always use the 'rf' setting */
3157 onoff = true;
3159 switch (sync_pclk_edge) {
3160 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3161 rf = false;
3162 break;
3163 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3164 rf = true;
3165 break;
3166 default:
3167 BUG();
3168 }
3170 l = FLD_VAL(onoff, 17, 17) |
3171 FLD_VAL(rf, 16, 16) |
3172 FLD_VAL(de, 15, 15) |
3173 FLD_VAL(ipc, 14, 14) |
3174 FLD_VAL(hs, 13, 13) |
3175 FLD_VAL(vs, 12, 12);
3177 dispc_write_reg(DISPC_POL_FREQ(channel), l);
3179 if (dispc.feat->has_ctrl_core_sma_sw_1) {
3180 const int shifts[] = {
3181 [OMAP_DSS_CHANNEL_LCD] = 0,
3182 [OMAP_DSS_CHANNEL_LCD2] = 1,
3183 [OMAP_DSS_CHANNEL_LCD3] = 2,
3184 };
3186 u32 mask, val;
3188 mask = (1 << 0) | (1 << 3) | (1 << 6);
3189 val = (rf << 0) | (ipc << 3) | (onoff << 6);
3191 mask <<= 16 + shifts[channel];
3192 val <<= 16 + shifts[channel];
3194 regmap_update_bits(dispc.syscon, CTRL_CORE_SMA_SW_1, mask, val);
3195 }
3196 }
3198 /* change name to mode? */
3199 void dispc_mgr_set_timings(enum omap_channel channel,
3200 const struct omap_video_timings *timings)
3201 {
3202 unsigned xtot, ytot;
3203 unsigned long ht, vt;
3204 struct omap_video_timings t = *timings;
3206 DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
3208 if (!dispc_mgr_timings_ok(channel, &t)) {
3209 BUG();
3210 return;
3211 }
3213 if (dss_mgr_is_lcd(channel)) {
3214 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
3215 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
3216 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
3218 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
3219 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
3221 ht = timings->pixelclock / xtot;
3222 vt = timings->pixelclock / xtot / ytot;
3224 DSSDBG("pck %u\n", timings->pixelclock);
3225 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
3226 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
3227 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
3228 t.vsync_level, t.hsync_level, t.data_pclk_edge,
3229 t.de_level, t.sync_pclk_edge);
3231 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
3232 } else {
3233 if (t.interlace == true)
3234 t.y_res /= 2;
3235 }
3237 dispc_mgr_set_size(channel, t.x_res, t.y_res);
3238 }
3239 EXPORT_SYMBOL(dispc_mgr_set_timings);
3241 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
3242 u16 pck_div)
3243 {
3244 BUG_ON(lck_div < 1);
3245 BUG_ON(pck_div < 1);
3247 dispc_write_reg(DISPC_DIVISORo(channel),
3248 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
3250 if (dss_has_feature(FEAT_CORE_CLK_DIV) == false &&
3251 channel == OMAP_DSS_CHANNEL_LCD)
3252 dispc.core_clk_rate = dispc_fclk_rate() / lck_div;
3253 }
3255 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
3256 int *pck_div)
3257 {
3258 u32 l;
3259 l = dispc_read_reg(DISPC_DIVISORo(channel));
3260 *lck_div = FLD_GET(l, 23, 16);
3261 *pck_div = FLD_GET(l, 7, 0);
3262 }
3264 unsigned long dispc_fclk_rate(void)
3265 {
3266 struct pll_data *pll;
3267 unsigned long r = 0;
3269 switch (dss_get_dispc_clk_source()) {
3270 case OMAP_DSS_CLK_SRC_FCK:
3271 r = dss_get_dispc_clk_rate();
3272 break;
3274 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3275 if (dispc.feat->alt_clk_dsi_pll)
3276 pll = dsi_get_pll_data_from_id(0);
3277 else
3278 pll = dss_dpll_get_pll_data(0);
3280 r = pll_get_hsdiv_rate(pll, 0);
3281 break;
3283 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3284 if (dispc.feat->alt_clk_dsi_pll)
3285 pll = dsi_get_pll_data_from_id(1);
3286 else
3287 pll = dss_dpll_get_pll_data(1);
3289 r = pll_get_hsdiv_rate(pll, 0);
3290 break;
3292 default:
3293 return 0;
3294 }
3296 return r;
3297 }
3299 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
3300 {
3301 struct pll_data *pll;
3302 int lcd;
3303 unsigned long r;
3304 u32 l;
3306 if (dss_mgr_is_lcd(channel)) {
3307 l = dispc_read_reg(DISPC_DIVISORo(channel));
3309 lcd = FLD_GET(l, 23, 16);
3311 switch (dss_get_lcd_clk_source(channel)) {
3312 case OMAP_DSS_CLK_SRC_FCK:
3313 r = dss_get_dispc_clk_rate();
3314 break;
3316 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3317 if (dispc.feat->alt_clk_dsi_pll)
3318 pll = dsi_get_pll_data_from_id(0);
3319 else
3320 pll = dss_dpll_get_pll_data(0);
3322 r = pll_get_hsdiv_rate(pll, 0);
3323 break;
3325 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3326 if (dispc.feat->alt_clk_dsi_pll)
3327 pll = dsi_get_pll_data_from_id(1);
3328 else
3329 pll = dss_dpll_get_pll_data(1);
3331 r = pll_get_hsdiv_rate(pll, 0);
3332 break;
3334 default:
3335 return 0;
3336 }
3338 return r / lcd;
3339 } else {
3340 return dispc_fclk_rate();
3341 }
3342 }
3344 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
3345 {
3346 unsigned long r;
3348 if (dss_mgr_is_lcd(channel)) {
3349 int pcd;
3350 u32 l;
3352 l = dispc_read_reg(DISPC_DIVISORo(channel));
3354 pcd = FLD_GET(l, 7, 0);
3356 r = dispc_mgr_lclk_rate(channel);
3358 return r / pcd;
3359 } else {
3360 return dispc.tv_pclk_rate;
3361 }
3362 }
3364 void dispc_set_tv_pclk(unsigned long pclk)
3365 {
3366 dispc.tv_pclk_rate = pclk;
3367 }
3369 unsigned long dispc_core_clk_rate(void)
3370 {
3371 return dispc.core_clk_rate;
3372 }
3374 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3375 {
3376 enum omap_channel channel;
3378 if (plane == OMAP_DSS_WB)
3379 return 0;
3381 channel = dispc_ovl_get_channel_out(plane);
3383 return dispc_mgr_pclk_rate(channel);
3384 }
3386 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
3387 {
3388 enum omap_channel channel;
3390 if (plane == OMAP_DSS_WB)
3391 return 0;
3393 channel = dispc_ovl_get_channel_out(plane);
3395 return dispc_mgr_lclk_rate(channel);
3396 }
3398 static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
3399 {
3400 int lcd, pcd;
3401 enum omap_dss_clk_source lcd_clk_src;
3403 seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3405 lcd_clk_src = dss_get_lcd_clk_source(channel);
3407 seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
3408 dss_get_generic_clk_source_name(lcd_clk_src),
3409 dss_feat_get_clk_source_name(lcd_clk_src));
3411 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3413 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3414 dispc_mgr_lclk_rate(channel), lcd);
3415 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3416 dispc_mgr_pclk_rate(channel), pcd);
3417 }
3419 void dispc_dump_clocks(struct seq_file *s)
3420 {
3421 int lcd;
3422 u32 l;
3423 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
3425 if (dispc_runtime_get())
3426 return;
3428 seq_printf(s, "- DISPC -\n");
3430 seq_printf(s, "dispc fclk source = %s (%s)\n",
3431 dss_get_generic_clk_source_name(dispc_clk_src),
3432 dss_feat_get_clk_source_name(dispc_clk_src));
3434 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
3436 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3437 seq_printf(s, "- DISPC-CORE-CLK -\n");
3438 l = dispc_read_reg(DISPC_DIVISOR);
3439 lcd = FLD_GET(l, 23, 16);
3441 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3442 (dispc_fclk_rate()/lcd), lcd);
3443 }
3445 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
3447 if (dss_has_feature(FEAT_MGR_LCD2))
3448 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3449 if (dss_has_feature(FEAT_MGR_LCD3))
3450 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
3452 dispc_runtime_put();
3453 }
3455 static void dispc_dump_regs(struct seq_file *s)
3456 {
3457 int i, j;
3458 const char *mgr_names[] = {
3459 [OMAP_DSS_CHANNEL_LCD] = "LCD",
3460 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
3461 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
3462 [OMAP_DSS_CHANNEL_LCD3] = "LCD3",
3463 };
3464 const char *ovl_names[] = {
3465 [OMAP_DSS_GFX] = "GFX",
3466 [OMAP_DSS_VIDEO1] = "VID1",
3467 [OMAP_DSS_VIDEO2] = "VID2",
3468 [OMAP_DSS_VIDEO3] = "VID3",
3469 };
3470 const char **p_names;
3472 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
3474 if (dispc_runtime_get())
3475 return;
3477 /* DISPC common registers */
3478 DUMPREG(DISPC_REVISION);
3479 DUMPREG(DISPC_SYSCONFIG);
3480 DUMPREG(DISPC_SYSSTATUS);
3481 DUMPREG(DISPC_IRQSTATUS);
3482 DUMPREG(DISPC_IRQENABLE);
3483 DUMPREG(DISPC_CONTROL);
3484 DUMPREG(DISPC_CONFIG);
3485 DUMPREG(DISPC_CAPABLE);
3486 DUMPREG(DISPC_LINE_STATUS);
3487 DUMPREG(DISPC_LINE_NUMBER);
3488 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3489 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
3490 DUMPREG(DISPC_GLOBAL_ALPHA);
3491 if (dss_has_feature(FEAT_MGR_LCD2)) {
3492 DUMPREG(DISPC_CONTROL2);
3493 DUMPREG(DISPC_CONFIG2);
3494 }
3495 if (dss_has_feature(FEAT_MGR_LCD3)) {
3496 DUMPREG(DISPC_CONTROL3);
3497 DUMPREG(DISPC_CONFIG3);
3498 }
3499 if (dss_has_feature(FEAT_MFLAG))
3500 DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE);
3502 #undef DUMPREG
3504 #define DISPC_REG(i, name) name(i)
3505 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
3506 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
3507 dispc_read_reg(DISPC_REG(i, r)))
3509 p_names = mgr_names;
3511 /* DISPC channel specific registers */
3512 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3513 DUMPREG(i, DISPC_DEFAULT_COLOR);
3514 DUMPREG(i, DISPC_TRANS_COLOR);
3515 DUMPREG(i, DISPC_SIZE_MGR);
3517 if (i == OMAP_DSS_CHANNEL_DIGIT)
3518 continue;
3520 DUMPREG(i, DISPC_TIMING_H);
3521 DUMPREG(i, DISPC_TIMING_V);
3522 DUMPREG(i, DISPC_POL_FREQ);
3523 DUMPREG(i, DISPC_DIVISORo);
3525 DUMPREG(i, DISPC_DATA_CYCLE1);
3526 DUMPREG(i, DISPC_DATA_CYCLE2);
3527 DUMPREG(i, DISPC_DATA_CYCLE3);
3529 if (dss_has_feature(FEAT_CPR)) {
3530 DUMPREG(i, DISPC_CPR_COEF_R);
3531 DUMPREG(i, DISPC_CPR_COEF_G);
3532 DUMPREG(i, DISPC_CPR_COEF_B);
3533 }
3534 }
3536 p_names = ovl_names;
3538 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3539 DUMPREG(i, DISPC_OVL_BA0);
3540 DUMPREG(i, DISPC_OVL_BA1);
3541 DUMPREG(i, DISPC_OVL_POSITION);
3542 DUMPREG(i, DISPC_OVL_SIZE);
3543 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3544 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3545 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3546 DUMPREG(i, DISPC_OVL_ROW_INC);
3547 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3549 if (dss_has_feature(FEAT_PRELOAD))
3550 DUMPREG(i, DISPC_OVL_PRELOAD);
3551 if (dss_has_feature(FEAT_MFLAG))
3552 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3554 if (i == OMAP_DSS_GFX) {
3555 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3556 DUMPREG(i, DISPC_OVL_TABLE_BA);
3557 continue;
3558 }
3560 DUMPREG(i, DISPC_OVL_FIR);
3561 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3562 DUMPREG(i, DISPC_OVL_ACCU0);
3563 DUMPREG(i, DISPC_OVL_ACCU1);
3564 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3565 DUMPREG(i, DISPC_OVL_BA0_UV);
3566 DUMPREG(i, DISPC_OVL_BA1_UV);
3567 DUMPREG(i, DISPC_OVL_FIR2);
3568 DUMPREG(i, DISPC_OVL_ACCU2_0);
3569 DUMPREG(i, DISPC_OVL_ACCU2_1);
3570 }
3571 if (dss_has_feature(FEAT_ATTR2))
3572 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3573 }
3575 #undef DISPC_REG
3576 #undef DUMPREG
3578 #define DISPC_REG(plane, name, i) name(plane, i)
3579 #define DUMPREG(plane, name, i) \
3580 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3581 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
3582 dispc_read_reg(DISPC_REG(plane, name, i)))
3584 /* Video pipeline coefficient registers */
3586 /* start from OMAP_DSS_VIDEO1 */
3587 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3588 for (j = 0; j < 8; j++)
3589 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
3591 for (j = 0; j < 8; j++)
3592 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
3594 for (j = 0; j < 5; j++)
3595 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
3597 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3598 for (j = 0; j < 8; j++)
3599 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3600 }
3602 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3603 for (j = 0; j < 8; j++)
3604 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3606 for (j = 0; j < 8; j++)
3607 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3609 for (j = 0; j < 8; j++)
3610 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3611 }
3612 }
3614 dispc_runtime_put();
3616 #undef DISPC_REG
3617 #undef DUMPREG
3618 }
3620 /* calculate clock rates using dividers in cinfo */
3621 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3622 struct dispc_clock_info *cinfo)
3623 {
3624 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3625 return -EINVAL;
3626 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
3627 return -EINVAL;
3629 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3630 cinfo->pck = cinfo->lck / cinfo->pck_div;
3632 return 0;
3633 }
3635 bool dispc_div_calc(unsigned long dispc,
3636 unsigned long pck_min, unsigned long pck_max,
3637 dispc_div_calc_func func, void *data)
3638 {
3639 int lckd, lckd_start, lckd_stop;
3640 int pckd, pckd_start, pckd_stop;
3641 unsigned long pck, lck;
3642 unsigned long lck_max;
3643 unsigned long pckd_hw_min, pckd_hw_max;
3644 unsigned min_fck_per_pck;
3645 unsigned long fck;
3647 #ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK
3648 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
3649 #else
3650 min_fck_per_pck = 0;
3651 #endif
3653 pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3654 pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3656 lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
3658 pck_min = pck_min ? pck_min : 1;
3659 pck_max = pck_max ? pck_max : ULONG_MAX;
3661 lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul);
3662 lckd_stop = min(dispc / pck_min, 255ul);
3664 for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) {
3665 lck = dispc / lckd;
3667 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min);
3668 pckd_stop = min(lck / pck_min, pckd_hw_max);
3670 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) {
3671 pck = lck / pckd;
3673 /*
3674 * For OMAP2/3 the DISPC fclk is the same as LCD's logic
3675 * clock, which means we're configuring DISPC fclk here
3676 * also. Thus we need to use the calculated lck. For
3677 * OMAP4+ the DISPC fclk is a separate clock.
3678 */
3679 if (dss_has_feature(FEAT_CORE_CLK_DIV))
3680 fck = dispc_core_clk_rate();
3681 else
3682 fck = lck;
3684 if (fck < pck * min_fck_per_pck)
3685 continue;
3687 if (func(lckd, pckd, lck, pck, data))
3688 return true;
3689 }
3690 }
3692 return false;
3693 }
3695 void dispc_mgr_set_clock_div(enum omap_channel channel,
3696 const struct dispc_clock_info *cinfo)
3697 {
3698 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3699 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3701 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
3702 }
3704 int dispc_mgr_get_clock_div(enum omap_channel channel,
3705 struct dispc_clock_info *cinfo)
3706 {
3707 unsigned long fck;
3709 fck = dispc_fclk_rate();
3711 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3712 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
3714 cinfo->lck = fck / cinfo->lck_div;
3715 cinfo->pck = cinfo->lck / cinfo->pck_div;
3717 return 0;
3718 }
3720 u32 dispc_read_irqstatus(void)
3721 {
3722 return dispc_read_reg(DISPC_IRQSTATUS);
3723 }
3724 EXPORT_SYMBOL(dispc_read_irqstatus);
3726 void dispc_clear_irqstatus(u32 mask)
3727 {
3728 dispc_write_reg(DISPC_IRQSTATUS, mask);
3729 }
3730 EXPORT_SYMBOL(dispc_clear_irqstatus);
3732 u32 dispc_read_irqenable(void)
3733 {
3734 return dispc_read_reg(DISPC_IRQENABLE);
3735 }
3736 EXPORT_SYMBOL(dispc_read_irqenable);
3738 void dispc_write_irqenable(u32 mask)
3739 {
3740 u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3742 /* clear the irqstatus for newly enabled irqs */
3743 dispc_clear_irqstatus((mask ^ old_mask) & mask);
3745 if (omapdss_display_share())
3746 /* Should not clear already enabled interrupts since remote
3747 * core must be using it */
3748 dispc_write_reg(DISPC_IRQENABLE, mask | old_mask);
3749 else
3750 dispc_write_reg(DISPC_IRQENABLE, mask);
3751 }
3752 EXPORT_SYMBOL(dispc_write_irqenable);
3754 void dispc_enable_sidle(void)
3755 {
3756 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3757 }
3759 void dispc_disable_sidle(void)
3760 {
3761 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3762 }
3764 static void _omap_dispc_initial_config(void)
3765 {
3766 u32 l;
3768 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3769 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3770 l = dispc_read_reg(DISPC_DIVISOR);
3771 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3772 l = FLD_MOD(l, 1, 0, 0);
3773 l = FLD_MOD(l, 1, 23, 16);
3774 dispc_write_reg(DISPC_DIVISOR, l);
3776 dispc.core_clk_rate = dispc_fclk_rate();
3777 }
3779 /* FUNCGATED */
3780 if (dss_has_feature(FEAT_FUNCGATED))
3781 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3783 dispc_setup_color_conv_coef();
3785 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3787 dispc_init_fifos();
3789 dispc_configure_burst_sizes();
3791 dispc_ovl_enable_zorder_planes();
3793 if (dispc.feat->mstandby_workaround)
3794 REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0);
3796 if (dss_has_feature(FEAT_MFLAG))
3797 dispc_init_mflag();
3798 }
3800 static const struct dispc_features omap24xx_dispc_feats __initconst = {
3801 .sw_start = 5,
3802 .fp_start = 15,
3803 .bp_start = 27,
3804 .sw_max = 64,
3805 .vp_max = 255,
3806 .hp_max = 256,
3807 .mgr_width_start = 10,
3808 .mgr_height_start = 26,
3809 .mgr_width_max = 2048,
3810 .mgr_height_max = 2048,
3811 .max_lcd_pclk = 66500000,
3812 .calc_scaling = dispc_ovl_calc_scaling_24xx,
3813 .calc_core_clk = calc_core_clk_24xx,
3814 .num_fifos = 3,
3815 .no_framedone_tv = true,
3816 .set_max_preload = false,
3817 .alt_clk_dsi_pll = false,
3818 .last_pixel_inc_missing = true,
3819 };
3821 static const struct dispc_features omap34xx_rev1_0_dispc_feats __initconst = {
3822 .sw_start = 5,
3823 .fp_start = 15,
3824 .bp_start = 27,
3825 .sw_max = 64,
3826 .vp_max = 255,
3827 .hp_max = 256,
3828 .mgr_width_start = 10,
3829 .mgr_height_start = 26,
3830 .mgr_width_max = 2048,
3831 .mgr_height_max = 2048,
3832 .max_lcd_pclk = 173000000,
3833 .max_tv_pclk = 59000000,
3834 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3835 .calc_core_clk = calc_core_clk_34xx,
3836 .num_fifos = 3,
3837 .no_framedone_tv = true,
3838 .set_max_preload = false,
3839 .alt_clk_dsi_pll = true,
3840 .last_pixel_inc_missing = true,
3841 };
3843 static const struct dispc_features omap34xx_rev3_0_dispc_feats __initconst = {
3844 .sw_start = 7,
3845 .fp_start = 19,
3846 .bp_start = 31,
3847 .sw_max = 256,
3848 .vp_max = 4095,
3849 .hp_max = 4096,
3850 .mgr_width_start = 10,
3851 .mgr_height_start = 26,
3852 .mgr_width_max = 2048,
3853 .mgr_height_max = 2048,
3854 .max_lcd_pclk = 173000000,
3855 .max_tv_pclk = 59000000,
3856 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3857 .calc_core_clk = calc_core_clk_34xx,
3858 .num_fifos = 3,
3859 .no_framedone_tv = true,
3860 .set_max_preload = false,
3861 .alt_clk_dsi_pll = true,
3862 .last_pixel_inc_missing = true,
3863 };
3865 static const struct dispc_features omap44xx_dispc_feats __initconst = {
3866 .sw_start = 7,
3867 .fp_start = 19,
3868 .bp_start = 31,
3869 .sw_max = 256,
3870 .vp_max = 4095,
3871 .hp_max = 4096,
3872 .mgr_width_start = 10,
3873 .mgr_height_start = 26,
3874 .mgr_width_max = 2048,
3875 .mgr_height_max = 2048,
3876 .max_lcd_pclk = 170000000,
3877 .max_tv_pclk = 185625000,
3878 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3879 .calc_core_clk = calc_core_clk_44xx,
3880 .num_fifos = 5,
3881 .gfx_fifo_workaround = true,
3882 .set_max_preload = true,
3883 .alt_clk_dsi_pll = true,
3884 };
3886 static const struct dispc_features omap54xx_dispc_feats __initconst = {
3887 .sw_start = 7,
3888 .fp_start = 19,
3889 .bp_start = 31,
3890 .sw_max = 256,
3891 .vp_max = 4095,
3892 .hp_max = 4096,
3893 .mgr_width_start = 11,
3894 .mgr_height_start = 27,
3895 .mgr_width_max = 4096,
3896 .mgr_height_max = 4096,
3897 .max_lcd_pclk = 170000000,
3898 .max_tv_pclk = 186000000,
3899 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3900 .calc_core_clk = calc_core_clk_44xx,
3901 .num_fifos = 5,
3902 .gfx_fifo_workaround = true,
3903 .mstandby_workaround = true,
3904 .set_max_preload = true,
3905 .alt_clk_dsi_pll = true,
3906 };
3908 static const struct dispc_features dra7xx_dispc_feats __initconst = {
3909 .sw_start = 7,
3910 .fp_start = 19,
3911 .bp_start = 31,
3912 .sw_max = 256,
3913 .vp_max = 4095,
3914 .hp_max = 4096,
3915 .mgr_width_start = 11,
3916 .mgr_height_start = 27,
3917 .mgr_width_max = 4096,
3918 .mgr_height_max = 4096,
3919 .max_lcd_pclk = 170000000,
3920 .max_tv_pclk = 186000000,
3921 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3922 .calc_core_clk = calc_core_clk_44xx,
3923 .num_fifos = 5,
3924 .gfx_fifo_workaround = true,
3925 .mstandby_workaround = true,
3926 .set_max_preload = true,
3927 .alt_clk_dsi_pll = false,
3928 .has_ctrl_core_sma_sw_1 = true,
3929 };
3931 static int __init dispc_init_features(struct platform_device *pdev)
3932 {
3933 const struct dispc_features *src;
3934 struct dispc_features *dst;
3936 dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
3937 if (!dst) {
3938 dev_err(&pdev->dev, "Failed to allocate DISPC Features\n");
3939 return -ENOMEM;
3940 }
3942 switch (omapdss_get_version()) {
3943 case OMAPDSS_VER_OMAP24xx:
3944 src = &omap24xx_dispc_feats;
3945 break;
3947 case OMAPDSS_VER_OMAP34xx_ES1:
3948 src = &omap34xx_rev1_0_dispc_feats;
3949 break;
3951 case OMAPDSS_VER_OMAP34xx_ES3:
3952 case OMAPDSS_VER_OMAP3630:
3953 case OMAPDSS_VER_AM35xx:
3954 case OMAPDSS_VER_AM43xx:
3955 src = &omap34xx_rev3_0_dispc_feats;
3956 break;
3958 case OMAPDSS_VER_OMAP4430_ES1:
3959 case OMAPDSS_VER_OMAP4430_ES2:
3960 case OMAPDSS_VER_OMAP4:
3961 src = &omap44xx_dispc_feats;
3962 break;
3964 case OMAPDSS_VER_OMAP5:
3965 src = &omap54xx_dispc_feats;
3966 break;
3968 case OMAPDSS_VER_DRA74xx:
3969 case OMAPDSS_VER_DRA72xx:
3970 src = &dra7xx_dispc_feats;
3971 break;
3973 default:
3974 return -ENODEV;
3975 }
3977 memcpy(dst, src, sizeof(*dst));
3978 dispc.feat = dst;
3980 return 0;
3981 }
3983 static irqreturn_t dispc_irq_handler(int irq, void *arg)
3984 {
3985 if (!dispc.is_enabled)
3986 return IRQ_NONE;
3988 return dispc.user_handler(irq, dispc.user_data);
3989 }
3991 int dispc_request_irq(irq_handler_t handler, void *dev_id)
3992 {
3993 int r;
3995 if (dispc.user_handler != NULL)
3996 return -EBUSY;
3998 dispc.user_handler = handler;
3999 dispc.user_data = dev_id;
4001 /* ensure the dispc_irq_handler sees the values above */
4002 smp_wmb();
4004 r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler,
4005 IRQF_SHARED, "OMAP DISPC", &dispc);
4006 if (r) {
4007 dispc.user_handler = NULL;
4008 dispc.user_data = NULL;
4009 }
4011 return r;
4012 }
4013 EXPORT_SYMBOL(dispc_request_irq);
4015 void dispc_free_irq(void *dev_id)
4016 {
4017 devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc);
4019 dispc.user_handler = NULL;
4020 dispc.user_data = NULL;
4021 }
4022 EXPORT_SYMBOL(dispc_free_irq);
4024 /* DISPC HW IP initialisation */
4025 static int __init omap_dispchw_probe(struct platform_device *pdev)
4026 {
4027 u32 rev;
4028 int r = 0;
4029 struct resource *dispc_mem;
4031 dispc.pdev = pdev;
4033 spin_lock_init(&dispc.control_lock);
4035 r = dispc_init_features(dispc.pdev);
4036 if (r)
4037 return r;
4039 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
4040 if (!dispc_mem) {
4041 DSSERR("can't get IORESOURCE_MEM DISPC\n");
4042 return -EINVAL;
4043 }
4045 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
4046 resource_size(dispc_mem));
4047 if (!dispc.base) {
4048 DSSERR("can't ioremap DISPC\n");
4049 return -ENOMEM;
4050 }
4052 dispc.irq = platform_get_irq(dispc.pdev, 0);
4053 if (dispc.irq < 0) {
4054 DSSERR("platform_get_irq failed\n");
4055 return -ENODEV;
4056 }
4058 if (dispc.feat->has_ctrl_core_sma_sw_1) {
4059 struct device_node *np = pdev->dev.of_node;
4061 dispc.syscon = syscon_regmap_lookup_by_phandle(np, "syscon");
4062 if (IS_ERR(dispc.syscon)) {
4063 dev_err(&pdev->dev, "failed to get syscon regmap\n");
4064 return PTR_ERR(dispc.syscon);
4065 }
4066 }
4068 pm_runtime_enable(&pdev->dev);
4069 pm_runtime_irq_safe(&pdev->dev);
4071 r = dispc_runtime_get();
4072 if (r)
4073 goto err_runtime_get;
4075 _omap_dispc_initial_config();
4077 rev = dispc_read_reg(DISPC_REVISION);
4078 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
4079 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4081 dispc_runtime_put();
4083 dss_init_overlay_managers();
4085 dss_debugfs_create_file("dispc", dispc_dump_regs);
4087 return 0;
4089 err_runtime_get:
4090 pm_runtime_disable(&pdev->dev);
4091 return r;
4092 }
4094 static int __exit omap_dispchw_remove(struct platform_device *pdev)
4095 {
4096 pm_runtime_disable(&pdev->dev);
4098 dss_uninit_overlay_managers();
4100 return 0;
4101 }
4103 static int dispc_runtime_suspend(struct device *dev)
4104 {
4105 dispc.is_enabled = false;
4106 /* ensure the dispc_irq_handler sees the is_enabled value */
4107 smp_wmb();
4108 /* wait for current handler to finish before turning the DISPC off */
4109 synchronize_irq(dispc.irq);
4111 dispc_save_context();
4113 return 0;
4114 }
4116 static int dispc_runtime_resume(struct device *dev)
4117 {
4118 /*
4119 * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME)
4120 * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in
4121 * _omap_dispc_initial_config(). We can thus use it to detect if
4122 * we have lost register context.
4123 */
4124 if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) {
4125 _omap_dispc_initial_config();
4127 dispc_restore_context();
4128 }
4130 dispc.is_enabled = true;
4131 /* ensure the dispc_irq_handler sees the is_enabled value */
4132 smp_wmb();
4134 return 0;
4135 }
4137 static const struct dev_pm_ops dispc_pm_ops = {
4138 .runtime_suspend = dispc_runtime_suspend,
4139 .runtime_resume = dispc_runtime_resume,
4140 };
4142 static const struct of_device_id dispc_of_match[] = {
4143 { .compatible = "ti,omap2-dispc", },
4144 { .compatible = "ti,omap3-dispc", },
4145 { .compatible = "ti,omap4-dispc", },
4146 { .compatible = "ti,omap5-dispc", },
4147 { .compatible = "ti,dra7-dispc", },
4148 {},
4149 };
4151 static struct platform_driver omap_dispchw_driver = {
4152 .remove = __exit_p(omap_dispchw_remove),
4153 .driver = {
4154 .name = "omapdss_dispc",
4155 .owner = THIS_MODULE,
4156 .pm = &dispc_pm_ops,
4157 .of_match_table = dispc_of_match,
4158 },
4159 };
4161 int __init dispc_init_platform_driver(void)
4162 {
4163 return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe);
4164 }
4166 void __exit dispc_uninit_platform_driver(void)
4167 {
4168 platform_driver_unregister(&omap_dispchw_driver);
4169 }