1 /*
2 * linux/drivers/video/omap2/dss/dss.h
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
23 #ifndef __OMAP2_DSS_H
24 #define __OMAP2_DSS_H
26 #include <linux/interrupt.h>
27 #include <linux/i2c.h>
29 #ifdef pr_fmt
30 #undef pr_fmt
31 #endif
33 #ifdef DSS_SUBSYS_NAME
34 #define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt
35 #else
36 #define pr_fmt(fmt) fmt
37 #endif
39 #define DSSDBG(format, ...) \
40 pr_debug(format, ## __VA_ARGS__)
42 #ifdef DSS_SUBSYS_NAME
43 #define DSSERR(format, ...) \
44 printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
45 ## __VA_ARGS__)
46 #else
47 #define DSSERR(format, ...) \
48 printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
49 #endif
51 #ifdef DSS_SUBSYS_NAME
52 #define DSSINFO(format, ...) \
53 printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
54 ## __VA_ARGS__)
55 #else
56 #define DSSINFO(format, ...) \
57 printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
58 #endif
60 #ifdef DSS_SUBSYS_NAME
61 #define DSSWARN(format, ...) \
62 printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
63 ## __VA_ARGS__)
64 #else
65 #define DSSWARN(format, ...) \
66 printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
67 #endif
69 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
70 number. For example 7:0 */
71 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
72 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
73 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
74 #define FLD_MOD(orig, val, start, end) \
75 (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
77 enum dss_io_pad_mode {
78 DSS_IO_PAD_MODE_RESET,
79 DSS_IO_PAD_MODE_RFBI,
80 DSS_IO_PAD_MODE_BYPASS,
81 };
83 enum dss_hdmi_venc_clk_source_select {
84 DSS_VENC_TV_CLK = 0,
85 DSS_HDMI_M_PCLK = 1,
86 };
88 enum dss_dsi_content_type {
89 DSS_DSI_CONTENT_DCS,
90 DSS_DSI_CONTENT_GENERIC,
91 };
93 enum dss_writeback_channel {
94 DSS_WB_LCD1_MGR = 0,
95 DSS_WB_LCD2_MGR = 1,
96 DSS_WB_TV_MGR = 2,
97 DSS_WB_OVL0 = 3,
98 DSS_WB_OVL1 = 4,
99 DSS_WB_OVL2 = 5,
100 DSS_WB_OVL3 = 6,
101 DSS_WB_LCD3_MGR = 7,
102 };
104 enum dss_dpll {
105 DSS_DPLL_VIDEO1 = 0,
106 DSS_DPLL_VIDEO2,
107 DSS_DPLL_HDMI,
108 DSS_DPLL_NONE,
109 };
111 struct dss_clock_info {
112 /* rates that we get with dividers below */
113 unsigned long fck;
115 /* dividers */
116 u16 fck_div;
117 };
119 struct dispc_clock_info {
120 /* rates that we get with dividers below */
121 unsigned long lck;
122 unsigned long pck;
124 /* dividers */
125 u16 lck_div;
126 u16 pck_div;
127 };
129 struct dsi_clock_info {
130 /* rates that we get with dividers below */
131 unsigned long fint;
132 unsigned long clkin4ddr;
133 unsigned long clkin;
134 unsigned long dsi_pll_hsdiv_dispc_clk; /* OMAP3: DSI1_PLL_CLK
135 * OMAP4: PLLx_CLK1 */
136 unsigned long dsi_pll_hsdiv_dsi_clk; /* OMAP3: DSI2_PLL_CLK
137 * OMAP4: PLLx_CLK2 */
138 unsigned long lp_clk;
140 /* dividers */
141 u16 regn;
142 u16 regm;
143 u16 regm_dispc; /* OMAP3: REGM3
144 * OMAP4: REGM4 */
145 u16 regm_dsi; /* OMAP3: REGM4
146 * OMAP4: REGM5 */
147 u16 lp_clk_div;
148 };
150 struct dss_dpll_cinfo {
151 unsigned long fint, clkin, clkout, hsdiv_clk;
153 u16 regm, regn, regm_hsdiv;
154 };
156 struct reg_field {
157 u16 reg;
158 u8 high;
159 u8 low;
160 };
162 struct dss_lcd_mgr_config {
163 enum dss_io_pad_mode io_pad_mode;
165 bool stallmode;
166 bool fifohandcheck;
168 struct dispc_clock_info clock_info;
170 int video_port_width;
172 int lcden_sig_polarity;
173 };
175 struct dpi_common_ops {
176 int (*enable) (struct omap_dss_device *dssdev);
177 void (*disable) (struct omap_dss_device *dssdev);
178 void (*set_timings) (struct omap_dss_device *dssdev,
179 struct omap_video_timings *timings);
180 int (*check_timings) (struct omap_dss_device *dssdev,
181 struct omap_video_timings *timings);
182 void (*set_data_lines) (struct omap_dss_device *dssdev,
183 int data_lines);
184 };
186 struct seq_file;
187 struct platform_device;
189 /* core */
190 struct platform_device *dss_get_core_pdev(void);
191 struct bus_type *dss_get_bus(void);
192 struct regulator *dss_get_vdds_dsi(void);
193 struct regulator *dss_get_vdds_sdi(void);
194 int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask);
195 void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask);
196 int dss_set_min_bus_tput(struct device *dev, unsigned long tput);
197 int dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *));
199 struct omap_dss_device *dss_alloc_and_init_device(struct device *parent);
200 int dss_add_device(struct omap_dss_device *dssdev);
201 void dss_unregister_device(struct omap_dss_device *dssdev);
202 void dss_unregister_child_devices(struct device *parent);
203 void dss_put_device(struct omap_dss_device *dssdev);
204 void dss_copy_device_pdata(struct omap_dss_device *dst,
205 const struct omap_dss_device *src);
206 int dss_mgr_blank(struct omap_overlay_manager *mgr,
207 bool wait_for_go);
209 /* output */
210 void dss_register_output(struct omap_dss_output *out);
211 void dss_unregister_output(struct omap_dss_output *out);
213 /* display */
214 int dss_suspend_all_devices(void);
215 int dss_resume_all_devices(void);
217 void dss_disable_all_devices(void);
219 int display_init_sysfs(struct platform_device *pdev,
220 struct omap_dss_device *dssdev);
221 void display_uninit_sysfs(struct platform_device *pdev,
222 struct omap_dss_device *dssdev);
224 /* manager */
225 int dss_init_overlay_managers(struct platform_device *pdev);
226 void dss_uninit_overlay_managers(struct platform_device *pdev);
227 int dss_mgr_simple_check(struct omap_overlay_manager *mgr,
228 const struct omap_overlay_manager_info *info);
229 int dss_mgr_check_timings(struct omap_overlay_manager *mgr,
230 const struct omap_video_timings *timings);
231 int dss_mgr_check(struct omap_overlay_manager *mgr,
232 struct omap_overlay_manager_info *info,
233 const struct omap_video_timings *mgr_timings,
234 const struct dss_lcd_mgr_config *config,
235 struct omap_overlay_info **overlay_infos);
237 static inline bool dss_mgr_is_lcd(enum omap_channel id)
238 {
239 if (id == OMAP_DSS_CHANNEL_LCD || id == OMAP_DSS_CHANNEL_LCD2 ||
240 id == OMAP_DSS_CHANNEL_LCD3)
241 return true;
242 else
243 return false;
244 }
246 int dss_manager_kobj_init(struct omap_overlay_manager *mgr,
247 struct platform_device *pdev);
248 void dss_manager_kobj_uninit(struct omap_overlay_manager *mgr);
250 /* overlay */
251 void dss_init_overlays(struct platform_device *pdev);
252 void dss_uninit_overlays(struct platform_device *pdev);
253 void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr);
254 int dss_ovl_simple_check(struct omap_overlay *ovl,
255 const struct omap_overlay_info *info);
256 int dss_ovl_check(struct omap_overlay *ovl, struct omap_overlay_info *info,
257 const struct omap_video_timings *mgr_timings);
258 bool dss_ovl_use_replication(struct dss_lcd_mgr_config config,
259 enum omap_color_mode mode);
260 int dss_overlay_kobj_init(struct omap_overlay *ovl,
261 struct platform_device *pdev);
262 void dss_overlay_kobj_uninit(struct omap_overlay *ovl);
264 /* DSS */
265 int dss_init_platform_driver(void) __init;
266 void dss_uninit_platform_driver(void);
268 unsigned long dss_get_dispc_clk_rate(void);
269 int dss_dpi_select_source(int module_id, enum omap_channel channel);
270 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
271 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void);
272 void dss_use_dpll_lcd(enum omap_channel channel, bool use_dpll);
273 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src);
274 void dss_dump_clocks(struct seq_file *s);
276 #if defined(CONFIG_OMAP2_DSS_DEBUGFS)
277 void dss_debug_dump_clocks(struct seq_file *s);
278 #endif
280 int dss_get_ctx_loss_count(void);
282 void dss_sdi_init(int datapairs);
283 int dss_sdi_enable(void);
284 void dss_sdi_disable(void);
286 void dss_select_dsi_clk_source(int dsi_module,
287 enum omap_dss_clk_source clk_src);
288 void dss_select_lcd_clk_source(enum omap_channel channel,
289 enum omap_dss_clk_source clk_src);
290 enum omap_dss_clk_source dss_get_dispc_clk_source(void);
291 enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module);
292 enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
294 void dss_set_venc_output(enum omap_dss_venc_type type);
295 void dss_set_dac_pwrdn_bgz(bool enable);
297 unsigned long dss_get_dpll4_rate(void);
298 int dss_calc_clock_rates(struct dss_clock_info *cinfo);
299 int dss_set_clock_div(struct dss_clock_info *cinfo);
300 int dss_calc_clock_div(unsigned long req_pck, struct dss_clock_info *dss_cinfo,
301 struct dispc_clock_info *dispc_cinfo);
303 /* SDI */
304 int sdi_init_platform_driver(void) __init;
305 void sdi_uninit_platform_driver(void) __exit;
307 /* DSI */
308 #ifdef CONFIG_OMAP2_DSS_DSI
310 struct dentry;
311 struct file_operations;
313 int dsi_init_platform_driver(void) __init;
314 void dsi_uninit_platform_driver(void) __exit;
316 int dsi_runtime_get(struct platform_device *dsidev);
317 void dsi_runtime_put(struct platform_device *dsidev);
319 void dsi_dump_clocks(struct seq_file *s);
321 void dsi_irq_handler(void);
322 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt);
324 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev);
325 int dsi_pll_set_clock_div(struct platform_device *dsidev,
326 struct dsi_clock_info *cinfo);
327 int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev,
328 unsigned long req_pck, struct dsi_clock_info *cinfo,
329 struct dispc_clock_info *dispc_cinfo);
330 int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
331 bool enable_hsdiv);
332 void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes);
333 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev);
334 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev);
335 struct platform_device *dsi_get_dsidev_from_id(int module);
336 #else
337 static inline int dsi_runtime_get(struct platform_device *dsidev)
338 {
339 return 0;
340 }
341 static inline void dsi_runtime_put(struct platform_device *dsidev)
342 {
343 }
344 static inline u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
345 {
346 WARN("%s: DSI not compiled in, returning pixel_size as 0\n", __func__);
347 return 0;
348 }
349 static inline unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
350 {
351 WARN("%s: DSI not compiled in, returning rate as 0\n", __func__);
352 return 0;
353 }
354 static inline int dsi_pll_set_clock_div(struct platform_device *dsidev,
355 struct dsi_clock_info *cinfo)
356 {
357 WARN("%s: DSI not compiled in\n", __func__);
358 return -ENODEV;
359 }
360 static inline int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev,
361 unsigned long req_pck,
362 struct dsi_clock_info *dsi_cinfo,
363 struct dispc_clock_info *dispc_cinfo)
364 {
365 WARN("%s: DSI not compiled in\n", __func__);
366 return -ENODEV;
367 }
368 static inline int dsi_pll_init(struct platform_device *dsidev,
369 bool enable_hsclk, bool enable_hsdiv)
370 {
371 WARN("%s: DSI not compiled in\n", __func__);
372 return -ENODEV;
373 }
374 static inline void dsi_pll_uninit(struct platform_device *dsidev,
375 bool disconnect_lanes)
376 {
377 }
378 static inline void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
379 {
380 }
381 static inline void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
382 {
383 }
384 static inline struct platform_device *dsi_get_dsidev_from_id(int module)
385 {
386 return NULL;
387 }
388 #endif
390 /* DPI */
391 void dpi_common_set_ops(struct dpi_common_ops *ops);
392 int omap_dpi_init_platform_driver(void) __init;
393 void omap_dpi_uninit_platform_driver(void) __exit;
395 int dra7xx_dpi_init_platform_driver(void) __init;
396 void dra7xx_dpi_uninit_platform_driver(void) __exit;
398 /* DISPC */
399 int dispc_init_platform_driver(void) __init;
400 void dispc_uninit_platform_driver(void) __exit;
401 void dispc_dump_clocks(struct seq_file *s);
403 void dispc_enable_sidle(void);
404 void dispc_disable_sidle(void);
406 void dispc_lcd_enable_signal(bool enable);
407 void dispc_pck_free_enable(bool enable);
408 void dispc_enable_fifomerge(bool enable);
409 void dispc_enable_gamma_table(bool enable);
410 void dispc_set_loadmode(enum omap_dss_load_mode mode);
412 bool dispc_mgr_timings_ok(enum omap_channel channel,
413 const struct omap_video_timings *timings);
414 unsigned long dispc_fclk_rate(void);
415 void dispc_find_clk_divs(unsigned long req_pck, unsigned long fck,
416 struct dispc_clock_info *cinfo);
417 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
418 struct dispc_clock_info *cinfo);
421 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
422 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
423 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
424 bool manual_update);
426 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
427 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
428 unsigned long dispc_core_clk_rate(void);
429 void dispc_mgr_set_clock_div(enum omap_channel channel,
430 const struct dispc_clock_info *cinfo);
431 int dispc_mgr_get_clock_div(enum omap_channel channel,
432 struct dispc_clock_info *cinfo);
434 u32 dispc_wb_get_framedone_irq(void);
435 bool dispc_wb_go_busy(void);
436 void dispc_wb_go(void);
437 void dispc_wb_enable(bool enable);
438 bool dispc_wb_is_enabled(void);
439 void dispc_wb_set_channel_in(enum dss_writeback_channel channel);
440 int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
441 bool mem_to_mem, const struct omap_video_timings *timings);
443 /* VENC */
444 #ifdef CONFIG_OMAP2_DSS_VENC
445 int venc_init_platform_driver(void) __init;
446 void venc_uninit_platform_driver(void) __exit;
447 unsigned long venc_get_pixel_clock(void);
448 #else
449 static inline unsigned long venc_get_pixel_clock(void)
450 {
451 WARN("%s: VENC not compiled in, returning pclk as 0\n", __func__);
452 return 0;
453 }
454 #endif
455 int omapdss_venc_display_enable(struct omap_dss_device *dssdev);
456 void omapdss_venc_display_disable(struct omap_dss_device *dssdev);
457 void omapdss_venc_set_timings(struct omap_dss_device *dssdev,
458 struct omap_video_timings *timings);
459 int omapdss_venc_check_timings(struct omap_dss_device *dssdev,
460 struct omap_video_timings *timings);
461 u32 omapdss_venc_get_wss(struct omap_dss_device *dssdev);
462 int omapdss_venc_set_wss(struct omap_dss_device *dssdev, u32 wss);
463 void omapdss_venc_set_type(struct omap_dss_device *dssdev,
464 enum omap_dss_venc_type type);
465 void omapdss_venc_invert_vid_out_polarity(struct omap_dss_device *dssdev,
466 bool invert_polarity);
467 int venc_panel_init(void);
468 void venc_panel_exit(void);
470 /* HDMI */
471 #if defined(CONFIG_OMAP4_DSS_HDMI) || defined(CONFIG_OMAP5_DSS_HDMI)
472 int hdmi_init_platform_driver(void) __init;
473 void hdmi_uninit_platform_driver(void) __exit;
475 unsigned long hdmi_get_pixel_clock(void);
476 #else
477 static inline unsigned long hdmi_get_pixel_clock(void)
478 {
479 WARN("%s: HDMI not compiled in, returning pclk as 0\n", __func__);
480 return 0;
481 }
482 #endif
483 struct i2c_adapter *omapdss_hdmi_adapter(void);
484 int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev);
485 void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev);
486 int omapdss_hdmi_core_enable(struct omap_dss_device *dssdev);
487 void omapdss_hdmi_core_disable(struct omap_dss_device *dssdev);
488 void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev,
489 struct omap_video_timings *timings);
490 int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
491 struct omap_video_timings *timings);
492 int omapdss_hdmi_read_edid(u8 *buf, int len);
493 bool omapdss_hdmi_detect(void);
494 int omapdss_hdmi_get_range(void);
495 int omapdss_hdmi_set_range(int range);
496 int omapdss_hdmi_get_deepcolor(void);
497 int omapdss_hdmi_set_deepcolor(struct omap_dss_device *dssdev, int val,
498 bool hdmi_restart);
499 int omapdss_hdmi_display_3d_enable(struct omap_dss_device *dssdev,
500 struct s3d_disp_info *info, int code);
501 void sel_i2c(void);
502 void sel_hdmi(void);
503 int omapdss_hdmi_display_set_mode(struct omap_dss_device *dssdev,
504 struct fb_videomode *mode);
505 int hdmi_panel_init(void);
506 void hdmi_panel_exit(void);
507 #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) || \
508 defined(CONFIG_OMAP5_DSS_HDMI_AUDIO)
509 int hdmi_audio_enable(void);
510 void hdmi_audio_disable(void);
511 int hdmi_audio_start(void);
512 void hdmi_audio_stop(void);
513 bool hdmi_mode_has_audio(void);
514 int hdmi_audio_config(struct omap_dss_audio *audio);
515 #endif
517 /* RFBI */
518 int rfbi_init_platform_driver(void) __init;
519 void rfbi_uninit_platform_driver(void) __exit;
522 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
523 static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
524 {
525 int b;
526 for (b = 0; b < 32; ++b) {
527 if (irqstatus & (1 << b))
528 irq_arr[b]++;
529 }
530 }
531 #endif
533 bool dss_dpll_disabled(enum dss_dpll dpll);
534 int dss_dpll_calc_clock_div_pck(enum dss_dpll dpll, unsigned long pck_req,
535 struct dss_dpll_cinfo *dpll_cinfo,
536 struct dispc_clock_info *dispc_cinfo);
537 int dss_dpll_set_clock_div(enum dss_dpll dpll, struct dss_dpll_cinfo *cinfo);
538 void dss_dpll_enable_ctrl(enum dss_dpll dpll, bool enable);
539 int dss_dpll_activate(enum dss_dpll dpll);
540 void dss_dpll_set_control_mux(enum omap_channel channel, enum dss_dpll dpll);
541 void dss_dpll_disable(enum dss_dpll dpll);
542 int dss_dpll_configure(struct platform_device *pdev);
543 int dss_dpll_configure_ctrl(void);
544 void dss_dpll_unconfigure_ctrl(void);
546 #endif