15c9d011ddc82d656798c1aced82697a3164e01f
1 /*
2 * hdmi.c
3 *
4 * HDMI interface DSS driver setting for TI's OMAP4 family of processor.
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
6 * Authors: Yong Zhi
7 * Mythri pk <mythripk@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
22 #define DSS_SUBSYS_NAME "HDMI"
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/err.h>
27 #include <linux/io.h>
28 #include <linux/interrupt.h>
29 #include <linux/mutex.h>
30 #include <linux/delay.h>
31 #include <linux/string.h>
32 #include <linux/platform_device.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/clk.h>
35 #include <linux/gpio.h>
36 #include <linux/regulator/consumer.h>
37 #include <linux/slab.h>
38 #include <linux/of_gpio.h>
39 #include <video/omapdss.h>
40 #include <linux/i2c.h>
41 #include <linux/i2c-algo-bit.h>
43 #include "ti_hdmi.h"
44 #include "dss.h"
45 #include "dss_features.h"
47 /* HDMI EDID Length move this */
48 #define HDMI_EDID_MAX_LENGTH 256
49 #define EDID_TIMING_DESCRIPTOR_SIZE 0x12
50 #define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36
51 #define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80
52 #define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4
53 #define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4
55 #define HDMI_DEFAULT_REGN 16
56 #define HDMI_DEFAULT_REGM2 1
58 static struct {
59 struct mutex lock;
60 struct platform_device *pdev;
61 #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) || \
62 defined(CONFIG_OMAP5_DSS_HDMI_AUDIO)
63 struct platform_device *audio_pdev;
64 #endif
66 struct hdmi_ip_data ip_data;
67 int hdmi_irq;
69 struct clk *sys_clk;
70 struct regulator *vdda_hdmi_dac_reg;
72 /* GPIO pins */
73 int ct_cp_hpd_gpio;
74 int ls_oe_gpio;
75 int hpd_gpio;
77 /* level shifter state */
78 enum level_shifter_state ls_state;
80 /* i2c adapter info */
81 struct i2c_adapter *adap;
82 struct i2c_algo_bit_data bit_data;
83 int scl_pin;
84 int sda_pin;
86 struct omap_dss_output output;
87 } hdmi;
89 /*
90 * Logic for the below structure :
91 * user enters the CEA or VESA timings by specifying the HDMI/DVI code.
92 * There is a correspondence between CEA/VESA timing and code, please
93 * refer to section 6.3 in HDMI 1.3 specification for timing code.
94 *
95 * In the below structure, cea_vesa_timings corresponds to all OMAP4
96 * supported CEA and VESA timing values.code_cea corresponds to the CEA
97 * code, It is used to get the timing from cea_vesa_timing array.Similarly
98 * with code_vesa. Code_index is used for back mapping, that is once EDID
99 * is read from the TV, EDID is parsed to find the timing values and then
100 * map it to corresponding CEA or VESA index.
101 */
103 static const struct hdmi_config cea_timings[] = {
104 {
105 { 640, 480, 25200, 96, 16, 48, 2, 10, 33,
106 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
107 false, },
108 { 1, HDMI_HDMI },
109 },
110 {
111 { 720, 480, 27027, 62, 16, 60, 6, 9, 30,
112 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
113 false, },
114 { 2, HDMI_HDMI },
115 },
116 {
117 { 1280, 720, 74250, 40, 110, 220, 5, 5, 20,
118 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
119 false, },
120 { 4, HDMI_HDMI },
121 },
122 {
123 { 1920, 540, 74250, 44, 88, 148, 5, 2, 15,
124 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
125 true, },
126 { 5, HDMI_HDMI },
127 },
128 {
129 { 1440, 240, 27027, 124, 38, 114, 3, 4, 15,
130 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
131 true, },
132 { 6, HDMI_HDMI },
133 },
134 {
135 { 1920, 1080, 148500, 44, 88, 148, 5, 4, 36,
136 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
137 false, },
138 { 16, HDMI_HDMI },
139 },
140 {
141 { 720, 576, 27000, 64, 12, 68, 5, 5, 39,
142 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
143 false, },
144 { 17, HDMI_HDMI },
145 },
146 {
147 { 1280, 720, 74250, 40, 440, 220, 5, 5, 20,
148 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
149 false, },
150 { 19, HDMI_HDMI },
151 },
152 {
153 { 1920, 540, 74250, 44, 528, 148, 5, 2, 15,
154 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
155 true, },
156 { 20, HDMI_HDMI },
157 },
158 {
159 { 1440, 288, 27000, 126, 24, 138, 3, 2, 19,
160 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
161 true, },
162 { 21, HDMI_HDMI },
163 },
164 {
165 { 1440, 576, 54000, 128, 24, 136, 5, 5, 39,
166 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
167 false, },
168 { 29, HDMI_HDMI },
169 },
170 {
171 { 1920, 1080, 148500, 44, 528, 148, 5, 4, 36,
172 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
173 false, },
174 { 31, HDMI_HDMI },
175 },
176 {
177 { 1920, 1080, 74250, 44, 638, 148, 5, 4, 36,
178 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
179 false, },
180 { 32, HDMI_HDMI },
181 },
182 {
183 { 2880, 480, 108108, 248, 64, 240, 6, 9, 30,
184 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
185 false, },
186 { 35, HDMI_HDMI },
187 },
188 {
189 { 2880, 576, 108000, 256, 48, 272, 5, 5, 39,
190 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
191 false, },
192 { 37, HDMI_HDMI },
193 },
194 };
196 static const struct hdmi_config vesa_timings[] = {
197 /* VESA From Here */
198 {
199 { 640, 480, 25175, 96, 16, 48, 2, 11, 31,
200 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
201 false, },
202 { 4, HDMI_DVI },
203 },
204 {
205 { 800, 600, 40000, 128, 40, 88, 4, 1, 23,
206 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
207 false, },
208 { 9, HDMI_DVI },
209 },
210 {
211 { 848, 480, 33750, 112, 16, 112, 8, 6, 23,
212 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
213 false, },
214 { 0xE, HDMI_DVI },
215 },
216 {
217 { 1280, 768, 79500, 128, 64, 192, 7, 3, 20,
218 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
219 false, },
220 { 0x17, HDMI_DVI },
221 },
222 {
223 { 1280, 800, 83500, 128, 72, 200, 6, 3, 22,
224 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
225 false, },
226 { 0x1C, HDMI_DVI },
227 },
228 {
229 { 1360, 768, 85500, 112, 64, 256, 6, 3, 18,
230 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
231 false, },
232 { 0x27, HDMI_DVI },
233 },
234 {
235 { 1280, 960, 108000, 112, 96, 312, 3, 1, 36,
236 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
237 false, },
238 { 0x20, HDMI_DVI },
239 },
240 {
241 { 1280, 1024, 108000, 112, 48, 248, 3, 1, 38,
242 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
243 false, },
244 { 0x23, HDMI_DVI },
245 },
246 {
247 { 1024, 768, 65000, 136, 24, 160, 6, 3, 29,
248 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
249 false, },
250 { 0x10, HDMI_DVI },
251 },
252 {
253 { 1400, 1050, 121750, 144, 88, 232, 4, 3, 32,
254 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
255 false, },
256 { 0x2A, HDMI_DVI },
257 },
258 {
259 { 1440, 900, 106500, 152, 80, 232, 6, 3, 25,
260 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
261 false, },
262 { 0x2F, HDMI_DVI },
263 },
264 {
265 { 1680, 1050, 146250, 176 , 104, 280, 6, 3, 30,
266 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
267 false, },
268 { 0x3A, HDMI_DVI },
269 },
270 {
271 { 1366, 768, 85500, 143, 70, 213, 3, 3, 24,
272 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
273 false, },
274 { 0x51, HDMI_DVI },
275 },
276 {
277 { 1920, 1080, 148500, 44, 148, 80, 5, 4, 36,
278 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
279 false, },
280 { 0x52, HDMI_DVI },
281 },
282 {
283 { 1280, 768, 68250, 32, 48, 80, 7, 3, 12,
284 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
285 false, },
286 { 0x16, HDMI_DVI },
287 },
288 {
289 { 1400, 1050, 101000, 32, 48, 80, 4, 3, 23,
290 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
291 false, },
292 { 0x29, HDMI_DVI },
293 },
294 {
295 { 1680, 1050, 119000, 32, 48, 80, 6, 3, 21,
296 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
297 false, },
298 { 0x39, HDMI_DVI },
299 },
300 {
301 { 1280, 800, 79500, 32, 48, 80, 6, 3, 14,
302 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
303 false, },
304 { 0x1B, HDMI_DVI },
305 },
306 {
307 { 1280, 720, 74250, 40, 110, 220, 5, 5, 20,
308 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
309 false, },
310 { 0x55, HDMI_DVI },
311 },
312 {
313 { 1920, 1200, 154000, 32, 48, 80, 6, 3, 26,
314 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
315 false, },
316 { 0x44, HDMI_DVI },
317 },
318 };
320 static const struct hdmi_config s3d_timings[] = {
321 {
322 { 1280, 1470, 148500, 40, 110, 220, 5, 5, 20,
323 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
324 false, },
325 { 4, HDMI_HDMI },
326 },
327 {
328 { 1280, 1470, 148500, 40, 440, 220, 5, 5, 20,
329 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
330 false, },
331 { 19, HDMI_HDMI },
332 },
333 {
334 { 1920, 2205, 148500, 44, 638, 148, 5, 4, 36,
335 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
336 false, },
337 { 32, HDMI_HDMI },
338 },
339 };
341 static void hdmi_set_ls_state(enum level_shifter_state state)
342 {
343 bool hpd_enable = false;
344 bool ls_enable = false;
346 /* return early if we have nothing to do */
347 if (state == hdmi.ls_state)
348 return;
350 sel_i2c();
352 switch (state) {
353 case LS_HPD_ON:
354 hpd_enable = true;
355 break;
357 case LS_ENABLED:
358 hpd_enable = true;
359 ls_enable = true;
360 break;
362 case LS_DISABLED:
363 default:
364 break;
365 }
367 gpio_set_value_cansleep(hdmi.ct_cp_hpd_gpio, hpd_enable);
369 gpio_set_value_cansleep(hdmi.ls_oe_gpio, ls_enable);
371 /* wait 300us after asserting CT_CP_HPD for the 5V rail to reach 90% */
372 if (hdmi.ls_state == LS_DISABLED)
373 udelay(300);
375 hdmi.ls_state = state;
377 sel_hdmi();
378 }
380 static int hdmi_runtime_get(void)
381 {
382 int r;
384 DSSDBG("hdmi_runtime_get\n");
386 r = pm_runtime_get_sync(&hdmi.pdev->dev);
387 WARN_ON(r < 0);
388 if (r < 0)
389 return r;
391 return 0;
392 }
394 static void hdmi_runtime_put(void)
395 {
396 int r;
398 DSSDBG("hdmi_runtime_put\n");
400 r = pm_runtime_put_sync(&hdmi.pdev->dev);
401 WARN_ON(r < 0 && r != -ENOSYS);
402 }
404 static int __init hdmi_init_display(struct omap_dss_device *dssdev)
405 {
406 int r;
408 struct gpio gpios[] = {
409 { hdmi.ct_cp_hpd_gpio, GPIOF_OUT_INIT_LOW, "hdmi_ct_cp_hpd" },
410 { hdmi.ls_oe_gpio, GPIOF_OUT_INIT_LOW, "hdmi_ls_oe" },
411 { hdmi.hpd_gpio, GPIOF_DIR_IN, "hdmi_hpd" },
412 };
414 DSSDBG("init_display\n");
416 if (hdmi.vdda_hdmi_dac_reg == NULL) {
417 struct regulator *reg;
419 reg = devm_regulator_get(&hdmi.pdev->dev, "vdda_hdmi_dac");
421 /* DT HACK: try VDAC to make omapdss work for o4 sdp/panda */
422 if (IS_ERR(reg))
423 reg = devm_regulator_get(&hdmi.pdev->dev, "VDAC");
425 if (IS_ERR(reg)) {
426 DSSERR("can't get VDDA_HDMI_DAC regulator\n");
427 return PTR_ERR(reg);
428 }
430 hdmi.vdda_hdmi_dac_reg = reg;
431 }
433 r = gpio_request_array(gpios, ARRAY_SIZE(gpios));
434 if (r)
435 return r;
437 return 0;
438 }
440 static void hdmi_uninit_display(struct omap_dss_device *dssdev)
441 {
442 DSSDBG("uninit_display\n");
444 gpio_free(hdmi.ct_cp_hpd_gpio);
445 gpio_free(hdmi.ls_oe_gpio);
446 gpio_free(hdmi.hpd_gpio);
447 }
449 static const struct hdmi_config *hdmi_find_timing(
450 const struct hdmi_config *timings_arr,
451 int len)
452 {
453 int i;
455 for (i = 0; i < len; i++) {
456 if (timings_arr[i].cm.code == hdmi.ip_data.cfg.cm.code)
457 return &timings_arr[i];
458 }
459 return NULL;
460 }
462 static const struct hdmi_config *hdmi_get_timings(void)
463 {
464 const struct hdmi_config *arr;
465 int len;
467 if (!hdmi.ip_data.cfg.s3d_enabled) {
468 if (hdmi.ip_data.cfg.cm.mode == HDMI_DVI) {
469 arr = vesa_timings;
470 len = ARRAY_SIZE(vesa_timings);
471 } else {
472 arr = cea_timings;
473 len = ARRAY_SIZE(cea_timings);
474 }
475 } else {
476 arr = s3d_timings;
477 len = ARRAY_SIZE(s3d_timings);
478 }
480 return hdmi_find_timing(arr, len);
481 }
483 static bool hdmi_timings_compare(struct omap_video_timings *timing1,
484 const struct omap_video_timings *timing2)
485 {
486 int timing1_vsync, timing1_hsync, timing2_vsync, timing2_hsync;
488 if ((DIV_ROUND_CLOSEST(timing2->pixel_clock, 1000) ==
489 DIV_ROUND_CLOSEST(timing1->pixel_clock, 1000)) &&
490 (timing2->x_res == timing1->x_res) &&
491 (timing2->y_res == timing1->y_res)) {
493 timing2_hsync = timing2->hfp + timing2->hsw + timing2->hbp;
494 timing1_hsync = timing1->hfp + timing1->hsw + timing1->hbp;
495 timing2_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
496 timing1_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
498 DSSDBG("timing1_hsync = %d timing1_vsync = %d"\
499 "timing2_hsync = %d timing2_vsync = %d\n",
500 timing1_hsync, timing1_vsync,
501 timing2_hsync, timing2_vsync);
503 if ((timing1_hsync == timing2_hsync) &&
504 (timing1_vsync == timing2_vsync)) {
505 return true;
506 }
507 }
508 return false;
509 }
511 static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing)
512 {
513 int i;
514 struct hdmi_cm cm = {-1};
515 DSSDBG("hdmi_get_code\n");
517 for (i = 0; i < ARRAY_SIZE(cea_timings); i++) {
518 if (hdmi_timings_compare(timing, &cea_timings[i].timings)) {
519 cm = cea_timings[i].cm;
520 goto end;
521 }
522 }
523 for (i = 0; i < ARRAY_SIZE(vesa_timings); i++) {
524 if (hdmi_timings_compare(timing, &vesa_timings[i].timings)) {
525 cm = vesa_timings[i].cm;
526 goto end;
527 }
528 }
529 for (i = 0; i < ARRAY_SIZE(s3d_timings); i++) {
530 if (hdmi_timings_compare(timing, &s3d_timings[i].timings)) {
531 cm = s3d_timings[i].cm;
532 goto end;
533 }
534 }
536 end: return cm;
538 }
540 unsigned long hdmi_get_pixel_clock(void)
541 {
542 /* HDMI Pixel Clock in Mhz */
543 return hdmi.ip_data.cfg.timings.pixel_clock * 1000;
544 }
546 static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
547 struct hdmi_pll_info *pi)
548 {
549 unsigned long clkin, refclk;
550 enum omapdss_version version = omapdss_get_version();
551 u32 mf;
553 clkin = clk_get_rate(hdmi.sys_clk) / 10000;
554 /*
555 * Input clock is predivided by N + 1
556 * out put of which is reference clk
557 */
558 if (dssdev->clocks.hdmi.regn == 0)
559 pi->regn = HDMI_DEFAULT_REGN;
560 else
561 pi->regn = dssdev->clocks.hdmi.regn;
563 refclk = clkin / pi->regn;
565 if (dssdev->clocks.hdmi.regm2 == 0) {
566 switch (version)
567 {
568 case OMAPDSS_VER_OMAP4430_ES1:
569 case OMAPDSS_VER_OMAP4430_ES2:
570 case OMAPDSS_VER_OMAP4:
571 pi->regm2 = HDMI_DEFAULT_REGM2;
572 break;
573 case OMAPDSS_VER_OMAP5:
574 case OMAPDSS_VER_DRA7xx:
575 if (phy <= 50000)
576 pi->regm2 = 5;
577 else
578 pi->regm2 = 1;
579 break;
580 default:
581 DSSWARN("invalid omapdss version");
582 break;
584 }
585 } else {
586 pi->regm2 = dssdev->clocks.hdmi.regm2;
587 }
589 /*
590 * multiplier is pixel_clk/ref_clk
591 * Multiplying by 100 to avoid fractional part removal
592 */
593 pi->regm = phy * pi->regm2 / refclk;
595 /*
596 * fractional multiplier is remainder of the difference between
597 * multiplier and actual phy(required pixel clock thus should be
598 * multiplied by 2^18(262144) divided by the reference clock
599 */
600 mf = (phy - pi->regm / pi->regm2 * refclk) * 262144;
601 pi->regmf = pi->regm2 * mf / refclk;
603 /*
604 * Dcofreq should be set to 1 if required pixel clock
605 * is greater than 1000MHz
606 */
607 pi->dcofreq = phy > 1000 * 100;
608 pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10;
610 /* Set the reference clock to sysclk reference */
611 pi->refsel = HDMI_REFSEL_SYSCLK;
613 DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf);
614 DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
615 }
617 static int hdmi_power_on_core(struct omap_dss_device *dssdev)
618 {
619 int r;
621 hdmi_set_ls_state(LS_ENABLED);
623 r = regulator_enable(hdmi.vdda_hdmi_dac_reg);
624 if (r)
625 goto err_vdac_enable;
627 r = hdmi_runtime_get();
628 if (r)
629 goto err_runtime_get;
631 /* Make selection of HDMI in DSS */
632 dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
634 return 0;
636 err_runtime_get:
637 regulator_disable(hdmi.vdda_hdmi_dac_reg);
638 err_vdac_enable:
639 hdmi_set_ls_state(LS_HPD_ON);
640 return r;
641 }
643 static void hdmi_power_off_core(struct omap_dss_device *dssdev)
644 {
645 hdmi_runtime_put();
646 regulator_disable(hdmi.vdda_hdmi_dac_reg);
648 hdmi_set_ls_state(LS_HPD_ON);
649 }
651 static int hdmi_power_on_full(struct omap_dss_device *dssdev)
652 {
653 int r;
654 struct omap_video_timings *p;
655 struct omap_overlay_manager *mgr = dssdev->output->manager;
656 unsigned long phy;
658 r = hdmi_power_on_core(dssdev);
659 if (r)
660 return r;
662 dss_mgr_disable(mgr);
664 p = &hdmi.ip_data.cfg.timings;
666 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res);
668 switch (hdmi.ip_data.cfg.deep_color) {
669 case HDMI_DEEP_COLOR_30BIT:
670 phy = (p->pixel_clock * 125) / 100 ;
671 break;
672 case HDMI_DEEP_COLOR_36BIT:
673 if (p->pixel_clock >= 148500) {
674 DSSERR("36 bit deep color not supported for the pixel clock %d\n",
675 p->pixel_clock);
676 goto err_deep_color;
677 }
678 phy = (p->pixel_clock * 150) / 100;
679 break;
680 case HDMI_DEEP_COLOR_24BIT:
681 default:
682 phy = p->pixel_clock;
683 break;
684 }
686 hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data);
688 hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
690 /* config the PLL and PHY hdmi_set_pll_pwrfirst */
691 r = hdmi.ip_data.ops->pll_enable(&hdmi.ip_data);
692 if (r) {
693 DSSDBG("Failed to lock PLL\n");
694 goto err_pll_enable;
695 }
697 r = hdmi.ip_data.ops->phy_enable(&hdmi.ip_data);
698 /*
699 * DRA7xx doesn't show the correct PHY transition changes in the
700 * WP_PWR_CTRL register, need to investigate
701 */
702 if (omapdss_get_version() == OMAPDSS_VER_DRA7xx)
703 r = 0;
705 if (r) {
706 DSSDBG("Failed to start PHY\n");
707 goto err_phy_enable;
708 }
710 hdmi.ip_data.ops->video_configure(&hdmi.ip_data);
712 /* bypass TV gamma table */
713 dispc_enable_gamma_table(0);
715 /* tv size */
716 dss_mgr_set_timings(mgr, p);
718 r = hdmi.ip_data.ops->video_enable(&hdmi.ip_data);
719 if (r)
720 goto err_vid_enable;
722 r = dss_mgr_enable(mgr);
723 if (r)
724 goto err_mgr_enable;
726 return 0;
728 err_mgr_enable:
729 hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
730 err_vid_enable:
731 hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
732 err_phy_enable:
733 hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
734 err_pll_enable:
735 err_deep_color:
736 hdmi_power_off_core(dssdev);
737 return -EIO;
738 }
740 static void hdmi_power_off_full(struct omap_dss_device *dssdev)
741 {
742 struct omap_overlay_manager *mgr = dssdev->output->manager;
744 dss_mgr_disable(mgr);
746 hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
747 hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
748 hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
750 hdmi.ip_data.cfg.deep_color = HDMI_DEEP_COLOR_24BIT;
752 hdmi_power_off_core(dssdev);
753 }
755 int omapdss_hdmi_set_deepcolor(struct omap_dss_device *dssdev, int val,
756 bool hdmi_restart)
757 {
758 int r;
760 if (!hdmi_restart) {
761 hdmi.ip_data.cfg.deep_color = val;
762 return 0;
763 }
765 omapdss_hdmi_display_disable(dssdev);
767 hdmi.ip_data.cfg.deep_color = val;
769 r = omapdss_hdmi_display_enable(dssdev);
770 if (r)
771 return r;
773 return 0;
774 }
776 int omapdss_hdmi_get_deepcolor(void)
777 {
778 return hdmi.ip_data.cfg.deep_color;
779 }
781 int omapdss_hdmi_set_range(int range)
782 {
783 int r = 0;
784 enum hdmi_range old_range;
786 old_range = hdmi.ip_data.cfg.range;
787 hdmi.ip_data.cfg.range = range;
789 /* HDMI 1.3 section 6.6 VGA (640x480) format requires Full Range */
790 if ((range == 0) &&
791 ((hdmi.ip_data.cfg.cm.code == 4 &&
792 hdmi.ip_data.cfg.cm.mode == HDMI_DVI) ||
793 (hdmi.ip_data.cfg.cm.code == 1 &&
794 hdmi.ip_data.cfg.cm.mode == HDMI_HDMI)))
795 return -EINVAL;
797 r = hdmi.ip_data.ops->configure_range(&hdmi.ip_data);
798 if (r)
799 hdmi.ip_data.cfg.range = old_range;
801 return r;
802 }
804 int omapdss_hdmi_get_range(void)
805 {
806 return hdmi.ip_data.cfg.range;
807 }
809 int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
810 struct omap_video_timings *timings)
811 {
812 struct hdmi_cm cm;
814 cm = hdmi_get_code(timings);
815 if (cm.code == -1) {
816 return -EINVAL;
817 }
819 return 0;
821 }
823 int omapdss_hdmi_display_3d_enable(struct omap_dss_device *dssdev,
824 struct s3d_disp_info *info, int code)
825 {
826 struct omap_dss_output *out = dssdev->output;
827 int r = 0;
829 DSSDBG("ENTER hdmi_display_3d_enable\n");
831 mutex_lock(&hdmi.lock);
833 if (out == NULL || out->manager == NULL) {
834 DSSERR("failed to enable display: no output/manager\n");
835 r = -ENODEV;
836 goto err0;
837 }
839 r = omap_dss_start_device(dssdev);
840 if (r) {
841 DSSERR("failed to start device\n");
842 goto err0;
843 }
845 if (dssdev->platform_enable) {
846 r = dssdev->platform_enable(dssdev);
847 if (r) {
848 DSSERR("failed to enable GPIO's\n");
849 goto err1;
850 }
851 }
853 /* hdmi.s3d_enabled will be updated when powering display up */
854 /* if there's no S3D support it will be reset to false */
855 switch (info->type) {
856 case S3D_DISP_OVERUNDER:
857 if (info->sub_samp == S3D_DISP_SUB_SAMPLE_NONE) {
858 dssdev->panel.s3d_info = *info;
859 hdmi.ip_data.cfg.s3d_info.frame_struct =
860 HDMI_S3D_FRAME_PACKING;
861 hdmi.ip_data.cfg.s3d_info.subsamp = false;
862 hdmi.ip_data.cfg.s3d_info.subsamp_pos = 0;
863 hdmi.ip_data.cfg.s3d_enabled = true;
864 hdmi.ip_data.cfg.s3d_info.vsi_enabled = true;
865 } else {
866 goto err2;
867 }
868 break;
869 case S3D_DISP_SIDEBYSIDE:
870 dssdev->panel.s3d_info = *info;
871 if (info->sub_samp == S3D_DISP_SUB_SAMPLE_NONE) {
872 hdmi.ip_data.cfg.s3d_info.frame_struct =
873 HDMI_S3D_SIDE_BY_SIDE_FULL;
874 hdmi.ip_data.cfg.s3d_info.subsamp = true;
875 hdmi.ip_data.cfg.s3d_info.subsamp_pos =
876 HDMI_S3D_HOR_EL_ER;
877 hdmi.ip_data.cfg.s3d_enabled = true;
878 hdmi.ip_data.cfg.s3d_info.vsi_enabled = true;
879 } else if (info->sub_samp == S3D_DISP_SUB_SAMPLE_H) {
880 hdmi.ip_data.cfg.s3d_info.frame_struct =
881 HDMI_S3D_SIDE_BY_SIDE_HALF;
882 hdmi.ip_data.cfg.s3d_info.subsamp = true;
883 hdmi.ip_data.cfg.s3d_info.subsamp_pos =
884 HDMI_S3D_HOR_EL_ER;
885 hdmi.ip_data.cfg.s3d_info.vsi_enabled = true;
886 } else {
887 goto err2;
888 }
889 break;
890 default:
891 goto err2;
892 }
893 if (hdmi.ip_data.cfg.s3d_enabled) {
894 hdmi.ip_data.cfg.cm.code = code;
895 hdmi.ip_data.cfg.cm.mode = HDMI_HDMI;
896 }
898 r = hdmi_power_on_full(dssdev);
899 if (r) {
900 DSSERR("failed to power on device\n");
901 goto err2;
902 }
904 mutex_unlock(&hdmi.lock);
905 return 0;
907 err2:
908 if (dssdev->platform_disable)
909 dssdev->platform_disable(dssdev);
910 err1:
911 omap_dss_stop_device(dssdev);
912 err0:
913 mutex_unlock(&hdmi.lock);
914 return r;
915 }
917 void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev,
918 struct omap_video_timings *timings)
919 {
920 struct hdmi_cm cm;
921 const struct hdmi_config *t;
923 mutex_lock(&hdmi.lock);
925 cm = hdmi_get_code(timings);
926 hdmi.ip_data.cfg.cm = cm;
928 t = hdmi_get_timings();
929 if (t != NULL)
930 hdmi.ip_data.cfg = *t;
932 mutex_unlock(&hdmi.lock);
933 }
935 static void hdmi_dump_regs(struct seq_file *s)
936 {
937 mutex_lock(&hdmi.lock);
939 if (hdmi_runtime_get()) {
940 mutex_unlock(&hdmi.lock);
941 return;
942 }
944 hdmi.ip_data.ops->dump_wrapper(&hdmi.ip_data, s);
945 hdmi.ip_data.ops->dump_pll(&hdmi.ip_data, s);
946 hdmi.ip_data.ops->dump_phy(&hdmi.ip_data, s);
947 hdmi.ip_data.ops->dump_core(&hdmi.ip_data, s);
949 hdmi_runtime_put();
950 mutex_unlock(&hdmi.lock);
951 }
953 int omapdss_hdmi_read_edid(u8 *buf, int len)
954 {
955 int r;
956 enum level_shifter_state restore_state = hdmi.ls_state;
958 /* skip if no monitor attached */
959 if (!gpio_get_value(hdmi.hpd_gpio))
960 return -ENODEV;
962 mutex_lock(&hdmi.lock);
964 r = hdmi_runtime_get();
965 BUG_ON(r);
968 hdmi_set_ls_state(LS_ENABLED);
970 r = hdmi.ip_data.ops->read_edid(&hdmi.ip_data, buf, len);
972 /* restore level shifter state */
973 hdmi_set_ls_state(restore_state);
975 hdmi_runtime_put();
976 mutex_unlock(&hdmi.lock);
978 return r;
979 }
981 bool omapdss_hdmi_detect(void)
982 {
983 int r;
985 mutex_lock(&hdmi.lock);
987 r = hdmi_runtime_get();
988 BUG_ON(r);
990 r = hdmi.ip_data.ops->detect(&hdmi.ip_data);
992 hdmi_runtime_put();
993 mutex_unlock(&hdmi.lock);
995 return r == 1;
996 }
998 int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev)
999 {
1000 struct omap_dss_output *out = dssdev->output;
1001 int r = 0;
1003 DSSDBG("ENTER hdmi_display_enable\n");
1005 mutex_lock(&hdmi.lock);
1007 if (out == NULL || out->manager == NULL) {
1008 DSSERR("failed to enable display: no output/manager\n");
1009 r = -ENODEV;
1010 goto err0;
1011 }
1013 hdmi.ip_data.hpd_gpio = hdmi.hpd_gpio;
1015 r = omap_dss_start_device(dssdev);
1016 if (r) {
1017 DSSERR("failed to start device\n");
1018 goto err0;
1019 }
1021 r = hdmi_power_on_full(dssdev);
1022 if (r) {
1023 DSSERR("failed to power on device\n");
1024 goto err1;
1025 }
1027 mutex_unlock(&hdmi.lock);
1028 return 0;
1030 err1:
1031 omap_dss_stop_device(dssdev);
1032 err0:
1033 mutex_unlock(&hdmi.lock);
1034 return r;
1035 }
1037 void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev)
1038 {
1039 DSSDBG("Enter hdmi_display_disable\n");
1041 mutex_lock(&hdmi.lock);
1043 hdmi_power_off_full(dssdev);
1045 omap_dss_stop_device(dssdev);
1047 mutex_unlock(&hdmi.lock);
1048 }
1050 int omapdss_hdmi_core_enable(struct omap_dss_device *dssdev)
1051 {
1052 int r = 0;
1054 DSSDBG("ENTER omapdss_hdmi_core_enable\n");
1056 mutex_lock(&hdmi.lock);
1058 hdmi.ip_data.hpd_gpio = hdmi.hpd_gpio;
1060 r = hdmi_power_on_core(dssdev);
1061 if (r) {
1062 DSSERR("failed to power on device\n");
1063 goto err0;
1064 }
1066 mutex_unlock(&hdmi.lock);
1067 return 0;
1069 err0:
1070 mutex_unlock(&hdmi.lock);
1071 return r;
1072 }
1074 void omapdss_hdmi_core_disable(struct omap_dss_device *dssdev)
1075 {
1076 DSSDBG("Enter omapdss_hdmi_core_disable\n");
1078 mutex_lock(&hdmi.lock);
1080 hdmi_power_off_core(dssdev);
1082 mutex_unlock(&hdmi.lock);
1083 }
1085 static irqreturn_t hdmi_irq_handler(int irq, void *arg)
1086 {
1087 int r = 0;
1089 r = hdmi.ip_data.ops->irq_handler(&hdmi.ip_data);
1090 DSSDBG("Received HDMI IRQ = %08x\n", r);
1092 r = hdmi.ip_data.ops->irq_core_handler(&hdmi.ip_data);
1093 DSSDBG("Received HDMI core IRQ = %08x\n", r);
1095 return IRQ_HANDLED;
1096 }
1098 static int hdmi_get_clocks(struct platform_device *pdev)
1099 {
1100 struct clk *clk;
1102 clk = clk_get(&pdev->dev, "sys_clk");
1103 if (IS_ERR(clk)) {
1104 DSSERR("can't get sys_clk\n");
1105 return PTR_ERR(clk);
1106 }
1108 hdmi.sys_clk = clk;
1110 return 0;
1111 }
1113 static void hdmi_put_clocks(void)
1114 {
1115 if (hdmi.sys_clk)
1116 clk_put(hdmi.sys_clk);
1117 }
1119 #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) || \
1120 defined(CONFIG_OMAP5_DSS_HDMI_AUDIO)
1121 static int hdmi_probe_audio(struct platform_device *pdev)
1122 {
1123 struct resource *res;
1124 struct platform_device *aud_pdev;
1125 u32 port_offset, port_size;
1126 struct resource aud_res[2] = {
1127 DEFINE_RES_MEM(-1, -1),
1128 DEFINE_RES_DMA(-1),
1129 };
1131 res = platform_get_resource(hdmi.pdev, IORESOURCE_MEM, 0);
1132 if (!res) {
1133 DSSERR("can't get IORESOURCE_MEM HDMI\n");
1134 return -EINVAL;
1135 }
1137 /*
1138 * Pass DMA audio port to audio drivers.
1139 * Audio drivers should not ioremap it.
1140 */
1141 hdmi.ip_data.ops->audio_get_dma_port(&port_offset, &port_size);
1143 aud_res[0].start = res->start + port_offset;
1144 aud_res[0].end = aud_res[0].start + port_size - 1;
1146 res = platform_get_resource(hdmi.pdev, IORESOURCE_DMA, 0);
1147 if (!res) {
1148 DSSERR("can't get IORESOURCE_DMA HDMI\n");
1149 return -EINVAL;
1150 }
1152 /* Pass the audio DMA request resource to audio drivers. */
1153 aud_res[1].start = res->start;
1155 /* create platform device for HDMI audio driver */
1156 aud_pdev = platform_device_register_simple("omap-hdmi-audio",
1157 pdev->id, aud_res,
1158 ARRAY_SIZE(aud_res));
1159 if (IS_ERR(aud_pdev)) {
1160 DSSERR("Can't instantiate hdmi-audio\n");
1161 return -ENODEV;
1162 }
1164 hdmi.audio_pdev = aud_pdev;
1166 return 0;
1167 }
1169 int hdmi_compute_acr(u32 sample_freq, u32 *n, u32 *cts)
1170 {
1171 int r;
1172 u32 deep_color;
1173 u32 pclk = hdmi.ip_data.cfg.timings.pixel_clock;
1175 if (n == NULL || cts == NULL || sample_freq == 0)
1176 return -EINVAL;
1178 /* TODO: When implemented, query deep color mode here. */
1179 deep_color = 100;
1181 switch (sample_freq) {
1182 case 32000:
1183 if (deep_color == 125 && pclk == 74250) {
1184 *n = 8192;
1185 break;
1186 }
1188 if (deep_color == 125 && pclk == 27027) {
1189 /*
1190 * For this specific configuration, no value within the
1191 * allowed interval of N (as per the HDMI spec) will
1192 * produce an integer value of CTS. The value we use
1193 * here will produce CTS = 11587.000427246, which is
1194 * slightly larger than the integer. This difference
1195 * could cause the audio clock at the sink to slowly
1196 * drift. The true solution requires alternating between
1197 * two CTS relevant values with careful timing in order
1198 * to, on average, obtain the true CTS float value.
1199 */
1200 *n = 13529;
1201 break;
1202 }
1204 if (deep_color == 150 && pclk == 27027) {
1205 *n = 8192;
1206 break;
1207 }
1209 *n = 4096;
1210 break;
1211 case 44100:
1212 if (deep_color == 125 && pclk == 27027) {
1213 *n = 12544;
1214 break;
1215 }
1217 *n = 6272;
1218 break;
1219 case 48000:
1220 if (deep_color == 125 && (pclk == 27027 || pclk == 74250)) {
1221 *n = 8192;
1222 break;
1223 }
1225 if (deep_color == 150 && pclk == 27027) {
1226 *n = 8192;
1227 break;
1228 }
1230 *n = 6144;
1231 break;
1232 case 88200:
1233 r = hdmi_compute_acr(44100, n, cts);
1234 *n *= 2;
1235 return r;
1236 case 96000:
1237 r = hdmi_compute_acr(48000, n, cts);
1238 *n *= 2;
1239 return r;
1240 case 176400:
1241 r = hdmi_compute_acr(44100, n, cts);
1242 *n *= 4;
1243 return r;
1244 case 192000:
1245 r = hdmi_compute_acr(48000, n, cts);
1246 *n *= 4;
1247 return r;
1248 default:
1249 return -EINVAL;
1250 }
1252 /*
1253 * Calculate CTS. See HDMI 1.3a or 1.4a specifications. Preserve the
1254 * remainder in case N is not a multiple of 128.
1255 */
1256 *cts = (*n / 128) * pclk * deep_color;
1257 *cts += (*n % 128) * pclk * deep_color / 128;
1258 *cts /= (sample_freq / 10);
1260 if ((pclk * (*n / 128) * deep_color) % (sample_freq / 10))
1261 DSSWARN("CTS is not integer fs[%u]pclk[%u]N[%u]\n",
1262 sample_freq, pclk, *n);
1264 return 0;
1265 }
1267 int hdmi_audio_enable(void)
1268 {
1269 DSSDBG("audio_enable\n");
1271 return hdmi.ip_data.ops->audio_enable(&hdmi.ip_data);
1272 }
1274 void hdmi_audio_disable(void)
1275 {
1276 DSSDBG("audio_disable\n");
1278 hdmi.ip_data.ops->audio_disable(&hdmi.ip_data);
1279 }
1281 int hdmi_audio_start(void)
1282 {
1283 DSSDBG("audio_start\n");
1285 return hdmi.ip_data.ops->audio_start(&hdmi.ip_data);
1286 }
1288 void hdmi_audio_stop(void)
1289 {
1290 DSSDBG("audio_stop\n");
1292 hdmi.ip_data.ops->audio_stop(&hdmi.ip_data);
1293 }
1295 bool hdmi_mode_has_audio(void)
1296 {
1297 if (hdmi.ip_data.cfg.cm.mode == HDMI_HDMI)
1298 return true;
1299 else
1300 return false;
1301 }
1303 int hdmi_audio_config(struct omap_dss_audio *audio)
1304 {
1305 return hdmi.ip_data.ops->audio_config(&hdmi.ip_data, audio);
1306 }
1308 #endif
1310 static struct omap_dss_device * __init hdmi_find_dssdev(struct platform_device *pdev)
1311 {
1312 struct omap_dss_board_info *pdata = pdev->dev.platform_data;
1313 const char *def_disp_name = omapdss_get_default_display_name();
1314 struct omap_dss_device *def_dssdev;
1315 int i;
1317 def_dssdev = NULL;
1319 for (i = 0; i < pdata->num_devices; ++i) {
1320 struct omap_dss_device *dssdev = pdata->devices[i];
1322 if (dssdev->type != OMAP_DISPLAY_TYPE_HDMI)
1323 continue;
1325 if (def_dssdev == NULL)
1326 def_dssdev = dssdev;
1328 if (def_disp_name != NULL &&
1329 strcmp(dssdev->name, def_disp_name) == 0) {
1330 def_dssdev = dssdev;
1331 break;
1332 }
1333 }
1335 return def_dssdev;
1336 }
1338 static void __init hdmi_probe_pdata(struct platform_device *pdev)
1339 {
1340 struct omap_dss_device *plat_dssdev;
1341 struct omap_dss_device *dssdev;
1342 struct omap_dss_hdmi_data *priv;
1343 int r;
1345 plat_dssdev = hdmi_find_dssdev(pdev);
1347 if (!plat_dssdev)
1348 return;
1350 dssdev = dss_alloc_and_init_device(&pdev->dev);
1351 if (!dssdev)
1352 return;
1354 dss_copy_device_pdata(dssdev, plat_dssdev);
1356 priv = dssdev->data;
1358 hdmi.ct_cp_hpd_gpio = priv->ct_cp_hpd_gpio;
1359 hdmi.ls_oe_gpio = priv->ls_oe_gpio;
1360 hdmi.hpd_gpio = priv->hpd_gpio;
1362 dssdev->channel = OMAP_DSS_CHANNEL_DIGIT;
1364 r = hdmi_init_display(dssdev);
1365 if (r) {
1366 DSSERR("device %s init failed: %d\n", dssdev->name, r);
1367 dss_put_device(dssdev);
1368 return;
1369 }
1371 r = omapdss_output_set_device(&hdmi.output, dssdev);
1372 if (r) {
1373 DSSERR("failed to connect output to new device: %s\n",
1374 dssdev->name);
1375 dss_put_device(dssdev);
1376 return;
1377 }
1379 r = dss_add_device(dssdev);
1380 if (r) {
1381 DSSERR("device %s register failed: %d\n", dssdev->name, r);
1382 omapdss_output_unset_device(&hdmi.output);
1383 hdmi_uninit_display(dssdev);
1384 dss_put_device(dssdev);
1385 return;
1386 }
1387 }
1389 struct i2c_adapter *omapdss_hdmi_adapter(void)
1390 {
1391 return hdmi.adap;
1392 }
1394 static void ddc_set_sda(void *data, int state)
1395 {
1396 if (state)
1397 gpio_direction_input(hdmi.sda_pin);
1398 else
1399 gpio_direction_output(hdmi.sda_pin, 0);
1400 }
1402 static void ddc_set_scl(void *data, int state)
1403 {
1404 if (state)
1405 gpio_direction_input(hdmi.scl_pin);
1406 else
1407 gpio_direction_output(hdmi.scl_pin, 0);
1408 }
1410 static int ddc_get_sda(void *data)
1411 {
1412 return gpio_get_value(hdmi.sda_pin);
1413 }
1415 static int ddc_get_scl(void *data)
1416 {
1417 return gpio_get_value(hdmi.scl_pin);
1418 }
1420 static int ddc_pre_xfer(struct i2c_adapter *adap)
1421 {
1422 /* don't read if no hdmi connected */
1423 if (!gpio_get_value(hdmi.hpd_gpio))
1424 return -ENODEV;
1426 gpio_set_value_cansleep(hdmi.ls_oe_gpio, 1);
1428 return 0;
1429 }
1430 static void ddc_post_xfer(struct i2c_adapter *adap)
1431 {
1432 hdmi_set_ls_state(hdmi.ls_state);
1433 }
1435 static void ddc_i2c_init(struct platform_device *pdev)
1436 {
1438 hdmi.adap = kzalloc(sizeof(*hdmi.adap), GFP_KERNEL);
1440 if (!hdmi.adap) {
1441 pr_err("Failed to allocate i2c adapter\n");
1442 return;
1443 }
1445 hdmi.adap->owner = THIS_MODULE;
1446 hdmi.adap->class = I2C_CLASS_DDC;
1447 hdmi.adap->dev.parent = &pdev->dev;
1448 hdmi.adap->algo_data = &hdmi.bit_data;
1449 hdmi.adap->algo = &i2c_bit_algo;
1450 hdmi.bit_data.udelay = 2;
1451 hdmi.bit_data.timeout = HZ/10;
1452 hdmi.bit_data.setsda = ddc_set_sda;
1453 hdmi.bit_data.setscl = ddc_set_scl;
1454 hdmi.bit_data.getsda = ddc_get_sda;
1455 hdmi.bit_data.getscl = ddc_get_scl;
1456 hdmi.bit_data.pre_xfer = ddc_pre_xfer;
1457 hdmi.bit_data.post_xfer = ddc_post_xfer;
1459 gpio_request(hdmi.sda_pin, "DDC SDA");
1460 gpio_request(hdmi.scl_pin, "DDC SCL");
1461 snprintf(hdmi.adap->name, sizeof(hdmi.adap->name),
1462 "DSS DDC-EDID adapter");
1463 if (i2c_add_adapter(hdmi.adap)) {
1464 DSSERR("Cannot initialize DDC I2c\n");
1465 kfree(hdmi.adap);
1466 hdmi.adap = NULL;
1467 }
1468 }
1470 static void init_sel_i2c_hdmi(void)
1471 {
1472 void __iomem *clk_base = ioremap(0x4A009000, SZ_4K);
1473 void __iomem *mcasp2_base = ioremap(0x48464000, SZ_1K);
1474 void __iomem *pinmux = ioremap(0x4a003600, SZ_1K);
1475 u32 val;
1477 if (omapdss_get_version() != OMAPDSS_VER_DRA7xx)
1478 goto err;
1480 if (!clk_base || !mcasp2_base || !pinmux)
1481 DSSERR("couldn't ioremap for clk or mcasp2\n");
1483 __raw_writel(0x40000, pinmux + 0xfc);
1484 /* sw supervised wkup */
1485 __raw_writel(0x2, clk_base + 0x8fc);
1487 /* enable clock domain */
1488 __raw_writel(0x2, clk_base + 0x860);
1490 /* see what status looks like */
1491 val = __raw_readl(clk_base + 0x8fc);
1492 printk("CM_L4PER2_CLKSTCTRL %x\n", val);
1494 /*
1495 * mcasp2 regs should be hopefully accessible, make mcasp2_aclkr
1496 * a gpio, write necessary stuff to MCASP_PFUNC and PDIR
1497 */
1498 __raw_writel(0x1 << 29, mcasp2_base + 0x10);
1499 __raw_writel(0x1 << 29, mcasp2_base + 0x14);
1501 err:
1502 iounmap(clk_base);
1503 iounmap(mcasp2_base);
1504 iounmap(pinmux);
1505 }
1507 /* use this to configure the pcf8575@22 to set LS_OE and CT_HPD */
1508 void sel_i2c(void)
1509 {
1510 void __iomem *base = ioremap(0x48464000, SZ_1K);
1512 if (omapdss_get_version() != OMAPDSS_VER_DRA7xx)
1513 goto err;
1515 /* PDOUT */
1516 __raw_writel(0x0, base + 0x18);
1518 DSSDBG("PDOUT sel_i2c %x\n", __raw_readl(base + 0x18));
1520 err:
1521 iounmap(base);
1522 }
1524 /* use this to read edid and detect hpd ? */
1525 void sel_hdmi(void)
1526 {
1527 void __iomem *base = ioremap(0x48464000, SZ_1K);
1529 if (omapdss_get_version() != OMAPDSS_VER_DRA7xx)
1530 goto err;
1532 /* PDOUT */
1533 __raw_writel(0x20000000, base + 0x18);
1535 DSSDBG("PDOUT sel_hdmi %x\n", __raw_readl(base + 0x18));
1537 err:
1538 iounmap(base);
1539 }
1541 static void __init hdmi_probe_of(struct platform_device *pdev)
1542 {
1543 struct device_node *node = pdev->dev.of_node;
1544 struct device_node *child;
1545 struct omap_dss_device *dssdev;
1546 int r, gpio;
1547 enum omap_channel channel;
1548 u32 v;
1549 int gpio_count;
1551 r = of_property_read_u32(node, "video-source", &v);
1552 if (r) {
1553 DSSERR("parsing channel failed\n");
1554 return;
1555 }
1557 channel = v;
1559 node = of_find_compatible_node(node, NULL, "ti,tpd12s015");
1560 if (!node)
1561 return;
1563 child = of_get_next_available_child(node, NULL);
1564 if (!child)
1565 return;
1567 gpio_count = of_gpio_count(node);
1569 /* OMAP4 derivatives have 3 pins defined, OMAP5 derivatives have 5 */
1570 if (gpio_count != 5 && gpio_count != 3) {
1571 DSSERR("wrong number of GPIOs\n");
1572 return;
1573 }
1575 gpio = of_get_gpio(node, 0);
1576 if (gpio_is_valid(gpio)) {
1577 hdmi.ct_cp_hpd_gpio = gpio;
1578 } else {
1579 DSSERR("failed to parse CT CP HPD gpio\n");
1580 return;
1581 }
1583 gpio = of_get_gpio(node, 1);
1584 if (gpio_is_valid(gpio)) {
1585 hdmi.ls_oe_gpio = gpio;
1586 } else {
1587 DSSERR("failed to parse LS OE gpio\n");
1588 return;
1589 }
1591 gpio = of_get_gpio(node, 2);
1592 if (gpio_is_valid(gpio)) {
1593 hdmi.hpd_gpio = gpio;
1594 } else {
1595 DSSERR("failed to parse HPD gpio\n");
1596 return;
1597 }
1599 /* if I2C SCL and SDA pins are defined, parse them */
1600 /* these will only be valid for OMAP5 derivatives */
1601 if (gpio_count == 5) {
1602 gpio = of_get_gpio(node, 3);
1603 if (gpio_is_valid(gpio)) {
1604 hdmi.scl_pin = gpio;
1605 } else {
1606 DSSERR("failed to parse SCL gpio\n");
1607 return;
1608 }
1610 gpio = of_get_gpio(node, 4);
1611 if (gpio_is_valid(gpio)) {
1612 hdmi.sda_pin = gpio;
1613 } else {
1614 DSSERR("failed to parse SDA gpio\n");
1615 return;
1616 }
1617 } else if (adapter != NULL) {
1618 hdmi.adap = adapter;
1620 /*
1621 * we have SEL_I2C_HDMI pin which acts as a control line to
1622 * a demux which choses the i2c lines to go either to hdmi
1623 * or to the other i2c2 slaves. This line is used as a mcasp2
1624 * gpio. Init the gpio pin so that it can be used to control
1625 * the demux.
1626 */
1627 init_sel_i2c_hdmi();
1628 sel_i2c();
1629 }
1631 dssdev = dss_alloc_and_init_device(&pdev->dev);
1632 if (!dssdev)
1633 return;
1635 dssdev->dev.of_node = child;
1636 dssdev->type = OMAP_DISPLAY_TYPE_HDMI;
1637 dssdev->name = child->name;
1638 dssdev->channel = channel;
1640 r = hdmi_init_display(dssdev);
1641 if (r) {
1642 DSSERR("device %s init failed: %d\n", dssdev->name, r);
1643 dss_put_device(dssdev);
1644 return;
1645 }
1647 r = omapdss_output_set_device(&hdmi.output, dssdev);
1648 if (r) {
1649 DSSERR("failed to connect output to new device: %s\n",
1650 dssdev->name);
1651 dss_put_device(dssdev);
1652 return;
1653 }
1655 r = dss_add_device(dssdev);
1656 if (r) {
1657 DSSERR("dss_add_device failed %d\n", r);
1658 dss_put_device(dssdev);
1659 return;
1660 }
1661 }
1663 static void __init hdmi_init_output(struct platform_device *pdev)
1664 {
1665 struct omap_dss_output *out = &hdmi.output;
1667 out->pdev = pdev;
1668 out->id = OMAP_DSS_OUTPUT_HDMI;
1669 out->type = OMAP_DISPLAY_TYPE_HDMI;
1671 dss_register_output(out);
1672 }
1674 static void __exit hdmi_uninit_output(struct platform_device *pdev)
1675 {
1676 struct omap_dss_output *out = &hdmi.output;
1678 dss_unregister_output(out);
1679 }
1681 /* HDMI HW IP initialisation */
1682 static int __init omapdss_hdmihw_probe(struct platform_device *pdev)
1683 {
1684 struct resource *res;
1685 int r;
1687 hdmi.pdev = pdev;
1689 mutex_init(&hdmi.lock);
1690 mutex_init(&hdmi.ip_data.lock);
1692 dss_init_hdmi_ip_ops(&hdmi.ip_data, omapdss_get_version());
1694 /* HDMI wrapper memory remap */
1695 res = platform_get_resource_byname(hdmi.pdev,
1696 IORESOURCE_MEM, "hdmi_wp");
1697 if (!res) {
1698 DSSERR("can't get WP IORESOURCE_MEM HDMI\n");
1699 return -EINVAL;
1700 }
1702 /* Base address taken from platform */
1703 hdmi.ip_data.base_wp = devm_request_and_ioremap(&pdev->dev, res);
1704 if (!hdmi.ip_data.base_wp) {
1705 DSSERR("can't ioremap WP\n");
1706 return -ENOMEM;
1707 }
1709 /* HDMI PLLCTRL memory remap */
1710 res = platform_get_resource_byname(hdmi.pdev,
1711 IORESOURCE_MEM, "pllctrl");
1712 if (!res) {
1713 DSSERR("can't get PLL CTRL IORESOURCE_MEM HDMI\n");
1714 return -EINVAL;
1715 }
1717 hdmi.ip_data.base_pllctrl = devm_request_and_ioremap(&pdev->dev, res);
1718 if (!hdmi.ip_data.base_pllctrl) {
1719 DSSERR("can't ioremap PLL ctrl\n");
1720 return -ENOMEM;
1721 }
1723 /* HDMI TXPHYCTRL memory remap */
1724 res = platform_get_resource_byname(hdmi.pdev,
1725 IORESOURCE_MEM, "hdmitxphy");
1726 if (!res) {
1727 DSSERR("can't get TXPHY CTRL IORESOURCE_MEM HDMI\n");
1728 return -EINVAL;
1729 }
1731 hdmi.ip_data.base_txphyctrl = devm_request_and_ioremap(&pdev->dev, res);
1732 if (!hdmi.ip_data.base_txphyctrl) {
1733 DSSERR("can't ioremap TXPHY ctrl\n");
1734 return -ENOMEM;
1735 }
1737 /* HDMI core memory remap */
1738 res = platform_get_resource_byname(hdmi.pdev,
1739 IORESOURCE_MEM, "hdmi_core");
1740 if (!res) {
1741 DSSERR("can't get core IORESOURCE_MEM HDMI\n");
1742 return -EINVAL;
1743 }
1745 hdmi.ip_data.base_core = devm_request_and_ioremap(&pdev->dev, res);
1746 if (!hdmi.ip_data.base_core) {
1747 DSSERR("can't ioremap core\n");
1748 return -ENOMEM;
1749 }
1751 r = hdmi_get_clocks(pdev);
1752 if (r) {
1753 DSSERR("can't get clocks\n");
1754 return r;
1755 }
1757 pm_runtime_enable(&pdev->dev);
1759 hdmi.hdmi_irq = platform_get_irq(pdev, 0);
1760 r = request_irq(hdmi.hdmi_irq, hdmi_irq_handler, 0, "OMAP HDMI", NULL);
1761 if (r < 0) {
1762 pr_err("hdmi: request_irq %s failed\n", pdev->name);
1763 return -EINVAL;
1764 }
1766 r = hdmi_panel_init();
1767 if (r) {
1768 DSSERR("can't init panel\n");
1769 goto err_panel_init;
1770 }
1772 dss_debugfs_create_file("hdmi", hdmi_dump_regs);
1774 hdmi_init_output(pdev);
1776 if (pdev->dev.of_node)
1777 hdmi_probe_of(pdev);
1778 else if (pdev->dev.platform_data)
1779 hdmi_probe_pdata(pdev);
1781 /* if i2c pins defined, setup I2C adapter */
1782 if (hdmi.scl_pin && hdmi.sda_pin)
1783 ddc_i2c_init(pdev);
1785 #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) || \
1786 defined(CONFIG_OMAP5_DSS_HDMI_AUDIO)
1787 r = hdmi_probe_audio(pdev);
1788 if (r)
1789 DSSWARN("could not create platform device for audio");
1790 #endif
1792 return 0;
1794 err_panel_init:
1795 hdmi_put_clocks();
1796 return r;
1797 }
1799 static int __exit hdmi_remove_child(struct device *dev, void *data)
1800 {
1801 struct omap_dss_device *dssdev = to_dss_device(dev);
1802 hdmi_uninit_display(dssdev);
1803 return 0;
1804 }
1806 static int __exit omapdss_hdmihw_remove(struct platform_device *pdev)
1807 {
1808 #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) || \
1809 defined(CONFIG_OMAP5_DSS_HDMI_AUDIO)
1810 if (hdmi.audio_pdev != NULL)
1811 platform_device_unregister(hdmi.audio_pdev);
1812 #endif
1814 kfree(hdmi.adap);
1816 device_for_each_child(&pdev->dev, NULL, hdmi_remove_child);
1818 dss_unregister_child_devices(&pdev->dev);
1820 hdmi_panel_exit();
1822 hdmi_uninit_output(pdev);
1824 pm_runtime_disable(&pdev->dev);
1826 hdmi_put_clocks();
1828 return 0;
1829 }
1831 static int hdmi_runtime_suspend(struct device *dev)
1832 {
1833 clk_disable_unprepare(hdmi.sys_clk);
1835 dispc_runtime_put();
1837 return 0;
1838 }
1840 static int hdmi_runtime_resume(struct device *dev)
1841 {
1842 int r;
1844 r = dispc_runtime_get();
1845 if (r < 0)
1846 return r;
1848 clk_prepare_enable(hdmi.sys_clk);
1850 return 0;
1851 }
1853 static const struct dev_pm_ops hdmi_pm_ops = {
1854 .runtime_suspend = hdmi_runtime_suspend,
1855 .runtime_resume = hdmi_runtime_resume,
1856 };
1858 #if defined(CONFIG_OF)
1859 static const struct of_device_id hdmi_of_match[] = {
1860 {
1861 .compatible = "ti,omap4-hdmi",
1862 },
1863 {},
1864 };
1865 #else
1866 #define hdmi_of_match NULL
1867 #endif
1869 static struct platform_driver omapdss_hdmihw_driver = {
1870 .remove = __exit_p(omapdss_hdmihw_remove),
1871 .driver = {
1872 .name = "omapdss_hdmi",
1873 .owner = THIS_MODULE,
1874 .pm = &hdmi_pm_ops,
1875 .of_match_table = hdmi_of_match,
1876 },
1877 };
1879 int __init hdmi_init_platform_driver(void)
1880 {
1881 return platform_driver_probe(&omapdss_hdmihw_driver, omapdss_hdmihw_probe);
1882 }
1884 void __exit hdmi_uninit_platform_driver(void)
1885 {
1886 platform_driver_unregister(&omapdss_hdmihw_driver);
1887 }