1 /*
2 * hdmi.c
3 *
4 * HDMI interface DSS driver setting for TI's OMAP4 family of processor.
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
6 * Authors: Yong Zhi
7 * Mythri pk <mythripk@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
22 #define DSS_SUBSYS_NAME "HDMI"
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/err.h>
27 #include <linux/io.h>
28 #include <linux/interrupt.h>
29 #include <linux/mutex.h>
30 #include <linux/delay.h>
31 #include <linux/string.h>
32 #include <linux/platform_device.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/clk.h>
35 #include <linux/gpio.h>
36 #include <linux/regulator/consumer.h>
37 #include <linux/slab.h>
38 #include <linux/of_gpio.h>
39 #include <linux/of_i2c.h>
40 #include <linux/fb.h>
41 #include <linux/omapfb.h>
42 #include <video/omapdss.h>
43 #include <linux/i2c.h>
44 #include <linux/i2c-algo-bit.h>
46 #include "ti_hdmi.h"
47 #include "dss.h"
48 #include "dss_features.h"
50 /* HDMI EDID Length move this */
51 #define HDMI_EDID_MAX_LENGTH 512
52 #define EDID_TIMING_DESCRIPTOR_SIZE 0x12
53 #define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36
54 #define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80
55 #define EDID_HDMI_VENDOR_SPECIFIC_DATA_BLOCK 128
56 #define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4
57 #define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4
59 static struct {
60 struct mutex lock;
61 struct platform_device *pdev;
62 #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) || \
63 defined(CONFIG_OMAP5_DSS_HDMI_AUDIO)
64 struct platform_device *audio_pdev;
65 #endif
66 int code;
67 int mode;
68 u8 edid[HDMI_EDID_MAX_LENGTH];
69 bool edid_set;
70 bool custom_set;
71 bool can_do_hdmi;
72 bool force_timings;
73 int source_physical_address;
75 struct hdmi_ip_data ip_data;
76 int hdmi_irq;
78 struct clk *sys_clk;
79 struct regulator *vdda_hdmi_dac_reg;
81 /* GPIO pins */
82 int ct_cp_hpd_gpio;
83 int ls_oe_gpio;
84 int hpd_gpio;
86 /* level shifter state */
87 enum level_shifter_state ls_state;
89 /*
90 * i2c adapter info(this could be either a bitbanged adapter, or a
91 * 'real' i2c adapter
92 */
93 struct i2c_adapter *adap;
95 /* these are needed in case it's a bitbanged adapter */
96 struct i2c_algo_bit_data bit_data;
97 int scl_pin;
98 int sda_pin;
100 struct omap_dss_output output;
101 } hdmi;
103 static const u8 edid_header[8] = {0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0};
105 /*
106 * Logic for the below structure :
107 * user enters the CEA or VESA timings by specifying the HDMI/DVI code.
108 * There is a correspondence between CEA/VESA timing and code, please
109 * refer to section 6.3 in HDMI 1.3 specification for timing code.
110 *
111 * In the below structure, cea_vesa_timings corresponds to all OMAP4
112 * supported CEA and VESA timing values.code_cea corresponds to the CEA
113 * code, It is used to get the timing from cea_vesa_timing array.Similarly
114 * with code_vesa. Code_index is used for back mapping, that is once EDID
115 * is read from the TV, EDID is parsed to find the timing values and then
116 * map it to corresponding CEA or VESA index.
117 */
119 static const struct hdmi_config cea_timings[] = {
120 {
121 { 640, 480, 25200, 96, 16, 48, 2, 10, 33,
122 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
123 false, },
124 { 1, HDMI_HDMI },
125 },
126 {
127 { 720, 480, 27027, 62, 16, 60, 6, 9, 30,
128 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
129 false, },
130 { 2, HDMI_HDMI },
131 },
132 {
133 { 1280, 720, 74250, 40, 110, 220, 5, 5, 20,
134 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
135 false, },
136 { 4, HDMI_HDMI },
137 },
138 {
139 { 1920, 540, 74250, 44, 88, 148, 5, 2, 15,
140 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
141 true, },
142 { 5, HDMI_HDMI },
143 },
144 {
145 { 1440, 240, 27027, 124, 38, 114, 3, 4, 15,
146 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
147 true, },
148 { 6, HDMI_HDMI },
149 },
150 {
151 { 1920, 1080, 148500, 44, 88, 148, 5, 4, 36,
152 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
153 false, },
154 { 16, HDMI_HDMI },
155 },
156 {
157 { 720, 576, 27000, 64, 12, 68, 5, 5, 39,
158 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
159 false, },
160 { 17, HDMI_HDMI },
161 },
162 {
163 { 1280, 720, 74250, 40, 440, 220, 5, 5, 20,
164 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
165 false, },
166 { 19, HDMI_HDMI },
167 },
168 {
169 { 1920, 540, 74250, 44, 528, 148, 5, 2, 15,
170 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
171 true, },
172 { 20, HDMI_HDMI },
173 },
174 {
175 { 1440, 288, 27000, 126, 24, 138, 3, 2, 19,
176 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
177 true, },
178 { 21, HDMI_HDMI },
179 },
180 {
181 { 1440, 576, 54000, 128, 24, 136, 5, 5, 39,
182 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
183 false, },
184 { 29, HDMI_HDMI },
185 },
186 {
187 { 1920, 1080, 148500, 44, 528, 148, 5, 4, 36,
188 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
189 false, },
190 { 31, HDMI_HDMI },
191 },
192 {
193 { 1920, 1080, 74250, 44, 638, 148, 5, 4, 36,
194 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
195 false, },
196 { 32, HDMI_HDMI },
197 },
198 {
199 { 2880, 480, 108108, 248, 64, 240, 6, 9, 30,
200 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
201 false, },
202 { 35, HDMI_HDMI },
203 },
204 {
205 { 2880, 576, 108000, 256, 48, 272, 5, 5, 39,
206 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
207 false, },
208 { 37, HDMI_HDMI },
209 },
210 };
212 static const struct hdmi_config vesa_timings[] = {
213 /* VESA From Here */
214 {
215 { 640, 480, 25175, 96, 16, 48, 2, 11, 31,
216 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
217 false, },
218 { 4, HDMI_DVI },
219 },
220 {
221 { 800, 600, 40000, 128, 40, 88, 4, 1, 23,
222 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
223 false, },
224 { 9, HDMI_DVI },
225 },
226 {
227 { 848, 480, 33750, 112, 16, 112, 8, 6, 23,
228 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
229 false, },
230 { 0xE, HDMI_DVI },
231 },
232 {
233 { 1280, 768, 79500, 128, 64, 192, 7, 3, 20,
234 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
235 false, },
236 { 0x17, HDMI_DVI },
237 },
238 {
239 { 1280, 800, 83500, 128, 72, 200, 6, 3, 22,
240 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
241 false, },
242 { 0x1C, HDMI_DVI },
243 },
244 {
245 { 1360, 768, 85500, 112, 64, 256, 6, 3, 18,
246 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
247 false, },
248 { 0x27, HDMI_DVI },
249 },
250 {
251 { 1280, 960, 108000, 112, 96, 312, 3, 1, 36,
252 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
253 false, },
254 { 0x20, HDMI_DVI },
255 },
256 {
257 { 1280, 1024, 108000, 112, 48, 248, 3, 1, 38,
258 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
259 false, },
260 { 0x23, HDMI_DVI },
261 },
262 {
263 { 1024, 768, 65000, 136, 24, 160, 6, 3, 29,
264 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
265 false, },
266 { 0x10, HDMI_DVI },
267 },
268 {
269 { 1400, 1050, 121750, 144, 88, 232, 4, 3, 32,
270 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
271 false, },
272 { 0x2A, HDMI_DVI },
273 },
274 {
275 { 1440, 900, 106500, 152, 80, 232, 6, 3, 25,
276 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
277 false, },
278 { 0x2F, HDMI_DVI },
279 },
280 {
281 { 1680, 1050, 146250, 176 , 104, 280, 6, 3, 30,
282 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
283 false, },
284 { 0x3A, HDMI_DVI },
285 },
286 {
287 { 1366, 768, 85500, 143, 70, 213, 3, 3, 24,
288 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
289 false, },
290 { 0x51, HDMI_DVI },
291 },
292 {
293 { 1920, 1080, 148500, 44, 148, 80, 5, 4, 36,
294 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
295 false, },
296 { 0x52, HDMI_DVI },
297 },
298 {
299 { 1280, 768, 68250, 32, 48, 80, 7, 3, 12,
300 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
301 false, },
302 { 0x16, HDMI_DVI },
303 },
304 {
305 { 1400, 1050, 101000, 32, 48, 80, 4, 3, 23,
306 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
307 false, },
308 { 0x29, HDMI_DVI },
309 },
310 {
311 { 1680, 1050, 119000, 32, 48, 80, 6, 3, 21,
312 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
313 false, },
314 { 0x39, HDMI_DVI },
315 },
316 {
317 { 1280, 800, 79500, 32, 48, 80, 6, 3, 14,
318 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
319 false, },
320 { 0x1B, HDMI_DVI },
321 },
322 {
323 { 1280, 720, 74250, 40, 110, 220, 5, 5, 20,
324 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
325 false, },
326 { 0x55, HDMI_DVI },
327 },
328 {
329 { 1920, 1200, 154000, 32, 48, 80, 6, 3, 26,
330 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
331 false, },
332 { 0x44, HDMI_DVI },
333 },
334 };
336 static const struct hdmi_config s3d_timings[] = {
337 {
338 { 1280, 1470, 148500, 40, 110, 220, 5, 5, 20,
339 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
340 false, },
341 { 4, HDMI_HDMI },
342 },
343 {
344 { 1280, 1470, 148500, 40, 440, 220, 5, 5, 20,
345 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
346 false, },
347 { 19, HDMI_HDMI },
348 },
349 {
350 { 1920, 2205, 148500, 44, 638, 148, 5, 4, 36,
351 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
352 false, },
353 { 32, HDMI_HDMI },
354 },
355 };
357 static void hdmi_set_ls_state(enum level_shifter_state state)
358 {
359 bool hpd_enable = false;
360 bool ls_enable = false;
362 /* return early if we have nothing to do */
363 if (state == hdmi.ls_state)
364 return;
366 sel_i2c();
368 switch (state) {
369 case LS_HPD_ON:
370 hpd_enable = true;
371 break;
373 case LS_ENABLED:
374 hpd_enable = true;
375 ls_enable = true;
376 break;
378 case LS_DISABLED:
379 default:
380 break;
381 }
383 gpio_set_value_cansleep(hdmi.ct_cp_hpd_gpio, hpd_enable);
385 gpio_set_value_cansleep(hdmi.ls_oe_gpio, ls_enable);
387 /* wait 300us after asserting CT_CP_HPD for the 5V rail to reach 90% */
388 if (hdmi.ls_state == LS_DISABLED)
389 udelay(300);
391 hdmi.ls_state = state;
393 sel_hdmi();
394 }
396 static int relaxed_fb_mode_is_equal(const struct fb_videomode *mode1,
397 const struct fb_videomode *mode2)
398 {
399 u32 ratio1 = mode1->flag & (FB_FLAG_RATIO_4_3 | FB_FLAG_RATIO_16_9);
400 u32 ratio2 = mode2->flag & (FB_FLAG_RATIO_4_3 | FB_FLAG_RATIO_16_9);
401 return (mode1->xres == mode2->xres &&
402 mode1->yres == mode2->yres &&
403 mode1->pixclock <= mode2->pixclock * 201 / 200 &&
404 mode1->pixclock >= mode2->pixclock * 200 / 201 &&
405 mode1->hsync_len + mode1->left_margin + mode1->right_margin ==
406 mode2->hsync_len + mode2->left_margin + mode2->right_margin &&
407 mode1->vsync_len + mode1->upper_margin + mode1->lower_margin ==
408 mode2->vsync_len + mode2->upper_margin + mode2->lower_margin &&
409 (!ratio1 || !ratio2 || ratio1 == ratio2) &&
410 (mode1->vmode & FB_VMODE_INTERLACED) ==
411 (mode2->vmode & FB_VMODE_INTERLACED));
413 }
415 static int hdmi_set_timings(struct fb_videomode *vm, bool check_only)
416 {
417 int i = 0;
418 int r = 0;
419 DSSDBG("hdmi_set_timings\n");
421 if (!vm->xres || !vm->yres || !vm->pixclock)
422 goto fail;
424 for (i = 0; i < CEA_MODEDB_SIZE; i++) {
425 if (relaxed_fb_mode_is_equal(cea_modes + i, vm)) {
426 *vm = cea_modes[i];
427 if (check_only)
428 return 1;
429 hdmi.ip_data.cfg.cm.code = i;
430 hdmi.ip_data.cfg.cm.mode = HDMI_HDMI;
431 hdmi.ip_data.cfg.timingsfb =
432 cea_modes[hdmi.ip_data.cfg.cm.code];
433 goto done;
434 }
435 }
436 for (i = 0; i < VESA_MODEDB_SIZE; i++) {
437 if (relaxed_fb_mode_is_equal(vesa_modes + i, vm)) {
438 *vm = vesa_modes[i];
439 if (check_only)
440 return 1;
441 hdmi.ip_data.cfg.cm.code = i;
442 hdmi.ip_data.cfg.cm.mode = HDMI_DVI;
443 hdmi.ip_data.cfg.timingsfb =
444 vesa_modes[hdmi.ip_data.cfg.cm.code];
445 goto done;
446 }
447 }
448 fail:
449 if (check_only)
450 return 0;
451 hdmi.ip_data.cfg.cm.code = 1;
452 hdmi.ip_data.cfg.cm.mode = HDMI_HDMI;
453 hdmi.ip_data.cfg.timingsfb = cea_modes[hdmi.ip_data.cfg.cm.code];
454 i = -1;
455 done:
456 DSSDBG("%s-%d\n", hdmi.ip_data.cfg.cm.mode ? "CEA" : "VESA",
457 hdmi.ip_data.cfg.cm.code);
459 /* convert fb timing to dss timings to be in sync. */
460 omapfb_fb2dss_timings(&hdmi.ip_data.cfg.timingsfb,&hdmi.ip_data.cfg.timings);
462 r = i >= 0 ? 1 : 0;
463 return r;
465 }
467 void hdmi_get_monspecs(struct omap_dss_device *dssdev)
468 {
469 int i, j;
470 char *edid = (char *)hdmi.edid;
471 struct fb_monspecs *specs = &dssdev->panel.monspecs;
472 u32 fclk = dispc_fclk_rate() / 1000;
473 u32 max_pclk = dssdev->clocks.hdmi.max_pixclk_khz;
475 if (max_pclk && max_pclk < fclk)
476 fclk = max_pclk;
478 memset(specs, 0x0, sizeof(*specs));
479 if (!hdmi.edid_set)
480 return;
481 fb_edid_to_monspecs(edid, specs);
482 if (specs->modedb == NULL)
483 return;
485 for (i = 1; i <= edid[0x7e] && i * 128 < HDMI_EDID_MAX_LENGTH; i++) {
486 if (edid[i * 128] == 0x2)
487 fb_edid_add_monspecs(edid + i * 128, specs);
488 }
489 if (hdmi.force_timings) {
490 for (i = 0; i < specs->modedb_len; i++) {
491 specs->modedb[i++] = hdmi.ip_data.cfg.timingsfb;
492 break;
493 }
494 specs->modedb_len = i;
495 hdmi.force_timings = false;
496 return;
497 }
499 hdmi.can_do_hdmi = specs->misc & FB_MISC_HDMI;
501 /* filter out resolutions we don't support */
502 for (i = j = 0; i < specs->modedb_len; i++) {
503 if (!hdmi_set_timings(&specs->modedb[i], true))
504 continue;
505 if (fclk < PICOS2KHZ(specs->modedb[i].pixclock))
506 continue;
507 if (specs->modedb[i].flag & FB_FLAG_PIXEL_REPEAT)
508 continue;
509 specs->modedb[j++] = specs->modedb[i];
510 }
511 specs->modedb_len = j;
513 }
515 static int hdmi_runtime_get(void)
516 {
517 int r;
519 DSSDBG("hdmi_runtime_get\n");
521 r = pm_runtime_get_sync(&hdmi.pdev->dev);
522 WARN_ON(r < 0);
523 if (r < 0)
524 return r;
526 return 0;
527 }
529 static void hdmi_runtime_put(void)
530 {
531 int r;
533 DSSDBG("hdmi_runtime_put\n");
535 r = pm_runtime_put_sync(&hdmi.pdev->dev);
536 WARN_ON(r < 0 && r != -ENOSYS);
537 }
539 static int __init hdmi_init_display(struct omap_dss_device *dssdev)
540 {
541 int r;
543 struct gpio gpios[] = {
544 { hdmi.ct_cp_hpd_gpio, GPIOF_OUT_INIT_LOW, "hdmi_ct_cp_hpd" },
545 { hdmi.ls_oe_gpio, GPIOF_OUT_INIT_LOW, "hdmi_ls_oe" },
546 { hdmi.hpd_gpio, GPIOF_DIR_IN, "hdmi_hpd" },
547 };
549 DSSDBG("init_display\n");
551 if (hdmi.vdda_hdmi_dac_reg == NULL) {
552 struct regulator *reg;
554 reg = devm_regulator_get(&hdmi.pdev->dev, "vdda_hdmi_dac");
556 /* DT HACK: try VDAC to make omapdss work for o4 sdp/panda */
557 if (IS_ERR(reg))
558 reg = devm_regulator_get(&hdmi.pdev->dev, "VDAC");
560 if (IS_ERR(reg)) {
561 DSSERR("can't get VDDA_HDMI_DAC regulator\n");
562 return PTR_ERR(reg);
563 }
565 hdmi.vdda_hdmi_dac_reg = reg;
566 }
568 r = gpio_request_array(gpios, ARRAY_SIZE(gpios));
569 if (r)
570 return r;
572 return 0;
573 }
575 static void hdmi_uninit_display(struct omap_dss_device *dssdev)
576 {
577 DSSDBG("uninit_display\n");
579 gpio_free(hdmi.ct_cp_hpd_gpio);
580 gpio_free(hdmi.ls_oe_gpio);
581 gpio_free(hdmi.hpd_gpio);
582 }
584 static const struct hdmi_config *hdmi_find_timing(
585 const struct hdmi_config *timings_arr,
586 int len)
587 {
588 int i;
590 for (i = 0; i < len; i++) {
591 if (timings_arr[i].cm.code == hdmi.ip_data.cfg.cm.code)
592 return &timings_arr[i];
593 }
594 return NULL;
595 }
597 static const struct hdmi_config *hdmi_get_timings(void)
598 {
599 const struct hdmi_config *arr;
600 int len;
602 if (!hdmi.ip_data.cfg.s3d_enabled) {
603 if (hdmi.ip_data.cfg.cm.mode == HDMI_DVI) {
604 arr = vesa_timings;
605 len = ARRAY_SIZE(vesa_timings);
606 } else {
607 arr = cea_timings;
608 len = ARRAY_SIZE(cea_timings);
609 }
610 } else {
611 arr = s3d_timings;
612 len = ARRAY_SIZE(s3d_timings);
613 }
615 return hdmi_find_timing(arr, len);
616 }
618 static bool hdmi_timings_compare(struct omap_video_timings *timing1,
619 const struct omap_video_timings *timing2)
620 {
621 int timing1_vsync, timing1_hsync, timing2_vsync, timing2_hsync;
623 if ((DIV_ROUND_CLOSEST(timing2->pixel_clock, 1000) ==
624 DIV_ROUND_CLOSEST(timing1->pixel_clock, 1000)) &&
625 (timing2->x_res == timing1->x_res) &&
626 (timing2->y_res == timing1->y_res)) {
628 timing2_hsync = timing2->hfp + timing2->hsw + timing2->hbp;
629 timing1_hsync = timing1->hfp + timing1->hsw + timing1->hbp;
630 timing2_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
631 timing1_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
633 DSSDBG("timing1_hsync = %d timing1_vsync = %d"\
634 "timing2_hsync = %d timing2_vsync = %d\n",
635 timing1_hsync, timing1_vsync,
636 timing2_hsync, timing2_vsync);
638 if ((timing1_hsync == timing2_hsync) &&
639 (timing1_vsync == timing2_vsync)) {
640 return true;
641 }
642 }
643 return false;
644 }
646 static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing)
647 {
648 int i;
649 struct hdmi_cm cm = {-1};
650 DSSDBG("hdmi_get_code\n");
652 for (i = 0; i < ARRAY_SIZE(cea_timings); i++) {
653 if (hdmi_timings_compare(timing, &cea_timings[i].timings)) {
654 cm = cea_timings[i].cm;
655 goto end;
656 }
657 }
658 for (i = 0; i < ARRAY_SIZE(vesa_timings); i++) {
659 if (hdmi_timings_compare(timing, &vesa_timings[i].timings)) {
660 cm = vesa_timings[i].cm;
661 goto end;
662 }
663 }
664 for (i = 0; i < ARRAY_SIZE(s3d_timings); i++) {
665 if (hdmi_timings_compare(timing, &s3d_timings[i].timings)) {
666 cm = s3d_timings[i].cm;
667 goto end;
668 }
669 }
671 end: return cm;
673 }
675 u8 *hdmi_read_valid_edid(void)
676 {
677 int ret, i;
679 if (hdmi.edid_set)
680 return hdmi.edid;
682 memset(hdmi.edid, 0, HDMI_EDID_MAX_LENGTH);
684 hdmi_runtime_get();
686 ret = hdmi.ip_data.ops->read_edid(&hdmi.ip_data, hdmi.edid,
687 HDMI_EDID_MAX_LENGTH);
689 hdmi_runtime_put();
691 for (i = 0; i < HDMI_EDID_MAX_LENGTH; i += 16)
692 DSSDBG("edid[%03x] = %02x %02x %02x %02x %02x %02x %02x %02x "\
693 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
694 hdmi.edid[i], hdmi.edid[i + 1], hdmi.edid[i + 2],
695 hdmi.edid[i + 3], hdmi.edid[i + 4], hdmi.edid[i + 5],
696 hdmi.edid[i + 6], hdmi.edid[i + 7], hdmi.edid[i + 8],
697 hdmi.edid[i + 9], hdmi.edid[i + 10], hdmi.edid[i + 11],
698 hdmi.edid[i + 12], hdmi.edid[i + 13], hdmi.edid[i + 14],
699 hdmi.edid[i + 15]);
701 if (ret) {
702 DSSWARN("failed to read E-EDID\n");
703 return NULL;
704 }
705 if (memcmp(hdmi.edid, edid_header, sizeof(edid_header))) {
706 DSSWARN("failed to read E-EDID: wrong header\n");
707 return NULL;
708 }
709 hdmi.edid_set = true;
711 return hdmi.edid;
712 }
714 unsigned long hdmi_get_pixel_clock(void)
715 {
716 /* HDMI Pixel Clock in Mhz */
717 return hdmi.ip_data.cfg.timings.pixel_clock * 1000;
718 }
720 static int hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
721 struct hdmi_pll_info *pi)
722 {
723 unsigned long clkin, refclk;
724 int phy_calc;
725 unsigned long regn_max, regn_min, regm_min, regm_max;
726 unsigned long fint_min, fint_max;
727 unsigned long dco_low_min, dco_high_min;
728 bool found = false;
729 u32 mf;
731 clkin = clk_get_rate(hdmi.sys_clk) / 10000;
733 fint_min = dss_feat_get_param_min(FEAT_PARAM_HDMIPLL_FINT) / 10000;
734 fint_max = dss_feat_get_param_max(FEAT_PARAM_HDMIPLL_FINT) / 10000;
736 /* clkin limits */
737 /* .62 MHz < CLKIN/REGN < 2.5MHz */
738 regn_min = clkin / fint_max + 1;
739 regn_max = clkin / fint_min;
741 /* Fractional limits on REGM */
742 regm_min = dss_feat_get_param_min(FEAT_PARAM_HDMIPLL_REGM);
743 regm_max = dss_feat_get_param_max(FEAT_PARAM_HDMIPLL_REGM);
745 /* DCO frequency ranges */
747 /* DCO lowest frequency supported */
748 dco_low_min = dss_feat_get_param_min(FEAT_PARAM_DCOFREQ_LOW) / 10000;
750 /* Starting frequency of high frequency range(in Mhz) */
751 dco_high_min = dss_feat_get_param_min(FEAT_PARAM_DCOFREQ_HIGH);
753 /* set dcofreq to 1 if required clock is > 1.25GHz */
754 pi->dcofreq = phy > (dco_high_min / 10000);
756 if (phy < dco_low_min) {
757 /* Calculate CLKOUTLDO - low frequency */
758 for (pi->regn = regn_min; pi->regn < regn_max; pi->regn++) {
759 refclk = clkin / pi->regn;
761 regm_min = ((dco_low_min / refclk) < regm_min) ?
762 regm_min : (dco_low_min / refclk);
764 for (pi->regm2 = 3; pi->regm2 <= 127; pi->regm2++) {
765 pi->regm = phy * pi->regm2 / refclk;
766 if (pi->regm < regm_min || pi->regm > regm_max)
767 continue;
769 pi->regsd = DIV_ROUND_UP((pi->regm * clkin / 100),
770 pi->regn * 250);
771 phy_calc = clkin * pi->regm / pi->regn /
772 pi->regm2;
774 if (pi->regsd && pi->regsd < 255 &&
775 phy_calc <= phy) {
776 found = true;
777 break;
778 }
779 }
781 if (found)
782 break;
783 }
784 } else {
785 pi->regm2 = 1;
787 /* CLKDCOLDO - high frequency */
788 for (pi->regn = regn_min; pi->regn < regn_max; pi->regn++) {
789 refclk = clkin / pi->regn;
790 pi->regm = phy / refclk;
792 if (pi->regm < regm_min || pi->regm > regm_max)
793 continue;
795 pi->regsd = DIV_ROUND_UP((pi->regm * clkin / 100),
796 pi->regn * 250);
798 phy_calc = clkin * pi->regm / pi->regn;
800 if (pi->regsd < 255 && phy_calc <= phy) {
801 found = true;
802 break;
803 }
804 }
805 }
807 if (!found) {
808 DSSERR("Failed to find pll settings\n");
809 return 1;
810 }
812 /*
813 * fractional multiplier is remainder of the difference between
814 * multiplier and actual phy(required pixel clock thus should be
815 * multiplied by 2^18(262144) divided by the reference clock
816 */
817 mf = (phy - refclk * pi->regm / pi->regm2) * 262144;
818 pi->regmf = pi->regm2 * mf / refclk;
820 if (pi->regmf > 262144)
821 pi->regmf = 0;
823 /* Set the reference clock to sysclk reference */
824 pi->refsel = HDMI_REFSEL_SYSCLK;
826 DSSERR("M = %d Mf = %d\n", pi->regm, pi->regmf);
827 DSSERR("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
829 return 0;
830 }
832 static int hdmi_power_on_core(struct omap_dss_device *dssdev)
833 {
834 int r;
836 hdmi_set_ls_state(LS_ENABLED);
838 r = regulator_enable(hdmi.vdda_hdmi_dac_reg);
839 if (r)
840 goto err_vdac_enable;
842 r = hdmi_runtime_get();
843 if (r)
844 goto err_runtime_get;
846 /* Make selection of HDMI in DSS */
847 dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
849 return 0;
851 err_runtime_get:
852 regulator_disable(hdmi.vdda_hdmi_dac_reg);
853 err_vdac_enable:
854 hdmi_set_ls_state(LS_HPD_ON);
855 return r;
856 }
858 static void hdmi_power_off_core(struct omap_dss_device *dssdev)
859 {
860 hdmi_runtime_put();
861 regulator_disable(hdmi.vdda_hdmi_dac_reg);
863 hdmi_set_ls_state(LS_HPD_ON);
864 }
866 static int hdmi_power_on_full(struct omap_dss_device *dssdev)
867 {
868 int r;
869 struct omap_video_timings *p;
870 struct omap_overlay_manager *mgr = dssdev->output->manager;
871 unsigned long phy;
873 r = hdmi_power_on_core(dssdev);
874 if (r)
875 return r;
877 dss_mgr_disable(mgr);
879 p = &hdmi.ip_data.cfg.timings;
881 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res);
882 #ifdef CONFIG_USE_FB_MODE_DB
883 if (!hdmi.custom_set) {
884 struct fb_videomode fb_mode = vesa_modes[4];
885 if ((hdmi.ip_data.cfg.cm.code != 4) &&
886 (hdmi.ip_data.cfg.cm.mode != HDMI_DVI)) {
887 if (hdmi.ip_data.cfg.cm.mode == HDMI_DVI)
888 fb_mode = vesa_modes[hdmi.ip_data.cfg.cm.code];
889 else
890 fb_mode = cea_modes[hdmi.ip_data.cfg.cm.code];
891 }
892 if (!hdmi_set_timings(&fb_mode, false)) {
893 /* Fallback in case we cannot set the timings */
894 DSSERR("fallback to vesa default code");
895 fb_mode = vesa_modes[4];
896 hdmi_set_timings(&fb_mode, false);
897 }
898 }
900 /* Update the panel timing in dssdev */
901 omapfb_fb2dss_timings(&hdmi.ip_data.cfg.timingsfb,
902 &dssdev->panel.timings);
903 #endif
904 switch (hdmi.ip_data.cfg.deep_color) {
905 case HDMI_DEEP_COLOR_30BIT:
906 phy = (p->pixel_clock * 125) / 100 ;
907 break;
908 case HDMI_DEEP_COLOR_36BIT:
909 phy = (p->pixel_clock * 150) / 100;
911 if (phy >= dss_feat_get_param_max(FEAT_PARAM_HDMI_PCLK)) {
912 DSSERR("36 bit deep color not supported for the pixel clock %d\n",
913 p->pixel_clock);
914 goto err_deep_color;
915 }
916 break;
917 case HDMI_DEEP_COLOR_24BIT:
918 default:
919 phy = p->pixel_clock;
920 break;
921 }
923 if (hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data))
924 goto err_pll_compute;
926 hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
928 /* config the PLL and PHY hdmi_set_pll_pwrfirst */
929 r = hdmi.ip_data.ops->pll_enable(&hdmi.ip_data);
930 if (r) {
931 DSSDBG("Failed to lock PLL\n");
932 goto err_pll_enable;
933 }
935 r = hdmi.ip_data.ops->phy_enable(&hdmi.ip_data);
936 /*
937 * DRA7xx doesn't show the correct PHY transition changes in the
938 * WP_PWR_CTRL register, need to investigate
939 */
940 if (omapdss_get_version() == OMAPDSS_VER_DRA7xx)
941 r = 0;
943 if (r) {
944 DSSDBG("Failed to start PHY\n");
945 goto err_phy_enable;
946 }
948 hdmi.ip_data.cfg.cm.mode = hdmi.can_do_hdmi ? hdmi.mode : HDMI_DVI;
950 hdmi.ip_data.ops->video_configure(&hdmi.ip_data);
952 /* bypass TV gamma table */
953 dispc_enable_gamma_table(0);
955 /* tv size */
956 dss_mgr_set_timings(mgr, p);
958 r = hdmi.ip_data.ops->video_enable(&hdmi.ip_data);
959 if (r)
960 goto err_vid_enable;
962 r = dss_mgr_enable(mgr);
963 if (r)
964 goto err_mgr_enable;
966 return 0;
968 err_mgr_enable:
969 hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
970 err_vid_enable:
971 hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
972 err_phy_enable:
973 hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
974 err_pll_enable:
975 err_pll_compute:
976 err_deep_color:
977 hdmi_power_off_core(dssdev);
978 return -EIO;
979 }
981 static void hdmi_power_off_full(struct omap_dss_device *dssdev)
982 {
983 struct omap_overlay_manager *mgr = dssdev->output->manager;
985 dss_mgr_disable(mgr);
987 hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
988 hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
989 hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
991 hdmi.ip_data.cfg.deep_color = HDMI_DEEP_COLOR_24BIT;
993 hdmi_power_off_core(dssdev);
994 }
996 int omapdss_hdmi_set_deepcolor(struct omap_dss_device *dssdev, int val,
997 bool hdmi_restart)
998 {
999 int r;
1001 if (!hdmi_restart) {
1002 hdmi.ip_data.cfg.deep_color = val;
1003 return 0;
1004 }
1006 omapdss_hdmi_display_disable(dssdev);
1008 hdmi.ip_data.cfg.deep_color = val;
1010 r = omapdss_hdmi_display_enable(dssdev);
1011 if (r)
1012 return r;
1014 return 0;
1015 }
1017 int omapdss_hdmi_get_deepcolor(void)
1018 {
1019 return hdmi.ip_data.cfg.deep_color;
1020 }
1022 int omapdss_hdmi_set_range(int range)
1023 {
1024 int r = 0;
1025 enum hdmi_range old_range;
1027 old_range = hdmi.ip_data.cfg.range;
1028 hdmi.ip_data.cfg.range = range;
1030 /* HDMI 1.3 section 6.6 VGA (640x480) format requires Full Range */
1031 if ((range == 0) &&
1032 ((hdmi.ip_data.cfg.cm.code == 4 &&
1033 hdmi.ip_data.cfg.cm.mode == HDMI_DVI) ||
1034 (hdmi.ip_data.cfg.cm.code == 1 &&
1035 hdmi.ip_data.cfg.cm.mode == HDMI_HDMI)))
1036 return -EINVAL;
1038 r = hdmi.ip_data.ops->configure_range(&hdmi.ip_data);
1039 if (r)
1040 hdmi.ip_data.cfg.range = old_range;
1042 return r;
1043 }
1045 int omapdss_hdmi_get_range(void)
1046 {
1047 return hdmi.ip_data.cfg.range;
1048 }
1050 int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
1051 struct omap_video_timings *timings)
1052 {
1053 #ifdef CONFIG_USE_FB_MODE_DB
1054 struct fb_videomode t;
1055 omapfb_dss2fb_timings(timings, &t);
1057 /* also check interlaced timings */
1058 if (!hdmi_set_timings(&t, true)) {
1059 t.yres *= 2;
1060 t.vmode |= FB_VMODE_INTERLACED;
1061 }
1062 if (!hdmi_set_timings(&t, true))
1063 return -EINVAL;
1064 #else
1065 struct hdmi_cm cm;
1067 cm = hdmi_get_code(timings);
1068 if (cm.code == -1) {
1069 return -EINVAL;
1070 }
1072 #endif
1073 return 0;
1075 }
1077 int omapdss_hdmi_display_set_mode(struct omap_dss_device *dssdev,
1078 struct fb_videomode *vm)
1079 {
1080 int r1, r2;
1081 /* turn the hdmi off and on to get new timings to use */
1082 hdmi.ip_data.set_mode = true;
1083 dssdev->driver->disable(dssdev);
1084 hdmi.ip_data.set_mode = false;
1085 r1 = hdmi_set_timings(vm, false) ? 0 : -EINVAL;
1086 hdmi.custom_set = true;
1087 hdmi.code = hdmi.ip_data.cfg.cm.code;
1088 hdmi.mode = hdmi.ip_data.cfg.cm.mode;
1089 r2 = dssdev->driver->enable(dssdev);
1090 return r1 ? : r2;
1091 }
1093 int omapdss_hdmi_display_3d_enable(struct omap_dss_device *dssdev,
1094 struct s3d_disp_info *info, int code)
1095 {
1096 struct omap_dss_output *out = dssdev->output;
1097 int r = 0;
1099 DSSDBG("ENTER hdmi_display_3d_enable\n");
1101 mutex_lock(&hdmi.lock);
1103 if (out == NULL || out->manager == NULL) {
1104 DSSERR("failed to enable display: no output/manager\n");
1105 r = -ENODEV;
1106 goto err0;
1107 }
1109 r = omap_dss_start_device(dssdev);
1110 if (r) {
1111 DSSERR("failed to start device\n");
1112 goto err0;
1113 }
1115 if (dssdev->platform_enable) {
1116 r = dssdev->platform_enable(dssdev);
1117 if (r) {
1118 DSSERR("failed to enable GPIO's\n");
1119 goto err1;
1120 }
1121 }
1123 /* hdmi.s3d_enabled will be updated when powering display up */
1124 /* if there's no S3D support it will be reset to false */
1125 switch (info->type) {
1126 case S3D_DISP_OVERUNDER:
1127 if (info->sub_samp == S3D_DISP_SUB_SAMPLE_NONE) {
1128 dssdev->panel.s3d_info = *info;
1129 hdmi.ip_data.cfg.s3d_info.frame_struct =
1130 HDMI_S3D_FRAME_PACKING;
1131 hdmi.ip_data.cfg.s3d_info.subsamp = false;
1132 hdmi.ip_data.cfg.s3d_info.subsamp_pos = 0;
1133 hdmi.ip_data.cfg.s3d_enabled = true;
1134 hdmi.ip_data.cfg.s3d_info.vsi_enabled = true;
1135 } else {
1136 goto err2;
1137 }
1138 break;
1139 case S3D_DISP_SIDEBYSIDE:
1140 dssdev->panel.s3d_info = *info;
1141 if (info->sub_samp == S3D_DISP_SUB_SAMPLE_NONE) {
1142 hdmi.ip_data.cfg.s3d_info.frame_struct =
1143 HDMI_S3D_SIDE_BY_SIDE_FULL;
1144 hdmi.ip_data.cfg.s3d_info.subsamp = true;
1145 hdmi.ip_data.cfg.s3d_info.subsamp_pos =
1146 HDMI_S3D_HOR_EL_ER;
1147 hdmi.ip_data.cfg.s3d_enabled = true;
1148 hdmi.ip_data.cfg.s3d_info.vsi_enabled = true;
1149 } else if (info->sub_samp == S3D_DISP_SUB_SAMPLE_H) {
1150 hdmi.ip_data.cfg.s3d_info.frame_struct =
1151 HDMI_S3D_SIDE_BY_SIDE_HALF;
1152 hdmi.ip_data.cfg.s3d_info.subsamp = true;
1153 hdmi.ip_data.cfg.s3d_info.subsamp_pos =
1154 HDMI_S3D_HOR_EL_ER;
1155 hdmi.ip_data.cfg.s3d_info.vsi_enabled = true;
1156 } else {
1157 goto err2;
1158 }
1159 break;
1160 default:
1161 goto err2;
1162 }
1163 if (hdmi.ip_data.cfg.s3d_enabled) {
1164 hdmi.ip_data.cfg.cm.code = code;
1165 hdmi.ip_data.cfg.cm.mode = HDMI_HDMI;
1166 }
1168 r = hdmi_power_on_full(dssdev);
1169 if (r) {
1170 DSSERR("failed to power on device\n");
1171 goto err2;
1172 }
1174 mutex_unlock(&hdmi.lock);
1175 return 0;
1177 err2:
1178 if (dssdev->platform_disable)
1179 dssdev->platform_disable(dssdev);
1180 err1:
1181 omap_dss_stop_device(dssdev);
1182 err0:
1183 mutex_unlock(&hdmi.lock);
1184 return r;
1185 }
1187 void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev,
1188 struct omap_video_timings *timings)
1189 {
1190 #ifdef CONFIG_USE_FB_MODE_DB
1191 struct fb_videomode t;
1193 DSSDBG("x_res= %d y_res = %d\n",
1194 dssdev->panel.timings.x_res,
1195 dssdev->panel.timings.y_res);
1197 omapfb_dss2fb_timings(&dssdev->panel.timings, &t);
1198 /* also check interlaced timings */
1199 if (!hdmi_set_timings(&t, true)) {
1200 t.yres *= 2;
1201 t.vmode |= FB_VMODE_INTERLACED;
1202 }
1203 omapdss_hdmi_display_set_mode(dssdev, &t);
1204 #else
1205 struct hdmi_cm cm;
1206 const struct hdmi_config *t;
1208 mutex_lock(&hdmi.lock);
1210 cm = hdmi_get_code(timings);
1211 hdmi.ip_data.cfg.cm = cm;
1213 t = hdmi_get_timings();
1214 if (t != NULL)
1215 hdmi.ip_data.cfg = *t;
1217 mutex_unlock(&hdmi.lock);
1218 #endif
1219 }
1221 static void hdmi_dump_regs(struct seq_file *s)
1222 {
1223 mutex_lock(&hdmi.lock);
1225 if (hdmi_runtime_get()) {
1226 mutex_unlock(&hdmi.lock);
1227 return;
1228 }
1230 hdmi.ip_data.ops->dump_wrapper(&hdmi.ip_data, s);
1231 hdmi.ip_data.ops->dump_pll(&hdmi.ip_data, s);
1232 hdmi.ip_data.ops->dump_phy(&hdmi.ip_data, s);
1233 hdmi.ip_data.ops->dump_core(&hdmi.ip_data, s);
1235 hdmi_runtime_put();
1236 mutex_unlock(&hdmi.lock);
1237 }
1239 int omapdss_hdmi_read_edid(u8 *buf, int len)
1240 {
1241 int r;
1242 enum level_shifter_state restore_state = hdmi.ls_state;
1244 /* skip if no monitor attached */
1245 if (!gpio_get_value(hdmi.hpd_gpio))
1246 return -ENODEV;
1248 mutex_lock(&hdmi.lock);
1250 r = hdmi_runtime_get();
1251 BUG_ON(r);
1254 hdmi_set_ls_state(LS_ENABLED);
1256 r = hdmi.ip_data.ops->read_edid(&hdmi.ip_data, buf, len);
1258 /* restore level shifter state */
1259 hdmi_set_ls_state(restore_state);
1261 hdmi_runtime_put();
1262 mutex_unlock(&hdmi.lock);
1264 return r;
1265 }
1267 bool omapdss_hdmi_detect(void)
1268 {
1269 int r;
1271 mutex_lock(&hdmi.lock);
1273 r = hdmi_runtime_get();
1274 BUG_ON(r);
1276 r = hdmi.ip_data.ops->detect(&hdmi.ip_data);
1278 hdmi_runtime_put();
1279 mutex_unlock(&hdmi.lock);
1281 return r == 1;
1282 }
1284 int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev)
1285 {
1286 struct omap_dss_output *out = dssdev->output;
1287 int r = 0;
1289 DSSDBG("ENTER hdmi_display_enable\n");
1291 mutex_lock(&hdmi.lock);
1293 if (out == NULL || out->manager == NULL) {
1294 DSSERR("failed to enable display: no output/manager\n");
1295 r = -ENODEV;
1296 goto err0;
1297 }
1299 hdmi.ip_data.hpd_gpio = hdmi.hpd_gpio;
1301 r = omap_dss_start_device(dssdev);
1302 if (r) {
1303 DSSERR("failed to start device\n");
1304 goto err0;
1305 }
1307 r = hdmi_power_on_full(dssdev);
1308 if (r) {
1309 DSSERR("failed to power on device\n");
1310 goto err1;
1311 }
1313 mutex_unlock(&hdmi.lock);
1314 return 0;
1316 err1:
1317 omap_dss_stop_device(dssdev);
1318 err0:
1319 mutex_unlock(&hdmi.lock);
1320 return r;
1321 }
1323 void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev)
1324 {
1325 DSSDBG("Enter hdmi_display_disable\n");
1327 mutex_lock(&hdmi.lock);
1329 hdmi_power_off_full(dssdev);
1331 omap_dss_stop_device(dssdev);
1333 mutex_unlock(&hdmi.lock);
1334 }
1336 int omapdss_hdmi_core_enable(struct omap_dss_device *dssdev)
1337 {
1338 int r = 0;
1340 DSSDBG("ENTER omapdss_hdmi_core_enable\n");
1342 mutex_lock(&hdmi.lock);
1344 hdmi.ip_data.hpd_gpio = hdmi.hpd_gpio;
1346 r = hdmi_power_on_core(dssdev);
1347 if (r) {
1348 DSSERR("failed to power on device\n");
1349 goto err0;
1350 }
1352 mutex_unlock(&hdmi.lock);
1353 return 0;
1355 err0:
1356 mutex_unlock(&hdmi.lock);
1357 return r;
1358 }
1360 void omapdss_hdmi_core_disable(struct omap_dss_device *dssdev)
1361 {
1362 DSSDBG("Enter omapdss_hdmi_core_disable\n");
1364 mutex_lock(&hdmi.lock);
1366 hdmi_power_off_core(dssdev);
1368 mutex_unlock(&hdmi.lock);
1369 }
1371 void omapdss_hdmi_clear_edid(void)
1372 {
1373 hdmi.edid_set = false;
1374 hdmi.custom_set = false;
1375 }
1377 ssize_t omapdss_get_edid(char *buf)
1378 {
1379 ssize_t size = hdmi.edid_set ? HDMI_EDID_MAX_LENGTH : 0;
1380 memcpy(buf, hdmi.edid, size);
1381 return size;
1382 }
1384 static irqreturn_t hdmi_irq_handler(int irq, void *arg)
1385 {
1386 int r = 0;
1388 r = hdmi.ip_data.ops->irq_handler(&hdmi.ip_data);
1389 DSSDBG("Received HDMI IRQ = %08x\n", r);
1391 r = hdmi.ip_data.ops->irq_core_handler(&hdmi.ip_data);
1392 DSSDBG("Received HDMI core IRQ = %08x\n", r);
1394 return IRQ_HANDLED;
1395 }
1397 static int hdmi_get_clocks(struct platform_device *pdev)
1398 {
1399 struct clk *clk;
1401 clk = clk_get(&pdev->dev, "sys_clk");
1402 if (IS_ERR(clk)) {
1403 DSSERR("can't get sys_clk\n");
1404 return PTR_ERR(clk);
1405 }
1407 hdmi.sys_clk = clk;
1409 return 0;
1410 }
1412 static void hdmi_put_clocks(void)
1413 {
1414 if (hdmi.sys_clk)
1415 clk_put(hdmi.sys_clk);
1416 }
1418 #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) || \
1419 defined(CONFIG_OMAP5_DSS_HDMI_AUDIO)
1420 static int hdmi_probe_audio(struct platform_device *pdev)
1421 {
1422 struct resource *res;
1423 struct platform_device *aud_pdev;
1424 u32 port_offset, port_size;
1425 struct resource aud_res[2] = {
1426 DEFINE_RES_MEM(-1, -1),
1427 DEFINE_RES_DMA(-1),
1428 };
1430 res = platform_get_resource(hdmi.pdev, IORESOURCE_MEM, 0);
1431 if (!res) {
1432 DSSERR("can't get IORESOURCE_MEM HDMI\n");
1433 return -EINVAL;
1434 }
1436 /*
1437 * Pass DMA audio port to audio drivers.
1438 * Audio drivers should not ioremap it.
1439 */
1440 hdmi.ip_data.ops->audio_get_dma_port(&port_offset, &port_size);
1442 aud_res[0].start = res->start + port_offset;
1443 aud_res[0].end = aud_res[0].start + port_size - 1;
1445 res = platform_get_resource(hdmi.pdev, IORESOURCE_DMA, 0);
1446 if (!res) {
1447 DSSERR("can't get IORESOURCE_DMA HDMI\n");
1448 return -EINVAL;
1449 }
1451 /* Pass the audio DMA request resource to audio drivers. */
1452 aud_res[1].start = res->start;
1454 /* create platform device for HDMI audio driver */
1455 aud_pdev = platform_device_register_simple("omap-hdmi-audio",
1456 pdev->id, aud_res,
1457 ARRAY_SIZE(aud_res));
1458 if (IS_ERR(aud_pdev)) {
1459 DSSERR("Can't instantiate hdmi-audio\n");
1460 return -ENODEV;
1461 }
1463 hdmi.audio_pdev = aud_pdev;
1465 return 0;
1466 }
1468 int hdmi_compute_acr(u32 sample_freq, u32 *n, u32 *cts)
1469 {
1470 int r;
1471 u32 deep_color;
1472 u32 pclk = hdmi.ip_data.cfg.timings.pixel_clock;
1474 if (n == NULL || cts == NULL || sample_freq == 0)
1475 return -EINVAL;
1477 /* TODO: When implemented, query deep color mode here. */
1478 deep_color = 100;
1480 switch (sample_freq) {
1481 case 32000:
1482 if (deep_color == 125 && pclk == 74250) {
1483 *n = 8192;
1484 break;
1485 }
1487 if (deep_color == 125 && pclk == 27027) {
1488 /*
1489 * For this specific configuration, no value within the
1490 * allowed interval of N (as per the HDMI spec) will
1491 * produce an integer value of CTS. The value we use
1492 * here will produce CTS = 11587.000427246, which is
1493 * slightly larger than the integer. This difference
1494 * could cause the audio clock at the sink to slowly
1495 * drift. The true solution requires alternating between
1496 * two CTS relevant values with careful timing in order
1497 * to, on average, obtain the true CTS float value.
1498 */
1499 *n = 13529;
1500 break;
1501 }
1503 if (deep_color == 150 && pclk == 27027) {
1504 *n = 8192;
1505 break;
1506 }
1508 *n = 4096;
1509 break;
1510 case 44100:
1511 if (deep_color == 125 && pclk == 27027) {
1512 *n = 12544;
1513 break;
1514 }
1516 *n = 6272;
1517 break;
1518 case 48000:
1519 if (deep_color == 125 && (pclk == 27027 || pclk == 74250)) {
1520 *n = 8192;
1521 break;
1522 }
1524 if (deep_color == 150 && pclk == 27027) {
1525 *n = 8192;
1526 break;
1527 }
1529 *n = 6144;
1530 break;
1531 case 88200:
1532 r = hdmi_compute_acr(44100, n, cts);
1533 *n *= 2;
1534 return r;
1535 case 96000:
1536 r = hdmi_compute_acr(48000, n, cts);
1537 *n *= 2;
1538 return r;
1539 case 176400:
1540 r = hdmi_compute_acr(44100, n, cts);
1541 *n *= 4;
1542 return r;
1543 case 192000:
1544 r = hdmi_compute_acr(48000, n, cts);
1545 *n *= 4;
1546 return r;
1547 default:
1548 return -EINVAL;
1549 }
1551 /*
1552 * Calculate CTS. See HDMI 1.3a or 1.4a specifications. Preserve the
1553 * remainder in case N is not a multiple of 128.
1554 */
1555 *cts = (*n / 128) * pclk * deep_color;
1556 *cts += (*n % 128) * pclk * deep_color / 128;
1557 *cts /= (sample_freq / 10);
1559 if ((pclk * (*n / 128) * deep_color) % (sample_freq / 10))
1560 DSSWARN("CTS is not integer fs[%u]pclk[%u]N[%u]\n",
1561 sample_freq, pclk, *n);
1563 return 0;
1564 }
1566 int hdmi_audio_enable(void)
1567 {
1568 DSSDBG("audio_enable\n");
1570 return hdmi.ip_data.ops->audio_enable(&hdmi.ip_data);
1571 }
1573 void hdmi_audio_disable(void)
1574 {
1575 DSSDBG("audio_disable\n");
1577 hdmi.ip_data.ops->audio_disable(&hdmi.ip_data);
1578 }
1580 int hdmi_audio_start(void)
1581 {
1582 DSSDBG("audio_start\n");
1584 return hdmi.ip_data.ops->audio_start(&hdmi.ip_data);
1585 }
1587 void hdmi_audio_stop(void)
1588 {
1589 DSSDBG("audio_stop\n");
1591 hdmi.ip_data.ops->audio_stop(&hdmi.ip_data);
1592 }
1594 bool hdmi_mode_has_audio(void)
1595 {
1596 if (hdmi.ip_data.cfg.cm.mode == HDMI_HDMI)
1597 return true;
1598 else
1599 return false;
1600 }
1602 int hdmi_audio_config(struct omap_dss_audio *audio)
1603 {
1604 return hdmi.ip_data.ops->audio_config(&hdmi.ip_data, audio);
1605 }
1607 #endif
1609 static struct omap_dss_device * __init hdmi_find_dssdev(struct platform_device *pdev)
1610 {
1611 struct omap_dss_board_info *pdata = pdev->dev.platform_data;
1612 const char *def_disp_name = omapdss_get_default_display_name();
1613 struct omap_dss_device *def_dssdev;
1614 int i;
1616 def_dssdev = NULL;
1618 for (i = 0; i < pdata->num_devices; ++i) {
1619 struct omap_dss_device *dssdev = pdata->devices[i];
1621 if (dssdev->type != OMAP_DISPLAY_TYPE_HDMI)
1622 continue;
1624 if (def_dssdev == NULL)
1625 def_dssdev = dssdev;
1627 if (def_disp_name != NULL &&
1628 strcmp(dssdev->name, def_disp_name) == 0) {
1629 def_dssdev = dssdev;
1630 break;
1631 }
1632 }
1634 return def_dssdev;
1635 }
1637 static void __init hdmi_probe_pdata(struct platform_device *pdev)
1638 {
1639 struct omap_dss_device *plat_dssdev;
1640 struct omap_dss_device *dssdev;
1641 struct omap_dss_hdmi_data *priv;
1642 int r;
1644 plat_dssdev = hdmi_find_dssdev(pdev);
1646 if (!plat_dssdev)
1647 return;
1649 dssdev = dss_alloc_and_init_device(&pdev->dev);
1650 if (!dssdev)
1651 return;
1653 dss_copy_device_pdata(dssdev, plat_dssdev);
1655 priv = dssdev->data;
1657 hdmi.ct_cp_hpd_gpio = priv->ct_cp_hpd_gpio;
1658 hdmi.ls_oe_gpio = priv->ls_oe_gpio;
1659 hdmi.hpd_gpio = priv->hpd_gpio;
1661 dssdev->channel = OMAP_DSS_CHANNEL_DIGIT;
1663 r = hdmi_init_display(dssdev);
1664 if (r) {
1665 DSSERR("device %s init failed: %d\n", dssdev->name, r);
1666 dss_put_device(dssdev);
1667 return;
1668 }
1670 r = omapdss_output_set_device(&hdmi.output, dssdev);
1671 if (r) {
1672 DSSERR("failed to connect output to new device: %s\n",
1673 dssdev->name);
1674 dss_put_device(dssdev);
1675 return;
1676 }
1678 r = dss_add_device(dssdev);
1679 if (r) {
1680 DSSERR("device %s register failed: %d\n", dssdev->name, r);
1681 omapdss_output_unset_device(&hdmi.output);
1682 hdmi_uninit_display(dssdev);
1683 dss_put_device(dssdev);
1684 return;
1685 }
1686 }
1688 struct i2c_adapter *omapdss_hdmi_adapter(void)
1689 {
1690 return hdmi.adap;
1691 }
1693 static void ddc_set_sda(void *data, int state)
1694 {
1695 if (state)
1696 gpio_direction_input(hdmi.sda_pin);
1697 else
1698 gpio_direction_output(hdmi.sda_pin, 0);
1699 }
1701 static void ddc_set_scl(void *data, int state)
1702 {
1703 if (state)
1704 gpio_direction_input(hdmi.scl_pin);
1705 else
1706 gpio_direction_output(hdmi.scl_pin, 0);
1707 }
1709 static int ddc_get_sda(void *data)
1710 {
1711 return gpio_get_value(hdmi.sda_pin);
1712 }
1714 static int ddc_get_scl(void *data)
1715 {
1716 return gpio_get_value(hdmi.scl_pin);
1717 }
1719 static int ddc_pre_xfer(struct i2c_adapter *adap)
1720 {
1721 /* don't read if no hdmi connected */
1722 if (!gpio_get_value(hdmi.hpd_gpio))
1723 return -ENODEV;
1725 gpio_set_value_cansleep(hdmi.ls_oe_gpio, 1);
1727 return 0;
1728 }
1729 static void ddc_post_xfer(struct i2c_adapter *adap)
1730 {
1731 hdmi_set_ls_state(hdmi.ls_state);
1732 }
1734 static void ddc_i2c_init(struct platform_device *pdev)
1735 {
1737 hdmi.adap = kzalloc(sizeof(*hdmi.adap), GFP_KERNEL);
1739 if (!hdmi.adap) {
1740 pr_err("Failed to allocate i2c adapter\n");
1741 return;
1742 }
1744 hdmi.adap->owner = THIS_MODULE;
1745 hdmi.adap->class = I2C_CLASS_DDC;
1746 hdmi.adap->dev.parent = &pdev->dev;
1747 hdmi.adap->algo_data = &hdmi.bit_data;
1748 hdmi.adap->algo = &i2c_bit_algo;
1749 hdmi.bit_data.udelay = 2;
1750 hdmi.bit_data.timeout = HZ/10;
1751 hdmi.bit_data.setsda = ddc_set_sda;
1752 hdmi.bit_data.setscl = ddc_set_scl;
1753 hdmi.bit_data.getsda = ddc_get_sda;
1754 hdmi.bit_data.getscl = ddc_get_scl;
1755 hdmi.bit_data.pre_xfer = ddc_pre_xfer;
1756 hdmi.bit_data.post_xfer = ddc_post_xfer;
1758 gpio_request(hdmi.sda_pin, "DDC SDA");
1759 gpio_request(hdmi.scl_pin, "DDC SCL");
1760 snprintf(hdmi.adap->name, sizeof(hdmi.adap->name),
1761 "DSS DDC-EDID adapter");
1762 if (i2c_add_adapter(hdmi.adap)) {
1763 DSSERR("Cannot initialize DDC I2c\n");
1764 kfree(hdmi.adap);
1765 hdmi.adap = NULL;
1766 }
1767 }
1769 static void init_sel_i2c_hdmi(void)
1770 {
1771 void __iomem *clk_base = ioremap(0x4A009000, SZ_4K);
1772 void __iomem *mcasp2_base = ioremap(0x48464000, SZ_1K);
1773 void __iomem *pinmux = ioremap(0x4a003600, SZ_1K);
1774 u32 val;
1776 if (omapdss_get_version() != OMAPDSS_VER_DRA7xx)
1777 goto err;
1779 if (!clk_base || !mcasp2_base || !pinmux)
1780 DSSERR("couldn't ioremap for clk or mcasp2\n");
1782 __raw_writel(0x40000, pinmux + 0xfc);
1783 /* sw supervised wkup */
1784 __raw_writel(0x2, clk_base + 0x8fc);
1786 /* enable clock domain */
1787 __raw_writel(0x2, clk_base + 0x860);
1789 /* see what status looks like */
1790 val = __raw_readl(clk_base + 0x8fc);
1791 printk("CM_L4PER2_CLKSTCTRL %x\n", val);
1793 /*
1794 * mcasp2 regs should be hopefully accessible, make mcasp2_aclkr
1795 * a gpio, write necessary stuff to MCASP_PFUNC and PDIR
1796 */
1797 __raw_writel(0x1 << 29, mcasp2_base + 0x10);
1798 __raw_writel(0x1 << 29, mcasp2_base + 0x14);
1800 err:
1801 iounmap(clk_base);
1802 iounmap(mcasp2_base);
1803 iounmap(pinmux);
1804 }
1806 /* use this to configure the pcf8575@22 to set LS_OE and CT_HPD */
1807 void sel_i2c(void)
1808 {
1809 void __iomem *base = ioremap(0x48464000, SZ_1K);
1811 if (omapdss_get_version() != OMAPDSS_VER_DRA7xx)
1812 goto err;
1814 /* PDOUT */
1815 __raw_writel(0x0, base + 0x18);
1817 DSSDBG("PDOUT sel_i2c %x\n", __raw_readl(base + 0x18));
1819 err:
1820 iounmap(base);
1821 }
1823 /* use this to read edid and detect hpd ? */
1824 void sel_hdmi(void)
1825 {
1826 void __iomem *base = ioremap(0x48464000, SZ_1K);
1828 if (omapdss_get_version() != OMAPDSS_VER_DRA7xx)
1829 goto err;
1831 /* PDOUT */
1832 __raw_writel(0x20000000, base + 0x18);
1834 DSSDBG("PDOUT sel_hdmi %x\n", __raw_readl(base + 0x18));
1836 err:
1837 iounmap(base);
1838 }
1840 static void __init hdmi_probe_of(struct platform_device *pdev)
1841 {
1842 struct device_node *node = pdev->dev.of_node;
1843 struct device_node *child;
1844 struct omap_dss_device *dssdev;
1845 struct device_node *adapter_node;
1846 struct i2c_adapter *adapter = NULL;
1847 int r, gpio;
1848 enum omap_channel channel;
1849 u32 v;
1850 int gpio_count;
1852 r = of_property_read_u32(node, "video-source", &v);
1853 if (r) {
1854 DSSERR("parsing channel failed\n");
1855 return;
1856 }
1858 channel = v;
1860 node = of_find_compatible_node(node, NULL, "ti,tpd12s015");
1861 if (!node)
1862 return;
1864 child = of_get_next_available_child(node, NULL);
1865 if (!child)
1866 return;
1868 gpio_count = of_gpio_count(node);
1870 /* OMAP4 derivatives have 3 pins defined, OMAP5 derivatives have 5 */
1871 if (gpio_count != 5 && gpio_count != 3) {
1872 DSSERR("wrong number of GPIOs\n");
1873 return;
1874 }
1876 gpio = of_get_gpio(node, 0);
1877 if (gpio_is_valid(gpio)) {
1878 hdmi.ct_cp_hpd_gpio = gpio;
1879 } else {
1880 DSSERR("failed to parse CT CP HPD gpio\n");
1881 return;
1882 }
1884 gpio = of_get_gpio(node, 1);
1885 if (gpio_is_valid(gpio)) {
1886 hdmi.ls_oe_gpio = gpio;
1887 } else {
1888 DSSERR("failed to parse LS OE gpio\n");
1889 return;
1890 }
1892 gpio = of_get_gpio(node, 2);
1893 if (gpio_is_valid(gpio)) {
1894 hdmi.hpd_gpio = gpio;
1895 } else {
1896 DSSERR("failed to parse HPD gpio\n");
1897 return;
1898 }
1900 adapter_node = of_parse_phandle(node, "hdmi_ddc", 0);
1901 if (adapter_node)
1902 adapter = of_find_i2c_adapter_by_node(adapter_node);
1904 /*
1905 * if I2C SCL and SDA pins are defined, parse them, if an adapter is
1906 * present, use the i2c adapter rather than bitbanging i2c. If there
1907 * isn't an adapter either, assume that we are using the hdmi core IP's
1908 * ddc.
1909 */
1910 if (gpio_count == 5) {
1911 gpio = of_get_gpio(node, 3);
1912 if (gpio_is_valid(gpio)) {
1913 hdmi.scl_pin = gpio;
1914 } else {
1915 DSSERR("failed to parse SCL gpio\n");
1916 return;
1917 }
1919 gpio = of_get_gpio(node, 4);
1920 if (gpio_is_valid(gpio)) {
1921 hdmi.sda_pin = gpio;
1922 } else {
1923 DSSERR("failed to parse SDA gpio\n");
1924 return;
1925 }
1926 } else if (adapter != NULL) {
1927 hdmi.adap = adapter;
1929 /*
1930 * we have SEL_I2C_HDMI pin which acts as a control line to
1931 * a demux which choses the i2c lines to go either to hdmi
1932 * or to the other i2c2 slaves. This line is used as a mcasp2
1933 * gpio. Init the gpio pin so that it can be used to control
1934 * the demux.
1935 */
1936 init_sel_i2c_hdmi();
1937 sel_i2c();
1938 }
1940 dssdev = dss_alloc_and_init_device(&pdev->dev);
1941 if (!dssdev)
1942 return;
1944 dssdev->dev.of_node = child;
1945 dssdev->type = OMAP_DISPLAY_TYPE_HDMI;
1946 dssdev->name = child->name;
1947 dssdev->channel = channel;
1949 r = hdmi_init_display(dssdev);
1950 if (r) {
1951 DSSERR("device %s init failed: %d\n", dssdev->name, r);
1952 dss_put_device(dssdev);
1953 return;
1954 }
1956 r = omapdss_output_set_device(&hdmi.output, dssdev);
1957 if (r) {
1958 DSSERR("failed to connect output to new device: %s\n",
1959 dssdev->name);
1960 dss_put_device(dssdev);
1961 return;
1962 }
1964 r = dss_add_device(dssdev);
1965 if (r) {
1966 DSSERR("dss_add_device failed %d\n", r);
1967 dss_put_device(dssdev);
1968 return;
1969 }
1970 }
1972 static void __init hdmi_init_output(struct platform_device *pdev)
1973 {
1974 struct omap_dss_output *out = &hdmi.output;
1976 out->pdev = pdev;
1977 out->id = OMAP_DSS_OUTPUT_HDMI;
1978 out->type = OMAP_DISPLAY_TYPE_HDMI;
1980 dss_register_output(out);
1981 }
1983 static void __exit hdmi_uninit_output(struct platform_device *pdev)
1984 {
1985 struct omap_dss_output *out = &hdmi.output;
1987 dss_unregister_output(out);
1988 }
1990 /* HDMI HW IP initialisation */
1991 static int __init omapdss_hdmihw_probe(struct platform_device *pdev)
1992 {
1993 struct resource *res;
1994 int r;
1996 hdmi.pdev = pdev;
1998 mutex_init(&hdmi.lock);
1999 mutex_init(&hdmi.ip_data.lock);
2001 dss_init_hdmi_ip_ops(&hdmi.ip_data, omapdss_get_version());
2003 /* HDMI wrapper memory remap */
2004 res = platform_get_resource_byname(hdmi.pdev,
2005 IORESOURCE_MEM, "hdmi_wp");
2006 if (!res) {
2007 DSSERR("can't get WP IORESOURCE_MEM HDMI\n");
2008 return -EINVAL;
2009 }
2011 /* Base address taken from platform */
2012 hdmi.ip_data.base_wp = devm_request_and_ioremap(&pdev->dev, res);
2013 if (!hdmi.ip_data.base_wp) {
2014 DSSERR("can't ioremap WP\n");
2015 return -ENOMEM;
2016 }
2018 /* HDMI PLLCTRL memory remap */
2019 res = platform_get_resource_byname(hdmi.pdev,
2020 IORESOURCE_MEM, "pllctrl");
2021 if (!res) {
2022 DSSERR("can't get PLL CTRL IORESOURCE_MEM HDMI\n");
2023 return -EINVAL;
2024 }
2026 hdmi.ip_data.base_pllctrl = devm_request_and_ioremap(&pdev->dev, res);
2027 if (!hdmi.ip_data.base_pllctrl) {
2028 DSSERR("can't ioremap PLL ctrl\n");
2029 return -ENOMEM;
2030 }
2032 /* HDMI TXPHYCTRL memory remap */
2033 res = platform_get_resource_byname(hdmi.pdev,
2034 IORESOURCE_MEM, "hdmitxphy");
2035 if (!res) {
2036 DSSERR("can't get TXPHY CTRL IORESOURCE_MEM HDMI\n");
2037 return -EINVAL;
2038 }
2040 hdmi.ip_data.base_txphyctrl = devm_request_and_ioremap(&pdev->dev, res);
2041 if (!hdmi.ip_data.base_txphyctrl) {
2042 DSSERR("can't ioremap TXPHY ctrl\n");
2043 return -ENOMEM;
2044 }
2046 /* HDMI core memory remap */
2047 res = platform_get_resource_byname(hdmi.pdev,
2048 IORESOURCE_MEM, "hdmi_core");
2049 if (!res) {
2050 DSSERR("can't get core IORESOURCE_MEM HDMI\n");
2051 return -EINVAL;
2052 }
2054 hdmi.ip_data.base_core = devm_request_and_ioremap(&pdev->dev, res);
2055 if (!hdmi.ip_data.base_core) {
2056 DSSERR("can't ioremap core\n");
2057 return -ENOMEM;
2058 }
2060 r = hdmi_get_clocks(pdev);
2061 if (r) {
2062 DSSERR("can't get clocks\n");
2063 return r;
2064 }
2066 pm_runtime_enable(&pdev->dev);
2068 hdmi.hdmi_irq = platform_get_irq(pdev, 0);
2069 r = request_irq(hdmi.hdmi_irq, hdmi_irq_handler, 0, "OMAP HDMI", NULL);
2070 if (r < 0) {
2071 pr_err("hdmi: request_irq %s failed\n", pdev->name);
2072 return -EINVAL;
2073 }
2075 r = hdmi_panel_init();
2076 if (r) {
2077 DSSERR("can't init panel\n");
2078 goto err_panel_init;
2079 }
2081 hdmi.edid_set = false;
2083 dss_debugfs_create_file("hdmi", hdmi_dump_regs);
2085 hdmi_init_output(pdev);
2087 if (pdev->dev.of_node)
2088 hdmi_probe_of(pdev);
2089 else if (pdev->dev.platform_data)
2090 hdmi_probe_pdata(pdev);
2092 /* if i2c pins defined, setup I2C adapter */
2093 if (hdmi.scl_pin && hdmi.sda_pin)
2094 ddc_i2c_init(pdev);
2096 #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) || \
2097 defined(CONFIG_OMAP5_DSS_HDMI_AUDIO)
2098 r = hdmi_probe_audio(pdev);
2099 if (r)
2100 DSSWARN("could not create platform device for audio");
2101 #endif
2103 return 0;
2105 err_panel_init:
2106 hdmi_put_clocks();
2107 return r;
2108 }
2110 static int __exit hdmi_remove_child(struct device *dev, void *data)
2111 {
2112 struct omap_dss_device *dssdev = to_dss_device(dev);
2113 hdmi_uninit_display(dssdev);
2114 return 0;
2115 }
2117 static int __exit omapdss_hdmihw_remove(struct platform_device *pdev)
2118 {
2119 #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) || \
2120 defined(CONFIG_OMAP5_DSS_HDMI_AUDIO)
2121 if (hdmi.audio_pdev != NULL)
2122 platform_device_unregister(hdmi.audio_pdev);
2123 #endif
2125 kfree(hdmi.adap);
2127 device_for_each_child(&pdev->dev, NULL, hdmi_remove_child);
2129 dss_unregister_child_devices(&pdev->dev);
2131 hdmi_panel_exit();
2133 hdmi_uninit_output(pdev);
2135 pm_runtime_disable(&pdev->dev);
2137 hdmi_put_clocks();
2139 return 0;
2140 }
2142 static int hdmi_runtime_suspend(struct device *dev)
2143 {
2144 clk_disable_unprepare(hdmi.sys_clk);
2146 dispc_runtime_put();
2148 return 0;
2149 }
2151 static int hdmi_runtime_resume(struct device *dev)
2152 {
2153 int r;
2155 r = dispc_runtime_get();
2156 if (r < 0)
2157 return r;
2159 clk_prepare_enable(hdmi.sys_clk);
2161 return 0;
2162 }
2164 static const struct dev_pm_ops hdmi_pm_ops = {
2165 .runtime_suspend = hdmi_runtime_suspend,
2166 .runtime_resume = hdmi_runtime_resume,
2167 };
2169 #if defined(CONFIG_OF)
2170 static const struct of_device_id hdmi_of_match[] = {
2171 {
2172 .compatible = "ti,omap4-hdmi",
2173 },
2174 {},
2175 };
2176 #else
2177 #define hdmi_of_match NULL
2178 #endif
2180 static struct platform_driver omapdss_hdmihw_driver = {
2181 .remove = __exit_p(omapdss_hdmihw_remove),
2182 .driver = {
2183 .name = "omapdss_hdmi",
2184 .owner = THIS_MODULE,
2185 .pm = &hdmi_pm_ops,
2186 .of_match_table = hdmi_of_match,
2187 },
2188 };
2190 int __init hdmi_init_platform_driver(void)
2191 {
2192 return platform_driver_probe(&omapdss_hdmihw_driver, omapdss_hdmihw_probe);
2193 }
2195 void __exit hdmi_uninit_platform_driver(void)
2196 {
2197 platform_driver_unregister(&omapdss_hdmihw_driver);
2198 }