6c634771ca585e78a29e707e891a8a561f928d2e
1 /*
2 * include/video/dsscomp.h
3 *
4 * DSS Composition header file
5 *
6 * Copyright (C) 2011 Texas Instruments, Inc
7 * Author: Lajos Molnar <molnar@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
22 #ifndef _LINUX_DSSCOMP_H
23 #define _LINUX_DSSCOMP_H
25 #ifdef __KERNEL__
26 #include <video/omapdss.h>
27 #else
29 /* exporting enumerations from arch/arm/plat-omap/include/plat/display.h */
30 enum omap_plane {
31 OMAP_DSS_GFX = 0,
32 OMAP_DSS_VIDEO1 = 1,
33 OMAP_DSS_VIDEO2 = 2,
34 OMAP_DSS_VIDEO3 = 3,
35 OMAP_DSS_WB = 4,
36 };
38 enum omap_channel {
39 OMAP_DSS_CHANNEL_LCD = 0,
40 OMAP_DSS_CHANNEL_DIGIT = 1,
41 OMAP_DSS_CHANNEL_LCD2 = 2,
42 };
44 enum omap_color_mode {
45 OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
46 OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
47 OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
48 OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
50 /* also referred to as RGB 12-BPP, 16-bit container */
51 OMAP_DSS_COLOR_RGB12U = 1 << 4, /* xRGB12-4444 */
52 OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16-4444 */
53 OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16-565 */
55 /* also referred to as RGB 24-BPP, 32-bit container */
56 OMAP_DSS_COLOR_RGB24U = 1 << 7, /* xRGB24-8888 */
57 OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24-888 */
58 OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
59 OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
60 OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32-8888 */
61 OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32-8888 */
63 /* also referred to as RGBx 32 in TRM */
64 OMAP_DSS_COLOR_RGBX24 = 1 << 13, /* RGBx32-8888 */
65 OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32-8888 */
66 OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */
68 /* also referred to as RGBA12-4444 in TRM */
69 OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16-4444 */
71 OMAP_DSS_COLOR_RGBX12 = 1 << 16, /* RGBx16-4444 */
72 OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16-4444 */
73 OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16-1555 */
75 /* also referred to as xRGB16-555 in TRM */
76 OMAP_DSS_COLOR_XRGB15 = 1 << 18, /* xRGB16-1555 */
77 OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16-1555 */
78 };
80 enum omap_dss_trans_key_type {
81 OMAP_DSS_COLOR_KEY_GFX_DST = 0,
82 OMAP_DSS_COLOR_KEY_VID_SRC = 1,
83 };
85 enum omap_dss_display_state {
86 OMAP_DSS_DISPLAY_DISABLED = 0,
87 OMAP_DSS_DISPLAY_ACTIVE,
88 OMAP_DSS_DISPLAY_SUSPENDED,
89 OMAP_DSS_DISPLAY_TRANSITION,
90 };
92 struct omap_video_timings {
93 /* Unit: pixels */
94 __u16 x_res;
95 /* Unit: pixels */
96 __u16 y_res;
97 /* Unit: KHz */
98 __u32 pixel_clock;
99 /* Unit: pixel clocks */
100 __u16 hsw; /* Horizontal synchronization pulse width */
101 /* Unit: pixel clocks */
102 __u16 hfp; /* Horizontal front porch */
103 /* Unit: pixel clocks */
104 __u16 hbp; /* Horizontal back porch */
105 /* Unit: line clocks */
106 __u16 vsw; /* Vertical synchronization pulse width */
107 /* Unit: line clocks */
108 __u16 vfp; /* Vertical front porch */
109 /* Unit: line clocks */
110 __u16 vbp; /* Vertical back porch */
111 };
113 /* YUV to RGB color conversion info */
114 struct omap_dss_cconv_coefs {
115 __s16 ry, rcr, rcb;
116 __s16 gy, gcr, gcb;
117 __s16 by, bcr, bcb;
119 /* Y is 16..235, UV is 16..240 if not fullrange. Otherwise 0..255 */
120 __u16 full_range;
121 } __aligned(4);
123 struct omap_dss_cpr_coefs {
124 __s16 rr, rg, rb;
125 __s16 gr, gg, gb;
126 __s16 br, bg, bb;
127 };
129 /*
130 * Stereoscopic Panel types
131 * row, column, overunder, sidebyside options
132 * are with respect to native scan order
133 */
134 enum s3d_disp_type {
135 S3D_DISP_NONE = 0,
136 S3D_DISP_FRAME_SEQ,
137 S3D_DISP_ROW_IL,
138 S3D_DISP_COL_IL,
139 S3D_DISP_PIX_IL,
140 S3D_DISP_CHECKB,
141 S3D_DISP_OVERUNDER,
142 S3D_DISP_SIDEBYSIDE,
143 };
145 /* Subsampling direction is based on native panel scan order.*/
146 enum s3d_disp_sub_sampling {
147 S3D_DISP_SUB_SAMPLE_NONE = 0,
148 S3D_DISP_SUB_SAMPLE_V,
149 S3D_DISP_SUB_SAMPLE_H,
150 };
152 /*
153 * Indicates if display expects left view first followed by right or viceversa
154 * For row interlaved displays, defines first row view
155 * For column interleaved displays, defines first column view
156 * For checkerboard, defines first pixel view
157 * For overunder, defines top view
158 * For sidebyside, defines west view
159 */
160 enum s3d_disp_order {
161 S3D_DISP_ORDER_L = 0,
162 S3D_DISP_ORDER_R = 1,
163 };
165 /*
166 * Indicates current view
167 * Used mainly for displays that need to trigger a sync signal
168 */
169 enum s3d_disp_view {
170 S3D_DISP_VIEW_L = 0,
171 S3D_DISP_VIEW_R,
172 };
174 struct s3d_disp_info {
175 enum s3d_disp_type type;
176 enum s3d_disp_sub_sampling sub_samp;
177 enum s3d_disp_order order;
178 /*
179 * Gap between left and right views
180 * For over/under units are lines
181 * For sidebyside units are pixels
182 * For other types ignored
183 */
184 unsigned int gap;
185 };
187 #endif
189 /* copy of fb_videomode */
190 struct dsscomp_videomode {
191 const char *name; /* optional */
192 __u32 refresh; /* optional */
193 __u32 xres;
194 __u32 yres;
195 __u32 pixclock;
196 __u32 left_margin;
197 __u32 right_margin;
198 __u32 upper_margin;
199 __u32 lower_margin;
200 __u32 hsync_len;
201 __u32 vsync_len;
202 __u32 sync;
203 __u32 vmode;
204 __u32 flag;
205 };
207 enum omap_dss_ilace_mode {
208 OMAP_DSS_ILACE = (1 << 0), /* interlaced vs. progressive */
209 OMAP_DSS_ILACE_SEQ = (1 << 1), /* sequential vs interleaved */
210 OMAP_DSS_ILACE_SWAP = (1 << 2), /* swap fields, e.g. TB=>BT */
212 OMAP_DSS_ILACE_NONE = 0,
213 OMAP_DSS_ILACE_IL_TB = OMAP_DSS_ILACE,
214 OMAP_DSS_ILACE_IL_BT = OMAP_DSS_ILACE | OMAP_DSS_ILACE_SWAP,
215 OMAP_DSS_ILACE_SEQ_TB = OMAP_DSS_ILACE_IL_TB | OMAP_DSS_ILACE_SEQ,
216 OMAP_DSS_ILACE_SEQ_BT = OMAP_DSS_ILACE_IL_BT | OMAP_DSS_ILACE_SEQ,
217 };
219 /* YUV VC1 range mapping info */
220 struct dss2_vc1_range_map_info {
221 __u8 enable; /* bool */
223 __u8 range_y; /* 0..7 */
224 __u8 range_uv; /* 0..7 */
225 } __aligned(4);
227 /* standard rectangle */
228 struct dss2_rect_t {
229 __s32 x; /* left */
230 __s32 y; /* top */
231 __u32 w; /* width */
232 __u32 h; /* height */
233 } __aligned(4);
235 /* decimation constraints */
236 struct dss2_decim {
237 __u8 min_x;
238 __u8 max_x; /* 0 is same as 255 */
239 __u8 min_y;
240 __u8 max_y; /* 0 is same as 255 */
241 } __aligned(4);
243 /*
244 * A somewhat more user friendly interface to the DSS2. This is a
245 * direct interface to the DSS2 overlay and overlay_manager modules.
246 * User-space APIs are provided for HW-specific control of DSS in
247 * contrast with V4L2/FB that are more generic, but in this process
248 * omit HW-specific features.
249 *
250 * For now managers are specified by display index as opposed to manager
251 * type, so that display0 is always the default display (e.g. HDMI on
252 * panda, and LCD blaze.) For now you would need to query the displays
253 * or use sysfs to find a specific display.
254 *
255 * Userspace operations are as follows:
256 *
257 * 1) check if DSS supports an overlay configuration, use DSSCIOC_CHECK_OVL
258 * ioctl with the manager, overlay, and setup-mode information filled out.
259 * All fields should be filled out as it may influence whether DSS can
260 * display/render the overlay.
261 *
262 * If proper address information is not available, it may be possible to
263 * use a type-of-address enumeration instead for luma/rgb and chroma (if
264 * applicable) frames.
265 *
266 * Do this for each overlay before attempting to configure DSS.
267 *
268 * 2) configure DSS pipelines for display/manager using DSSCIOC_SETUP_MANAGER
269 * ioctl. You can delay applying the settings until an dss2_manager_apply()
270 * is called for the internal composition object, if the APPLY bit of setup mode
271 * is not set. However the CAPTURE/DISPLAY bits of the setup mode settings will
272 * determine if at this time a capture will take place (in case of capture
273 * only mode). You may also set up additional pipelines with
274 * dss2_overlay_setup() before this.
275 *
276 * 3) On OMAP4/5 you can use the DSS WB pipeline to copy (and convert) a buffer
277 * using DSS. Use the DSSCIOC_WB_COPY ioctl for this. This is a blocking
278 * call, and it may possibly fail if an ongoing WB capture mode has been
279 * scheduled (which is outside of the current scope of the DSS2 interface.)
280 *
281 * There is also a one-shot configuration API (DSSCIOC_SETUP_DISPC). This
282 * allows you to set-up all overlays on all managers in one call. This call
283 * performs additional functionality:
284 *
285 * - it maps userspace 1D buffers into TILER 1D for the duration of the display
286 * - it disables all overlays that were specified before, but are no longer
287 * specified
288 *
289 */
291 /*
292 * DSS2 overlay information. This structure contains all information
293 * needed to set up the overlay for a particular buffer to be displayed
294 * at a particular orientation.
295 *
296 * The following information is deemed to be set globally, so it is not
297 * included:
298 * - whether to enable zorder (always enabled)
299 * - whether to replicate/truncate color fields (it is decided per the
300 * whole manager/overlay settings, and is enabled unless overlay is
301 * directed to WB.)
302 *
303 * There is also no support for CLUT formats
304 *
305 * Requirements:
306 *
307 * 1) 0 <= crop.x <= crop.x + crop.w <= width
308 * 2) 0 <= crop.y <= crop.y + crop.h <= height
309 * 3) win.x <= win.x + win.w and win.w >= 0
310 * 4) win.y <= win.y + win.h and win.h >= 0
311 *
312 * 5) color_mode is supported by overlay
313 * 6) requested scaling is supported by overlay and functional clocks
314 *
315 * Notes:
316 *
317 * 1) Any portions of X:[pos_x, pos_x + out_width] and
318 * Y:[pos_y, pos_y + out_height] outside of the screen
319 * X:[0, screen.width], Y:[0, screen.height] will be cropped
320 * automatically without changing the scaling ratio.
321 *
322 * 2) Crop region will be adjusted to the pixel granularity:
323 * (2-by-1) for YUV422, (2-by-2) for YUV420. This will
324 * not modify the output region. Crop region is for the
325 * original (unrotated) buffer, so it does not change with
326 * rotation.
327 *
328 * 3) Rotation will not modify the output region, specifically
329 * its height and width. Also the coordinate system of the
330 * display is always (0,0) = top left.
331 *
332 * 4) cconv and vc1 only needs to be filled for YUV color modes.
333 *
334 * 5) vc1.range_y and vc1.range_uv only needs to be filled if
335 * vc1.enable is true.
336 */
337 struct dss2_ovl_cfg {
338 __u16 width; /* buffer width */
339 __u16 height; /* buffer height */
340 __u32 stride; /* buffer stride */
342 enum omap_color_mode color_mode;
343 __u8 pre_mult_alpha; /* bool */
344 __u8 global_alpha; /* 0..255 */
345 __u8 rotation; /* 0..3 (*90 degrees clockwise) */
346 __u8 mirror; /* left-to-right: mirroring is applied after rotation */
348 enum omap_dss_ilace_mode ilace; /* interlace mode */
350 struct dss2_rect_t win; /* output window - on display */
351 struct dss2_rect_t crop; /* crop window - in source buffer */
353 struct dss2_decim decim; /* predecimation limits */
355 struct omap_dss_cconv_coefs cconv;
356 struct dss2_vc1_range_map_info vc1;
358 __u8 ix; /* ovl index same as sysfs/overlay# */
359 __u8 zorder; /* 0..3 */
360 __u8 enabled; /* bool */
361 __u8 zonly; /* only set zorder and enabled bit */
362 __u8 mgr_ix; /* mgr index */
363 } __aligned(4);
365 enum omapdss_buffer_type {
366 OMAP_DSS_BUFTYPE_SDMA,
367 OMAP_DSS_BUFTYPE_TILER_8BIT,
368 OMAP_DSS_BUFTYPE_TILER_16BIT,
369 OMAP_DSS_BUFTYPE_TILER_32BIT,
370 OMAP_DSS_BUFTYPE_TILER_PAGE,
371 };
373 enum omapdss_buffer_addressing_type {
374 OMAP_DSS_BUFADDR_DIRECT, /* using direct addresses */
375 OMAP_DSS_BUFADDR_BYTYPE, /* using buffer types */
376 OMAP_DSS_BUFADDR_ION, /* using ion handle(s) */
377 OMAP_DSS_BUFADDR_GRALLOC, /* using gralloc handle */
378 OMAP_DSS_BUFADDR_OVL_IX, /* using a prior overlay */
379 OMAP_DSS_BUFADDR_LAYER_IX, /* using a Post2 layer */
380 OMAP_DSS_BUFADDR_FB, /* using framebuffer memory */
381 };
383 struct dss2_ovl_info {
384 struct dss2_ovl_cfg cfg;
386 enum omapdss_buffer_addressing_type addressing;
388 union {
389 /* user-space interfaces */
390 struct {
391 void *address; /* main buffer address */
392 void *uv_address; /* uv buffer */
393 };
395 /*
396 * For DSSCIOC_CHECK_OVL we allow specifying just the
397 * type of each buffer. This is used if we need to
398 * check whether DSS will be able to display a buffer
399 * if using a particular memory type before spending
400 * time to map/copy the buffer into that type of
401 * memory.
402 */
403 struct {
404 enum omapdss_buffer_type ba_type;
405 enum omapdss_buffer_type uv_type;
406 };
408 /* kernel-space interfaces */
410 /*
411 * for fbmem, highest 4-bits of address is fb index,
412 * rest of the bits are the offset
413 */
414 struct {
415 __u32 ba; /* base address or index */
416 __u32 uv; /* uv address */
417 };
418 };
419 };
421 /*
422 * DSS2 manager information.
423 *
424 * The following information is deemed to be set globally, so it is not
425 * included:
426 * gamma correction
427 * whether to enable zorder (always enabled)
428 * whether to replicate/truncate color fields (it is decided per the
429 * whole manager/overlay settings, and is enabled unless overlay is
430 * directed to WB.)
431 * Notes:
432 *
433 * 1) trans_key_type and trans_enabled only need to be filled if
434 * trans_enabled is true, and alpha_blending is false.
435 */
436 struct dss2_mgr_info {
437 __u32 ix; /* display index same as sysfs/display# */
439 __u32 default_color;
441 enum omap_dss_trans_key_type trans_key_type;
442 __u32 trans_key;
443 struct omap_dss_cpr_coefs cpr_coefs;
445 __u8 trans_enabled; /* bool */
447 __u8 interlaced; /* bool */
448 __u8 alpha_blending; /* bool - overrides trans_enabled */
449 __u8 cpr_enabled; /* bool */
450 __u8 swap_rb; /* bool - swap red and blue */
451 } __aligned(4);
453 /*
454 * ioctl: DSSCIOC_SETUP_MGR, struct dsscomp_setup_mgr_data
455 *
456 * 1. sets manager of each ovl in composition to the display
457 * 2. calls set_dss_ovl_info() for each ovl to set up the
458 * overlay staging structures (this is a wrapper around ovl->set_info())
459 * 3. calls set_dss_mgr_info() for mgr to set up the manager
460 * staging structures (this is a wrapper around mgr->set_info())
461 * 4. if update is true:
462 * calls manager->apply()
463 * calls driver->update() in a non-blocking fashion
464 * this will program the DSS synchronously
465 *
466 * Notes:
467 *
468 * 1) x, y, w, h only needs to be set if update is true.
469 *
470 * All non-specified pipelines that currently are on the same display
471 * will remain the same as on the previous frame. You may want to
472 * disable unused pipelines to avoid surprises.
473 *
474 * If get_sync_obj is false, it returns 0 on success, <0 error value
475 * on failure.
476 *
477 * If get_sync_obj is true, it returns fd on success, or a negative value
478 * on failure. You can use the fd to wait on (using DSSCIOC_WAIT ioctl()).
479 *
480 * Note: frames do not get eclipsed when the display turns off. Queue a
481 * blank frame to eclipse old frames. Blank frames get eclipsed when
482 * programmed into DSS.
483 *
484 * (A blank frame is queued to the display automatically in Android before
485 * the display is turned off.)
486 *
487 * All overlays to be used on the frame must be listed. There is no way
488 * to add another overlay to a defined frame.
489 */
490 enum dsscomp_setup_mode {
491 DSSCOMP_SETUP_MODE_APPLY = (1 << 0), /* applies changes to cache */
492 DSSCOMP_SETUP_MODE_DISPLAY = (1 << 1), /* calls display update */
493 DSSCOMP_SETUP_MODE_CAPTURE = (1 << 2), /* capture to WB */
495 /* just apply changes for next vsync/update */
496 DSSCOMP_SETUP_APPLY = DSSCOMP_SETUP_MODE_APPLY,
497 /* trigger an update (wait for vsync) */
498 DSSCOMP_SETUP_DISPLAY =
499 DSSCOMP_SETUP_MODE_APPLY | DSSCOMP_SETUP_MODE_DISPLAY,
500 /* capture to WB - WB must be configured */
501 DSSCOMP_SETUP_CAPTURE =
502 DSSCOMP_SETUP_MODE_APPLY | DSSCOMP_SETUP_MODE_CAPTURE,
503 /* display and capture to WB - WB must be configured */
504 DSSCOMP_SETUP_DISPLAY_CAPTURE =
505 DSSCOMP_SETUP_DISPLAY | DSSCOMP_SETUP_CAPTURE,
506 };
508 struct dsscomp_setup_mgr_data {
509 __u32 sync_id; /* synchronization ID - for debugging */
511 struct dss2_rect_t win; /* update region, set w/h to 0 for fullscreen */
512 enum dsscomp_setup_mode mode;
513 __u16 num_ovls; /* # of overlays used in the composition */
514 __u16 get_sync_obj; /* ioctl should return a sync object */
516 struct dss2_mgr_info mgr;
517 struct dss2_ovl_info ovls[0]; /* up to 5 overlays to set up */
518 };
520 /*
521 * ioctl: DSSCIOC_CHECK_OVL, struct dsscomp_check_ovl_data
522 *
523 * DISPLAY and/or CAPTURE bits must be filled for the mode field
524 * correctly to be able to decide correctly if DSS can properly
525 * render the overlay.
526 *
527 * ovl.ix is ignored.
528 *
529 * Returns a positive bitmask regarding which overlay of DSS can
530 * render the overlay as it is configured for the display/display's
531 * manager. NOTE: that overlays that are assigned to other displays
532 * may be returned. If there is an invalid configuration (negative
533 * sizes, etc.), a negative error value is returned.
534 *
535 * ovl->decim's min values will be modified to the smallest decimation that
536 * DSS can use to support the overlay configuration.
537 *
538 * Assumptions:
539 * - zorder will be distinct from other pipelines on that manager
540 * - overlay will be enabled and routed to the display specified
541 */
542 struct dsscomp_check_ovl_data {
543 enum dsscomp_setup_mode mode;
544 struct dss2_mgr_info mgr;
545 struct dss2_ovl_info ovl;
546 };
548 /*
549 * This structure is used to set up the entire DISPC (all managers),
550 * and is analogous to dsscomp_setup_mgr_data.
551 *
552 * Additional features:
553 * - all overlays that were specified in a prior use of this
554 * structure, and are no longer specified, will be disabled.
555 * - 1D buffers under 4M will be mapped into TILER1D.
556 *
557 * Limitations:
558 * - only DISPLAY mode is supported (DISPLAY and APPLY bits will
559 * automatically be set)
560 * - getting a sync object is not supported.
561 */
562 struct dsscomp_setup_dispc_data {
563 __u32 sync_id; /* synchronization ID - for debugging */
565 enum dsscomp_setup_mode mode;
566 __u16 num_ovls; /* # of overlays used in the composition */
567 __u16 num_mgrs; /* # of managers used in the composition */
568 __u16 get_sync_obj; /* ioctl should return a sync object */
570 struct dss2_mgr_info mgrs[3];
571 struct dss2_ovl_info ovls[5]; /* up to 5 overlays to set up */
572 };
574 /*
575 * ioctl: DSSCIOC_WB_COPY, struct dsscomp_wb_copy_data
576 *
577 * Requirements:
578 * wb.ix must be OMAP_DSS_WB.
579 *
580 * Returns 0 on success (copy is completed), non-0 on failure.
581 */
582 struct dsscomp_wb_copy_data {
583 struct dss2_ovl_info ovl, wb;
584 };
586 /*
587 * ioctl: DSSCIOC_QUERY_DISPLAY, struct dsscomp_display_info
588 *
589 * Gets informations about the display. Fill in ix and modedb_len before
590 * calling ioctl, and rest of the fields are filled in by ioctl. Up to
591 * modedb_len timings are retrieved in the order of display preference.
592 *
593 * Returns: 0 on success, non-0 error value on failure.
594 */
595 struct dsscomp_display_info {
596 __u32 ix; /* display index (sysfs/display#) */
597 __u32 overlays_available; /* bitmask of available overlays */
598 __u32 overlays_owned; /* bitmask of owned overlays */
599 enum omap_channel channel;
600 enum omap_dss_display_state state;
601 __u8 enabled; /* bool: resume-state if suspended */
602 struct omap_video_timings timings;
603 struct s3d_disp_info s3d_info; /* any S3D specific information */
604 struct dss2_mgr_info mgr; /* manager information */
605 __u16 width_in_mm; /* screen dimensions */
606 __u16 height_in_mm;
608 __u32 modedb_len; /* number of video timings */
609 struct dsscomp_videomode modedb[]; /* display supported timings */
610 };
612 /*
613 * ioctl: DSSCIOC_SETUP_DISPLAY, struct dsscomp_setup_display_data
614 *
615 * Gets informations about the display. Fill in ix before calling
616 * ioctl, and rest of the fields are filled in by ioctl.
617 *
618 * Returns: 0 on success, non-0 error value on failure.
619 */
620 struct dsscomp_setup_display_data {
621 __u32 ix; /* display index (sysfs/display#) */
622 struct dsscomp_videomode mode; /* video timings */
623 };
625 /*
626 * ioctl: DSSCIOC_WAIT, struct dsscomp_wait_data
627 *
628 * Use this ioctl to wait for one of the following events:
629 *
630 * A) the moment a composition is programmed into DSS
631 * B) the moment a composition is first displayed (or captured)
632 * C) the moment when a composition is no longer queued or displayed on a
633 * display (it is released). (A composition is assumed to be superceded
634 * when another composition has been programmed into DSS, even if that
635 * subsequent composition does not update/specify all overlays used by
636 * the prior composition; moreover, even if it uses the same buffers.)
637 *
638 * Set timeout to desired timeout value in microseconds.
639 *
640 * This ioctl must be used on the sync object returned by the
641 * DSSCIOC_SETUP_MGR or DSSCIOC_SETUP_DISPC ioctls.
642 *
643 * Returns: >=0 on success, <0 error value on failure (e.g. -ETIME).
644 */
645 enum dsscomp_wait_phase {
646 DSSCOMP_WAIT_PROGRAMMED = 1,
647 DSSCOMP_WAIT_DISPLAYED,
648 DSSCOMP_WAIT_RELEASED,
649 };
651 struct dsscomp_wait_data {
652 __u32 timeout_us; /* timeout in microseconds */
653 enum dsscomp_wait_phase phase; /* phase to wait for */
654 };
656 /* IOCTLS */
657 #define DSSCIOC_SETUP_MGR _IOW('O', 128, struct dsscomp_setup_mgr_data)
658 #define DSSCIOC_CHECK_OVL _IOWR('O', 129, struct dsscomp_check_ovl_data)
659 #define DSSCIOC_WB_COPY _IOW('O', 130, struct dsscomp_wb_copy_data)
660 #define DSSCIOC_QUERY_DISPLAY _IOWR('O', 131, struct dsscomp_display_info)
661 #define DSSCIOC_WAIT _IOW('O', 132, struct dsscomp_wait_data)
663 #define DSSCIOC_SETUP_DISPC _IOW('O', 133, struct dsscomp_setup_dispc_data)
664 #define DSSCIOC_SETUP_DISPLAY \
665 _IOW('O', 134, struct dsscomp_setup_display_data)
666 #endif