include/video/omapdss.h

   1 /*
   2  * Copyright (C) 2008 Nokia Corporation
   3  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef __OMAP_OMAPDSS_H
  19 #define __OMAP_OMAPDSS_H
  20
  21 #include <linux/list.h>
  22 #include <linux/kobject.h>
  23 #include <linux/device.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/fb.h>
  26 #include <sound/asound.h>
  27
  28 #define DISPC_IRQ_FRAMEDONE             (1 << 0)
  29 #define DISPC_IRQ_VSYNC                 (1 << 1)
  30 #define DISPC_IRQ_EVSYNC_EVEN           (1 << 2)
  31 #define DISPC_IRQ_EVSYNC_ODD            (1 << 3)
  32 #define DISPC_IRQ_ACBIAS_COUNT_STAT     (1 << 4)
  33 #define DISPC_IRQ_PROG_LINE_NUM         (1 << 5)
  34 #define DISPC_IRQ_GFX_FIFO_UNDERFLOW    (1 << 6)
  35 #define DISPC_IRQ_GFX_END_WIN           (1 << 7)
  36 #define DISPC_IRQ_PAL_GAMMA_MASK        (1 << 8)
  37 #define DISPC_IRQ_OCP_ERR               (1 << 9)
  38 #define DISPC_IRQ_VID1_FIFO_UNDERFLOW   (1 << 10)
  39 #define DISPC_IRQ_VID1_END_WIN          (1 << 11)
  40 #define DISPC_IRQ_VID2_FIFO_UNDERFLOW   (1 << 12)
  41 #define DISPC_IRQ_VID2_END_WIN          (1 << 13)
  42 #define DISPC_IRQ_SYNC_LOST             (1 << 14)
  43 #define DISPC_IRQ_SYNC_LOST_DIGIT       (1 << 15)
  44 #define DISPC_IRQ_WAKEUP                (1 << 16)
  45 #define DISPC_IRQ_SYNC_LOST2            (1 << 17)
  46 #define DISPC_IRQ_VSYNC2                (1 << 18)
  47 #define DISPC_IRQ_VID3_END_WIN          (1 << 19)
  48 #define DISPC_IRQ_VID3_FIFO_UNDERFLOW   (1 << 20)
  49 #define DISPC_IRQ_ACBIAS_COUNT_STAT2    (1 << 21)
  50 #define DISPC_IRQ_FRAMEDONE2            (1 << 22)
  51 #define DISPC_IRQ_FRAMEDONEWB           (1 << 23)
  52 #define DISPC_IRQ_FRAMEDONETV           (1 << 24)
  53 #define DISPC_IRQ_WBBUFFEROVERFLOW      (1 << 25)
  54 #define DISPC_IRQ_SYNC_LOST3            (1 << 27)
  55 #define DISPC_IRQ_VSYNC3                (1 << 28)
  56 #define DISPC_IRQ_ACBIAS_COUNT_STAT3    (1 << 29)
  57 #define DISPC_IRQ_FRAMEDONE3            (1 << 30)
  58
  59 struct omap_dss_device;
  60 struct omap_overlay_manager;
  61 struct dss_lcd_mgr_config;
  62 struct snd_aes_iec958;
  63 struct snd_cea_861_aud_if;
  64
  65 enum omap_display_type {
  66         OMAP_DISPLAY_TYPE_NONE          = 0,
  67         OMAP_DISPLAY_TYPE_DPI           = 1 << 0,
  68         OMAP_DISPLAY_TYPE_DBI           = 1 << 1,
  69         OMAP_DISPLAY_TYPE_SDI           = 1 << 2,
  70         OMAP_DISPLAY_TYPE_DSI           = 1 << 3,
  71         OMAP_DISPLAY_TYPE_VENC          = 1 << 4,
  72         OMAP_DISPLAY_TYPE_HDMI          = 1 << 5,
  73 };
  74
  75 enum omap_plane {
  76         OMAP_DSS_GFX    = 0,
  77         OMAP_DSS_VIDEO1 = 1,
  78         OMAP_DSS_VIDEO2 = 2,
  79         OMAP_DSS_VIDEO3 = 3,
  80         OMAP_DSS_WB     = 4,
  81 };
  82
  83 enum omap_channel {
  84         OMAP_DSS_CHANNEL_LCD    = 0,
  85         OMAP_DSS_CHANNEL_DIGIT  = 1,
  86         OMAP_DSS_CHANNEL_LCD2   = 2,
  87         OMAP_DSS_CHANNEL_LCD3   = 3,
  88 };
  89
  90 enum omap_color_mode {
  91         OMAP_DSS_COLOR_CLUT1    = 1 << 0,  /* BITMAP 1 */
  92         OMAP_DSS_COLOR_CLUT2    = 1 << 1,  /* BITMAP 2 */
  93         OMAP_DSS_COLOR_CLUT4    = 1 << 2,  /* BITMAP 4 */
  94         OMAP_DSS_COLOR_CLUT8    = 1 << 3,  /* BITMAP 8 */
  95         OMAP_DSS_COLOR_RGB12U   = 1 << 4,  /* RGB12, 16-bit container */
  96         OMAP_DSS_COLOR_ARGB16   = 1 << 5,  /* ARGB16 */
  97         OMAP_DSS_COLOR_RGB16    = 1 << 6,  /* RGB16 */
  98         OMAP_DSS_COLOR_RGB24U   = 1 << 7,  /* RGB24, 32-bit container */
  99         OMAP_DSS_COLOR_RGB24P   = 1 << 8,  /* RGB24, 24-bit container */
 100         OMAP_DSS_COLOR_YUV2     = 1 << 9,  /* YUV2 4:2:2 co-sited */
 101         OMAP_DSS_COLOR_UYVY     = 1 << 10, /* UYVY 4:2:2 co-sited */
 102         OMAP_DSS_COLOR_ARGB32   = 1 << 11, /* ARGB32 */
 103         OMAP_DSS_COLOR_RGBA32   = 1 << 12, /* RGBA32 */
 104         OMAP_DSS_COLOR_RGBX32   = 1 << 13, /* RGBx32 */
 105         OMAP_DSS_COLOR_NV12             = 1 << 14, /* NV12 format: YUV 4:2:0 */
 106         OMAP_DSS_COLOR_RGBA16           = 1 << 15, /* RGBA16 - 4444 */
 107         OMAP_DSS_COLOR_RGBX16           = 1 << 16, /* RGBx16 - 4444 */
 108         OMAP_DSS_COLOR_ARGB16_1555      = 1 << 17, /* ARGB16 - 1555 */
 109         OMAP_DSS_COLOR_XRGB16_1555      = 1 << 18, /* xRGB16 - 1555 */
 110 };
 111
 112 enum omap_dss_load_mode {
 113         OMAP_DSS_LOAD_CLUT_AND_FRAME    = 0,
 114         OMAP_DSS_LOAD_CLUT_ONLY         = 1,
 115         OMAP_DSS_LOAD_FRAME_ONLY        = 2,
 116         OMAP_DSS_LOAD_CLUT_ONCE_FRAME   = 3,
 117 };
 118
 119 enum omap_dss_trans_key_type {
 120         OMAP_DSS_COLOR_KEY_GFX_DST = 0,
 121         OMAP_DSS_COLOR_KEY_VID_SRC = 1,
 122 };
 123
 124 enum omap_rfbi_te_mode {
 125         OMAP_DSS_RFBI_TE_MODE_1 = 1,
 126         OMAP_DSS_RFBI_TE_MODE_2 = 2,
 127 };
 128
 129 enum omap_dss_signal_level {
 130         OMAPDSS_SIG_ACTIVE_HIGH = 0,
 131         OMAPDSS_SIG_ACTIVE_LOW  = 1,
 132 };
 133
 134 enum omap_dss_signal_edge {
 135         OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
 136         OMAPDSS_DRIVE_SIG_RISING_EDGE,
 137         OMAPDSS_DRIVE_SIG_FALLING_EDGE,
 138 };
 139
 140 enum omap_dss_venc_type {
 141         OMAP_DSS_VENC_TYPE_COMPOSITE,
 142         OMAP_DSS_VENC_TYPE_SVIDEO,
 143 };
 144
 145 enum omap_dss_dsi_pixel_format {
 146         OMAP_DSS_DSI_FMT_RGB888,
 147         OMAP_DSS_DSI_FMT_RGB666,
 148         OMAP_DSS_DSI_FMT_RGB666_PACKED,
 149         OMAP_DSS_DSI_FMT_RGB565,
 150 };
 151
 152 enum omap_dss_dsi_mode {
 153         OMAP_DSS_DSI_CMD_MODE = 0,
 154         OMAP_DSS_DSI_VIDEO_MODE,
 155 };
 156
 157 enum omap_display_caps {
 158         OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE      = 1 << 0,
 159         OMAP_DSS_DISPLAY_CAP_TEAR_ELIM          = 1 << 1,
 160 };
 161
 162 enum omap_dss_display_state {
 163         OMAP_DSS_DISPLAY_DISABLED = 0,
 164         OMAP_DSS_DISPLAY_ACTIVE,
 165         OMAP_DSS_DISPLAY_SUSPENDED,
 166 };
 167
 168 enum omap_dss_audio_state {
 169         OMAP_DSS_AUDIO_DISABLED = 0,
 170         OMAP_DSS_AUDIO_ENABLED,
 171         OMAP_DSS_AUDIO_CONFIGURED,
 172         OMAP_DSS_AUDIO_PLAYING,
 173 };
 174
 175 enum omap_dss_rotation_type {
 176         OMAP_DSS_ROT_DMA        = 1 << 0,
 177         OMAP_DSS_ROT_VRFB       = 1 << 1,
 178         OMAP_DSS_ROT_TILER      = 1 << 2,
 179 };
 180
 181 /* clockwise rotation angle */
 182 enum omap_dss_rotation_angle {
 183         OMAP_DSS_ROT_0   = 0,
 184         OMAP_DSS_ROT_90  = 1,
 185         OMAP_DSS_ROT_180 = 2,
 186         OMAP_DSS_ROT_270 = 3,
 187 };
 188
 189 enum omap_overlay_caps {
 190         OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
 191         OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1,
 192         OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2,
 193         OMAP_DSS_OVL_CAP_ZORDER = 1 << 3,
 194         OMAP_DSS_OVL_CAP_POS = 1 << 4,
 195         OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5,
 196 };
 197
 198 enum omap_overlay_manager_caps {
 199         OMAP_DSS_DUMMY_VALUE, /* add a dummy value to prevent compiler error */
 200 };
 201
 202 enum omap_dss_clk_source {
 203         OMAP_DSS_CLK_SRC_FCK = 0,               /* OMAP2/3: DSS1_ALWON_FCLK
 204                                                  * OMAP4: DSS_FCLK */
 205         OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,   /* OMAP3: DSI1_PLL_FCLK
 206                                                  * OMAP4: PLL1_CLK1 */
 207         OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,     /* OMAP3: DSI2_PLL_FCLK
 208                                                  * OMAP4: PLL1_CLK2 */
 209         OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC,  /* OMAP4: PLL2_CLK1 */
 210         OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI,    /* OMAP4: PLL2_CLK2 */
 211 };
 212
 213 enum omap_hdmi_flags {
 214         OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP = 1 << 0,
 215 };
 216
 217 enum omap_dss_output_id {
 218         OMAP_DSS_OUTPUT_DPI     = 1 << 0,
 219         OMAP_DSS_OUTPUT_DBI     = 1 << 1,
 220         OMAP_DSS_OUTPUT_SDI     = 1 << 2,
 221         OMAP_DSS_OUTPUT_DSI1    = 1 << 3,
 222         OMAP_DSS_OUTPUT_DSI2    = 1 << 4,
 223         OMAP_DSS_OUTPUT_VENC    = 1 << 5,
 224         OMAP_DSS_OUTPUT_HDMI    = 1 << 6,
 225         OMAP_DSS_OUTPUT_DPI1    = 1 << 7,
 226         OMAP_DSS_OUTPUT_DPI2    = 1 << 8,
 227 };
 228
 229 /* Stereoscopic Panel types
 230  * row, column, overunder, sidebyside options
 231  * are with respect to native scan order
 232 */
 233 enum s3d_disp_type {
 234         S3D_DISP_NONE = 0,
 235         S3D_DISP_FRAME_SEQ,
 236         S3D_DISP_ROW_IL,
 237         S3D_DISP_COL_IL,
 238         S3D_DISP_PIX_IL,
 239         S3D_DISP_CHECKB,
 240         S3D_DISP_OVERUNDER,
 241         S3D_DISP_SIDEBYSIDE,
 242 };
 243
 244 /* Subsampling direction is based on native panel scan order.
 245 */
 246 enum s3d_disp_sub_sampling {
 247         S3D_DISP_SUB_SAMPLE_NONE = 0,
 248         S3D_DISP_SUB_SAMPLE_V,
 249         S3D_DISP_SUB_SAMPLE_H,
 250 };
 251
 252 /* Indicates if display expects left view first followed by right or viceversa
 253  * For row interlaved displays, defines first row view
 254  * For column interleaved displays, defines first column view
 255  * For checkerboard, defines first pixel view
 256  * For overunder, defines top view
 257  * For sidebyside, defines west view
 258 */
 259 enum s3d_disp_order {
 260         S3D_DISP_ORDER_L = 0,
 261         S3D_DISP_ORDER_R = 1,
 262 };
 263
 264 /* S3D information */
 265 struct s3d_disp_info {
 266         enum s3d_disp_type type;
 267         enum s3d_disp_sub_sampling sub_samp;
 268         enum s3d_disp_order order;
 269         /* Gap between left and right views
 270          * For over/under units are lines
 271          * For sidebyside units are pixels
 272           *For other types ignored*/
 273         unsigned int gap;
 274 };
 275
 276 /* RFBI */
 277
 278 struct rfbi_timings {
 279         int cs_on_time;
 280         int cs_off_time;
 281         int we_on_time;
 282         int we_off_time;
 283         int re_on_time;
 284         int re_off_time;
 285         int we_cycle_time;
 286         int re_cycle_time;
 287         int cs_pulse_width;
 288         int access_time;
 289
 290         int clk_div;
 291
 292         u32 tim[5];             /* set by rfbi_convert_timings() */
 293
 294         int converted;
 295 };
 296
 297 void omap_rfbi_write_command(const void *buf, u32 len);
 298 void omap_rfbi_read_data(void *buf, u32 len);
 299 void omap_rfbi_write_data(const void *buf, u32 len);
 300 void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
 301                 u16 x, u16 y,
 302                 u16 w, u16 h);
 303 int omap_rfbi_enable_te(bool enable, unsigned line);
 304 int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
 305                              unsigned hs_pulse_time, unsigned vs_pulse_time,
 306                              int hs_pol_inv, int vs_pol_inv, int extif_div);
 307 void rfbi_bus_lock(void);
 308 void rfbi_bus_unlock(void);
 309
 310 /* DSI */
 311
 312 struct omap_dss_dsi_videomode_timings {
 313         /* DSI video mode blanking data */
 314         /* Unit: byte clock cycles */
 315         u16 hsa;
 316         u16 hfp;
 317         u16 hbp;
 318         /* Unit: line clocks */
 319         u16 vsa;
 320         u16 vfp;
 321         u16 vbp;
 322
 323         /* DSI blanking modes */
 324         int blanking_mode;
 325         int hsa_blanking_mode;
 326         int hbp_blanking_mode;
 327         int hfp_blanking_mode;
 328
 329         /* Video port sync events */
 330         bool vp_vsync_end;
 331         bool vp_hsync_end;
 332
 333         bool ddr_clk_always_on;
 334         int window_sync;
 335 };
 336
 337 void dsi_bus_lock(struct omap_dss_device *dssdev);
 338 void dsi_bus_unlock(struct omap_dss_device *dssdev);
 339 int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
 340                 int len);
 341 int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
 342                 int len);
 343 int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd);
 344 int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel);
 345 int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
 346                 u8 param);
 347 int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel,
 348                 u8 param);
 349 int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel,
 350                 u8 param1, u8 param2);
 351 int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
 352                 u8 *data, int len);
 353 int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
 354                 u8 *data, int len);
 355 int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
 356                 u8 *buf, int buflen);
 357 int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf,
 358                 int buflen);
 359 int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param,
 360                 u8 *buf, int buflen);
 361 int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel,
 362                 u8 param1, u8 param2, u8 *buf, int buflen);
 363 int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
 364                 u16 len);
 365 int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
 366 int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel);
 367 int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel);
 368 void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel);
 369
 370 enum omapdss_version {
 371         OMAPDSS_VER_UNKNOWN = 0,
 372         OMAPDSS_VER_OMAP24xx,
 373         OMAPDSS_VER_OMAP34xx_ES1,       /* OMAP3430 ES1.0, 2.0 */
 374         OMAPDSS_VER_OMAP34xx_ES3,       /* OMAP3430 ES3.0+ */
 375         OMAPDSS_VER_OMAP3630,
 376         OMAPDSS_VER_AM35xx,
 377         OMAPDSS_VER_OMAP4430_ES1,       /* OMAP4430 ES1.0 */
 378         OMAPDSS_VER_OMAP4430_ES2,       /* OMAP4430 ES2.0, 2.1, 2.2 */
 379         OMAPDSS_VER_OMAP4,              /* All other OMAP4s */
 380         OMAPDSS_VER_OMAP5,
 381         OMAPDSS_VER_DRA7xx,
 382 };
 383
 384 /* Board specific data */
 385 struct omap_dss_board_info {
 386         int (*get_context_loss_count)(struct device *dev);
 387         int num_devices;
 388         struct omap_dss_device **devices;
 389         struct omap_dss_device *default_device;
 390         int (*dsi_enable_pads)(int dsi_id, unsigned lane_mask);
 391         void (*dsi_disable_pads)(int dsi_id, unsigned lane_mask);
 392         int (*set_min_bus_tput)(struct device *dev, unsigned long r);
 393         enum omapdss_version version;
 394 };
 395
 396 /* Init with the board info */
 397 extern int omap_display_init(struct omap_dss_board_info *board_data);
 398 /* HDMI mux init*/
 399 extern int omap_hdmi_init(enum omap_hdmi_flags flags);
 400
 401 struct omap_video_timings {
 402         /* Unit: pixels */
 403         u16 x_res;
 404         /* Unit: pixels */
 405         u16 y_res;
 406         /* Unit: KHz */
 407         u32 pixel_clock;
 408         /* Unit: pixel clocks */
 409         u16 hsw;        /* Horizontal synchronization pulse width */
 410         /* Unit: pixel clocks */
 411         u16 hfp;        /* Horizontal front porch */
 412         /* Unit: pixel clocks */
 413         u16 hbp;        /* Horizontal back porch */
 414         /* Unit: line clocks */
 415         u16 vsw;        /* Vertical synchronization pulse width */
 416         /* Unit: line clocks */
 417         u16 vfp;        /* Vertical front porch */
 418         /* Unit: line clocks */
 419         u16 vbp;        /* Vertical back porch */
 420
 421         /* Vsync logic level */
 422         enum omap_dss_signal_level vsync_level;
 423         /* Hsync logic level */
 424         enum omap_dss_signal_level hsync_level;
 425         /* Interlaced or Progressive timings */
 426         bool interlace;
 427         /* Pixel clock edge to drive LCD data */
 428         enum omap_dss_signal_edge data_pclk_edge;
 429         /* Data enable logic level */
 430         enum omap_dss_signal_level de_level;
 431         /* Pixel clock edges to drive HSYNC and VSYNC signals */
 432         enum omap_dss_signal_edge sync_pclk_edge;
 433 };
 434
 435 #ifdef CONFIG_OMAP2_DSS_VENC
 436 /* Hardcoded timings for tv modes. Venc only uses these to
 437  * identify the mode, and does not actually use the configs
 438  * itself. However, the configs should be something that
 439  * a normal monitor can also show */
 440 extern const struct omap_video_timings omap_dss_pal_timings;
 441 extern const struct omap_video_timings omap_dss_ntsc_timings;
 442 #endif
 443
 444 enum omapdss_completion_status {
 445         DSS_COMPLETION_PROGRAMMED       = (1 << 1),
 446         DSS_COMPLETION_DISPLAYED        = (1 << 2),
 447
 448         DSS_COMPLETION_CHANGED_SET      = (1 << 3),
 449         DSS_COMPLETION_CHANGED_CACHE    = (1 << 4),
 450         DSS_COMPLETION_CHANGED          = (3 << 3),
 451
 452         DSS_COMPLETION_RELEASED         = (15 << 5),
 453         DSS_COMPLETION_ECLIPSED_SET     = (1 << 5),
 454         DSS_COMPLETION_ECLIPSED_CACHE   = (1 << 6),
 455         DSS_COMPLETION_ECLIPSED_SHADOW  = (1 << 7),
 456         DSS_COMPLETION_TORN             = (1 << 8),
 457 };
 458
 459 struct omapdss_ovl_cb {
 460         /* optional callback method */
 461         u32 (*fn)(void *data, int id, int status);
 462         void *data;
 463         u32 mask;
 464 };
 465
 466 struct omap_dss_cconv_coefs {
 467         s16 ry, rcr, rcb;
 468         s16 gy, gcr, gcb;
 469         s16 by, bcr, bcb;
 470         u16 full_range;
 471 } __aligned(4);
 472
 473 /* Writeback data structures */
 474 enum omap_writeback_source {
 475         OMAP_WB_LCD1            = 0,
 476         OMAP_WB_TV              = 1,
 477         OMAP_WB_LCD2            = 2,
 478         OMAP_WB_GFX             = 3,
 479         OMAP_WB_VID1            = 4,
 480         OMAP_WB_VID2            = 5,
 481         OMAP_WB_VID3            = 6
 482 };
 483
 484 enum omap_writeback_capturemode {
 485         OMAP_WB_CAPTURE_ALL             = 0x0,
 486         OMAP_WB_CAPTURE_1               = 0x1,
 487         OMAP_WB_CAPTURE_1_OF_2  = 0x2,
 488         OMAP_WB_CAPTURE_1_OF_3  = 0x3,
 489         OMAP_WB_CAPTURE_1_OF_4  = 0x4,
 490         OMAP_WB_CAPTURE_1_OF_5  = 0x5,
 491         OMAP_WB_CAPTURE_1_OF_6  = 0x6,
 492         OMAP_WB_CAPTURE_1_OF_7  = 0x7
 493 };
 494
 495 enum omap_writeback_mode {
 496         OMAP_WB_CAPTURE_MODE    = 0x0,
 497         OMAP_WB_MEM2MEM_MODE    = 0x1,
 498 };
 499
 500 struct omap_writeback_info {
 501         bool                                    enabled;
 502         bool                                    info_dirty;
 503         enum omap_writeback_source              source;
 504         u16                                     width;
 505         u16                                     height;
 506         u16                                     out_width;
 507         u16                                     out_height;
 508         enum omap_color_mode                    dss_mode;
 509         enum omap_writeback_capturemode         capturemode;
 510         /* capture or mem2mem mode */
 511         enum omap_writeback_mode                mode;
 512         u32                                     paddr;
 513         /* NV12 support*/
 514         u32                                     p_uv_addr;
 515         u8                                      rotation;
 516         enum omap_dss_rotation_type             rotation_type;
 517         bool force_1d;
 518 };
 519
 520 struct omap_writeback {
 521         struct kobject                  kobj;
 522         struct list_head                list;
 523         bool                            info_dirty;
 524         int                             width;
 525         int                             height;
 526         /* mutex to control access to wb data */
 527         struct mutex                    lock;
 528         struct omap_writeback_info      info;
 529         struct completion               wb_completion;
 530
 531         bool (*check_wb)(struct omap_writeback *wb);
 532         int (*set_wb_info)(struct omap_writeback *wb,
 533                         struct omap_writeback_info *info);
 534         void (*get_wb_info)(struct omap_writeback *wb,
 535                         struct omap_writeback_info *info);
 536         int (*register_framedone)(struct omap_writeback *wb);
 537         int (*wait_framedone)(struct omap_writeback *wb);
 538 };
 539
 540 struct omap_dss_cpr_coefs {
 541         s16 rr, rg, rb;
 542         s16 gr, gg, gb;
 543         s16 br, bg, bb;
 544 };
 545
 546 struct omap_overlay_info {
 547         u32 paddr;
 548         u32 p_uv_addr;  /* for NV12 format */
 549         u16 screen_width;
 550         u16 width;
 551         u16 height;
 552         enum omap_color_mode color_mode;
 553         u8 rotation;
 554         enum omap_dss_rotation_type rotation_type;
 555         bool mirror;
 556
 557         u16 pos_x;
 558         u16 pos_y;
 559         u16 out_width;  /* if 0, out_width == width */
 560         u16 out_height; /* if 0, out_height == height */
 561         u8 global_alpha;
 562         u8 pre_mult_alpha;
 563         u8 zorder;
 564         u16 min_x_decim, max_x_decim, min_y_decim, max_y_decim;
 565
 566         struct omapdss_ovl_cb cb;
 567         struct omap_dss_cconv_coefs cconv;
 568         bool force_1d;
 569         bool mflag_en;
 570 };
 571
 572 struct omap_overlay {
 573         struct kobject kobj;
 574         struct list_head list;
 575
 576         /* static fields */
 577         const char *name;
 578         enum omap_plane id;
 579         enum omap_color_mode supported_modes;
 580         enum omap_overlay_caps caps;
 581         bool enabled;
 582
 583         /* dynamic fields */
 584         struct omap_overlay_manager *manager;
 585
 586         /*
 587          * The following functions do not block:
 588          *
 589          * is_enabled
 590          * set_overlay_info
 591          * get_overlay_info
 592          *
 593          * The rest of the functions may block and cannot be called from
 594          * interrupt context
 595          */
 596
 597         int (*enable)(struct omap_overlay *ovl);
 598         int (*disable)(struct omap_overlay *ovl);
 599         bool (*is_enabled)(struct omap_overlay *ovl);
 600
 601         int (*set_manager)(struct omap_overlay *ovl,
 602                 struct omap_overlay_manager *mgr);
 603         int (*unset_manager)(struct omap_overlay *ovl);
 604
 605         int (*set_overlay_info)(struct omap_overlay *ovl,
 606                         struct omap_overlay_info *info);
 607         void (*get_overlay_info)(struct omap_overlay *ovl,
 608                         struct omap_overlay_info *info);
 609
 610         int (*wait_for_go)(struct omap_overlay *ovl);
 611
 612         struct omap_dss_device *(*get_device)(struct omap_overlay *ovl);
 613 };
 614
 615 struct omap_overlay_manager_info {
 616         u32 default_color;
 617
 618         enum omap_dss_trans_key_type trans_key_type;
 619         u32 trans_key;
 620         bool trans_enabled;
 621
 622         bool partial_alpha_enabled;
 623
 624         bool cpr_enable;
 625         struct omap_dss_cpr_coefs cpr_coefs;
 626
 627         struct omapdss_ovl_cb cb;
 628 };
 629
 630 struct omap_overlay_manager {
 631         struct kobject kobj;
 632
 633         /* static fields */
 634         const char *name;
 635         enum omap_channel id;
 636         enum omap_overlay_manager_caps caps;
 637         struct list_head overlays;
 638         enum omap_display_type supported_displays;
 639         enum omap_dss_output_id supported_outputs;
 640
 641         /* dynamic fields */
 642         struct omap_dss_output *output;
 643
 644         /* Overlays associated with the manager */
 645         struct omap_overlay *ovls[5];
 646
 647         /* No of overlays for the manager that requires update */
 648         u16 num_ovls;
 649
 650         /*
 651          * The following functions do not block:
 652          *
 653          * set_manager_info
 654          * get_manager_info
 655          * apply
 656          *
 657          * The rest of the functions may block and cannot be called from
 658          * interrupt context
 659          */
 660
 661         int (*set_output)(struct omap_overlay_manager *mgr,
 662                 struct omap_dss_output *output);
 663         int (*unset_output)(struct omap_overlay_manager *mgr);
 664
 665         int (*set_manager_info)(struct omap_overlay_manager *mgr,
 666                         struct omap_overlay_manager_info *info);
 667         void (*get_manager_info)(struct omap_overlay_manager *mgr,
 668                         struct omap_overlay_manager_info *info);
 669
 670         int (*apply)(struct omap_overlay_manager *mgr);
 671         int (*wait_for_go)(struct omap_overlay_manager *mgr);
 672         int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
 673         int (*blank)(struct omap_overlay_manager *mgr, bool wait_for_vsync);
 674         void (*dump_cb)(struct omap_overlay_manager *mgr, struct seq_file *s);
 675         int (*set_ovl)(struct omap_overlay_manager *mgr);
 676         int (*wb_apply)(struct omap_overlay_manager *mgr,
 677                 struct omap_writeback *wb);
 678
 679         struct omap_dss_device *(*get_device)(struct omap_overlay_manager *mgr);
 680 };
 681
 682 /* 22 pins means 1 clk lane and 10 data lanes */
 683 #define OMAP_DSS_MAX_DSI_PINS 22
 684
 685 struct omap_dsi_pin_config {
 686         int num_pins;
 687         /*
 688          * pin numbers in the following order:
 689          * clk+, clk-
 690          * data1+, data1-
 691          * data2+, data2-
 692          * ...
 693          */
 694         int pins[OMAP_DSS_MAX_DSI_PINS];
 695 };
 696
 697 struct omap_dss_writeback_info {
 698         u32 paddr;
 699         u32 p_uv_addr;
 700         u16 buf_width;
 701         u16 width;
 702         u16 height;
 703         enum omap_color_mode color_mode;
 704         u8 rotation;
 705         enum omap_dss_rotation_type rotation_type;
 706         bool mirror;
 707         u8 pre_mult_alpha;
 708 };
 709
 710 struct omap_dss_output {
 711         struct list_head list;
 712
 713         /* display type supported by the output */
 714         enum omap_display_type type;
 715
 716         /* output instance */
 717         enum omap_dss_output_id id;
 718
 719         /* output's platform device pointer */
 720         struct platform_device *pdev;
 721
 722         /* dynamic fields */
 723         struct omap_overlay_manager *manager;
 724
 725         struct omap_dss_device *device;
 726 };
 727
 728 struct omap_dss_device {
 729         struct device dev;
 730
 731         enum omap_display_type type;
 732
 733         enum omap_channel channel;
 734
 735         bool first_vsync;
 736
 737         union {
 738                 struct {
 739                         u8 data_lines;
 740                 } dpi;
 741
 742                 struct {
 743                         u8 channel;
 744                         u8 data_lines;
 745                 } rfbi;
 746
 747                 struct {
 748                         u8 datapairs;
 749                 } sdi;
 750
 751                 struct {
 752                         int module;
 753
 754                         bool ext_te;
 755                         u8 ext_te_gpio;
 756                 } dsi;
 757
 758                 struct {
 759                         enum omap_dss_venc_type type;
 760                         bool invert_polarity;
 761                 } venc;
 762         } phy;
 763
 764         struct {
 765                 struct {
 766                         struct {
 767                                 u16 lck_div;
 768                                 u16 pck_div;
 769                                 enum omap_dss_clk_source lcd_clk_src;
 770                         } channel;
 771
 772                         enum omap_dss_clk_source dispc_fclk_src;
 773                 } dispc;
 774
 775                 struct {
 776                         /* regn is one greater than TRM's REGN value */
 777                         u16 regn;
 778                         u16 regm;
 779                         u16 regm_dispc;
 780                         u16 regm_dsi;
 781
 782                         u16 lp_clk_div;
 783                         enum omap_dss_clk_source dsi_fclk_src;
 784                 } dsi;
 785
 786                 struct {
 787                         /* regn is one greater than TRM's REGN value */
 788                         u16 regn;
 789                         u16 regm2;
 790                 } hdmi;
 791         } clocks;
 792
 793         struct {
 794                 struct omap_video_timings timings;
 795
 796                 enum omap_dss_dsi_pixel_format dsi_pix_fmt;
 797                 enum omap_dss_dsi_mode dsi_mode;
 798                 struct omap_dss_dsi_videomode_timings dsi_vm_timings;
 799                 struct s3d_disp_info s3d_info;
 800                 u32 width_in_um;
 801                 u32 height_in_um;
 802         } panel;
 803
 804         struct {
 805                 u8 pixel_size;
 806                 struct rfbi_timings rfbi_timings;
 807         } ctrl;
 808
 809         int reset_gpio;
 810
 811         int max_backlight_level;
 812
 813         const char *name;
 814
 815         /* used to match device to driver */
 816         const char *driver_name;
 817
 818         void *data;
 819
 820         struct omap_dss_driver *driver;
 821
 822         /* helper variable for driver suspend/resume */
 823         bool activate_after_resume;
 824
 825         enum omap_display_caps caps;
 826
 827         struct omap_dss_output *output;
 828
 829         enum omap_dss_display_state state;
 830
 831         struct blocking_notifier_head state_notifiers;
 832
 833         enum omap_dss_audio_state audio_state;
 834
 835         /* platform specific  */
 836         int (*platform_enable)(struct omap_dss_device *dssdev);
 837         void (*platform_disable)(struct omap_dss_device *dssdev);
 838         int (*set_backlight)(struct omap_dss_device *dssdev, int level);
 839         int (*get_backlight)(struct omap_dss_device *dssdev);
 840 };
 841
 842 struct omap_dss_hdmi_data
 843 {
 844         int ct_cp_hpd_gpio;
 845         int ls_oe_gpio;
 846         int hpd_gpio;
 847 };
 848
 849 struct omap_dss_audio {
 850         struct snd_aes_iec958 *iec;
 851         struct snd_cea_861_aud_if *cea;
 852 };
 853
 854 struct omap_dss_driver {
 855         struct device_driver driver;
 856
 857         int (*probe)(struct omap_dss_device *);
 858         void (*remove)(struct omap_dss_device *);
 859
 860         int (*enable)(struct omap_dss_device *display);
 861         void (*disable)(struct omap_dss_device *display);
 862         int (*run_test)(struct omap_dss_device *display, int test);
 863
 864         int (*update)(struct omap_dss_device *dssdev,
 865                                u16 x, u16 y, u16 w, u16 h);
 866         int (*sync)(struct omap_dss_device *dssdev);
 867
 868         int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
 869         int (*get_te)(struct omap_dss_device *dssdev);
 870
 871         u8 (*get_rotate)(struct omap_dss_device *dssdev);
 872         int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
 873
 874         bool (*get_mirror)(struct omap_dss_device *dssdev);
 875         int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
 876
 877         int (*memory_read)(struct omap_dss_device *dssdev,
 878                         void *buf, size_t size,
 879                         u16 x, u16 y, u16 w, u16 h);
 880
 881         void (*get_resolution)(struct omap_dss_device *dssdev,
 882                         u16 *xres, u16 *yres);
 883         void (*get_dimensions)(struct omap_dss_device *dssdev,
 884                         u32 *width, u32 *height);
 885         int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
 886
 887         int (*check_timings)(struct omap_dss_device *dssdev,
 888                         struct omap_video_timings *timings);
 889         void (*set_timings)(struct omap_dss_device *dssdev,
 890                         struct omap_video_timings *timings);
 891         void (*get_timings)(struct omap_dss_device *dssdev,
 892                         struct omap_video_timings *timings);
 893
 894         int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
 895         u32 (*get_wss)(struct omap_dss_device *dssdev);
 896
 897         int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
 898         bool (*detect)(struct omap_dss_device *dssdev);
 899
 900         /* for wrapping around state changes */
 901         void (*disable_orig)(struct omap_dss_device *display);
 902         int (*enable_orig)(struct omap_dss_device *display);
 903
 904         /*
 905          * For display drivers that support audio. This encompasses
 906          * HDMI and DisplayPort at the moment.
 907          */
 908         /*
 909          * Note: These functions might sleep. Do not call while
 910          * holding a spinlock/readlock.
 911          */
 912         int (*audio_enable)(struct omap_dss_device *dssdev);
 913         void (*audio_disable)(struct omap_dss_device *dssdev);
 914         bool (*audio_supported)(struct omap_dss_device *dssdev);
 915         int (*audio_config)(struct omap_dss_device *dssdev,
 916                 struct omap_dss_audio *audio);
 917         /* Note: These functions may not sleep */
 918         int (*audio_start)(struct omap_dss_device *dssdev);
 919         void (*audio_stop)(struct omap_dss_device *dssdev);
 920
 921         int (*s3d_enable)(struct omap_dss_device *dssdev,
 922                                 struct s3d_disp_info *info, int code);
 923 };
 924
 925 enum omapdss_version omapdss_get_version(void);
 926
 927 int omap_dss_register_driver(struct omap_dss_driver *);
 928 void omap_dss_unregister_driver(struct omap_dss_driver *);
 929
 930 void omap_dss_get_device(struct omap_dss_device *dssdev);
 931 void omap_dss_put_device(struct omap_dss_device *dssdev);
 932 #define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
 933 struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
 934 struct omap_dss_device *omap_dss_find_device(void *data,
 935                 int (*match)(struct omap_dss_device *dssdev, void *data));
 936 const char *omapdss_get_default_display_name(void);
 937
 938 int omap_dss_start_device(struct omap_dss_device *dssdev);
 939 void omap_dss_stop_device(struct omap_dss_device *dssdev);
 940
 941 int dss_feat_get_num_mgrs(void);
 942 int dss_feat_get_num_ovls(void);
 943 enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel);
 944 enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel);
 945 enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane);
 946
 947
 948
 949 int omap_dss_get_num_overlay_managers(void);
 950 struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
 951
 952 int omap_dss_get_num_overlays(void);
 953 struct omap_overlay *omap_dss_get_overlay(int num);
 954
 955 struct omap_dss_output *omap_dss_get_output(enum omap_dss_output_id id);
 956 int omapdss_output_set_device(struct omap_dss_output *out,
 957                 struct omap_dss_device *dssdev);
 958 int omapdss_output_unset_device(struct omap_dss_output *out);
 959
 960 void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
 961                 u16 *xres, u16 *yres);
 962 int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
 963 void omapdss_default_get_timings(struct omap_dss_device *dssdev,
 964                 struct omap_video_timings *timings);
 965
 966 typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
 967 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
 968 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
 969
 970 u32 dispc_read_irqstatus(void);
 971 void dispc_clear_irqstatus(u32 mask);
 972 u32 dispc_read_irqenable(void);
 973 void dispc_write_irqenable(u32 mask);
 974
 975 int dispc_request_irq(irq_handler_t handler, void *dev_id);
 976 void dispc_free_irq(void *dev_id);
 977
 978 int dispc_runtime_get(void);
 979 void dispc_runtime_put(void);
 980
 981 void dispc_mgr_enable(enum omap_channel channel, bool enable);
 982 bool dispc_mgr_is_enabled(enum omap_channel channel);
 983 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel);
 984 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel);
 985 u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel);
 986 bool dispc_mgr_go_busy(enum omap_channel channel);
 987 void dispc_mgr_go(enum omap_channel channel);
 988 void dispc_mgr_set_lcd_config(enum omap_channel channel,
 989                 const struct dss_lcd_mgr_config *config);
 990 void dispc_mgr_set_timings(enum omap_channel channel,
 991                 const struct omap_video_timings *timings);
 992 void dispc_mgr_setup(enum omap_channel channel,
 993                 const struct omap_overlay_manager_info *info);
 994
 995 int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
 996                 const struct omap_overlay_info *oi,
 997                 const struct omap_video_timings *timings,
 998                 int *x_predecim, int *y_predecim);
 999
1000 int dispc_ovl_enable(enum omap_plane plane, bool enable);
1001 bool dispc_ovl_enabled(enum omap_plane plane);
1002 void dispc_ovl_set_channel_out(enum omap_plane plane,
1003                 enum omap_channel channel);
1004 int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
1005                 bool replication, const struct omap_video_timings *mgr_timings,
1006                 bool mem_to_mem);
1007
1008 #define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
1009 #define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
1010
1011 void omapdss_display_get_dimensions(struct omap_dss_device *dssdev,
1012                                 u32 *width_in_um, u32 *height_in_um);
1013 void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
1014                 bool enable);
1015 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);
1016 void omapdss_dsi_set_timings(struct omap_dss_device *dssdev,
1017                 struct omap_video_timings *timings);
1018 void omapdss_dsi_set_size(struct omap_dss_device *dssdev, u16 w, u16 h);
1019 void omapdss_dsi_set_pixel_format(struct omap_dss_device *dssdev,
1020                 enum omap_dss_dsi_pixel_format fmt);
1021 void omapdss_dsi_set_operation_mode(struct omap_dss_device *dssdev,
1022                 enum omap_dss_dsi_mode mode);
1023 void omapdss_dsi_set_videomode_timings(struct omap_dss_device *dssdev,
1024                 struct omap_dss_dsi_videomode_timings *timings);
1025
1026 int omap_dsi_update(struct omap_dss_device *dssdev, int channel,
1027                 void (*callback)(int, void *), void *data);
1028 int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel);
1029 int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id);
1030 void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel);
1031 int omapdss_dsi_configure_pins(struct omap_dss_device *dssdev,
1032                 const struct omap_dsi_pin_config *pin_cfg);
1033 int omapdss_dsi_set_clocks(struct omap_dss_device *dssdev,
1034                 unsigned long ddr_clk, unsigned long lp_clk);
1035
1036 int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
1037 void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
1038                 bool disconnect_lanes, bool enter_ulps);
1039
1040 int omapdss_dpi_display_enable(struct omap_dss_device *dssdev);
1041 void omapdss_dpi_display_disable(struct omap_dss_device *dssdev);
1042 void omapdss_dpi_set_timings(struct omap_dss_device *dssdev,
1043                 struct omap_video_timings *timings);
1044 int dpi_check_timings(struct omap_dss_device *dssdev,
1045                         struct omap_video_timings *timings);
1046 void omapdss_dpi_set_data_lines(struct omap_dss_device *dssdev, int data_lines);
1047
1048 int omapdss_sdi_display_enable(struct omap_dss_device *dssdev);
1049 void omapdss_sdi_display_disable(struct omap_dss_device *dssdev);
1050 void omapdss_sdi_set_timings(struct omap_dss_device *dssdev,
1051                 struct omap_video_timings *timings);
1052 void omapdss_sdi_set_datapairs(struct omap_dss_device *dssdev, int datapairs);
1053
1054 int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev);
1055 void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev);
1056 int omap_rfbi_update(struct omap_dss_device *dssdev, void (*callback)(void *),
1057                 void *data);
1058 int omap_rfbi_configure(struct omap_dss_device *dssdev);
1059 void omapdss_rfbi_set_size(struct omap_dss_device *dssdev, u16 w, u16 h);
1060 void omapdss_rfbi_set_pixel_size(struct omap_dss_device *dssdev,
1061                 int pixel_size);
1062 void omapdss_rfbi_set_data_lines(struct omap_dss_device *dssdev,
1063                 int data_lines);
1064 void omapdss_rfbi_set_interface_timings(struct omap_dss_device *dssdev,
1065                 struct rfbi_timings *timings);
1066
1067 int dispc_scaling_decision(enum omap_plane plane, struct omap_overlay_info *oi,
1068                 enum omap_channel channel,
1069                 u16 *x_decim, u16 *y_decim, bool *three_tap);
1070 int omap_dss_manager_unregister_callback(struct omap_overlay_manager *mgr,
1071                                          struct omapdss_ovl_cb *cb);
1072
1073 /* generic callback handling */
1074 static inline void dss_ovl_cb(struct omapdss_ovl_cb *cb, int id, int status)
1075 {
1076         if (cb->fn && (cb->mask & status))
1077                 cb->mask &= cb->fn(cb->data, id, status);
1078         if (status & DSS_COMPLETION_RELEASED)
1079                 cb->mask = 0;
1080         if (!cb->mask)
1081                 cb->fn = NULL;
1082 }
1083
1084 int omapdss_compat_init(void);
1085 void omapdss_compat_uninit(void);
1086
1087 struct dss_mgr_ops {
1088         void (*start_update)(struct omap_overlay_manager *mgr);
1089         int (*enable)(struct omap_overlay_manager *mgr);
1090         void (*disable)(struct omap_overlay_manager *mgr);
1091         void (*set_timings)(struct omap_overlay_manager *mgr,
1092                         const struct omap_video_timings *timings);
1093         void (*set_lcd_config)(struct omap_overlay_manager *mgr,
1094                         const struct dss_lcd_mgr_config *config);
1095         int (*register_framedone_handler)(struct omap_overlay_manager *mgr,
1096                         void (*handler)(void *), void *data);
1097         void (*unregister_framedone_handler)(struct omap_overlay_manager *mgr,
1098                         void (*handler)(void *), void *data);
1099 };
1100
1101 int dss_install_mgr_ops(const struct dss_mgr_ops *mgr_ops);
1102 void dss_uninstall_mgr_ops(void);
1103
1104 void dss_mgr_set_timings(struct omap_overlay_manager *mgr,
1105                 const struct omap_video_timings *timings);
1106 void dss_mgr_set_lcd_config(struct omap_overlay_manager *mgr,
1107                 const struct dss_lcd_mgr_config *config);
1108 int dss_mgr_enable(struct omap_overlay_manager *mgr);
1109 void dss_mgr_disable(struct omap_overlay_manager *mgr);
1110 void dss_mgr_start_update(struct omap_overlay_manager *mgr);
1111 int dss_mgr_register_framedone_handler(struct omap_overlay_manager *mgr,
1112                 void (*handler)(void *), void *data);
1113 void dss_mgr_unregister_framedone_handler(struct omap_overlay_manager *mgr,
1114                 void (*handler)(void *), void *data);
1115 #endif