1 /*
2 * Copyright (C) 2008 Nokia Corporation
3 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
18 #ifndef __OMAP_OMAPDSS_H
19 #define __OMAP_OMAPDSS_H
21 #include <linux/list.h>
22 #include <linux/kobject.h>
23 #include <linux/device.h>
24 #include <linux/interrupt.h>
25 #include <linux/fb.h>
26 #include <sound/asound.h>
28 #define DISPC_IRQ_FRAMEDONE (1 << 0)
29 #define DISPC_IRQ_VSYNC (1 << 1)
30 #define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
31 #define DISPC_IRQ_EVSYNC_ODD (1 << 3)
32 #define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
33 #define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
34 #define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
35 #define DISPC_IRQ_GFX_END_WIN (1 << 7)
36 #define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
37 #define DISPC_IRQ_OCP_ERR (1 << 9)
38 #define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
39 #define DISPC_IRQ_VID1_END_WIN (1 << 11)
40 #define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
41 #define DISPC_IRQ_VID2_END_WIN (1 << 13)
42 #define DISPC_IRQ_SYNC_LOST (1 << 14)
43 #define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
44 #define DISPC_IRQ_WAKEUP (1 << 16)
45 #define DISPC_IRQ_SYNC_LOST2 (1 << 17)
46 #define DISPC_IRQ_VSYNC2 (1 << 18)
47 #define DISPC_IRQ_VID3_END_WIN (1 << 19)
48 #define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20)
49 #define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
50 #define DISPC_IRQ_FRAMEDONE2 (1 << 22)
51 #define DISPC_IRQ_FRAMEDONEWB (1 << 23)
52 #define DISPC_IRQ_FRAMEDONETV (1 << 24)
53 #define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25)
54 #define DISPC_IRQ_SYNC_LOST3 (1 << 27)
55 #define DISPC_IRQ_VSYNC3 (1 << 28)
56 #define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 29)
57 #define DISPC_IRQ_FRAMEDONE3 (1 << 30)
59 struct omap_dss_device;
60 struct omap_overlay_manager;
61 struct dss_lcd_mgr_config;
62 struct snd_aes_iec958;
63 struct snd_cea_861_aud_if;
65 enum omap_display_type {
66 OMAP_DISPLAY_TYPE_NONE = 0,
67 OMAP_DISPLAY_TYPE_DPI = 1 << 0,
68 OMAP_DISPLAY_TYPE_DBI = 1 << 1,
69 OMAP_DISPLAY_TYPE_SDI = 1 << 2,
70 OMAP_DISPLAY_TYPE_DSI = 1 << 3,
71 OMAP_DISPLAY_TYPE_VENC = 1 << 4,
72 OMAP_DISPLAY_TYPE_HDMI = 1 << 5,
73 };
75 enum omap_plane {
76 OMAP_DSS_GFX = 0,
77 OMAP_DSS_VIDEO1 = 1,
78 OMAP_DSS_VIDEO2 = 2,
79 OMAP_DSS_VIDEO3 = 3,
80 OMAP_DSS_WB = 4,
81 };
83 enum omap_channel {
84 OMAP_DSS_CHANNEL_LCD = 0,
85 OMAP_DSS_CHANNEL_DIGIT = 1,
86 OMAP_DSS_CHANNEL_LCD2 = 2,
87 OMAP_DSS_CHANNEL_LCD3 = 3,
88 };
90 enum omap_color_mode {
91 OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
92 OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
93 OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
94 OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
95 OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
96 OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
97 OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
98 OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
99 OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
100 OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
101 OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
102 OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
103 OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
104 OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
105 OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */
106 OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */
107 OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */
108 OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */
109 OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */
110 OMAP_DSS_COLOR_BGRA32 = 1 << 19, /* BGRA32 */
111 };
113 enum omap_dss_load_mode {
114 OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
115 OMAP_DSS_LOAD_CLUT_ONLY = 1,
116 OMAP_DSS_LOAD_FRAME_ONLY = 2,
117 OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
118 };
120 enum omap_dss_trans_key_type {
121 OMAP_DSS_COLOR_KEY_GFX_DST = 0,
122 OMAP_DSS_COLOR_KEY_VID_SRC = 1,
123 };
125 enum omap_rfbi_te_mode {
126 OMAP_DSS_RFBI_TE_MODE_1 = 1,
127 OMAP_DSS_RFBI_TE_MODE_2 = 2,
128 };
130 enum omap_dss_signal_level {
131 OMAPDSS_SIG_ACTIVE_HIGH = 0,
132 OMAPDSS_SIG_ACTIVE_LOW = 1,
133 };
135 enum omap_dss_signal_edge {
136 OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
137 OMAPDSS_DRIVE_SIG_RISING_EDGE,
138 OMAPDSS_DRIVE_SIG_FALLING_EDGE,
139 };
141 enum omap_dss_venc_type {
142 OMAP_DSS_VENC_TYPE_COMPOSITE,
143 OMAP_DSS_VENC_TYPE_SVIDEO,
144 };
146 enum omap_dss_dsi_pixel_format {
147 OMAP_DSS_DSI_FMT_RGB888,
148 OMAP_DSS_DSI_FMT_RGB666,
149 OMAP_DSS_DSI_FMT_RGB666_PACKED,
150 OMAP_DSS_DSI_FMT_RGB565,
151 };
153 enum omap_dss_dsi_mode {
154 OMAP_DSS_DSI_CMD_MODE = 0,
155 OMAP_DSS_DSI_VIDEO_MODE,
156 };
158 enum omap_display_caps {
159 OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
160 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
161 };
163 enum omap_dss_display_state {
164 OMAP_DSS_DISPLAY_DISABLED = 0,
165 OMAP_DSS_DISPLAY_ACTIVE,
166 OMAP_DSS_DISPLAY_SUSPENDED,
167 };
169 enum omap_dss_audio_state {
170 OMAP_DSS_AUDIO_DISABLED = 0,
171 OMAP_DSS_AUDIO_ENABLED,
172 OMAP_DSS_AUDIO_CONFIGURED,
173 OMAP_DSS_AUDIO_PLAYING,
174 };
176 enum omap_dss_rotation_type {
177 OMAP_DSS_ROT_DMA = 1 << 0,
178 OMAP_DSS_ROT_VRFB = 1 << 1,
179 OMAP_DSS_ROT_TILER = 1 << 2,
180 };
182 /* clockwise rotation angle */
183 enum omap_dss_rotation_angle {
184 OMAP_DSS_ROT_0 = 0,
185 OMAP_DSS_ROT_90 = 1,
186 OMAP_DSS_ROT_180 = 2,
187 OMAP_DSS_ROT_270 = 3,
188 };
190 enum omap_overlay_caps {
191 OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
192 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1,
193 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2,
194 OMAP_DSS_OVL_CAP_ZORDER = 1 << 3,
195 OMAP_DSS_OVL_CAP_POS = 1 << 4,
196 OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5,
197 };
199 enum omap_overlay_manager_caps {
200 OMAP_DSS_DUMMY_VALUE, /* add a dummy value to prevent compiler error */
201 };
203 enum omap_dss_clk_source {
204 OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK
205 * OMAP4: DSS_FCLK */
206 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK
207 * OMAP4: PLL1_CLK1 */
208 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK
209 * OMAP4: PLL1_CLK2 */
210 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */
211 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */
212 };
214 enum omap_hdmi_flags {
215 OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP = 1 << 0,
216 };
218 enum omap_dss_output_id {
219 OMAP_DSS_OUTPUT_DPI = 1 << 0,
220 OMAP_DSS_OUTPUT_DBI = 1 << 1,
221 OMAP_DSS_OUTPUT_SDI = 1 << 2,
222 OMAP_DSS_OUTPUT_DSI1 = 1 << 3,
223 OMAP_DSS_OUTPUT_DSI2 = 1 << 4,
224 OMAP_DSS_OUTPUT_VENC = 1 << 5,
225 OMAP_DSS_OUTPUT_HDMI = 1 << 6,
226 OMAP_DSS_OUTPUT_DPI1 = 1 << 7,
227 OMAP_DSS_OUTPUT_DPI2 = 1 << 8,
228 };
230 /* Stereoscopic Panel types
231 * row, column, overunder, sidebyside options
232 * are with respect to native scan order
233 */
234 enum s3d_disp_type {
235 S3D_DISP_NONE = 0,
236 S3D_DISP_FRAME_SEQ,
237 S3D_DISP_ROW_IL,
238 S3D_DISP_COL_IL,
239 S3D_DISP_PIX_IL,
240 S3D_DISP_CHECKB,
241 S3D_DISP_OVERUNDER,
242 S3D_DISP_SIDEBYSIDE,
243 };
245 /* Subsampling direction is based on native panel scan order.
246 */
247 enum s3d_disp_sub_sampling {
248 S3D_DISP_SUB_SAMPLE_NONE = 0,
249 S3D_DISP_SUB_SAMPLE_V,
250 S3D_DISP_SUB_SAMPLE_H,
251 };
253 /* Indicates if display expects left view first followed by right or viceversa
254 * For row interlaved displays, defines first row view
255 * For column interleaved displays, defines first column view
256 * For checkerboard, defines first pixel view
257 * For overunder, defines top view
258 * For sidebyside, defines west view
259 */
260 enum s3d_disp_order {
261 S3D_DISP_ORDER_L = 0,
262 S3D_DISP_ORDER_R = 1,
263 };
265 /* S3D information */
266 struct s3d_disp_info {
267 enum s3d_disp_type type;
268 enum s3d_disp_sub_sampling sub_samp;
269 enum s3d_disp_order order;
270 /* Gap between left and right views
271 * For over/under units are lines
272 * For sidebyside units are pixels
273 *For other types ignored*/
274 unsigned int gap;
275 };
277 /* RFBI */
279 struct rfbi_timings {
280 int cs_on_time;
281 int cs_off_time;
282 int we_on_time;
283 int we_off_time;
284 int re_on_time;
285 int re_off_time;
286 int we_cycle_time;
287 int re_cycle_time;
288 int cs_pulse_width;
289 int access_time;
291 int clk_div;
293 u32 tim[5]; /* set by rfbi_convert_timings() */
295 int converted;
296 };
298 void omap_rfbi_write_command(const void *buf, u32 len);
299 void omap_rfbi_read_data(void *buf, u32 len);
300 void omap_rfbi_write_data(const void *buf, u32 len);
301 void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
302 u16 x, u16 y,
303 u16 w, u16 h);
304 int omap_rfbi_enable_te(bool enable, unsigned line);
305 int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
306 unsigned hs_pulse_time, unsigned vs_pulse_time,
307 int hs_pol_inv, int vs_pol_inv, int extif_div);
308 void rfbi_bus_lock(void);
309 void rfbi_bus_unlock(void);
311 /* DSI */
313 struct omap_dss_dsi_videomode_timings {
314 /* DSI video mode blanking data */
315 /* Unit: byte clock cycles */
316 u16 hsa;
317 u16 hfp;
318 u16 hbp;
319 /* Unit: line clocks */
320 u16 vsa;
321 u16 vfp;
322 u16 vbp;
324 /* DSI blanking modes */
325 int blanking_mode;
326 int hsa_blanking_mode;
327 int hbp_blanking_mode;
328 int hfp_blanking_mode;
330 /* Video port sync events */
331 bool vp_vsync_end;
332 bool vp_hsync_end;
334 bool ddr_clk_always_on;
335 int window_sync;
336 };
338 void dsi_bus_lock(struct omap_dss_device *dssdev);
339 void dsi_bus_unlock(struct omap_dss_device *dssdev);
340 int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
341 int len);
342 int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
343 int len);
344 int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd);
345 int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel);
346 int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
347 u8 param);
348 int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel,
349 u8 param);
350 int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel,
351 u8 param1, u8 param2);
352 int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
353 u8 *data, int len);
354 int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
355 u8 *data, int len);
356 int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
357 u8 *buf, int buflen);
358 int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf,
359 int buflen);
360 int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param,
361 u8 *buf, int buflen);
362 int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel,
363 u8 param1, u8 param2, u8 *buf, int buflen);
364 int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
365 u16 len);
366 int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
367 int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel);
368 int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel);
369 void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel);
371 enum omapdss_version {
372 OMAPDSS_VER_UNKNOWN = 0,
373 OMAPDSS_VER_OMAP24xx,
374 OMAPDSS_VER_OMAP34xx_ES1, /* OMAP3430 ES1.0, 2.0 */
375 OMAPDSS_VER_OMAP34xx_ES3, /* OMAP3430 ES3.0+ */
376 OMAPDSS_VER_OMAP3630,
377 OMAPDSS_VER_AM35xx,
378 OMAPDSS_VER_OMAP4430_ES1, /* OMAP4430 ES1.0 */
379 OMAPDSS_VER_OMAP4430_ES2, /* OMAP4430 ES2.0, 2.1, 2.2 */
380 OMAPDSS_VER_OMAP4, /* All other OMAP4s */
381 OMAPDSS_VER_OMAP5,
382 OMAPDSS_VER_DRA7xx,
383 };
385 /* Board specific data */
386 struct omap_dss_board_info {
387 int (*get_context_loss_count)(struct device *dev);
388 int num_devices;
389 struct omap_dss_device **devices;
390 struct omap_dss_device *default_device;
391 int (*dsi_enable_pads)(int dsi_id, unsigned lane_mask);
392 void (*dsi_disable_pads)(int dsi_id, unsigned lane_mask);
393 int (*set_min_bus_tput)(struct device *dev, unsigned long r);
394 enum omapdss_version version;
395 };
397 /* Init with the board info */
398 extern int omap_display_init(struct omap_dss_board_info *board_data);
399 /* HDMI mux init*/
400 extern int omap_hdmi_init(enum omap_hdmi_flags flags);
402 struct omap_video_timings {
403 /* Unit: pixels */
404 u16 x_res;
405 /* Unit: pixels */
406 u16 y_res;
407 /* Unit: KHz */
408 u32 pixel_clock;
409 /* Unit: pixel clocks */
410 u16 hsw; /* Horizontal synchronization pulse width */
411 /* Unit: pixel clocks */
412 u16 hfp; /* Horizontal front porch */
413 /* Unit: pixel clocks */
414 u16 hbp; /* Horizontal back porch */
415 /* Unit: line clocks */
416 u16 vsw; /* Vertical synchronization pulse width */
417 /* Unit: line clocks */
418 u16 vfp; /* Vertical front porch */
419 /* Unit: line clocks */
420 u16 vbp; /* Vertical back porch */
422 /* Vsync logic level */
423 enum omap_dss_signal_level vsync_level;
424 /* Hsync logic level */
425 enum omap_dss_signal_level hsync_level;
426 /* Interlaced or Progressive timings */
427 bool interlace;
428 /* Pixel clock edge to drive LCD data */
429 enum omap_dss_signal_edge data_pclk_edge;
430 /* Data enable logic level */
431 enum omap_dss_signal_level de_level;
432 /* Pixel clock edges to drive HSYNC and VSYNC signals */
433 enum omap_dss_signal_edge sync_pclk_edge;
434 };
436 #ifdef CONFIG_OMAP2_DSS_VENC
437 /* Hardcoded timings for tv modes. Venc only uses these to
438 * identify the mode, and does not actually use the configs
439 * itself. However, the configs should be something that
440 * a normal monitor can also show */
441 extern const struct omap_video_timings omap_dss_pal_timings;
442 extern const struct omap_video_timings omap_dss_ntsc_timings;
443 #endif
445 enum omapdss_completion_status {
446 DSS_COMPLETION_PROGRAMMED = (1 << 1),
447 DSS_COMPLETION_DISPLAYED = (1 << 2),
449 DSS_COMPLETION_CHANGED_SET = (1 << 3),
450 DSS_COMPLETION_CHANGED_CACHE = (1 << 4),
451 DSS_COMPLETION_CHANGED = (3 << 3),
453 DSS_COMPLETION_RELEASED = (15 << 5),
454 DSS_COMPLETION_ECLIPSED_SET = (1 << 5),
455 DSS_COMPLETION_ECLIPSED_CACHE = (1 << 6),
456 DSS_COMPLETION_ECLIPSED_SHADOW = (1 << 7),
457 DSS_COMPLETION_TORN = (1 << 8),
458 };
460 struct omapdss_ovl_cb {
461 /* optional callback method */
462 u32 (*fn)(void *data, int id, int status);
463 void *data;
464 u32 mask;
465 };
467 struct omap_dss_cconv_coefs {
468 s16 ry, rcr, rcb;
469 s16 gy, gcr, gcb;
470 s16 by, bcr, bcb;
471 u16 full_range;
472 } __aligned(4);
474 /* Writeback data structures */
475 enum omap_writeback_source {
476 OMAP_WB_LCD1 = 0,
477 OMAP_WB_TV = 1,
478 OMAP_WB_LCD2 = 2,
479 OMAP_WB_GFX = 3,
480 OMAP_WB_VID1 = 4,
481 OMAP_WB_VID2 = 5,
482 OMAP_WB_VID3 = 6
483 };
485 enum omap_writeback_capturemode {
486 OMAP_WB_CAPTURE_ALL = 0x0,
487 OMAP_WB_CAPTURE_1 = 0x1,
488 OMAP_WB_CAPTURE_1_OF_2 = 0x2,
489 OMAP_WB_CAPTURE_1_OF_3 = 0x3,
490 OMAP_WB_CAPTURE_1_OF_4 = 0x4,
491 OMAP_WB_CAPTURE_1_OF_5 = 0x5,
492 OMAP_WB_CAPTURE_1_OF_6 = 0x6,
493 OMAP_WB_CAPTURE_1_OF_7 = 0x7
494 };
496 enum omap_writeback_mode {
497 OMAP_WB_CAPTURE_MODE = 0x0,
498 OMAP_WB_MEM2MEM_MODE = 0x1,
499 };
501 struct omap_writeback_info {
502 bool enabled;
503 bool info_dirty;
504 enum omap_writeback_source source;
505 u16 width;
506 u16 height;
507 u16 out_width;
508 u16 out_height;
509 enum omap_color_mode dss_mode;
510 enum omap_writeback_capturemode capturemode;
511 /* capture or mem2mem mode */
512 enum omap_writeback_mode mode;
513 u32 paddr;
514 /* NV12 support*/
515 u32 p_uv_addr;
516 u8 rotation;
517 enum omap_dss_rotation_type rotation_type;
518 bool force_1d;
519 };
521 struct omap_writeback {
522 struct kobject kobj;
523 struct list_head list;
524 bool info_dirty;
525 int width;
526 int height;
527 /* mutex to control access to wb data */
528 struct mutex lock;
529 struct omap_writeback_info info;
530 struct completion wb_completion;
532 bool (*check_wb)(struct omap_writeback *wb);
533 int (*set_wb_info)(struct omap_writeback *wb,
534 struct omap_writeback_info *info);
535 void (*get_wb_info)(struct omap_writeback *wb,
536 struct omap_writeback_info *info);
537 int (*register_framedone)(struct omap_writeback *wb);
538 int (*wait_framedone)(struct omap_writeback *wb);
539 };
541 struct omap_dss_cpr_coefs {
542 s16 rr, rg, rb;
543 s16 gr, gg, gb;
544 s16 br, bg, bb;
545 };
547 struct omap_overlay_info {
548 u32 paddr;
549 u32 p_uv_addr; /* for NV12 format */
550 u16 screen_width;
551 u16 width;
552 u16 height;
553 enum omap_color_mode color_mode;
554 u8 rotation;
555 enum omap_dss_rotation_type rotation_type;
556 bool mirror;
558 u16 pos_x;
559 u16 pos_y;
560 u16 out_width; /* if 0, out_width == width */
561 u16 out_height; /* if 0, out_height == height */
562 u8 global_alpha;
563 u8 pre_mult_alpha;
564 u8 wb_source;
565 u8 zorder;
566 u16 min_x_decim, max_x_decim, min_y_decim, max_y_decim;
568 struct omapdss_ovl_cb cb;
569 struct omap_dss_cconv_coefs cconv;
570 bool force_1d;
571 bool mflag_en;
572 };
574 struct omap_overlay {
575 struct kobject kobj;
576 struct list_head list;
578 /* static fields */
579 const char *name;
580 enum omap_plane id;
581 enum omap_color_mode supported_modes;
582 enum omap_overlay_caps caps;
583 bool enabled;
585 /* dynamic fields */
586 struct omap_overlay_manager *manager;
588 /*
589 * The following functions do not block:
590 *
591 * is_enabled
592 * set_overlay_info
593 * get_overlay_info
594 *
595 * The rest of the functions may block and cannot be called from
596 * interrupt context
597 */
599 int (*enable)(struct omap_overlay *ovl);
600 int (*disable)(struct omap_overlay *ovl);
601 bool (*is_enabled)(struct omap_overlay *ovl);
603 int (*set_manager)(struct omap_overlay *ovl,
604 struct omap_overlay_manager *mgr);
605 int (*unset_manager)(struct omap_overlay *ovl);
607 int (*set_overlay_info)(struct omap_overlay *ovl,
608 struct omap_overlay_info *info);
609 void (*get_overlay_info)(struct omap_overlay *ovl,
610 struct omap_overlay_info *info);
612 int (*wait_for_go)(struct omap_overlay *ovl);
614 struct omap_dss_device *(*get_device)(struct omap_overlay *ovl);
615 };
617 struct omap_overlay_manager_info {
618 u32 default_color;
620 enum omap_dss_trans_key_type trans_key_type;
621 u32 trans_key;
622 bool trans_enabled;
624 bool partial_alpha_enabled;
626 bool cpr_enable;
627 struct omap_dss_cpr_coefs cpr_coefs;
629 struct omapdss_ovl_cb cb;
630 };
632 struct omap_overlay_manager {
633 struct kobject kobj;
635 /* static fields */
636 const char *name;
637 enum omap_channel id;
638 enum omap_overlay_manager_caps caps;
639 struct list_head overlays;
640 enum omap_display_type supported_displays;
641 enum omap_dss_output_id supported_outputs;
643 /* dynamic fields */
644 struct omap_dss_output *output;
646 /* Overlays associated with the manager */
647 struct omap_overlay *ovls[5];
649 /* No of overlays for the manager that requires update */
650 u16 num_ovls;
652 /*
653 * The following functions do not block:
654 *
655 * set_manager_info
656 * get_manager_info
657 * apply
658 *
659 * The rest of the functions may block and cannot be called from
660 * interrupt context
661 */
663 int (*set_output)(struct omap_overlay_manager *mgr,
664 struct omap_dss_output *output);
665 int (*unset_output)(struct omap_overlay_manager *mgr);
667 int (*set_manager_info)(struct omap_overlay_manager *mgr,
668 struct omap_overlay_manager_info *info);
669 void (*get_manager_info)(struct omap_overlay_manager *mgr,
670 struct omap_overlay_manager_info *info);
672 int (*apply)(struct omap_overlay_manager *mgr);
673 int (*wait_for_go)(struct omap_overlay_manager *mgr);
674 int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
675 int (*blank)(struct omap_overlay_manager *mgr, bool wait_for_vsync);
676 void (*dump_cb)(struct omap_overlay_manager *mgr, struct seq_file *s);
677 int (*set_ovl)(struct omap_overlay_manager *mgr);
678 int (*wb_apply)(struct omap_overlay_manager *mgr,
679 struct omap_writeback *wb);
681 struct omap_dss_device *(*get_device)(struct omap_overlay_manager *mgr);
682 };
684 /* 22 pins means 1 clk lane and 10 data lanes */
685 #define OMAP_DSS_MAX_DSI_PINS 22
687 struct omap_dsi_pin_config {
688 int num_pins;
689 /*
690 * pin numbers in the following order:
691 * clk+, clk-
692 * data1+, data1-
693 * data2+, data2-
694 * ...
695 */
696 int pins[OMAP_DSS_MAX_DSI_PINS];
697 };
699 struct omap_dss_writeback_info {
700 u32 paddr;
701 u32 p_uv_addr;
702 u16 buf_width;
703 u16 width;
704 u16 height;
705 enum omap_color_mode color_mode;
706 u8 rotation;
707 enum omap_dss_rotation_type rotation_type;
708 bool mirror;
709 u8 pre_mult_alpha;
710 };
712 struct omap_dss_output {
713 struct list_head list;
715 /* display type supported by the output */
716 enum omap_display_type type;
718 /* output instance */
719 enum omap_dss_output_id id;
721 /* output's platform device pointer */
722 struct platform_device *pdev;
724 /* dynamic fields */
725 struct omap_overlay_manager *manager;
727 struct omap_dss_device *device;
728 };
730 struct omap_dss_device {
731 struct device dev;
733 enum omap_display_type type;
735 enum omap_channel channel;
737 bool first_vsync;
739 union {
740 struct {
741 u8 data_lines;
742 } dpi;
744 struct {
745 u8 channel;
746 u8 data_lines;
747 } rfbi;
749 struct {
750 u8 datapairs;
751 } sdi;
753 struct {
754 int module;
756 bool ext_te;
757 u8 ext_te_gpio;
758 } dsi;
760 struct {
761 enum omap_dss_venc_type type;
762 bool invert_polarity;
763 } venc;
764 } phy;
766 struct {
767 struct {
768 struct {
769 u16 lck_div;
770 u16 pck_div;
771 enum omap_dss_clk_source lcd_clk_src;
772 } channel;
774 enum omap_dss_clk_source dispc_fclk_src;
775 } dispc;
777 struct {
778 /* regn is one greater than TRM's REGN value */
779 u16 regn;
780 u16 regm;
781 u16 regm_dispc;
782 u16 regm_dsi;
784 u16 lp_clk_div;
785 enum omap_dss_clk_source dsi_fclk_src;
786 } dsi;
788 struct {
789 /* regn is one greater than TRM's REGN value */
790 u16 regn;
791 u16 regm2;
792 u32 max_pixclk_khz;
793 } hdmi;
794 } clocks;
796 struct {
797 struct omap_video_timings timings;
798 struct fb_monspecs monspecs;
800 enum omap_dss_dsi_pixel_format dsi_pix_fmt;
801 enum omap_dss_dsi_mode dsi_mode;
802 struct omap_dss_dsi_videomode_timings dsi_vm_timings;
803 struct s3d_disp_info s3d_info;
804 u32 width_in_um;
805 u32 height_in_um;
806 u16 fb_xres;
807 u16 fb_yres;
808 } panel;
810 struct {
811 u8 pixel_size;
812 struct rfbi_timings rfbi_timings;
813 } ctrl;
815 int reset_gpio;
817 int max_backlight_level;
819 const char *name;
821 /* used to match device to driver */
822 const char *driver_name;
824 void *data;
826 struct omap_dss_driver *driver;
828 /* helper variable for driver suspend/resume */
829 bool activate_after_resume;
831 enum omap_display_caps caps;
833 struct omap_dss_output *output;
835 enum omap_dss_display_state state;
837 struct blocking_notifier_head state_notifiers;
839 enum omap_dss_audio_state audio_state;
841 /* platform specific */
842 int (*platform_enable)(struct omap_dss_device *dssdev);
843 void (*platform_disable)(struct omap_dss_device *dssdev);
844 int (*set_backlight)(struct omap_dss_device *dssdev, int level);
845 int (*get_backlight)(struct omap_dss_device *dssdev);
846 };
848 struct omap_dss_hdmi_data
849 {
850 int ct_cp_hpd_gpio;
851 int ls_oe_gpio;
852 int hpd_gpio;
853 };
855 struct omap_dss_audio {
856 struct snd_aes_iec958 *iec;
857 struct snd_cea_861_aud_if *cea;
858 };
860 struct omap_dss_driver {
861 struct device_driver driver;
863 int (*probe)(struct omap_dss_device *);
864 void (*remove)(struct omap_dss_device *);
866 int (*enable)(struct omap_dss_device *display);
867 void (*disable)(struct omap_dss_device *display);
868 int (*run_test)(struct omap_dss_device *display, int test);
870 int (*update)(struct omap_dss_device *dssdev,
871 u16 x, u16 y, u16 w, u16 h);
872 int (*sync)(struct omap_dss_device *dssdev);
874 int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
875 int (*get_te)(struct omap_dss_device *dssdev);
877 u8 (*get_rotate)(struct omap_dss_device *dssdev);
878 int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
880 bool (*get_mirror)(struct omap_dss_device *dssdev);
881 int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
883 int (*memory_read)(struct omap_dss_device *dssdev,
884 void *buf, size_t size,
885 u16 x, u16 y, u16 w, u16 h);
887 void (*get_resolution)(struct omap_dss_device *dssdev,
888 u16 *xres, u16 *yres);
889 void (*get_dimensions)(struct omap_dss_device *dssdev,
890 u32 *width, u32 *height);
891 int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
893 int (*check_timings)(struct omap_dss_device *dssdev,
894 struct omap_video_timings *timings);
895 void (*set_timings)(struct omap_dss_device *dssdev,
896 struct omap_video_timings *timings);
897 void (*get_timings)(struct omap_dss_device *dssdev,
898 struct omap_video_timings *timings);
900 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
901 u32 (*get_wss)(struct omap_dss_device *dssdev);
903 int (*get_modedb)(struct omap_dss_device *dssdev,
904 struct fb_videomode *modedb,
905 int modedb_len);
906 int (*set_mode)(struct omap_dss_device *dssdev,
907 struct fb_videomode *mode);
909 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
910 bool (*detect)(struct omap_dss_device *dssdev);
912 /* for wrapping around state changes */
913 void (*disable_orig)(struct omap_dss_device *display);
914 int (*enable_orig)(struct omap_dss_device *display);
916 /*
917 * For display drivers that support audio. This encompasses
918 * HDMI and DisplayPort at the moment.
919 */
920 /*
921 * Note: These functions might sleep. Do not call while
922 * holding a spinlock/readlock.
923 */
924 int (*audio_enable)(struct omap_dss_device *dssdev);
925 void (*audio_disable)(struct omap_dss_device *dssdev);
926 bool (*audio_supported)(struct omap_dss_device *dssdev);
927 int (*audio_config)(struct omap_dss_device *dssdev,
928 struct omap_dss_audio *audio);
929 /* Note: These functions may not sleep */
930 int (*audio_start)(struct omap_dss_device *dssdev);
931 void (*audio_stop)(struct omap_dss_device *dssdev);
933 int (*s3d_enable)(struct omap_dss_device *dssdev,
934 struct s3d_disp_info *info, int code);
935 };
937 enum omapdss_version omapdss_get_version(void);
939 int omap_dss_register_driver(struct omap_dss_driver *);
940 void omap_dss_unregister_driver(struct omap_dss_driver *);
942 void omap_dss_get_device(struct omap_dss_device *dssdev);
943 void omap_dss_put_device(struct omap_dss_device *dssdev);
944 #define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
945 struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
946 struct omap_dss_device *omap_dss_find_device(void *data,
947 int (*match)(struct omap_dss_device *dssdev, void *data));
948 const char *omapdss_get_default_display_name(void);
950 int omap_dss_start_device(struct omap_dss_device *dssdev);
951 void omap_dss_stop_device(struct omap_dss_device *dssdev);
953 int dss_feat_get_num_mgrs(void);
954 int dss_feat_get_num_ovls(void);
955 enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel);
956 enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel);
957 enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane);
961 int omap_dss_get_num_overlay_managers(void);
962 struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
964 int omap_dss_get_num_overlays(void);
965 struct omap_overlay *omap_dss_get_overlay(int num);
967 struct omap_dss_output *omap_dss_get_output(enum omap_dss_output_id id);
968 int omapdss_output_set_device(struct omap_dss_output *out,
969 struct omap_dss_device *dssdev);
970 int omapdss_output_unset_device(struct omap_dss_output *out);
972 void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
973 u16 *xres, u16 *yres);
974 int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
975 void omapdss_default_get_timings(struct omap_dss_device *dssdev,
976 struct omap_video_timings *timings);
978 typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
979 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
980 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
982 u32 dispc_read_irqstatus(void);
983 void dispc_clear_irqstatus(u32 mask);
984 u32 dispc_read_irqenable(void);
985 void dispc_write_irqenable(u32 mask);
987 int dispc_request_irq(irq_handler_t handler, void *dev_id);
988 void dispc_free_irq(void *dev_id);
990 int dispc_runtime_get(void);
991 void dispc_runtime_put(void);
993 void dispc_mgr_enable(enum omap_channel channel, bool enable);
994 bool dispc_mgr_is_enabled(enum omap_channel channel);
995 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel);
996 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel);
997 u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel);
998 bool dispc_mgr_go_busy(enum omap_channel channel);
999 void dispc_mgr_go(enum omap_channel channel);
1000 void dispc_mgr_set_lcd_config(enum omap_channel channel,
1001 const struct dss_lcd_mgr_config *config);
1002 void dispc_mgr_set_timings(enum omap_channel channel,
1003 const struct omap_video_timings *timings);
1004 void dispc_mgr_setup(enum omap_channel channel,
1005 const struct omap_overlay_manager_info *info);
1007 int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
1008 const struct omap_overlay_info *oi,
1009 const struct omap_video_timings *timings,
1010 int *x_predecim, int *y_predecim);
1012 int dispc_ovl_enable(enum omap_plane plane, bool enable);
1013 bool dispc_ovl_enabled(enum omap_plane plane);
1014 void dispc_ovl_set_channel_out(enum omap_plane plane,
1015 enum omap_channel channel);
1016 int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
1017 bool replication, const struct omap_video_timings *mgr_timings,
1018 bool mem_to_mem);
1020 #define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
1021 #define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
1023 void omapdss_display_get_dimensions(struct omap_dss_device *dssdev,
1024 u32 *width_in_um, u32 *height_in_um);
1025 void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
1026 bool enable);
1027 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);
1028 void omapdss_dsi_set_timings(struct omap_dss_device *dssdev,
1029 struct omap_video_timings *timings);
1030 void omapdss_dsi_set_size(struct omap_dss_device *dssdev, u16 w, u16 h);
1031 void omapdss_dsi_set_pixel_format(struct omap_dss_device *dssdev,
1032 enum omap_dss_dsi_pixel_format fmt);
1033 void omapdss_dsi_set_operation_mode(struct omap_dss_device *dssdev,
1034 enum omap_dss_dsi_mode mode);
1035 void omapdss_dsi_set_videomode_timings(struct omap_dss_device *dssdev,
1036 struct omap_dss_dsi_videomode_timings *timings);
1038 int omap_dsi_update(struct omap_dss_device *dssdev, int channel,
1039 void (*callback)(int, void *), void *data);
1040 int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel);
1041 int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id);
1042 void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel);
1043 int omapdss_dsi_configure_pins(struct omap_dss_device *dssdev,
1044 const struct omap_dsi_pin_config *pin_cfg);
1045 int omapdss_dsi_set_clocks(struct omap_dss_device *dssdev,
1046 unsigned long ddr_clk, unsigned long lp_clk);
1048 int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
1049 void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
1050 bool disconnect_lanes, bool enter_ulps);
1052 int omapdss_dpi_display_enable(struct omap_dss_device *dssdev);
1053 void omapdss_dpi_display_disable(struct omap_dss_device *dssdev);
1054 void omapdss_dpi_set_timings(struct omap_dss_device *dssdev,
1055 struct omap_video_timings *timings);
1056 int dpi_check_timings(struct omap_dss_device *dssdev,
1057 struct omap_video_timings *timings);
1058 void omapdss_dpi_set_data_lines(struct omap_dss_device *dssdev, int data_lines);
1060 int omapdss_sdi_display_enable(struct omap_dss_device *dssdev);
1061 void omapdss_sdi_display_disable(struct omap_dss_device *dssdev);
1062 void omapdss_sdi_set_timings(struct omap_dss_device *dssdev,
1063 struct omap_video_timings *timings);
1064 void omapdss_sdi_set_datapairs(struct omap_dss_device *dssdev, int datapairs);
1066 int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev);
1067 void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev);
1068 int omap_rfbi_update(struct omap_dss_device *dssdev, void (*callback)(void *),
1069 void *data);
1070 int omap_rfbi_configure(struct omap_dss_device *dssdev);
1071 void omapdss_rfbi_set_size(struct omap_dss_device *dssdev, u16 w, u16 h);
1072 void omapdss_rfbi_set_pixel_size(struct omap_dss_device *dssdev,
1073 int pixel_size);
1074 void omapdss_rfbi_set_data_lines(struct omap_dss_device *dssdev,
1075 int data_lines);
1076 void omapdss_rfbi_set_interface_timings(struct omap_dss_device *dssdev,
1077 struct rfbi_timings *timings);
1079 int dispc_scaling_decision(enum omap_plane plane, struct omap_overlay_info *oi,
1080 enum omap_channel channel,
1081 u16 *x_decim, u16 *y_decim, bool *three_tap);
1082 int omap_dss_manager_unregister_callback(struct omap_overlay_manager *mgr,
1083 struct omapdss_ovl_cb *cb);
1085 /* generic callback handling */
1086 static inline void dss_ovl_cb(struct omapdss_ovl_cb *cb, int id, int status)
1087 {
1088 if (cb->fn && (cb->mask & status))
1089 cb->mask &= cb->fn(cb->data, id, status);
1090 if (status & DSS_COMPLETION_RELEASED)
1091 cb->mask = 0;
1092 if (!cb->mask)
1093 cb->fn = NULL;
1094 }
1096 int omapdss_compat_init(void);
1097 void omapdss_compat_uninit(void);
1099 struct dss_mgr_ops {
1100 void (*start_update)(struct omap_overlay_manager *mgr);
1101 int (*enable)(struct omap_overlay_manager *mgr);
1102 void (*disable)(struct omap_overlay_manager *mgr);
1103 void (*set_timings)(struct omap_overlay_manager *mgr,
1104 const struct omap_video_timings *timings);
1105 void (*set_lcd_config)(struct omap_overlay_manager *mgr,
1106 const struct dss_lcd_mgr_config *config);
1107 int (*register_framedone_handler)(struct omap_overlay_manager *mgr,
1108 void (*handler)(void *), void *data);
1109 void (*unregister_framedone_handler)(struct omap_overlay_manager *mgr,
1110 void (*handler)(void *), void *data);
1111 };
1113 int dss_install_mgr_ops(const struct dss_mgr_ops *mgr_ops);
1114 void dss_uninstall_mgr_ops(void);
1116 void dss_mgr_set_timings(struct omap_overlay_manager *mgr,
1117 const struct omap_video_timings *timings);
1118 void dss_mgr_set_lcd_config(struct omap_overlay_manager *mgr,
1119 const struct dss_lcd_mgr_config *config);
1120 int dss_mgr_enable(struct omap_overlay_manager *mgr);
1121 void dss_mgr_disable(struct omap_overlay_manager *mgr);
1122 void dss_mgr_start_update(struct omap_overlay_manager *mgr);
1123 int dss_mgr_register_framedone_handler(struct omap_overlay_manager *mgr,
1124 void (*handler)(void *), void *data);
1125 void dss_mgr_unregister_framedone_handler(struct omap_overlay_manager *mgr,
1126 void (*handler)(void *), void *data);
1127 #endif