1 /*
2 * Copyright (C) 2008 Nokia Corporation
3 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
18 #ifndef __OMAP_OMAPDSS_H
19 #define __OMAP_OMAPDSS_H
21 #include <linux/list.h>
22 #include <linux/kobject.h>
23 #include <linux/device.h>
24 #include <linux/interrupt.h>
26 #include <video/videomode.h>
28 #define DISPC_IRQ_FRAMEDONE (1 << 0)
29 #define DISPC_IRQ_VSYNC (1 << 1)
30 #define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
31 #define DISPC_IRQ_EVSYNC_ODD (1 << 3)
32 #define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
33 #define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
34 #define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
35 #define DISPC_IRQ_GFX_END_WIN (1 << 7)
36 #define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
37 #define DISPC_IRQ_OCP_ERR (1 << 9)
38 #define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
39 #define DISPC_IRQ_VID1_END_WIN (1 << 11)
40 #define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
41 #define DISPC_IRQ_VID2_END_WIN (1 << 13)
42 #define DISPC_IRQ_SYNC_LOST (1 << 14)
43 #define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
44 #define DISPC_IRQ_WAKEUP (1 << 16)
45 #define DISPC_IRQ_SYNC_LOST2 (1 << 17)
46 #define DISPC_IRQ_VSYNC2 (1 << 18)
47 #define DISPC_IRQ_VID3_END_WIN (1 << 19)
48 #define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20)
49 #define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
50 #define DISPC_IRQ_FRAMEDONE2 (1 << 22)
51 #define DISPC_IRQ_FRAMEDONEWB (1 << 23)
52 #define DISPC_IRQ_FRAMEDONETV (1 << 24)
53 #define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25)
54 #define DISPC_IRQ_SYNC_LOST3 (1 << 27)
55 #define DISPC_IRQ_VSYNC3 (1 << 28)
56 #define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 29)
57 #define DISPC_IRQ_FRAMEDONE3 (1 << 30)
59 struct omap_dss_device;
60 struct omap_overlay_manager;
61 struct dss_lcd_mgr_config;
62 struct snd_aes_iec958;
63 struct snd_cea_861_aud_if;
64 struct hdmi_avi_infoframe;
66 enum omap_display_type {
67 OMAP_DISPLAY_TYPE_NONE = 0,
68 OMAP_DISPLAY_TYPE_DPI = 1 << 0,
69 OMAP_DISPLAY_TYPE_DBI = 1 << 1,
70 OMAP_DISPLAY_TYPE_SDI = 1 << 2,
71 OMAP_DISPLAY_TYPE_DSI = 1 << 3,
72 OMAP_DISPLAY_TYPE_VENC = 1 << 4,
73 OMAP_DISPLAY_TYPE_HDMI = 1 << 5,
74 OMAP_DISPLAY_TYPE_DVI = 1 << 6,
75 };
77 enum omap_plane {
78 OMAP_DSS_GFX = 0,
79 OMAP_DSS_VIDEO1 = 1,
80 OMAP_DSS_VIDEO2 = 2,
81 OMAP_DSS_VIDEO3 = 3,
82 OMAP_DSS_WB = 4,
83 };
85 enum omap_channel {
86 OMAP_DSS_CHANNEL_LCD = 0,
87 OMAP_DSS_CHANNEL_DIGIT = 1,
88 OMAP_DSS_CHANNEL_LCD2 = 2,
89 OMAP_DSS_CHANNEL_LCD3 = 3,
90 };
92 enum omap_color_mode {
93 OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
94 OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
95 OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
96 OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
97 OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
98 OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
99 OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
100 OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
101 OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
102 OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
103 OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
104 OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
105 OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
106 OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
107 OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */
108 OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */
109 OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */
110 OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */
111 OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */
112 };
114 enum omap_dss_load_mode {
115 OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
116 OMAP_DSS_LOAD_CLUT_ONLY = 1,
117 OMAP_DSS_LOAD_FRAME_ONLY = 2,
118 OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
119 };
121 enum omap_dss_trans_key_type {
122 OMAP_DSS_COLOR_KEY_GFX_DST = 0,
123 OMAP_DSS_COLOR_KEY_VID_SRC = 1,
124 };
126 enum omap_rfbi_te_mode {
127 OMAP_DSS_RFBI_TE_MODE_1 = 1,
128 OMAP_DSS_RFBI_TE_MODE_2 = 2,
129 };
131 enum omap_dss_signal_level {
132 OMAPDSS_SIG_ACTIVE_LOW,
133 OMAPDSS_SIG_ACTIVE_HIGH,
134 };
136 enum omap_dss_signal_edge {
137 OMAPDSS_DRIVE_SIG_FALLING_EDGE,
138 OMAPDSS_DRIVE_SIG_RISING_EDGE,
139 };
141 enum omap_dss_venc_type {
142 OMAP_DSS_VENC_TYPE_COMPOSITE,
143 OMAP_DSS_VENC_TYPE_SVIDEO,
144 };
146 enum omap_dss_dsi_pixel_format {
147 OMAP_DSS_DSI_FMT_RGB888,
148 OMAP_DSS_DSI_FMT_RGB666,
149 OMAP_DSS_DSI_FMT_RGB666_PACKED,
150 OMAP_DSS_DSI_FMT_RGB565,
151 };
153 enum omap_dss_dsi_mode {
154 OMAP_DSS_DSI_CMD_MODE = 0,
155 OMAP_DSS_DSI_VIDEO_MODE,
156 };
158 enum omap_display_caps {
159 OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
160 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
161 };
163 enum omap_dss_display_state {
164 OMAP_DSS_DISPLAY_DISABLED = 0,
165 OMAP_DSS_DISPLAY_ACTIVE,
166 };
168 enum omap_dss_audio_state {
169 OMAP_DSS_AUDIO_DISABLED = 0,
170 OMAP_DSS_AUDIO_ENABLED,
171 OMAP_DSS_AUDIO_CONFIGURED,
172 OMAP_DSS_AUDIO_PLAYING,
173 };
175 struct omap_dss_audio {
176 struct snd_aes_iec958 *iec;
177 struct snd_cea_861_aud_if *cea;
178 };
180 enum omap_dss_rotation_type {
181 OMAP_DSS_ROT_DMA = 1 << 0,
182 OMAP_DSS_ROT_VRFB = 1 << 1,
183 OMAP_DSS_ROT_TILER = 1 << 2,
184 };
186 /* clockwise rotation angle */
187 enum omap_dss_rotation_angle {
188 OMAP_DSS_ROT_0 = 0,
189 OMAP_DSS_ROT_90 = 1,
190 OMAP_DSS_ROT_180 = 2,
191 OMAP_DSS_ROT_270 = 3,
192 };
194 enum omap_overlay_caps {
195 OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
196 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1,
197 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2,
198 OMAP_DSS_OVL_CAP_ZORDER = 1 << 3,
199 OMAP_DSS_OVL_CAP_POS = 1 << 4,
200 OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5,
201 };
203 enum omap_overlay_manager_caps {
204 OMAP_DSS_DUMMY_VALUE, /* add a dummy value to prevent compiler error */
205 };
207 enum omap_dss_clk_source {
208 OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK
209 * OMAP4: DSS_FCLK */
210 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK
211 * OMAP4: PLL1_CLK1 */
212 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK
213 * OMAP4: PLL1_CLK2 */
214 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */
215 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */
216 };
218 enum omap_hdmi_flags {
219 OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP = 1 << 0,
220 };
222 enum omap_dss_output_id {
223 OMAP_DSS_OUTPUT_DPI = 1 << 0,
224 OMAP_DSS_OUTPUT_DBI = 1 << 1,
225 OMAP_DSS_OUTPUT_SDI = 1 << 2,
226 OMAP_DSS_OUTPUT_DSI1 = 1 << 3,
227 OMAP_DSS_OUTPUT_DSI2 = 1 << 4,
228 OMAP_DSS_OUTPUT_VENC = 1 << 5,
229 OMAP_DSS_OUTPUT_HDMI = 1 << 6,
230 };
232 /* RFBI */
234 struct rfbi_timings {
235 int cs_on_time;
236 int cs_off_time;
237 int we_on_time;
238 int we_off_time;
239 int re_on_time;
240 int re_off_time;
241 int we_cycle_time;
242 int re_cycle_time;
243 int cs_pulse_width;
244 int access_time;
246 int clk_div;
248 u32 tim[5]; /* set by rfbi_convert_timings() */
250 int converted;
251 };
253 /* DSI */
255 enum omap_dss_dsi_trans_mode {
256 /* Sync Pulses: both sync start and end packets sent */
257 OMAP_DSS_DSI_PULSE_MODE,
258 /* Sync Events: only sync start packets sent */
259 OMAP_DSS_DSI_EVENT_MODE,
260 /* Burst: only sync start packets sent, pixels are time compressed */
261 OMAP_DSS_DSI_BURST_MODE,
262 };
264 struct omap_dss_dsi_videomode_timings {
265 unsigned long hsclk;
267 unsigned ndl;
268 unsigned bitspp;
270 /* pixels */
271 u16 hact;
272 /* lines */
273 u16 vact;
275 /* DSI video mode blanking data */
276 /* Unit: byte clock cycles */
277 u16 hss;
278 u16 hsa;
279 u16 hse;
280 u16 hfp;
281 u16 hbp;
282 /* Unit: line clocks */
283 u16 vsa;
284 u16 vfp;
285 u16 vbp;
287 /* DSI blanking modes */
288 int blanking_mode;
289 int hsa_blanking_mode;
290 int hbp_blanking_mode;
291 int hfp_blanking_mode;
293 enum omap_dss_dsi_trans_mode trans_mode;
295 bool ddr_clk_always_on;
296 int window_sync;
297 };
299 struct omap_dss_dsi_config {
300 enum omap_dss_dsi_mode mode;
301 enum omap_dss_dsi_pixel_format pixel_format;
302 const struct omap_video_timings *timings;
304 unsigned long hs_clk_min, hs_clk_max;
305 unsigned long lp_clk_min, lp_clk_max;
307 bool ddr_clk_always_on;
308 enum omap_dss_dsi_trans_mode trans_mode;
309 };
311 enum omapdss_version {
312 OMAPDSS_VER_UNKNOWN = 0,
313 OMAPDSS_VER_OMAP24xx,
314 OMAPDSS_VER_OMAP34xx_ES1, /* OMAP3430 ES1.0, 2.0 */
315 OMAPDSS_VER_OMAP34xx_ES3, /* OMAP3430 ES3.0+ */
316 OMAPDSS_VER_OMAP3630,
317 OMAPDSS_VER_AM35xx,
318 OMAPDSS_VER_OMAP4430_ES1, /* OMAP4430 ES1.0 */
319 OMAPDSS_VER_OMAP4430_ES2, /* OMAP4430 ES2.0, 2.1, 2.2 */
320 OMAPDSS_VER_OMAP4, /* All other OMAP4s */
321 OMAPDSS_VER_OMAP5,
322 OMAPDSS_VER_AM43xx,
323 OMAPDSS_VER_DRA74xx,
324 OMAPDSS_VER_DRA72xx,
325 };
327 /* Board specific data */
328 struct omap_dss_board_info {
329 int num_devices;
330 struct omap_dss_device **devices;
331 struct omap_dss_device *default_device;
332 const char *default_display_name;
333 int (*dsi_enable_pads)(int dsi_id, unsigned lane_mask);
334 void (*dsi_disable_pads)(int dsi_id, unsigned lane_mask);
335 int (*set_min_bus_tput)(struct device *dev, unsigned long r);
336 enum omapdss_version version;
337 };
339 /* Init with the board info */
340 extern int omap_display_init(struct omap_dss_board_info *board_data);
341 /* HDMI mux init*/
342 extern int omap_hdmi_init(enum omap_hdmi_flags flags);
344 struct omap_video_timings {
345 /* Unit: pixels */
346 u16 x_res;
347 /* Unit: pixels */
348 u16 y_res;
349 /* Unit: Hz */
350 u32 pixelclock;
351 /* Unit: pixel clocks */
352 u16 hsw; /* Horizontal synchronization pulse width */
353 /* Unit: pixel clocks */
354 u16 hfp; /* Horizontal front porch */
355 /* Unit: pixel clocks */
356 u16 hbp; /* Horizontal back porch */
357 /* Unit: line clocks */
358 u16 vsw; /* Vertical synchronization pulse width */
359 /* Unit: line clocks */
360 u16 vfp; /* Vertical front porch */
361 /* Unit: line clocks */
362 u16 vbp; /* Vertical back porch */
364 /* Vsync logic level */
365 enum omap_dss_signal_level vsync_level;
366 /* Hsync logic level */
367 enum omap_dss_signal_level hsync_level;
368 /* Interlaced or Progressive timings */
369 bool interlace;
370 /* Pixel clock edge to drive LCD data */
371 enum omap_dss_signal_edge data_pclk_edge;
372 /* Data enable logic level */
373 enum omap_dss_signal_level de_level;
374 /* Pixel clock edges to drive HSYNC and VSYNC signals */
375 enum omap_dss_signal_edge sync_pclk_edge;
376 };
378 #ifdef CONFIG_OMAP2_DSS_VENC
379 /* Hardcoded timings for tv modes. Venc only uses these to
380 * identify the mode, and does not actually use the configs
381 * itself. However, the configs should be something that
382 * a normal monitor can also show */
383 extern const struct omap_video_timings omap_dss_pal_timings;
384 extern const struct omap_video_timings omap_dss_ntsc_timings;
385 #endif
387 struct omap_dss_cpr_coefs {
388 s16 rr, rg, rb;
389 s16 gr, gg, gb;
390 s16 br, bg, bb;
391 };
393 struct omap_overlay_info {
394 dma_addr_t paddr;
395 dma_addr_t p_uv_addr; /* for NV12 format */
396 u16 screen_width;
397 u16 width;
398 u16 height;
399 enum omap_color_mode color_mode;
400 u8 rotation;
401 enum omap_dss_rotation_type rotation_type;
402 bool mirror;
404 u16 pos_x;
405 u16 pos_y;
406 u16 out_width; /* if 0, out_width == width */
407 u16 out_height; /* if 0, out_height == height */
408 u8 global_alpha;
409 u8 pre_mult_alpha;
410 u8 zorder;
411 };
413 struct omap_overlay {
414 struct kobject kobj;
415 struct list_head list;
417 /* static fields */
418 const char *name;
419 enum omap_plane id;
420 enum omap_color_mode supported_modes;
421 enum omap_overlay_caps caps;
423 /* dynamic fields */
424 struct omap_overlay_manager *manager;
426 /*
427 * The following functions do not block:
428 *
429 * is_enabled
430 * set_overlay_info
431 * get_overlay_info
432 *
433 * The rest of the functions may block and cannot be called from
434 * interrupt context
435 */
437 int (*enable)(struct omap_overlay *ovl);
438 int (*disable)(struct omap_overlay *ovl);
439 bool (*is_enabled)(struct omap_overlay *ovl);
441 int (*set_manager)(struct omap_overlay *ovl,
442 struct omap_overlay_manager *mgr);
443 int (*unset_manager)(struct omap_overlay *ovl);
445 int (*set_overlay_info)(struct omap_overlay *ovl,
446 struct omap_overlay_info *info);
447 void (*get_overlay_info)(struct omap_overlay *ovl,
448 struct omap_overlay_info *info);
450 int (*wait_for_go)(struct omap_overlay *ovl);
452 struct omap_dss_device *(*get_device)(struct omap_overlay *ovl);
453 };
455 struct omap_overlay_manager_info {
456 u32 default_color;
458 enum omap_dss_trans_key_type trans_key_type;
459 u32 trans_key;
460 bool trans_enabled;
462 bool partial_alpha_enabled;
464 bool cpr_enable;
465 struct omap_dss_cpr_coefs cpr_coefs;
466 };
468 struct omap_overlay_manager {
469 struct kobject kobj;
471 /* static fields */
472 const char *name;
473 enum omap_channel id;
474 enum omap_overlay_manager_caps caps;
475 struct list_head overlays;
476 enum omap_display_type supported_displays;
477 enum omap_dss_output_id supported_outputs;
479 /* dynamic fields */
480 struct omap_dss_device *output;
482 /*
483 * The following functions do not block:
484 *
485 * set_manager_info
486 * get_manager_info
487 * apply
488 *
489 * The rest of the functions may block and cannot be called from
490 * interrupt context
491 */
493 int (*set_output)(struct omap_overlay_manager *mgr,
494 struct omap_dss_device *output);
495 int (*unset_output)(struct omap_overlay_manager *mgr);
497 int (*set_manager_info)(struct omap_overlay_manager *mgr,
498 struct omap_overlay_manager_info *info);
499 void (*get_manager_info)(struct omap_overlay_manager *mgr,
500 struct omap_overlay_manager_info *info);
502 int (*apply)(struct omap_overlay_manager *mgr);
503 int (*wait_for_go)(struct omap_overlay_manager *mgr);
504 int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
506 struct omap_dss_device *(*get_device)(struct omap_overlay_manager *mgr);
507 };
509 /* 22 pins means 1 clk lane and 10 data lanes */
510 #define OMAP_DSS_MAX_DSI_PINS 22
512 struct omap_dsi_pin_config {
513 int num_pins;
514 /*
515 * pin numbers in the following order:
516 * clk+, clk-
517 * data1+, data1-
518 * data2+, data2-
519 * ...
520 */
521 int pins[OMAP_DSS_MAX_DSI_PINS];
522 };
524 struct omap_dss_writeback_info {
525 u32 paddr;
526 u32 p_uv_addr;
527 u16 buf_width;
528 u16 width;
529 u16 height;
530 enum omap_color_mode color_mode;
531 u8 rotation;
532 enum omap_dss_rotation_type rotation_type;
533 bool mirror;
534 u8 pre_mult_alpha;
535 };
537 struct omapdss_dpi_ops {
538 int (*connect)(struct omap_dss_device *dssdev,
539 struct omap_dss_device *dst);
540 void (*disconnect)(struct omap_dss_device *dssdev,
541 struct omap_dss_device *dst);
543 int (*enable)(struct omap_dss_device *dssdev);
544 void (*disable)(struct omap_dss_device *dssdev);
546 int (*check_timings)(struct omap_dss_device *dssdev,
547 struct omap_video_timings *timings);
548 void (*set_timings)(struct omap_dss_device *dssdev,
549 struct omap_video_timings *timings);
550 void (*get_timings)(struct omap_dss_device *dssdev,
551 struct omap_video_timings *timings);
553 void (*set_data_lines)(struct omap_dss_device *dssdev, int data_lines);
554 };
556 struct omapdss_sdi_ops {
557 int (*connect)(struct omap_dss_device *dssdev,
558 struct omap_dss_device *dst);
559 void (*disconnect)(struct omap_dss_device *dssdev,
560 struct omap_dss_device *dst);
562 int (*enable)(struct omap_dss_device *dssdev);
563 void (*disable)(struct omap_dss_device *dssdev);
565 int (*check_timings)(struct omap_dss_device *dssdev,
566 struct omap_video_timings *timings);
567 void (*set_timings)(struct omap_dss_device *dssdev,
568 struct omap_video_timings *timings);
569 void (*get_timings)(struct omap_dss_device *dssdev,
570 struct omap_video_timings *timings);
572 void (*set_datapairs)(struct omap_dss_device *dssdev, int datapairs);
573 };
575 struct omapdss_dvi_ops {
576 int (*connect)(struct omap_dss_device *dssdev,
577 struct omap_dss_device *dst);
578 void (*disconnect)(struct omap_dss_device *dssdev,
579 struct omap_dss_device *dst);
581 int (*enable)(struct omap_dss_device *dssdev);
582 void (*disable)(struct omap_dss_device *dssdev);
584 int (*check_timings)(struct omap_dss_device *dssdev,
585 struct omap_video_timings *timings);
586 void (*set_timings)(struct omap_dss_device *dssdev,
587 struct omap_video_timings *timings);
588 void (*get_timings)(struct omap_dss_device *dssdev,
589 struct omap_video_timings *timings);
590 };
592 struct omapdss_atv_ops {
593 int (*connect)(struct omap_dss_device *dssdev,
594 struct omap_dss_device *dst);
595 void (*disconnect)(struct omap_dss_device *dssdev,
596 struct omap_dss_device *dst);
598 int (*enable)(struct omap_dss_device *dssdev);
599 void (*disable)(struct omap_dss_device *dssdev);
601 int (*check_timings)(struct omap_dss_device *dssdev,
602 struct omap_video_timings *timings);
603 void (*set_timings)(struct omap_dss_device *dssdev,
604 struct omap_video_timings *timings);
605 void (*get_timings)(struct omap_dss_device *dssdev,
606 struct omap_video_timings *timings);
608 void (*set_type)(struct omap_dss_device *dssdev,
609 enum omap_dss_venc_type type);
610 void (*invert_vid_out_polarity)(struct omap_dss_device *dssdev,
611 bool invert_polarity);
613 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
614 u32 (*get_wss)(struct omap_dss_device *dssdev);
615 };
617 struct omapdss_hdmi_ops {
618 int (*connect)(struct omap_dss_device *dssdev,
619 struct omap_dss_device *dst);
620 void (*disconnect)(struct omap_dss_device *dssdev,
621 struct omap_dss_device *dst);
623 int (*enable)(struct omap_dss_device *dssdev);
624 void (*disable)(struct omap_dss_device *dssdev);
626 int (*check_timings)(struct omap_dss_device *dssdev,
627 struct omap_video_timings *timings);
628 void (*set_timings)(struct omap_dss_device *dssdev,
629 struct omap_video_timings *timings);
630 void (*get_timings)(struct omap_dss_device *dssdev,
631 struct omap_video_timings *timings);
633 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
634 bool (*detect)(struct omap_dss_device *dssdev);
636 int (*set_hdmi_mode)(struct omap_dss_device *dssdev, bool hdmi_mode);
637 int (*set_infoframe)(struct omap_dss_device *dssdev,
638 const struct hdmi_avi_infoframe *avi);
639 };
641 struct omapdss_dsi_ops {
642 int (*connect)(struct omap_dss_device *dssdev,
643 struct omap_dss_device *dst);
644 void (*disconnect)(struct omap_dss_device *dssdev,
645 struct omap_dss_device *dst);
647 int (*enable)(struct omap_dss_device *dssdev);
648 void (*disable)(struct omap_dss_device *dssdev, bool disconnect_lanes,
649 bool enter_ulps);
651 /* bus configuration */
652 int (*set_config)(struct omap_dss_device *dssdev,
653 const struct omap_dss_dsi_config *cfg);
654 int (*configure_pins)(struct omap_dss_device *dssdev,
655 const struct omap_dsi_pin_config *pin_cfg);
657 void (*enable_hs)(struct omap_dss_device *dssdev, int channel,
658 bool enable);
659 int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
661 int (*update)(struct omap_dss_device *dssdev, int channel,
662 void (*callback)(int, void *), void *data);
664 void (*bus_lock)(struct omap_dss_device *dssdev);
665 void (*bus_unlock)(struct omap_dss_device *dssdev);
667 int (*enable_video_output)(struct omap_dss_device *dssdev, int channel);
668 void (*disable_video_output)(struct omap_dss_device *dssdev,
669 int channel);
671 int (*request_vc)(struct omap_dss_device *dssdev, int *channel);
672 int (*set_vc_id)(struct omap_dss_device *dssdev, int channel,
673 int vc_id);
674 void (*release_vc)(struct omap_dss_device *dssdev, int channel);
676 /* data transfer */
677 int (*dcs_write)(struct omap_dss_device *dssdev, int channel,
678 u8 *data, int len);
679 int (*dcs_write_nosync)(struct omap_dss_device *dssdev, int channel,
680 u8 *data, int len);
681 int (*dcs_read)(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
682 u8 *data, int len);
684 int (*gen_write)(struct omap_dss_device *dssdev, int channel,
685 u8 *data, int len);
686 int (*gen_write_nosync)(struct omap_dss_device *dssdev, int channel,
687 u8 *data, int len);
688 int (*gen_read)(struct omap_dss_device *dssdev, int channel,
689 u8 *reqdata, int reqlen,
690 u8 *data, int len);
692 int (*bta_sync)(struct omap_dss_device *dssdev, int channel);
694 int (*set_max_rx_packet_size)(struct omap_dss_device *dssdev,
695 int channel, u16 plen);
696 };
698 struct omap_dss_device {
699 struct device *dev;
701 struct module *owner;
703 struct list_head panel_list;
705 /* alias in the form of "display%d" */
706 char alias[16];
708 enum omap_display_type type;
709 enum omap_display_type output_type;
711 union {
712 struct {
713 u8 data_lines;
714 } dpi;
716 struct {
717 u8 channel;
718 u8 data_lines;
719 } rfbi;
721 struct {
722 u8 datapairs;
723 } sdi;
725 struct {
726 int module;
727 } dsi;
729 struct {
730 enum omap_dss_venc_type type;
731 bool invert_polarity;
732 } venc;
733 } phy;
735 struct {
736 struct omap_video_timings timings;
738 enum omap_dss_dsi_pixel_format dsi_pix_fmt;
739 enum omap_dss_dsi_mode dsi_mode;
740 } panel;
742 struct {
743 u8 pixel_size;
744 struct rfbi_timings rfbi_timings;
745 } ctrl;
747 const char *name;
749 /* used to match device to driver */
750 const char *driver_name;
752 void *data;
754 struct omap_dss_driver *driver;
756 union {
757 const struct omapdss_dpi_ops *dpi;
758 const struct omapdss_sdi_ops *sdi;
759 const struct omapdss_dvi_ops *dvi;
760 const struct omapdss_hdmi_ops *hdmi;
761 const struct omapdss_atv_ops *atv;
762 const struct omapdss_dsi_ops *dsi;
763 } ops;
765 /* helper variable for driver suspend/resume */
766 bool activate_after_resume;
768 enum omap_display_caps caps;
770 struct omap_dss_device *src;
772 enum omap_dss_display_state state;
774 enum omap_dss_audio_state audio_state;
776 /* OMAP DSS output specific fields */
778 struct list_head list;
780 /* DISPC channel for this output */
781 enum omap_channel dispc_channel;
783 /* output instance */
784 enum omap_dss_output_id id;
786 /* the port number in the DT node */
787 int port_num;
789 /* dynamic fields */
790 struct omap_overlay_manager *manager;
792 struct omap_dss_device *dst;
793 };
795 struct omap_dss_hdmi_data
796 {
797 int ct_cp_hpd_gpio;
798 int ls_oe_gpio;
799 int hpd_gpio;
800 };
802 struct omap_dss_driver {
803 int (*probe)(struct omap_dss_device *);
804 void (*remove)(struct omap_dss_device *);
806 int (*connect)(struct omap_dss_device *dssdev);
807 void (*disconnect)(struct omap_dss_device *dssdev);
809 int (*enable)(struct omap_dss_device *display);
810 void (*disable)(struct omap_dss_device *display);
811 int (*run_test)(struct omap_dss_device *display, int test);
813 int (*update)(struct omap_dss_device *dssdev,
814 u16 x, u16 y, u16 w, u16 h);
815 int (*sync)(struct omap_dss_device *dssdev);
817 int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
818 int (*get_te)(struct omap_dss_device *dssdev);
820 u8 (*get_rotate)(struct omap_dss_device *dssdev);
821 int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
823 bool (*get_mirror)(struct omap_dss_device *dssdev);
824 int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
826 int (*memory_read)(struct omap_dss_device *dssdev,
827 void *buf, size_t size,
828 u16 x, u16 y, u16 w, u16 h);
830 void (*get_resolution)(struct omap_dss_device *dssdev,
831 u16 *xres, u16 *yres);
832 void (*get_dimensions)(struct omap_dss_device *dssdev,
833 u32 *width, u32 *height);
834 int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
836 int (*check_timings)(struct omap_dss_device *dssdev,
837 struct omap_video_timings *timings);
838 void (*set_timings)(struct omap_dss_device *dssdev,
839 struct omap_video_timings *timings);
840 void (*get_timings)(struct omap_dss_device *dssdev,
841 struct omap_video_timings *timings);
843 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
844 u32 (*get_wss)(struct omap_dss_device *dssdev);
846 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
847 bool (*detect)(struct omap_dss_device *dssdev);
849 int (*set_hdmi_mode)(struct omap_dss_device *dssdev, bool hdmi_mode);
850 int (*set_hdmi_infoframe)(struct omap_dss_device *dssdev,
851 const struct hdmi_avi_infoframe *avi);
852 };
854 enum omapdss_version omapdss_get_version(void);
855 bool omapdss_is_initialized(void);
857 int omap_dss_register_driver(struct omap_dss_driver *);
858 void omap_dss_unregister_driver(struct omap_dss_driver *);
860 int omapdss_register_display(struct omap_dss_device *dssdev);
861 void omapdss_unregister_display(struct omap_dss_device *dssdev);
863 struct omap_dss_device *omap_dss_get_device(struct omap_dss_device *dssdev);
864 void omap_dss_put_device(struct omap_dss_device *dssdev);
865 #define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
866 struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
867 struct omap_dss_device *omap_dss_find_device(void *data,
868 int (*match)(struct omap_dss_device *dssdev, void *data));
869 const char *omapdss_get_default_display_name(void);
871 void videomode_to_omap_video_timings(const struct videomode *vm,
872 struct omap_video_timings *ovt);
873 void omap_video_timings_to_videomode(const struct omap_video_timings *ovt,
874 struct videomode *vm);
876 int dss_feat_get_num_mgrs(void);
877 int dss_feat_get_num_ovls(void);
878 enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel);
879 enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel);
880 enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane);
884 int omap_dss_get_num_overlay_managers(void);
885 struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
887 int omap_dss_get_num_overlays(void);
888 struct omap_overlay *omap_dss_get_overlay(int num);
890 int omapdss_register_output(struct omap_dss_device *output);
891 void omapdss_unregister_output(struct omap_dss_device *output);
892 struct omap_dss_device *omap_dss_get_output(enum omap_dss_output_id id);
893 struct omap_dss_device *omap_dss_find_output(const char *name);
894 struct omap_dss_device *omap_dss_find_output_by_port_node(struct device_node *port);
895 int omapdss_output_set_device(struct omap_dss_device *out,
896 struct omap_dss_device *dssdev);
897 int omapdss_output_unset_device(struct omap_dss_device *out);
899 struct omap_dss_device *omapdss_find_output_from_display(struct omap_dss_device *dssdev);
900 struct omap_overlay_manager *omapdss_find_mgr_from_display(struct omap_dss_device *dssdev);
902 void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
903 u16 *xres, u16 *yres);
904 int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
905 void omapdss_default_get_timings(struct omap_dss_device *dssdev,
906 struct omap_video_timings *timings);
908 typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
909 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
910 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
912 u32 dispc_read_irqstatus(void);
913 void dispc_clear_irqstatus(u32 mask);
914 u32 dispc_read_irqenable(void);
915 void dispc_write_irqenable(u32 mask);
917 int dispc_request_irq(irq_handler_t handler, void *dev_id);
918 void dispc_free_irq(void *dev_id);
920 int dispc_runtime_get(void);
921 void dispc_runtime_put(void);
923 void dispc_mgr_enable(enum omap_channel channel, bool enable);
924 bool dispc_mgr_is_enabled(enum omap_channel channel);
925 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel);
926 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel);
927 u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel);
928 bool dispc_mgr_go_busy(enum omap_channel channel);
929 void dispc_mgr_go(enum omap_channel channel);
930 void dispc_mgr_set_lcd_config(enum omap_channel channel,
931 const struct dss_lcd_mgr_config *config);
932 void dispc_mgr_set_timings(enum omap_channel channel,
933 const struct omap_video_timings *timings);
934 void dispc_mgr_setup(enum omap_channel channel,
935 const struct omap_overlay_manager_info *info);
937 int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
938 const struct omap_overlay_info *oi,
939 const struct omap_video_timings *timings,
940 int *x_predecim, int *y_predecim);
942 int dispc_ovl_enable(enum omap_plane plane, bool enable);
943 bool dispc_ovl_enabled(enum omap_plane plane);
944 void dispc_ovl_set_channel_out(enum omap_plane plane,
945 enum omap_channel channel);
946 int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
947 bool replication, const struct omap_video_timings *mgr_timings,
948 bool mem_to_mem);
950 int omapdss_compat_init(void);
951 void omapdss_compat_uninit(void);
953 struct dss_mgr_ops {
954 int (*connect)(struct omap_overlay_manager *mgr,
955 struct omap_dss_device *dst);
956 void (*disconnect)(struct omap_overlay_manager *mgr,
957 struct omap_dss_device *dst);
959 void (*start_update)(struct omap_overlay_manager *mgr);
960 int (*enable)(struct omap_overlay_manager *mgr);
961 void (*disable)(struct omap_overlay_manager *mgr);
962 void (*set_timings)(struct omap_overlay_manager *mgr,
963 const struct omap_video_timings *timings);
964 void (*set_lcd_config)(struct omap_overlay_manager *mgr,
965 const struct dss_lcd_mgr_config *config);
966 int (*register_framedone_handler)(struct omap_overlay_manager *mgr,
967 void (*handler)(void *), void *data);
968 void (*unregister_framedone_handler)(struct omap_overlay_manager *mgr,
969 void (*handler)(void *), void *data);
970 };
972 int dss_install_mgr_ops(const struct dss_mgr_ops *mgr_ops);
973 void dss_uninstall_mgr_ops(void);
975 int dss_mgr_connect(struct omap_overlay_manager *mgr,
976 struct omap_dss_device *dst);
977 void dss_mgr_disconnect(struct omap_overlay_manager *mgr,
978 struct omap_dss_device *dst);
979 void dss_mgr_set_timings(struct omap_overlay_manager *mgr,
980 const struct omap_video_timings *timings);
981 void dss_mgr_set_lcd_config(struct omap_overlay_manager *mgr,
982 const struct dss_lcd_mgr_config *config);
983 int dss_mgr_enable(struct omap_overlay_manager *mgr);
984 void dss_mgr_disable(struct omap_overlay_manager *mgr);
985 void dss_mgr_start_update(struct omap_overlay_manager *mgr);
986 int dss_mgr_register_framedone_handler(struct omap_overlay_manager *mgr,
987 void (*handler)(void *), void *data);
988 void dss_mgr_unregister_framedone_handler(struct omap_overlay_manager *mgr,
989 void (*handler)(void *), void *data);
991 static inline bool omapdss_device_is_connected(struct omap_dss_device *dssdev)
992 {
993 return dssdev->src;
994 }
996 static inline bool omapdss_device_is_enabled(struct omap_dss_device *dssdev)
997 {
998 return dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
999 }
1001 struct device_node *
1002 omapdss_of_get_next_port(const struct device_node *parent,
1003 struct device_node *prev);
1005 struct device_node *
1006 omapdss_of_get_next_endpoint(const struct device_node *parent,
1007 struct device_node *prev);
1009 struct device_node *
1010 omapdss_of_get_first_endpoint(const struct device_node *parent);
1012 struct omap_dss_device *
1013 omapdss_of_find_source_for_first_ep(struct device_node *node);
1014 #endif