/* * DRA7xx Clock data * * Copyright (C) 2013 Texas Instruments, Inc. * * Paul Walmsley (paul@pwsan.com) * Rajendra Nayak (rnayak@ti.com) * Benoit Cousson (b-cousson@ti.com) * Mike Turquette (mturquette@ti.com) * * This file is automatically generated from the OMAP hardware databases. * We respectfully ask that any modifications to this file be coordinated * with the public linux-omap@vger.kernel.org mailing list and the * authors above to ensure that the autogeneration scripts are kept * up-to-date with the file contents. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * XXX Some of the ES1 clocks have been removed/changed; once support * is added for discriminating clocks by ES level, these should be added back * in. */ #include #include #include #include #include #include "soc.h" #include "iomap.h" #include "clock.h" #include "clock7xx.h" #include "cm1_7xx.h" #include "cm2_7xx.h" #include "cm-regbits-7xx.h" #include "prm7xx.h" #include "prm-regbits-7xx.h" #include "control.h" #define DRA7_DPLL_ABE_DEFFREQ 361267200 #define DRA7_DPLL_GMAC_DEFFREQ 1000000000 /* Root clocks */ DEFINE_CLK_FIXED_RATE(atl_clkin0_ck, CLK_IS_ROOT, 0, 0x0); DEFINE_CLK_FIXED_RATE(atl_clkin1_ck, CLK_IS_ROOT, 0, 0x0); DEFINE_CLK_FIXED_RATE(atl_clkin2_ck, CLK_IS_ROOT, 0, 0x0); DEFINE_CLK_FIXED_RATE(atlclkin3_ck, CLK_IS_ROOT, 0, 0x0); DEFINE_CLK_FIXED_RATE(hdmi_clkin_ck, CLK_IS_ROOT, 0, 0x0); DEFINE_CLK_FIXED_RATE(mlb_clkin_ck, CLK_IS_ROOT, 0, 0x0); DEFINE_CLK_FIXED_RATE(mlbp_clkin_ck, CLK_IS_ROOT, 0, 0x0); DEFINE_CLK_FIXED_RATE(pciesref_acs_clk_ck, CLK_IS_ROOT, 100000000, 0x0); DEFINE_CLK_FIXED_RATE(ref_clkin0_ck, CLK_IS_ROOT, 0, 0x0); DEFINE_CLK_FIXED_RATE(ref_clkin1_ck, CLK_IS_ROOT, 0, 0x0); DEFINE_CLK_FIXED_RATE(ref_clkin2_ck, CLK_IS_ROOT, 0, 0x0); DEFINE_CLK_FIXED_RATE(ref_clkin3_ck, CLK_IS_ROOT, 0, 0x0); DEFINE_CLK_FIXED_RATE(rmii_clk_ck, CLK_IS_ROOT, 0, 0x0); DEFINE_CLK_FIXED_RATE(sdvenc_clkin_ck, CLK_IS_ROOT, 0, 0x0); DEFINE_CLK_FIXED_RATE(secure_32k_clk_src_ck, CLK_IS_ROOT, 32768, 0x0); DEFINE_CLK_FIXED_RATE(sys_32k_ck, CLK_IS_ROOT, 32768, 0x0); DEFINE_CLK_FIXED_RATE(virt_12000000_ck, CLK_IS_ROOT, 12000000, 0x0); DEFINE_CLK_FIXED_RATE(virt_13000000_ck, CLK_IS_ROOT, 13000000, 0x0); DEFINE_CLK_FIXED_RATE(virt_16800000_ck, CLK_IS_ROOT, 16800000, 0x0); DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0); DEFINE_CLK_FIXED_RATE(virt_20000000_ck, CLK_IS_ROOT, 20000000, 0x0); DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0); DEFINE_CLK_FIXED_RATE(virt_27000000_ck, CLK_IS_ROOT, 27000000, 0x0); DEFINE_CLK_FIXED_RATE(virt_38400000_ck, CLK_IS_ROOT, 38400000, 0x0); static const struct clksel_rate div_1_8_rates[] = { { .div = 1, .val = 8, .flags = RATE_IN_7XX }, { .div = 0 }, }; static const char *sys_clkin1_parents[] = { "virt_12000000_ck", "virt_20000000_ck", "virt_16800000_ck", "virt_19200000_ck", "virt_26000000_ck", "virt_27000000_ck", "virt_38400000_ck", }; DEFINE_CLK_MUX(sys_clkin1, sys_clkin1_parents, NULL, 0x0, DRA7XX_CM_CLKSEL_SYS, DRA7XX_SYS_CLKSEL_SHIFT, DRA7XX_SYS_CLKSEL_WIDTH, CLK_MUX_INDEX_ONE, NULL); DEFINE_CLK_FIXED_RATE(sys_clkin2, CLK_IS_ROOT, 22579200, 0x0); DEFINE_CLK_FIXED_RATE(usb_otg_clkin_ck, CLK_IS_ROOT, 0, 0x0); DEFINE_CLK_FIXED_RATE(video1_clkin_ck, CLK_IS_ROOT, 0, 0x0); DEFINE_CLK_FIXED_RATE(video1_m2_clkin_ck, CLK_IS_ROOT, 0, 0x0); DEFINE_CLK_FIXED_RATE(video2_clkin_ck, CLK_IS_ROOT, 0, 0x0); DEFINE_CLK_FIXED_RATE(video2_m2_clkin_ck, CLK_IS_ROOT, 0, 0x0); /* Module clocks and DPLL outputs */ static const char *abe_dpll_sys_clk_mux_parents[] = { "sys_clkin1", "sys_clkin2", }; DEFINE_CLK_MUX(abe_dpll_sys_clk_mux, abe_dpll_sys_clk_mux_parents, NULL, 0x0, DRA7XX_CM_CLKSEL_ABE_PLL_SYS, DRA7XX_CLKSEL_0_0_SHIFT, DRA7XX_CLKSEL_0_0_WIDTH, 0x0, NULL); static const char *abe_dpll_bypass_clk_mux_parents[] = { "abe_dpll_sys_clk_mux", "sys_32k_ck", }; DEFINE_CLK_MUX(abe_dpll_bypass_clk_mux, abe_dpll_bypass_clk_mux_parents, NULL, 0x0, DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS, DRA7XX_CLKSEL_0_0_SHIFT, DRA7XX_CLKSEL_0_0_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(abe_dpll_clk_mux, abe_dpll_bypass_clk_mux_parents, NULL, 0x0, DRA7XX_CM_CLKSEL_ABE_PLL_REF, DRA7XX_CLKSEL_0_0_SHIFT, DRA7XX_CLKSEL_0_0_WIDTH, 0x0, NULL); /* DPLL_ABE */ static struct dpll_data dpll_abe_dd = { .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_ABE, .clk_bypass = &abe_dpll_bypass_clk_mux, .clk_ref = &abe_dpll_clk_mux, .control_reg = DRA7XX_CM_CLKMODE_DPLL_ABE, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_ABE, .idlest_reg = DRA7XX_CM_IDLEST_DPLL_ABE, .mult_mask = DRA7XX_DPLL_MULT_MASK, .div1_mask = DRA7XX_DPLL_DIV_MASK, .enable_mask = DRA7XX_DPLL_EN_MASK, .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK, .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK, .m4xen_mask = DRA7XX_DPLL_REGM4XEN_MASK, .lpmode_mask = DRA7XX_DPLL_LPMODE_EN_MASK, .max_multiplier = 2047, .max_divider = 128, .min_divider = 1, }; static const char *dpll_abe_ck_parents[] = { "abe_dpll_clk_mux", "abe_dpll_bypass_clk_mux" }; static struct clk dpll_abe_ck; static const struct clk_ops dpll_abe_ck_ops = { .enable = &omap3_noncore_dpll_enable, .disable = &omap3_noncore_dpll_disable, .recalc_rate = &omap4_dpll_regm4xen_recalc, .round_rate = &omap4_dpll_regm4xen_round_rate, .set_rate = &omap3_noncore_dpll_set_rate, .get_parent = &omap2_init_dpll_parent, }; static struct clk_hw_omap dpll_abe_ck_hw = { .hw = { .clk = &dpll_abe_ck, }, .dpll_data = &dpll_abe_dd, .ops = &clkhwops_omap3_dpll, }; DEFINE_STRUCT_CLK(dpll_abe_ck, dpll_abe_ck_parents, dpll_abe_ck_ops); static const char *dpll_abe_x2_ck_parents[] = { "dpll_abe_ck", }; static struct clk dpll_abe_x2_ck; static const struct clk_ops dpll_abe_x2_ck_ops = { .recalc_rate = &omap3_clkoutx2_recalc, }; static struct clk_hw_omap dpll_abe_x2_ck_hw = { .hw = { .clk = &dpll_abe_x2_ck, }, }; DEFINE_STRUCT_CLK(dpll_abe_x2_ck, dpll_abe_x2_ck_parents, dpll_abe_x2_ck_ops); static const struct clk_ops omap_hsdivider_ops = { .set_rate = &omap2_clksel_set_rate, .recalc_rate = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, }; DEFINE_CLK_OMAP_HSDIVIDER63(dpll_abe_m2x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck, 0x0, DRA7XX_CM_DIV_M2_DPLL_ABE, DRA7XX_DIVHS_MASK); static const struct clk_div_table abe_24m_fclk_rates[] = { { .div = 8, .val = 0 }, { .div = 16, .val = 1 }, { .div = 0 }, }; DEFINE_CLK_DIVIDER_TABLE(abe_24m_fclk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, 0x0, DRA7XX_CM_CLKSEL_ABE_24M, DRA7XX_CLKSEL_0_0_SHIFT, DRA7XX_CLKSEL_0_0_WIDTH, 0x0, abe_24m_fclk_rates, NULL); DEFINE_CLK_DIVIDER(abe_clk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, 0x0, DRA7XX_CM_CLKSEL_ABE, DRA7XX_CLKSEL_OPP_SHIFT, DRA7XX_CLKSEL_OPP_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); DEFINE_CLK_DIVIDER(aess_fclk, "abe_clk", &abe_clk, 0x0, DRA7XX_CM_CLKSEL_AESS_FCLK_DIV, DRA7XX_CLKSEL_0_0_SHIFT, DRA7XX_CLKSEL_0_0_WIDTH, 0x0, NULL); DEFINE_CLK_DIVIDER(abe_giclk_div, "aess_fclk", &aess_fclk, 0x0, DRA7XX_CM_CLKSEL_ABE_GICLK_DIV, DRA7XX_CLKSEL_0_0_SHIFT, DRA7XX_CLKSEL_0_0_WIDTH, 0x0, NULL); static const struct clk_div_table abe_lp_clk_div_rates[] = { { .div = 16, .val = 0 }, { .div = 32, .val = 1 }, { .div = 0 }, }; DEFINE_CLK_DIVIDER_TABLE(abe_lp_clk_div, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, 0x0, DRA7XX_CM_CLKSEL_ABE_LP_CLK, DRA7XX_CLKSEL_0_0_SHIFT, DRA7XX_CLKSEL_0_0_WIDTH, 0x0, abe_lp_clk_div_rates, NULL); DEFINE_CLK_DIVIDER(abe_sys_clk_div, "sys_clkin1", &sys_clkin1, 0x0, DRA7XX_CM_CLKSEL_ABE_SYS, DRA7XX_CLKSEL_0_0_SHIFT, DRA7XX_CLKSEL_0_0_WIDTH, 0x0, NULL); static const char *adc_gfclk_mux_parents[] = { "sys_clkin1", "sys_clkin2", "sys_32k_ck", }; DEFINE_CLK_MUX(adc_gfclk_mux, adc_gfclk_mux_parents, NULL, 0x0, DRA7XX_CM_CLKSEL_ADC_GFCLK, DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH, 0x0, NULL); /* DPLL_PCIE_REF */ static struct dpll_data dpll_pcie_ref_dd = { .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_PCIE_REF, .clk_bypass = &sys_clkin1, .clk_ref = &sys_clkin1, .control_reg = DRA7XX_CM_CLKMODE_DPLL_PCIE_REF, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF, .idlest_reg = DRA7XX_CM_IDLEST_DPLL_PCIE_REF, .mult_mask = DRA7XX_DPLL_MULT_MASK, .div1_mask = DRA7XX_DPLL_DIV_MASK, .enable_mask = DRA7XX_DPLL_EN_MASK, .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK, .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK, .max_multiplier = 4095, .max_divider = 256, .min_divider = 1, }; static const char *dpll_pcie_ref_ck_parents[] = { "sys_clkin1", }; static struct clk dpll_pcie_ref_ck; static const struct clk_ops dpll_pcie_ref_ck_ops = { .enable = &omap3_noncore_dpll_enable, .disable = &omap3_noncore_dpll_disable, .recalc_rate = &omap3_dpll_recalc, .round_rate = &omap2_dpll_round_rate, .set_rate = &omap3_noncore_dpll_set_rate, .get_parent = &omap2_init_dpll_parent, }; static struct clk_hw_omap dpll_pcie_ref_ck_hw = { .hw = { .clk = &dpll_pcie_ref_ck, }, .dpll_data = &dpll_pcie_ref_dd, .ops = &clkhwops_omap3_dpll, }; DEFINE_STRUCT_CLK(dpll_pcie_ref_ck, dpll_pcie_ref_ck_parents, dpll_pcie_ref_ck_ops); DEFINE_CLK_OMAP_HSDIVIDER63(dpll_pcie_ref_m2ldo_ck, "dpll_pcie_ref_ck", &dpll_pcie_ref_ck, 0x0, DRA7XX_CM_DIV_M2_DPLL_PCIE_REF, DRA7XX_DIVHS_MASK); /* APLL_PCIE */ static struct dpll_data apll_pcie_dd = { .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_PCIE_REF, .clk_bypass = &dpll_pcie_ref_ck, .clk_ref = &dpll_pcie_ref_ck, .control_reg = DRA7XX_CM_CLKMODE_DPLL_PCIE_REF, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF, .idlest_reg = DRA7XX_CM_IDLEST_DPLL_PCIE_REF, .mult_mask = DRA7XX_DPLL_MULT_MASK, .div1_mask = DRA7XX_DPLL_DIV_MASK, .enable_mask = DRA7XX_DPLL_EN_MASK, .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK, .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK, .max_multiplier = -1, .max_divider = 0, .min_divider = 1, }; static const char *apll_pcie_ck_parents[] = { "BUGGED", }; static struct clk apll_pcie_ck; static struct clk_hw_omap apll_pcie_ck_hw = { .hw = { .clk = &apll_pcie_ck, }, .dpll_data = &apll_pcie_dd, .ops = &clkhwops_omap3_dpll, }; DEFINE_STRUCT_CLK(apll_pcie_ck, apll_pcie_ck_parents, dpll_pcie_ref_ck_ops); static const char *apll_pcie_clkvcoldo_parents[] = { "apll_pcie_ck", }; static struct clk apll_pcie_clkvcoldo; static const struct clk_ops apll_pcie_clkvcoldo_ops = { }; static struct clk_hw_omap apll_pcie_clkvcoldo_hw = { .hw = { .clk = &apll_pcie_clkvcoldo, }, .clksel_reg = DRA7XX_CM_CLKVCOLDO_APLL_PCIE, }; DEFINE_STRUCT_CLK(apll_pcie_clkvcoldo, apll_pcie_clkvcoldo_parents, apll_pcie_clkvcoldo_ops); static struct clk apll_pcie_clkvcoldo_div; static struct clk_hw_omap apll_pcie_clkvcoldo_div_hw = { .hw = { .clk = &apll_pcie_clkvcoldo_div, }, .clksel_reg = DRA7XX_CM_CLKVCOLDO_APLL_PCIE, }; DEFINE_STRUCT_CLK(apll_pcie_clkvcoldo_div, apll_pcie_clkvcoldo_parents, apll_pcie_clkvcoldo_ops); DEFINE_CLK_OMAP_HSDIVIDER63(apll_pcie_m2_ck, "apll_pcie_ck", &apll_pcie_ck, 0x0, DRA7XX_CM_DIV_M2_APLL_PCIE, DRA7XX_DIVHS_0_6_MASK); DEFINE_CLK_DIVIDER(sys_clk1_dclk_div, "sys_clkin1", &sys_clkin1, 0x0, DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); DEFINE_CLK_DIVIDER(sys_clk2_dclk_div, "sys_clkin2", &sys_clkin2, 0x0, DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); DEFINE_CLK_OMAP_HSDIVIDER63(dpll_abe_m2_ck, "dpll_abe_ck", &dpll_abe_ck, 0x0, DRA7XX_CM_DIV_M2_DPLL_ABE, DRA7XX_DIVHS_MASK); DEFINE_CLK_DIVIDER(per_abe_x1_dclk_div, "dpll_abe_m2_ck", &dpll_abe_m2_ck, 0x0, DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); DEFINE_CLK_OMAP_HSDIVIDER63(dpll_abe_m3x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck, 0x0, DRA7XX_CM_DIV_M3_DPLL_ABE, DRA7XX_DIVHS_MASK); /* DPLL_CORE */ static struct dpll_data dpll_core_dd = { .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_CORE, .clk_bypass = &dpll_abe_m3x2_ck, .clk_ref = &sys_clkin1, .control_reg = DRA7XX_CM_CLKMODE_DPLL_CORE, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_CORE, .idlest_reg = DRA7XX_CM_IDLEST_DPLL_CORE, .mult_mask = DRA7XX_DPLL_MULT_MASK, .div1_mask = DRA7XX_DPLL_DIV_MASK, .enable_mask = DRA7XX_DPLL_EN_MASK, .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK, .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK, .max_multiplier = 2047, .max_divider = 128, .min_divider = 1, }; static const char *dpll_core_ck_parents[] = { "sys_clkin1", "dpll_abe_m3x2_ck" }; static struct clk dpll_core_ck; static const struct clk_ops dpll_core_ck_ops = { .recalc_rate = &omap3_dpll_recalc, .get_parent = &omap2_init_dpll_parent, }; static struct clk_hw_omap dpll_core_ck_hw = { .hw = { .clk = &dpll_core_ck, }, .dpll_data = &dpll_core_dd, .ops = &clkhwops_omap3_dpll, }; DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops); static const char *dpll_core_x2_ck_parents[] = { "dpll_core_ck", }; static struct clk dpll_core_x2_ck; static struct clk_hw_omap dpll_core_x2_ck_hw = { .hw = { .clk = &dpll_core_x2_ck, }, }; DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_abe_x2_ck_ops); DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_h12x2_ck, "dpll_core_x2_ck", &dpll_core_x2_ck, 0x0, DRA7XX_CM_DIV_H12_DPLL_CORE, DRA7XX_DIVHS_0_5_MASK); static const char *mpu_dpll_hs_clk_div_parents[] = { "dpll_core_h12x2_ck", }; static struct clk mpu_dpll_hs_clk_div; static struct clk_hw_omap mpu_dpll_hs_clk_div_hw = { .hw = { .clk = &mpu_dpll_hs_clk_div, }, }; DEFINE_STRUCT_CLK(mpu_dpll_hs_clk_div, mpu_dpll_hs_clk_div_parents, apll_pcie_clkvcoldo_ops); /* DPLL_MPU */ static struct dpll_data dpll_mpu_dd = { .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_MPU, .clk_bypass = &mpu_dpll_hs_clk_div, .clk_ref = &sys_clkin1, .control_reg = DRA7XX_CM_CLKMODE_DPLL_MPU, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_MPU, .idlest_reg = DRA7XX_CM_IDLEST_DPLL_MPU, .mult_mask = DRA7XX_DPLL_MULT_MASK, .div1_mask = DRA7XX_DPLL_DIV_MASK, .enable_mask = DRA7XX_DPLL_EN_MASK, .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK, .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK, .max_multiplier = 2047, .max_divider = 128, .min_divider = 1, }; static const char *dpll_mpu_ck_parents[] = { "sys_clkin1", "mpu_dpll_hs_clk_div" }; static struct clk dpll_mpu_ck; static const struct clk_ops dpll_mpu_ck_ops = { .enable = &omap3_noncore_dpll_enable, .disable = &omap3_noncore_dpll_disable, .recalc_rate = &omap3_dpll_recalc, .round_rate = &omap2_dpll_round_rate, .set_rate = &omap5_mpu_dpll_set_rate, .get_parent = &omap2_init_dpll_parent, }; static struct clk_hw_omap dpll_mpu_ck_hw = { .hw = { .clk = &dpll_mpu_ck, }, .dpll_data = &dpll_mpu_dd, .ops = &clkhwops_omap3_dpll, }; DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_mpu_ck_parents, dpll_mpu_ck_ops); DEFINE_CLK_OMAP_HSDIVIDER63(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck, 0x0, DRA7XX_CM_DIV_M2_DPLL_MPU, DRA7XX_DIVHS_MASK); static const char *mpu_dclk_div_parents[] = { "dpll_mpu_m2_ck", }; static struct clk mpu_dclk_div; static struct clk_hw_omap mpu_dclk_div_hw = { .hw = { .clk = &mpu_dclk_div, }, }; DEFINE_STRUCT_CLK(mpu_dclk_div, mpu_dclk_div_parents, apll_pcie_clkvcoldo_ops); static struct clk dsp_dpll_hs_clk_div; static struct clk_hw_omap dsp_dpll_hs_clk_div_hw = { .hw = { .clk = &dsp_dpll_hs_clk_div, }, }; DEFINE_STRUCT_CLK(dsp_dpll_hs_clk_div, mpu_dpll_hs_clk_div_parents, apll_pcie_clkvcoldo_ops); /* DPLL_DSP */ static struct dpll_data dpll_dsp_dd = { .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_DSP, .clk_bypass = &dsp_dpll_hs_clk_div, .clk_ref = &sys_clkin1, .control_reg = DRA7XX_CM_CLKMODE_DPLL_DSP, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_DSP, .idlest_reg = DRA7XX_CM_IDLEST_DPLL_DSP, .mult_mask = DRA7XX_DPLL_MULT_MASK, .div1_mask = DRA7XX_DPLL_DIV_MASK, .enable_mask = DRA7XX_DPLL_EN_MASK, .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK, .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK, .max_multiplier = 2047, .max_divider = 128, .min_divider = 1, }; static const char *dpll_dsp_ck_parents[] = { "sys_clkin1", "dsp_dpll_hs_clk_div" }; static struct clk dpll_dsp_ck; static struct clk_hw_omap dpll_dsp_ck_hw = { .hw = { .clk = &dpll_dsp_ck, }, .dpll_data = &dpll_dsp_dd, .ops = &clkhwops_omap3_dpll, }; DEFINE_STRUCT_CLK(dpll_dsp_ck, dpll_dsp_ck_parents, dpll_pcie_ref_ck_ops); DEFINE_CLK_OMAP_HSDIVIDER63(dpll_dsp_m2_ck, "dpll_dsp_ck", &dpll_dsp_ck, 0x0, DRA7XX_CM_DIV_M2_DPLL_DSP, DRA7XX_DIVHS_MASK); DEFINE_CLK_DIVIDER(dsp_gclk_div, "dpll_dsp_m2_ck", &dpll_dsp_m2_ck, 0x0, DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); static struct clk iva_dpll_hs_clk_div; static struct clk_hw_omap iva_dpll_hs_clk_div_hw = { .hw = { .clk = &iva_dpll_hs_clk_div, }, }; DEFINE_STRUCT_CLK(iva_dpll_hs_clk_div, mpu_dpll_hs_clk_div_parents, apll_pcie_clkvcoldo_ops); /* DPLL_IVA */ static struct dpll_data dpll_iva_dd = { .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_IVA, .clk_bypass = &iva_dpll_hs_clk_div, .clk_ref = &sys_clkin1, .control_reg = DRA7XX_CM_CLKMODE_DPLL_IVA, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_IVA, .idlest_reg = DRA7XX_CM_IDLEST_DPLL_IVA, .mult_mask = DRA7XX_DPLL_MULT_MASK, .div1_mask = DRA7XX_DPLL_DIV_MASK, .enable_mask = DRA7XX_DPLL_EN_MASK, .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK, .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK, .max_multiplier = 2047, .max_divider = 128, .min_divider = 1, }; static const char *dpll_iva_ck_parents[] = { "sys_clkin1", "iva_dpll_hs_clk_div" }; static struct clk dpll_iva_ck; static struct clk_hw_omap dpll_iva_ck_hw = { .hw = { .clk = &dpll_iva_ck, }, .dpll_data = &dpll_iva_dd, .ops = &clkhwops_omap3_dpll, }; DEFINE_STRUCT_CLK(dpll_iva_ck, dpll_iva_ck_parents, dpll_pcie_ref_ck_ops); DEFINE_CLK_OMAP_HSDIVIDER63(dpll_iva_m2_ck, "dpll_iva_ck", &dpll_iva_ck, 0x0, DRA7XX_CM_DIV_M2_DPLL_IVA, DRA7XX_DIVHS_MASK); static const char *iva_dclk_parents[] = { "dpll_iva_m2_ck", }; static struct clk iva_dclk; static struct clk_hw_omap iva_dclk_hw = { .hw = { .clk = &iva_dclk, }, }; DEFINE_STRUCT_CLK(iva_dclk, iva_dclk_parents, apll_pcie_clkvcoldo_ops); /* DPLL_GPU */ static struct dpll_data dpll_gpu_dd = { .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_GPU, .clk_bypass = &dpll_abe_m3x2_ck, .clk_ref = &sys_clkin1, .control_reg = DRA7XX_CM_CLKMODE_DPLL_GPU, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_GPU, .idlest_reg = DRA7XX_CM_IDLEST_DPLL_GPU, .mult_mask = DRA7XX_DPLL_MULT_MASK, .div1_mask = DRA7XX_DPLL_DIV_MASK, .enable_mask = DRA7XX_DPLL_EN_MASK, .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK, .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK, .max_multiplier = 2047, .max_divider = 128, .min_divider = 1, }; static struct clk dpll_gpu_ck; static struct clk_hw_omap dpll_gpu_ck_hw = { .hw = { .clk = &dpll_gpu_ck, }, .dpll_data = &dpll_gpu_dd, .ops = &clkhwops_omap3_dpll, }; DEFINE_STRUCT_CLK(dpll_gpu_ck, dpll_core_ck_parents, dpll_pcie_ref_ck_ops); DEFINE_CLK_OMAP_HSDIVIDER63(dpll_gpu_m2_ck, "dpll_gpu_ck", &dpll_gpu_ck, 0x0, DRA7XX_CM_DIV_M2_DPLL_GPU, DRA7XX_DIVHS_MASK); DEFINE_CLK_DIVIDER(gpu_dclk, "dpll_gpu_m2_ck", &dpll_gpu_m2_ck, 0x0, DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_m2_ck, "dpll_core_ck", &dpll_core_ck, 0x0, DRA7XX_CM_DIV_M2_DPLL_CORE, DRA7XX_DIVHS_MASK); static const char *core_dpll_out_dclk_div_parents[] = { "dpll_core_m2_ck", }; static struct clk core_dpll_out_dclk_div; static struct clk_hw_omap core_dpll_out_dclk_div_hw = { .hw = { .clk = &core_dpll_out_dclk_div, }, }; DEFINE_STRUCT_CLK(core_dpll_out_dclk_div, core_dpll_out_dclk_div_parents, apll_pcie_clkvcoldo_ops); /* DPLL_DDR */ static struct dpll_data dpll_ddr_dd = { .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_DDR, .clk_bypass = &dpll_abe_m3x2_ck, .clk_ref = &sys_clkin1, .control_reg = DRA7XX_CM_CLKMODE_DPLL_DDR, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_DDR, .idlest_reg = DRA7XX_CM_IDLEST_DPLL_DDR, .mult_mask = DRA7XX_DPLL_MULT_MASK, .div1_mask = DRA7XX_DPLL_DIV_MASK, .enable_mask = DRA7XX_DPLL_EN_MASK, .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK, .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK, .max_multiplier = 2047, .max_divider = 128, .min_divider = 1, }; static struct clk dpll_ddr_ck; static struct clk_hw_omap dpll_ddr_ck_hw = { .hw = { .clk = &dpll_ddr_ck, }, .dpll_data = &dpll_ddr_dd, .ops = &clkhwops_omap3_dpll, }; DEFINE_STRUCT_CLK(dpll_ddr_ck, dpll_core_ck_parents, dpll_pcie_ref_ck_ops); DEFINE_CLK_OMAP_HSDIVIDER63(dpll_ddr_m2_ck, "dpll_ddr_ck", &dpll_ddr_ck, 0x0, DRA7XX_CM_DIV_M2_DPLL_DDR, DRA7XX_DIVHS_MASK); DEFINE_CLK_DIVIDER(emif_phy_dclk_div, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, 0x0, DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); /* DPLL_GMAC */ static struct dpll_data dpll_gmac_dd = { .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_GMAC, .clk_bypass = &dpll_abe_m3x2_ck, .clk_ref = &sys_clkin1, .control_reg = DRA7XX_CM_CLKMODE_DPLL_GMAC, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_GMAC, .idlest_reg = DRA7XX_CM_IDLEST_DPLL_GMAC, .mult_mask = DRA7XX_DPLL_MULT_MASK, .div1_mask = DRA7XX_DPLL_DIV_MASK, .enable_mask = DRA7XX_DPLL_EN_MASK, .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK, .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK, .max_multiplier = 2047, .max_divider = 128, .min_divider = 1, }; static struct clk dpll_gmac_ck; static struct clk_hw_omap dpll_gmac_ck_hw = { .hw = { .clk = &dpll_gmac_ck, }, .dpll_data = &dpll_gmac_dd, .ops = &clkhwops_omap3_dpll, }; DEFINE_STRUCT_CLK(dpll_gmac_ck, dpll_core_ck_parents, dpll_pcie_ref_ck_ops); DEFINE_CLK_OMAP_HSDIVIDER63(dpll_gmac_m2_ck, "dpll_gmac_ck", &dpll_gmac_ck, 0x0, DRA7XX_CM_DIV_M2_DPLL_GMAC, DRA7XX_DIVHS_MASK); DEFINE_CLK_DIVIDER(gmac_250m_dclk_div, "dpll_gmac_m2_ck", &dpll_gmac_m2_ck, 0x0, DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); static const char *video2_dclk_div_parents[] = { "video2_m2_clkin", }; static struct clk video2_dclk_div; static struct clk_hw_omap video2_dclk_div_hw = { .hw = { .clk = &video2_dclk_div, }, }; DEFINE_STRUCT_CLK(video2_dclk_div, video2_dclk_div_parents, apll_pcie_clkvcoldo_ops); static const char *video1_dclk_div_parents[] = { "video1_m2_clkin", }; static struct clk video1_dclk_div; static struct clk_hw_omap video1_dclk_div_hw = { .hw = { .clk = &video1_dclk_div, }, }; DEFINE_STRUCT_CLK(video1_dclk_div, video1_dclk_div_parents, apll_pcie_clkvcoldo_ops); static const char *hdmi_dclk_div_parents[] = { "hdmi_clkin", }; static struct clk hdmi_dclk_div; static struct clk_hw_omap hdmi_dclk_div_hw = { .hw = { .clk = &hdmi_dclk_div, }, }; DEFINE_STRUCT_CLK(hdmi_dclk_div, hdmi_dclk_div_parents, apll_pcie_clkvcoldo_ops); DEFINE_CLK_FIXED_FACTOR(per_dpll_hs_clk_div, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, 0x0, 1, 2); /* DPLL_PER */ static struct dpll_data dpll_per_dd = { .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_PER, .clk_bypass = &per_dpll_hs_clk_div, .clk_ref = &sys_clkin1, .control_reg = DRA7XX_CM_CLKMODE_DPLL_PER, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_PER, .idlest_reg = DRA7XX_CM_IDLEST_DPLL_PER, .mult_mask = DRA7XX_DPLL_MULT_MASK, .div1_mask = DRA7XX_DPLL_DIV_MASK, .enable_mask = DRA7XX_DPLL_EN_MASK, .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK, .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK, .max_multiplier = 2047, .max_divider = 128, .min_divider = 1, }; static const char *dpll_per_ck_parents[] = { "sys_clkin1", "per_dpll_hs_clk_div" }; static struct clk dpll_per_ck; static struct clk_hw_omap dpll_per_ck_hw = { .hw = { .clk = &dpll_per_ck, }, .dpll_data = &dpll_per_dd, .ops = &clkhwops_omap3_dpll, }; DEFINE_STRUCT_CLK(dpll_per_ck, dpll_per_ck_parents, dpll_pcie_ref_ck_ops); DEFINE_CLK_OMAP_HSDIVIDER63(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0, DRA7XX_CM_DIV_M2_DPLL_PER, DRA7XX_DIVHS_MASK); static const char *func_96m_aon_dclk_div_parents[] = { "dpll_per_m2_ck", }; static struct clk func_96m_aon_dclk_div; static struct clk_hw_omap func_96m_aon_dclk_div_hw = { .hw = { .clk = &func_96m_aon_dclk_div, }, }; DEFINE_STRUCT_CLK(func_96m_aon_dclk_div, func_96m_aon_dclk_div_parents, apll_pcie_clkvcoldo_ops); DEFINE_CLK_FIXED_FACTOR(usb_dpll_hs_clk_div, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, 0x0, 1, 3); /* DPLL_USB */ static struct dpll_data dpll_usb_dd = { .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_USB, .clk_bypass = &usb_dpll_hs_clk_div, .flags = DPLL_J_TYPE, .clk_ref = &sys_clkin1, .control_reg = DRA7XX_CM_CLKMODE_DPLL_USB, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_USB, .idlest_reg = DRA7XX_CM_IDLEST_DPLL_USB, .mult_mask = DRA7XX_DPLL_MULT_MASK, .div1_mask = DRA7XX_DPLL_DIV_MASK, .enable_mask = DRA7XX_DPLL_EN_MASK, .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK, .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK, .sddiv_mask = DRA7XX_DPLL_SD_DIV_MASK, .max_multiplier = 4095, .max_divider = 256, .min_divider = 1, }; static const char *dpll_usb_ck_parents[] = { "sys_clkin1", "usb_dpll_hs_clk_div" }; static struct clk dpll_usb_ck; static const struct clk_ops dpll_usb_ck_ops = { .enable = &omap3_noncore_dpll_enable, .disable = &omap3_noncore_dpll_disable, .recalc_rate = &omap3_dpll_recalc, .round_rate = &omap2_dpll_round_rate, .set_rate = &omap3_noncore_dpll_set_rate, .get_parent = &omap2_init_dpll_parent, .init = &omap2_init_clk_clkdm, }; static struct clk_hw_omap dpll_usb_ck_hw = { .hw = { .clk = &dpll_usb_ck, }, .dpll_data = &dpll_usb_dd, .clkdm_name = "coreaon_clkdm", .ops = &clkhwops_omap3_dpll, }; DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_usb_ck_parents, dpll_usb_ck_ops); DEFINE_CLK_OMAP_HSDIVIDER63(dpll_usb_m2_ck, "dpll_usb_ck", &dpll_usb_ck, 0x0, DRA7XX_CM_DIV_M2_DPLL_USB, DRA7XX_DIVHS_0_6_MASK); DEFINE_CLK_DIVIDER(l3init_480m_dclk_div, "dpll_usb_m2_ck", &dpll_usb_m2_ck, 0x0, DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); DEFINE_CLK_DIVIDER(usb_otg_dclk_div, "usb_otg_clkin_ck", &usb_otg_clkin_ck, 0x0, DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); DEFINE_CLK_DIVIDER(sata_dclk_div, "sys_clkin1", &sys_clkin1, 0x0, DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); DEFINE_CLK_OMAP_HSDIVIDER63(dpll_pcie_ref_m2_ck, "dpll_pcie_ref_ck", &dpll_pcie_ref_ck, 0x0, DRA7XX_CM_DIV_M2_DPLL_PCIE_REF, DRA7XX_DIVHS_0_6_MASK); DEFINE_CLK_DIVIDER(pcie2_dclk_div, "dpll_pcie_ref_m2_ck", &dpll_pcie_ref_m2_ck, 0x0, DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); DEFINE_CLK_DIVIDER(pcie_dclk_div, "apll_pcie_m2_ck", &apll_pcie_m2_ck, 0x0, DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); DEFINE_CLK_DIVIDER(emu_dclk_div, "sys_clkin1", &sys_clkin1, 0x0, DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); DEFINE_CLK_DIVIDER(secure_32k_dclk_div, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, 0x0, DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); static struct clk eve_dpll_hs_clk_div; static struct clk_hw_omap eve_dpll_hs_clk_div_hw = { .hw = { .clk = &eve_dpll_hs_clk_div, }, }; DEFINE_STRUCT_CLK(eve_dpll_hs_clk_div, mpu_dpll_hs_clk_div_parents, apll_pcie_clkvcoldo_ops); /* DPLL_EVE */ static struct dpll_data dpll_eve_dd = { .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_EVE, .clk_bypass = &eve_dpll_hs_clk_div, .clk_ref = &sys_clkin1, .control_reg = DRA7XX_CM_CLKMODE_DPLL_EVE, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_EVE, .idlest_reg = DRA7XX_CM_IDLEST_DPLL_EVE, .mult_mask = DRA7XX_DPLL_MULT_MASK, .div1_mask = DRA7XX_DPLL_DIV_MASK, .enable_mask = DRA7XX_DPLL_EN_MASK, .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK, .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK, .max_multiplier = 2047, .max_divider = 128, .min_divider = 1, }; static const char *dpll_eve_ck_parents[] = { "sys_clkin1", "eve_dpll_hs_clk_div" }; static struct clk dpll_eve_ck; static struct clk_hw_omap dpll_eve_ck_hw = { .hw = { .clk = &dpll_eve_ck, }, .dpll_data = &dpll_eve_dd, .ops = &clkhwops_omap3_dpll, }; DEFINE_STRUCT_CLK(dpll_eve_ck, dpll_eve_ck_parents, dpll_pcie_ref_ck_ops); DEFINE_CLK_OMAP_HSDIVIDER63(dpll_eve_m2_ck, "dpll_eve_ck", &dpll_eve_ck, 0x0, DRA7XX_CM_DIV_M2_DPLL_EVE, DRA7XX_DIVHS_MASK); static const char *eve_dclk_div_parents[] = { "dpll_eve_m2_ck", }; static struct clk eve_dclk_div; static struct clk_hw_omap eve_dclk_div_hw = { .hw = { .clk = &eve_dclk_div, }, }; DEFINE_STRUCT_CLK(eve_dclk_div, eve_dclk_div_parents, apll_pcie_clkvcoldo_ops); static const char *clkoutmux0_clk_mux_parents[] = { "sys_clk1_dclk_div", "sys_clk2_dclk_div", "per_abe_x1_dclk_div", "mpu_dclk_div", "dsp_gclk_div", "iva_dclk", "gpu_dclk", "core_dpll_out_dclk_div", "emif_phy_dclk_div", "gmac_250m_dclk_div", "video2_dclk_div", "video1_dclk_div", "hdmi_dclk_div", "func_96m_aon_dclk_div", "l3init_480m_dclk_div", "usb_otg_dclk_div", "sata_dclk_div", "pcie2_dclk_div", "pcie_dclk_div", "emu_dclk_div", "secure_32k_dclk_div", "eve_dclk_div", }; DEFINE_CLK_MUX(clkoutmux0_clk_mux, clkoutmux0_clk_mux_parents, NULL, 0x0, DRA7XX_CM_CLKSEL_CLKOUTMUX0, DRA7XX_CLKSEL_0_4_SHIFT, DRA7XX_CLKSEL_0_4_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(clkoutmux1_clk_mux, clkoutmux0_clk_mux_parents, NULL, 0x0, DRA7XX_CM_CLKSEL_CLKOUTMUX1, DRA7XX_CLKSEL_0_4_SHIFT, DRA7XX_CLKSEL_0_4_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(clkoutmux2_clk_mux, clkoutmux0_clk_mux_parents, NULL, 0x0, DRA7XX_CM_CLKSEL_CLKOUTMUX2, DRA7XX_CLKSEL_0_4_SHIFT, DRA7XX_CLKSEL_0_4_WIDTH, 0x0, NULL); DEFINE_CLK_FIXED_FACTOR(custefuse_sys_gfclk_div, "sys_clkin1", &sys_clkin1, 0x0, 1, 2); DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_h13x2_ck, "dpll_core_x2_ck", &dpll_core_x2_ck, 0x0, DRA7XX_CM_DIV_H13_DPLL_CORE, DRA7XX_DIVHS_0_5_MASK); DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_h14x2_ck, "dpll_core_x2_ck", &dpll_core_x2_ck, 0x0, DRA7XX_CM_DIV_H14_DPLL_CORE, DRA7XX_DIVHS_0_5_MASK); DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_h22x2_ck, "dpll_core_x2_ck", &dpll_core_x2_ck, 0x0, DRA7XX_CM_DIV_H22_DPLL_CORE, DRA7XX_DIVHS_0_5_MASK); DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_h23x2_ck, "dpll_core_x2_ck", &dpll_core_x2_ck, 0x0, DRA7XX_CM_DIV_H23_DPLL_CORE, DRA7XX_DIVHS_0_5_MASK); DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_h24x2_ck, "dpll_core_x2_ck", &dpll_core_x2_ck, 0x0, DRA7XX_CM_DIV_H24_DPLL_CORE, DRA7XX_DIVHS_0_5_MASK); static const char *dpll_ddr_x2_ck_parents[] = { "dpll_ddr_ck", }; static struct clk dpll_ddr_x2_ck; static struct clk_hw_omap dpll_ddr_x2_ck_hw = { .hw = { .clk = &dpll_ddr_x2_ck, }, }; DEFINE_STRUCT_CLK(dpll_ddr_x2_ck, dpll_ddr_x2_ck_parents, dpll_abe_x2_ck_ops); DEFINE_CLK_OMAP_HSDIVIDER63(dpll_ddr_h11x2_ck, "dpll_ddr_x2_ck", &dpll_ddr_x2_ck, 0x0, DRA7XX_CM_DIV_H11_DPLL_DDR, DRA7XX_DIVHS_0_5_MASK); static const char *dpll_dsp_x2_ck_parents[] = { "dpll_dsp_ck", }; static struct clk dpll_dsp_x2_ck; static struct clk_hw_omap dpll_dsp_x2_ck_hw = { .hw = { .clk = &dpll_dsp_x2_ck, }, }; DEFINE_STRUCT_CLK(dpll_dsp_x2_ck, dpll_dsp_x2_ck_parents, dpll_abe_x2_ck_ops); DEFINE_CLK_OMAP_HSDIVIDER63(dpll_dsp_m3x2_ck, "dpll_dsp_x2_ck", &dpll_dsp_x2_ck, 0x0, DRA7XX_CM_DIV_M3_DPLL_DSP, DRA7XX_DIVHS_MASK); static const char *dpll_gmac_x2_ck_parents[] = { "dpll_gmac_ck", }; static struct clk dpll_gmac_x2_ck; static struct clk_hw_omap dpll_gmac_x2_ck_hw = { .hw = { .clk = &dpll_gmac_x2_ck, }, }; DEFINE_STRUCT_CLK(dpll_gmac_x2_ck, dpll_gmac_x2_ck_parents, dpll_abe_x2_ck_ops); DEFINE_CLK_OMAP_HSDIVIDER63(dpll_gmac_h11x2_ck, "dpll_gmac_x2_ck", &dpll_gmac_x2_ck, 0x0, DRA7XX_CM_DIV_H11_DPLL_GMAC, DRA7XX_DIVHS_0_5_MASK); DEFINE_CLK_OMAP_HSDIVIDER63(dpll_gmac_h12x2_ck, "dpll_gmac_x2_ck", &dpll_gmac_x2_ck, 0x0, DRA7XX_CM_DIV_H12_DPLL_GMAC, DRA7XX_DIVHS_0_5_MASK); DEFINE_CLK_OMAP_HSDIVIDER63(dpll_gmac_h13x2_ck, "dpll_gmac_x2_ck", &dpll_gmac_x2_ck, 0x0, DRA7XX_CM_DIV_H13_DPLL_GMAC, DRA7XX_DIVHS_0_5_MASK); DEFINE_CLK_OMAP_HSDIVIDER63(dpll_gmac_m3x2_ck, "dpll_gmac_x2_ck", &dpll_gmac_x2_ck, 0x0, DRA7XX_CM_DIV_M3_DPLL_GMAC, DRA7XX_DIVHS_MASK); static const char *dpll_per_x2_ck_parents[] = { "dpll_per_ck", }; static struct clk dpll_per_x2_ck; static struct clk_hw_omap dpll_per_x2_ck_hw = { .hw = { .clk = &dpll_per_x2_ck, }, }; DEFINE_STRUCT_CLK(dpll_per_x2_ck, dpll_per_x2_ck_parents, dpll_abe_x2_ck_ops); DEFINE_CLK_OMAP_HSDIVIDER63(dpll_per_h11x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, 0x0, DRA7XX_CM_DIV_H11_DPLL_PER, DRA7XX_DIVHS_0_5_MASK); DEFINE_CLK_OMAP_HSDIVIDER63(dpll_per_h12x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, 0x0, DRA7XX_CM_DIV_H12_DPLL_PER, DRA7XX_DIVHS_0_5_MASK); DEFINE_CLK_OMAP_HSDIVIDER63(dpll_per_h13x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, 0x0, DRA7XX_CM_DIV_H13_DPLL_PER, DRA7XX_DIVHS_0_5_MASK); DEFINE_CLK_OMAP_HSDIVIDER63(dpll_per_h14x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, 0x0, DRA7XX_CM_DIV_H14_DPLL_PER, DRA7XX_DIVHS_0_5_MASK); DEFINE_CLK_OMAP_HSDIVIDER63(dpll_per_m2x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, 0x0, DRA7XX_CM_DIV_M2_DPLL_PER, DRA7XX_DIVHS_MASK); static const char *dpll_usb_clkdcoldo_parents[] = { "dpll_usb_ck", }; static struct clk dpll_usb_clkdcoldo; static struct clk_hw_omap dpll_usb_clkdcoldo_hw = { .hw = { .clk = &dpll_usb_clkdcoldo, }, .clksel_reg = DRA7XX_CM_CLKDCOLDO_DPLL_USB, }; DEFINE_STRUCT_CLK(dpll_usb_clkdcoldo, dpll_usb_clkdcoldo_parents, apll_pcie_clkvcoldo_ops); static const char *eve_clk_parents[] = { "dpll_eve_m2_ck", "dpll_dsp_m3x2_ck", }; DEFINE_CLK_MUX(eve_clk, eve_clk_parents, NULL, 0x0, DRA7XX_CM_CLKSEL_EVE_CLK, DRA7XX_CLKSEL_0_0_SHIFT, DRA7XX_CLKSEL_0_0_WIDTH, 0x0, NULL); DEFINE_CLK_FIXED_FACTOR(func_128m_clk, "dpll_per_h11x2_ck", &dpll_per_h11x2_ck, 0x0, 1, 2); DEFINE_CLK_FIXED_FACTOR(func_12m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0, 1, 16); DEFINE_CLK_FIXED_FACTOR(func_24m_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1, 4); DEFINE_CLK_FIXED_FACTOR(func_48m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0, 1, 4); DEFINE_CLK_FIXED_FACTOR(func_96m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0, 1, 2); DEFINE_CLK_FIXED_FACTOR(gmii_m_clk_div, "dpll_gmac_h11x2_ck", &dpll_gmac_h11x2_ck, 0x0, 1, 2); static struct clk hdmi_clk2_div; static struct clk_hw_omap hdmi_clk2_div_hw = { .hw = { .clk = &hdmi_clk2_div, }, }; DEFINE_STRUCT_CLK(hdmi_clk2_div, hdmi_dclk_div_parents, apll_pcie_clkvcoldo_ops); static struct clk hdmi_div_clk; static struct clk_hw_omap hdmi_div_clk_hw = { .hw = { .clk = &hdmi_div_clk, }, }; DEFINE_STRUCT_CLK(hdmi_div_clk, hdmi_dclk_div_parents, apll_pcie_clkvcoldo_ops); DEFINE_CLK_MUX(hdmi_dpll_clk_mux, abe_dpll_sys_clk_mux_parents, NULL, 0x0, DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH, 0x0, NULL); static struct clk l3_iclk_div; static struct clk_hw_omap l3_iclk_div_hw = { .hw = { .clk = &l3_iclk_div, }, }; DEFINE_STRUCT_CLK(l3_iclk_div, mpu_dpll_hs_clk_div_parents, apll_pcie_clkvcoldo_ops); static const char *gpu_l3_iclk_parents[] = { "l3_iclk_div", }; static struct clk gpu_l3_iclk; static struct clk_hw_omap gpu_l3_iclk_hw = { .hw = { .clk = &gpu_l3_iclk, }, }; DEFINE_STRUCT_CLK(gpu_l3_iclk, gpu_l3_iclk_parents, apll_pcie_clkvcoldo_ops); static const struct clk_div_table l3init_60m_fclk_rates[] = { { .div = 1, .val = 0 }, { .div = 8, .val = 1 }, { .div = 0 }, }; DEFINE_CLK_DIVIDER_TABLE(l3init_60m_fclk, "dpll_usb_m2_ck", &dpll_usb_m2_ck, 0x0, DRA7XX_CM_CLKSEL_USB_60MHZ, DRA7XX_CLKSEL_0_0_SHIFT, DRA7XX_CLKSEL_0_0_WIDTH, 0x0, l3init_60m_fclk_rates, NULL); static const char *l4_root_clk_div_parents[] = { "l3_iclk_div", }; static struct clk l4_root_clk_div; static struct clk_hw_omap l4_root_clk_div_hw = { .hw = { .clk = &l4_root_clk_div, }, }; DEFINE_STRUCT_CLK(l4_root_clk_div, l4_root_clk_div_parents, apll_pcie_clkvcoldo_ops); DEFINE_CLK_DIVIDER(mlb_clk, "mlb_clkin_ck", &mlb_clkin_ck, 0x0, DRA7XX_CM_CLKSEL_MLB_MCASP, DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); DEFINE_CLK_DIVIDER(mlbp_clk, "mlbp_clkin_ck", &mlbp_clkin_ck, 0x0, DRA7XX_CM_CLKSEL_MLBP_MCASP, DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); DEFINE_CLK_DIVIDER(per_abe_x1_gfclk2_div, "dpll_abe_m2_ck", &dpll_abe_m2_ck, 0x0, DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX, DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); DEFINE_CLK_DIVIDER(timer_sys_clk_div, "sys_clkin1", &sys_clkin1, 0x0, DRA7XX_CM_CLKSEL_TIMER_SYS, DRA7XX_CLKSEL_0_0_SHIFT, DRA7XX_CLKSEL_0_0_WIDTH, 0x0, NULL); static const char *video1_clk2_div_parents[] = { "video1_clkin", }; static struct clk video1_clk2_div; static struct clk_hw_omap video1_clk2_div_hw = { .hw = { .clk = &video1_clk2_div, }, }; DEFINE_STRUCT_CLK(video1_clk2_div, video1_clk2_div_parents, apll_pcie_clkvcoldo_ops); static struct clk video1_div_clk; static struct clk_hw_omap video1_div_clk_hw = { .hw = { .clk = &video1_div_clk, }, }; DEFINE_STRUCT_CLK(video1_div_clk, video1_clk2_div_parents, apll_pcie_clkvcoldo_ops); DEFINE_CLK_MUX(video1_dpll_clk_mux, abe_dpll_sys_clk_mux_parents, NULL, 0x0, DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH, 0x0, NULL); static const char *video2_clk2_div_parents[] = { "video2_clkin", }; static struct clk video2_clk2_div; static struct clk_hw_omap video2_clk2_div_hw = { .hw = { .clk = &video2_clk2_div, }, }; DEFINE_STRUCT_CLK(video2_clk2_div, video2_clk2_div_parents, apll_pcie_clkvcoldo_ops); static struct clk video2_div_clk; static struct clk_hw_omap video2_div_clk_hw = { .hw = { .clk = &video2_div_clk, }, }; DEFINE_STRUCT_CLK(video2_div_clk, video2_clk2_div_parents, apll_pcie_clkvcoldo_ops); DEFINE_CLK_MUX(video2_dpll_clk_mux, abe_dpll_sys_clk_mux_parents, NULL, 0x0, DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH, 0x0, NULL); static const char *wkupaon_iclk_mux_parents[] = { "sys_clkin1", "abe_lp_clk_div", }; DEFINE_CLK_MUX(wkupaon_iclk_mux, wkupaon_iclk_mux_parents, NULL, 0x0, DRA7XX_CM_CLKSEL_WKUPAON, DRA7XX_CLKSEL_0_0_SHIFT, DRA7XX_CLKSEL_0_0_WIDTH, 0x0, NULL); /* Leaf clocks controlled by modules */ DEFINE_CLK_GATE(dss_32khz_clk, "sys_32k_ck", &sys_32k_ck, 0x0, DRA7XX_CM_DSS_DSS_CLKCTRL, DRA7XX_OPTFCLKEN_32KHZ_CLK_SHIFT, 0x0, NULL); DEFINE_CLK_GATE(dss_48mhz_clk, "func_48m_fclk", &func_48m_fclk, 0x0, DRA7XX_CM_DSS_DSS_CLKCTRL, DRA7XX_OPTFCLKEN_48MHZ_CLK_SHIFT, 0x0, NULL); DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_h12x2_ck", &dpll_per_h12x2_ck, 0x0, DRA7XX_CM_DSS_DSS_CLKCTRL, DRA7XX_OPTFCLKEN_DSSCLK_SHIFT, 0x0, NULL); DEFINE_CLK_GATE(dss_hdmi_clk, "hdmi_dpll_clk_mux", &hdmi_dpll_clk_mux, 0x0, DRA7XX_CM_DSS_DSS_CLKCTRL, DRA7XX_OPTFCLKEN_HDMI_CLK_SHIFT, 0x0, NULL); DEFINE_CLK_GATE(dss_video1_clk, "video1_dpll_clk_mux", &video1_dpll_clk_mux, 0x0, DRA7XX_CM_DSS_DSS_CLKCTRL, DRA7XX_OPTFCLKEN_VIDEO1_CLK_SHIFT, 0x0, NULL); DEFINE_CLK_GATE(dss_video2_clk, "video2_dpll_clk_mux", &video2_dpll_clk_mux, 0x0, DRA7XX_CM_DSS_DSS_CLKCTRL, DRA7XX_OPTFCLKEN_VIDEO2_CLK_SHIFT, 0x0, NULL); DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL, DRA7XX_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL); DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, DRA7XX_CM_L4PER_GPIO2_CLKCTRL, DRA7XX_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL); DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, DRA7XX_CM_L4PER_GPIO3_CLKCTRL, DRA7XX_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL); DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, DRA7XX_CM_L4PER_GPIO4_CLKCTRL, DRA7XX_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL); DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, DRA7XX_CM_L4PER_GPIO5_CLKCTRL, DRA7XX_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL); DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, DRA7XX_CM_L4PER_GPIO6_CLKCTRL, DRA7XX_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL); DEFINE_CLK_GATE(gpio7_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, DRA7XX_CM_L4PER_GPIO7_CLKCTRL, DRA7XX_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL); DEFINE_CLK_GATE(gpio8_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, DRA7XX_CM_L4PER_GPIO8_CLKCTRL, DRA7XX_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL); DEFINE_CLK_GATE(mmc1_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0, DRA7XX_CM_L3INIT_MMC1_CLKCTRL, DRA7XX_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL); DEFINE_CLK_GATE(mmc2_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0, DRA7XX_CM_L3INIT_MMC2_CLKCTRL, DRA7XX_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL); DEFINE_CLK_GATE(mmc3_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0, DRA7XX_CM_L4PER_MMC3_CLKCTRL, DRA7XX_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL); DEFINE_CLK_GATE(mmc4_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0, DRA7XX_CM_L4PER_MMC4_CLKCTRL, DRA7XX_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL); DEFINE_CLK_GATE(sata_ref_clk, "sys_clkin1", &sys_clkin1, 0x0, DRA7XX_CM_L3INIT_SATA_CLKCTRL, DRA7XX_OPTFCLKEN_REF_CLK_SHIFT, 0x0, NULL); DEFINE_CLK_GATE(usb_otg_ss1_refclk960m, "dpll_usb_clkdcoldo", &dpll_usb_clkdcoldo, 0x0, DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL, DRA7XX_OPTFCLKEN_REFCLK960M_SHIFT, 0x0, NULL); DEFINE_CLK_GATE(usb_otg_ss2_refclk960m, "dpll_usb_clkdcoldo", &dpll_usb_clkdcoldo, 0x0, DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL, DRA7XX_OPTFCLKEN_REFCLK960M_SHIFT, 0x0, NULL); DEFINE_CLK_GATE(usb_phy1_always_on_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0, DRA7XX_CM_COREAON_USB_PHY1_CORE_CLKCTRL, DRA7XX_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL); DEFINE_CLK_GATE(usb_phy2_always_on_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0, DRA7XX_CM_COREAON_USB_PHY2_CORE_CLKCTRL, DRA7XX_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL); DEFINE_CLK_GATE(usb_phy3_always_on_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0, DRA7XX_CM_COREAON_USB_PHY3_CORE_CLKCTRL, DRA7XX_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL); /* Remaining optional clocks */ static const char *atl_dpll_clk_mux_parents[] = { "sys_32k_ck", "video1_clkin", "video2_clkin", "hdmi_clkin", }; DEFINE_CLK_MUX(atl_dpll_clk_mux, atl_dpll_clk_mux_parents, NULL, 0x0, DRA7XX_CM_ATL_ATL_CLKCTRL, DRA7XX_CLKSEL_SOURCE1_SHIFT, DRA7XX_CLKSEL_SOURCE1_WIDTH, 0x0, NULL); static const char *atl_gfclk_mux_parents[] = { "l3_iclk_div", "dpll_abe_m2_ck", "atl_dpll_clk_mux", }; DEFINE_CLK_MUX(atl_gfclk_mux, atl_gfclk_mux_parents, NULL, 0x0, DRA7XX_CM_ATL_ATL_CLKCTRL, DRA7XX_CLKSEL_SOURCE2_SHIFT, DRA7XX_CLKSEL_SOURCE2_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(dcan1_sys_clk_mux, abe_dpll_sys_clk_mux_parents, NULL, 0x0, DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT, DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL); static const struct clk_div_table gmac_gmii_ref_clk_div_rates[] = { { .div = 2, .val = 0 }, { .div = 0 }, }; DEFINE_CLK_DIVIDER_TABLE(gmac_gmii_ref_clk_div, "dpll_gmac_m2_ck", &dpll_gmac_m2_ck, 0x0, DRA7XX_CM_GMAC_GMAC_CLKCTRL, DRA7XX_CLKSEL_REF_SHIFT, DRA7XX_CLKSEL_REF_WIDTH, 0x0, gmac_gmii_ref_clk_div_rates, NULL); static const char *gmac_rft_clk_mux_parents[] = { "video1_clkin", "video2_clkin", "dpll_abe_m2_ck", "hdmi_clkin", "l3_iclk_div", }; DEFINE_CLK_MUX(gmac_rft_clk_mux, gmac_rft_clk_mux_parents, NULL, 0x0, DRA7XX_CM_GMAC_GMAC_CLKCTRL, DRA7XX_CLKSEL_RFT_SHIFT, DRA7XX_CLKSEL_RFT_WIDTH, 0x0, NULL); static const char *gpu_core_gclk_mux_parents[] = { "dpll_core_h14x2_ck", "dpll_per_h14x2_ck", "dpll_gpu_m2_ck", }; DEFINE_CLK_MUX(gpu_core_gclk_mux, gpu_core_gclk_mux_parents, NULL, 0x0, DRA7XX_CM_GPU_GPU_CLKCTRL, DRA7XX_CLKSEL_CORE_CLK_SHIFT, DRA7XX_CLKSEL_CORE_CLK_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(gpu_hyd_gclk_mux, gpu_core_gclk_mux_parents, NULL, 0x0, DRA7XX_CM_GPU_GPU_CLKCTRL, DRA7XX_CLKSEL_HYD_CLK_SHIFT, DRA7XX_CLKSEL_HYD_CLK_WIDTH, 0x0, NULL); static const char *ipu1_gfclk_mux_parents[] = { "dpll_abe_m2x2_ck", "dpll_core_h22x2_ck", }; DEFINE_CLK_MUX(ipu1_gfclk_mux, ipu1_gfclk_mux_parents, NULL, 0x0, DRA7XX_CM_IPU1_IPU1_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT, DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL); static const struct clk_div_table l3instr_ts_gclk_div_rates[] = { { .div = 8, .val = 0 }, { .div = 16, .val = 1 }, { .div = 32, .val = 2 }, { .div = 0 }, }; DEFINE_CLK_DIVIDER_TABLE(l3instr_ts_gclk_div, "wkupaon_iclk_mux", &wkupaon_iclk_mux, 0x0, DRA7XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL, DRA7XX_CLKSEL_24_25_SHIFT, DRA7XX_CLKSEL_24_25_WIDTH, 0x0, l3instr_ts_gclk_div_rates, NULL); static const char *mcasp1_ahclkr_mux_parents[] = { "abe_24m_fclk", "abe_sys_clk_div", "func_24m_clk", "atlclkin3", "atl_clkin2", "atl_clkin1", "atl_clkin0", "sys_clkin2", "ref_clkin0", "ref_clkin1", "ref_clkin2", "ref_clkin3", "mlb_clk", "mlbp_clk", }; DEFINE_CLK_MUX(mcasp1_ahclkr_mux, mcasp1_ahclkr_mux_parents, NULL, 0x0, DRA7XX_CM_IPU_MCASP1_CLKCTRL, DRA7XX_CLKSEL_AHCLKR_SHIFT, DRA7XX_CLKSEL_AHCLKR_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(mcasp1_ahclkx_mux, mcasp1_ahclkr_mux_parents, NULL, 0x0, DRA7XX_CM_IPU_MCASP1_CLKCTRL, DRA7XX_CLKSEL_AHCLKX_SHIFT, DRA7XX_CLKSEL_AHCLKX_WIDTH, 0x0, NULL); static const char *mcasp1_aux_gfclk_mux_parents[] = { "per_abe_x1_gfclk2_div", "video1_clk2_div", "video2_clk2_div", "hdmi_clk2_div", }; DEFINE_CLK_MUX(mcasp1_aux_gfclk_mux, mcasp1_aux_gfclk_mux_parents, NULL, 0x0, DRA7XX_CM_IPU_MCASP1_CLKCTRL, DRA7XX_CLKSEL_AUX_CLK_SHIFT, DRA7XX_CLKSEL_AUX_CLK_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(mcasp2_ahclkr_mux, mcasp1_ahclkr_mux_parents, NULL, 0x0, DRA7XX_CM_L4PER2_MCASP2_CLKCTRL, DRA7XX_CLKSEL_AHCLKR_SHIFT, DRA7XX_CLKSEL_AHCLKR_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(mcasp2_ahclkx_mux, mcasp1_ahclkr_mux_parents, NULL, 0x0, DRA7XX_CM_L4PER2_MCASP2_CLKCTRL, DRA7XX_CLKSEL_AHCLKR_SHIFT, DRA7XX_CLKSEL_AHCLKR_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(mcasp2_aux_gfclk_mux, mcasp1_aux_gfclk_mux_parents, NULL, 0x0, DRA7XX_CM_L4PER2_MCASP2_CLKCTRL, DRA7XX_CLKSEL_AUX_CLK_SHIFT, DRA7XX_CLKSEL_AUX_CLK_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(mcasp3_ahclkx_mux, mcasp1_ahclkr_mux_parents, NULL, 0x0, DRA7XX_CM_L4PER2_MCASP3_CLKCTRL, DRA7XX_CLKSEL_AHCLKX_SHIFT, DRA7XX_CLKSEL_AHCLKX_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(mcasp3_aux_gfclk_mux, mcasp1_aux_gfclk_mux_parents, NULL, 0x0, DRA7XX_CM_L4PER2_MCASP3_CLKCTRL, DRA7XX_CLKSEL_AUX_CLK_SHIFT, DRA7XX_CLKSEL_AUX_CLK_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(mcasp4_ahclkx_mux, mcasp1_ahclkr_mux_parents, NULL, 0x0, DRA7XX_CM_L4PER2_MCASP4_CLKCTRL, DRA7XX_CLKSEL_AHCLKX_SHIFT, DRA7XX_CLKSEL_AHCLKX_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(mcasp4_aux_gfclk_mux, mcasp1_aux_gfclk_mux_parents, NULL, 0x0, DRA7XX_CM_L4PER2_MCASP4_CLKCTRL, DRA7XX_CLKSEL_AUX_CLK_SHIFT, DRA7XX_CLKSEL_AUX_CLK_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(mcasp5_ahclkx_mux, mcasp1_ahclkr_mux_parents, NULL, 0x0, DRA7XX_CM_L4PER2_MCASP5_CLKCTRL, DRA7XX_CLKSEL_AHCLKX_SHIFT, DRA7XX_CLKSEL_AHCLKX_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(mcasp5_aux_gfclk_mux, mcasp1_aux_gfclk_mux_parents, NULL, 0x0, DRA7XX_CM_L4PER2_MCASP5_CLKCTRL, DRA7XX_CLKSEL_AUX_CLK_SHIFT, DRA7XX_CLKSEL_AUX_CLK_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(mcasp6_ahclkx_mux, mcasp1_ahclkr_mux_parents, NULL, 0x0, DRA7XX_CM_L4PER2_MCASP6_CLKCTRL, DRA7XX_CLKSEL_AHCLKX_SHIFT, DRA7XX_CLKSEL_AHCLKX_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(mcasp6_aux_gfclk_mux, mcasp1_aux_gfclk_mux_parents, NULL, 0x0, DRA7XX_CM_L4PER2_MCASP6_CLKCTRL, DRA7XX_CLKSEL_AUX_CLK_SHIFT, DRA7XX_CLKSEL_AUX_CLK_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(mcasp7_ahclkx_mux, mcasp1_ahclkr_mux_parents, NULL, 0x0, DRA7XX_CM_L4PER2_MCASP7_CLKCTRL, DRA7XX_CLKSEL_AHCLKX_SHIFT, DRA7XX_CLKSEL_AHCLKX_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(mcasp7_aux_gfclk_mux, mcasp1_aux_gfclk_mux_parents, NULL, 0x0, DRA7XX_CM_L4PER2_MCASP7_CLKCTRL, DRA7XX_CLKSEL_AUX_CLK_SHIFT, DRA7XX_CLKSEL_AUX_CLK_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(mcasp8_ahclk_mux, mcasp1_ahclkr_mux_parents, NULL, 0x0, DRA7XX_CM_L4PER2_MCASP8_CLKCTRL, DRA7XX_CLKSEL_AUX_CLK_SHIFT, DRA7XX_CLKSEL_AUX_CLK_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(mcasp8_aux_gfclk_mux, mcasp1_aux_gfclk_mux_parents, NULL, 0x0, DRA7XX_CM_L4PER2_MCASP8_CLKCTRL, DRA7XX_CLKSEL_AHCLKX_SHIFT, DRA7XX_CLKSEL_AHCLKX_WIDTH, 0x0, NULL); static const char *mmc1_fclk_mux_parents[] = { "func_128m_clk", "dpll_per_m2x2_ck", }; DEFINE_CLK_MUX(mmc1_fclk_mux, mmc1_fclk_mux_parents, NULL, 0x0, DRA7XX_CM_L3INIT_MMC1_CLKCTRL, DRA7XX_CLKSEL_SOURCE_SHIFT, DRA7XX_CLKSEL_SOURCE_WIDTH, 0x0, NULL); DEFINE_CLK_DIVIDER(mmc1_fclk_div, "mmc1_fclk_mux", &mmc1_fclk_mux, 0x0, DRA7XX_CM_L3INIT_MMC1_CLKCTRL, DRA7XX_CLKSEL_DIV_SHIFT, DRA7XX_CLKSEL_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); DEFINE_CLK_MUX(mmc2_fclk_mux, mmc1_fclk_mux_parents, NULL, 0x0, DRA7XX_CM_L3INIT_MMC2_CLKCTRL, DRA7XX_CLKSEL_SOURCE_SHIFT, DRA7XX_CLKSEL_SOURCE_WIDTH, 0x0, NULL); DEFINE_CLK_DIVIDER(mmc2_fclk_div, "mmc2_fclk_mux", &mmc2_fclk_mux, 0x0, DRA7XX_CM_L3INIT_MMC2_CLKCTRL, DRA7XX_CLKSEL_DIV_SHIFT, DRA7XX_CLKSEL_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); static const char *mmc3_gfclk_mux_parents[] = { "func_48m_fclk", "dpll_per_m2x2_ck", }; DEFINE_CLK_MUX(mmc3_gfclk_mux, mmc3_gfclk_mux_parents, NULL, 0x0, DRA7XX_CM_L4PER_MMC3_CLKCTRL, DRA7XX_CLKSEL_MUX_SHIFT, DRA7XX_CLKSEL_MUX_WIDTH, 0x0, NULL); DEFINE_CLK_DIVIDER(mmc3_gfclk_div, "mmc3_gfclk_mux", &mmc3_gfclk_mux, 0x0, DRA7XX_CM_L4PER_MMC3_CLKCTRL, DRA7XX_CLKSEL_DIV_SHIFT, DRA7XX_CLKSEL_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); DEFINE_CLK_MUX(mmc4_gfclk_mux, mmc3_gfclk_mux_parents, NULL, 0x0, DRA7XX_CM_L4PER_MMC4_CLKCTRL, DRA7XX_CLKSEL_MUX_SHIFT, DRA7XX_CLKSEL_MUX_WIDTH, 0x0, NULL); DEFINE_CLK_DIVIDER(mmc4_gfclk_div, "mmc4_gfclk_mux", &mmc4_gfclk_mux, 0x0, DRA7XX_CM_L4PER_MMC4_CLKCTRL, DRA7XX_CLKSEL_DIV_SHIFT, DRA7XX_CLKSEL_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); static const char *qspi_gfclk_mux_parents[] = { "func_128m_clk", "dpll_per_h13x2_ck", }; DEFINE_CLK_MUX(qspi_gfclk_mux, qspi_gfclk_mux_parents, NULL, 0x0, DRA7XX_CM_L4PER2_QSPI_CLKCTRL, DRA7XX_CLKSEL_SOURCE_SHIFT, DRA7XX_CLKSEL_SOURCE_WIDTH, 0x0, NULL); DEFINE_CLK_DIVIDER(qspi_gfclk_div, "qspi_gfclk_mux", &qspi_gfclk_mux, 0x0, DRA7XX_CM_L4PER2_QSPI_CLKCTRL, DRA7XX_CLKSEL_DIV_SHIFT, DRA7XX_CLKSEL_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); static const char *timer10_gfclk_mux_parents[] = { "timer_sys_clk_div", "sys_32k_ck", "sys_clkin2", "ref_clkin0", "ref_clkin1", "ref_clkin2", "ref_clkin3", "abe_giclk_div", "video1_div_clk", "video2_div_clk", "hdmi_div_clk", }; DEFINE_CLK_MUX(timer10_gfclk_mux, timer10_gfclk_mux_parents, NULL, 0x0, DRA7XX_CM_L4PER_TIMER10_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT, DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(timer11_gfclk_mux, timer10_gfclk_mux_parents, NULL, 0x0, DRA7XX_CM_L4PER_TIMER11_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT, DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(timer13_gfclk_mux, timer10_gfclk_mux_parents, NULL, 0x0, DRA7XX_CM_L4PER3_TIMER13_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT, DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(timer14_gfclk_mux, timer10_gfclk_mux_parents, NULL, 0x0, DRA7XX_CM_L4PER3_TIMER14_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT, DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(timer15_gfclk_mux, timer10_gfclk_mux_parents, NULL, 0x0, DRA7XX_CM_L4PER3_TIMER15_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT, DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(timer16_gfclk_mux, timer10_gfclk_mux_parents, NULL, 0x0, DRA7XX_CM_L4PER3_TIMER16_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT, DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(timer1_gfclk_mux, timer10_gfclk_mux_parents, NULL, 0x0, DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT, DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(timer2_gfclk_mux, timer10_gfclk_mux_parents, NULL, 0x0, DRA7XX_CM_L4PER_TIMER2_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT, DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(timer3_gfclk_mux, timer10_gfclk_mux_parents, NULL, 0x0, DRA7XX_CM_L4PER_TIMER3_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT, DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(timer4_gfclk_mux, timer10_gfclk_mux_parents, NULL, 0x0, DRA7XX_CM_L4PER_TIMER4_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT, DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL); static const char *timer5_gfclk_mux_parents[] = { "timer_sys_clk_div", "sys_32k_ck", "sys_clkin2", "ref_clkin0", "ref_clkin1", "ref_clkin2", "ref_clkin3", "abe_giclk_div", "video1_div_clk", "video2_div_clk", "hdmi_div_clk", "clkoutmux0_clk_mux", }; DEFINE_CLK_MUX(timer5_gfclk_mux, timer5_gfclk_mux_parents, NULL, 0x0, DRA7XX_CM_IPU_TIMER5_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT, DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(timer6_gfclk_mux, timer5_gfclk_mux_parents, NULL, 0x0, DRA7XX_CM_IPU_TIMER6_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT, DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(timer7_gfclk_mux, timer5_gfclk_mux_parents, NULL, 0x0, DRA7XX_CM_IPU_TIMER7_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT, DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(timer8_gfclk_mux, timer5_gfclk_mux_parents, NULL, 0x0, DRA7XX_CM_IPU_TIMER8_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT, DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(timer9_gfclk_mux, timer10_gfclk_mux_parents, NULL, 0x0, DRA7XX_CM_L4PER_TIMER9_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT, DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(uart10_gfclk_mux, mmc3_gfclk_mux_parents, NULL, 0x0, DRA7XX_CM_WKUPAON_UART10_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT, DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(uart1_gfclk_mux, mmc3_gfclk_mux_parents, NULL, 0x0, DRA7XX_CM_L4PER_UART1_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT, DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(uart2_gfclk_mux, mmc3_gfclk_mux_parents, NULL, 0x0, DRA7XX_CM_L4PER_UART2_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT, DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(uart3_gfclk_mux, mmc3_gfclk_mux_parents, NULL, 0x0, DRA7XX_CM_L4PER_UART3_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT, DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(uart4_gfclk_mux, mmc3_gfclk_mux_parents, NULL, 0x0, DRA7XX_CM_L4PER_UART4_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT, DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(uart5_gfclk_mux, mmc3_gfclk_mux_parents, NULL, 0x0, DRA7XX_CM_L4PER_UART5_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT, DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(uart6_gfclk_mux, mmc3_gfclk_mux_parents, NULL, 0x0, DRA7XX_CM_IPU_UART6_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT, DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(uart7_gfclk_mux, mmc3_gfclk_mux_parents, NULL, 0x0, DRA7XX_CM_L4PER2_UART7_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT, DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(uart8_gfclk_mux, mmc3_gfclk_mux_parents, NULL, 0x0, DRA7XX_CM_L4PER2_UART8_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT, DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(uart9_gfclk_mux, mmc3_gfclk_mux_parents, NULL, 0x0, DRA7XX_CM_L4PER2_UART9_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT, DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL); static const char *vip1_gclk_mux_parents[] = { "l3_iclk_div", "dpll_core_h23x2_ck", }; DEFINE_CLK_MUX(vip1_gclk_mux, vip1_gclk_mux_parents, NULL, 0x0, DRA7XX_CM_CAM_VIP1_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT, DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(vip2_gclk_mux, vip1_gclk_mux_parents, NULL, 0x0, DRA7XX_CM_CAM_VIP2_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT, DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL); DEFINE_CLK_MUX(vip3_gclk_mux, vip1_gclk_mux_parents, NULL, 0x0, DRA7XX_CM_CAM_VIP3_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT, DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL); /* * clkdev */ static struct omap_clk dra7xx_clks[] = { CLK(NULL, "atl_clkin0_ck", &atl_clkin0_ck, CK_7XX), CLK(NULL, "atl_clkin1_ck", &atl_clkin1_ck, CK_7XX), CLK(NULL, "atl_clkin2_ck", &atl_clkin2_ck, CK_7XX), CLK(NULL, "atlclkin3_ck", &atlclkin3_ck, CK_7XX), CLK(NULL, "hdmi_clkin_ck", &hdmi_clkin_ck, CK_7XX), CLK(NULL, "mlb_clkin_ck", &mlb_clkin_ck, CK_7XX), CLK(NULL, "mlbp_clkin_ck", &mlbp_clkin_ck, CK_7XX), CLK(NULL, "pciesref_acs_clk_ck", &pciesref_acs_clk_ck, CK_7XX), CLK(NULL, "ref_clkin0_ck", &ref_clkin0_ck, CK_7XX), CLK(NULL, "ref_clkin1_ck", &ref_clkin1_ck, CK_7XX), CLK(NULL, "ref_clkin2_ck", &ref_clkin2_ck, CK_7XX), CLK(NULL, "ref_clkin3_ck", &ref_clkin3_ck, CK_7XX), CLK(NULL, "rmii_clk_ck", &rmii_clk_ck, CK_7XX), CLK(NULL, "sdvenc_clkin_ck", &sdvenc_clkin_ck, CK_7XX), CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_7XX), CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_7XX), CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_7XX), CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_7XX), CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_7XX), CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_7XX), CLK(NULL, "virt_20000000_ck", &virt_20000000_ck, CK_7XX), CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_7XX), CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_7XX), CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_7XX), CLK(NULL, "sys_clkin1", &sys_clkin1, CK_7XX), CLK(NULL, "sys_clkin2", &sys_clkin2, CK_7XX), CLK(NULL, "usb_otg_clkin_ck", &usb_otg_clkin_ck, CK_7XX), CLK(NULL, "video1_clkin_ck", &video1_clkin_ck, CK_7XX), CLK(NULL, "video1_m2_clkin_ck", &video1_m2_clkin_ck, CK_7XX), CLK(NULL, "video2_clkin_ck", &video2_clkin_ck, CK_7XX), CLK(NULL, "video2_m2_clkin_ck", &video2_m2_clkin_ck, CK_7XX), CLK(NULL, "abe_dpll_sys_clk_mux", &abe_dpll_sys_clk_mux, CK_7XX), CLK(NULL, "abe_dpll_bypass_clk_mux", &abe_dpll_bypass_clk_mux, CK_7XX), CLK(NULL, "abe_dpll_clk_mux", &abe_dpll_clk_mux, CK_7XX), CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_7XX), CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck, CK_7XX), CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_7XX), CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_7XX), CLK(NULL, "abe_clk", &abe_clk, CK_7XX), CLK(NULL, "aess_fclk", &aess_fclk, CK_7XX), CLK(NULL, "abe_giclk_div", &abe_giclk_div, CK_7XX), CLK(NULL, "abe_lp_clk_div", &abe_lp_clk_div, CK_7XX), CLK(NULL, "abe_sys_clk_div", &abe_sys_clk_div, CK_7XX), CLK(NULL, "adc_gfclk_mux", &adc_gfclk_mux, CK_7XX), CLK(NULL, "dpll_pcie_ref_ck", &dpll_pcie_ref_ck, CK_7XX), CLK(NULL, "dpll_pcie_ref_m2ldo_ck", &dpll_pcie_ref_m2ldo_ck, CK_7XX), CLK(NULL, "apll_pcie_ck", &apll_pcie_ck, CK_7XX), CLK(NULL, "apll_pcie_clkvcoldo", &apll_pcie_clkvcoldo, CK_7XX), CLK(NULL, "apll_pcie_clkvcoldo_div", &apll_pcie_clkvcoldo_div, CK_7XX), CLK(NULL, "apll_pcie_m2_ck", &apll_pcie_m2_ck, CK_7XX), CLK(NULL, "sys_clk1_dclk_div", &sys_clk1_dclk_div, CK_7XX), CLK(NULL, "sys_clk2_dclk_div", &sys_clk2_dclk_div, CK_7XX), CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_7XX), CLK(NULL, "per_abe_x1_dclk_div", &per_abe_x1_dclk_div, CK_7XX), CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, CK_7XX), CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_7XX), CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_7XX), CLK(NULL, "dpll_core_h12x2_ck", &dpll_core_h12x2_ck, CK_7XX), CLK(NULL, "mpu_dpll_hs_clk_div", &mpu_dpll_hs_clk_div, CK_7XX), CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_7XX), CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_7XX), CLK(NULL, "mpu_dclk_div", &mpu_dclk_div, CK_7XX), CLK(NULL, "dsp_dpll_hs_clk_div", &dsp_dpll_hs_clk_div, CK_7XX), CLK(NULL, "dpll_dsp_ck", &dpll_dsp_ck, CK_7XX), CLK(NULL, "dpll_dsp_m2_ck", &dpll_dsp_m2_ck, CK_7XX), CLK(NULL, "dsp_gclk_div", &dsp_gclk_div, CK_7XX), CLK(NULL, "iva_dpll_hs_clk_div", &iva_dpll_hs_clk_div, CK_7XX), CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_7XX), CLK(NULL, "dpll_iva_m2_ck", &dpll_iva_m2_ck, CK_7XX), CLK(NULL, "iva_dclk", &iva_dclk, CK_7XX), CLK(NULL, "dpll_gpu_ck", &dpll_gpu_ck, CK_7XX), CLK(NULL, "dpll_gpu_m2_ck", &dpll_gpu_m2_ck, CK_7XX), CLK(NULL, "gpu_dclk", &gpu_dclk, CK_7XX), CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_7XX), CLK(NULL, "core_dpll_out_dclk_div", &core_dpll_out_dclk_div, CK_7XX), CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck, CK_7XX), CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, CK_7XX), CLK(NULL, "emif_phy_dclk_div", &emif_phy_dclk_div, CK_7XX), CLK(NULL, "dpll_gmac_ck", &dpll_gmac_ck, CK_7XX), CLK(NULL, "dpll_gmac_m2_ck", &dpll_gmac_m2_ck, CK_7XX), CLK(NULL, "gmac_250m_dclk_div", &gmac_250m_dclk_div, CK_7XX), CLK(NULL, "video2_dclk_div", &video2_dclk_div, CK_7XX), CLK(NULL, "video1_dclk_div", &video1_dclk_div, CK_7XX), CLK(NULL, "hdmi_dclk_div", &hdmi_dclk_div, CK_7XX), CLK(NULL, "per_dpll_hs_clk_div", &per_dpll_hs_clk_div, CK_7XX), CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_7XX), CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_7XX), CLK(NULL, "func_96m_aon_dclk_div", &func_96m_aon_dclk_div, CK_7XX), CLK(NULL, "usb_dpll_hs_clk_div", &usb_dpll_hs_clk_div, CK_7XX), CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_7XX), CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_7XX), CLK(NULL, "l3init_480m_dclk_div", &l3init_480m_dclk_div, CK_7XX), CLK(NULL, "usb_otg_dclk_div", &usb_otg_dclk_div, CK_7XX), CLK(NULL, "sata_dclk_div", &sata_dclk_div, CK_7XX), CLK(NULL, "dpll_pcie_ref_m2_ck", &dpll_pcie_ref_m2_ck, CK_7XX), CLK(NULL, "pcie2_dclk_div", &pcie2_dclk_div, CK_7XX), CLK(NULL, "pcie_dclk_div", &pcie_dclk_div, CK_7XX), CLK(NULL, "emu_dclk_div", &emu_dclk_div, CK_7XX), CLK(NULL, "secure_32k_dclk_div", &secure_32k_dclk_div, CK_7XX), CLK(NULL, "eve_dpll_hs_clk_div", &eve_dpll_hs_clk_div, CK_7XX), CLK(NULL, "dpll_eve_ck", &dpll_eve_ck, CK_7XX), CLK(NULL, "dpll_eve_m2_ck", &dpll_eve_m2_ck, CK_7XX), CLK(NULL, "eve_dclk_div", &eve_dclk_div, CK_7XX), CLK(NULL, "clkoutmux0_clk_mux", &clkoutmux0_clk_mux, CK_7XX), CLK(NULL, "clkoutmux1_clk_mux", &clkoutmux1_clk_mux, CK_7XX), CLK(NULL, "clkoutmux2_clk_mux", &clkoutmux2_clk_mux, CK_7XX), CLK(NULL, "custefuse_sys_gfclk_div", &custefuse_sys_gfclk_div, CK_7XX), CLK(NULL, "dpll_core_h13x2_ck", &dpll_core_h13x2_ck, CK_7XX), CLK(NULL, "dpll_core_h14x2_ck", &dpll_core_h14x2_ck, CK_7XX), CLK(NULL, "dpll_core_h22x2_ck", &dpll_core_h22x2_ck, CK_7XX), CLK(NULL, "dpll_core_h23x2_ck", &dpll_core_h23x2_ck, CK_7XX), CLK(NULL, "dpll_core_h24x2_ck", &dpll_core_h24x2_ck, CK_7XX), CLK(NULL, "dpll_ddr_x2_ck", &dpll_ddr_x2_ck, CK_7XX), CLK(NULL, "dpll_ddr_h11x2_ck", &dpll_ddr_h11x2_ck, CK_7XX), CLK(NULL, "dpll_dsp_x2_ck", &dpll_dsp_x2_ck, CK_7XX), CLK(NULL, "dpll_dsp_m3x2_ck", &dpll_dsp_m3x2_ck, CK_7XX), CLK(NULL, "dpll_gmac_x2_ck", &dpll_gmac_x2_ck, CK_7XX), CLK(NULL, "dpll_gmac_h11x2_ck", &dpll_gmac_h11x2_ck, CK_7XX), CLK(NULL, "dpll_gmac_h12x2_ck", &dpll_gmac_h12x2_ck, CK_7XX), CLK(NULL, "dpll_gmac_h13x2_ck", &dpll_gmac_h13x2_ck, CK_7XX), CLK(NULL, "dpll_gmac_m3x2_ck", &dpll_gmac_m3x2_ck, CK_7XX), CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck, CK_7XX), CLK(NULL, "dpll_per_h11x2_ck", &dpll_per_h11x2_ck, CK_7XX), CLK(NULL, "dpll_per_h12x2_ck", &dpll_per_h12x2_ck, CK_7XX), CLK(NULL, "dpll_per_h13x2_ck", &dpll_per_h13x2_ck, CK_7XX), CLK(NULL, "dpll_per_h14x2_ck", &dpll_per_h14x2_ck, CK_7XX), CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_7XX), CLK(NULL, "dpll_usb_clkdcoldo", &dpll_usb_clkdcoldo, CK_7XX), CLK(NULL, "eve_clk", &eve_clk, CK_7XX), CLK(NULL, "func_128m_clk", &func_128m_clk, CK_7XX), CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_7XX), CLK(NULL, "func_24m_clk", &func_24m_clk, CK_7XX), CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_7XX), CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_7XX), CLK(NULL, "gmii_m_clk_div", &gmii_m_clk_div, CK_7XX), CLK(NULL, "hdmi_clk2_div", &hdmi_clk2_div, CK_7XX), CLK(NULL, "hdmi_div_clk", &hdmi_div_clk, CK_7XX), CLK(NULL, "hdmi_dpll_clk_mux", &hdmi_dpll_clk_mux, CK_7XX), CLK(NULL, "l3_iclk_div", &l3_iclk_div, CK_7XX), CLK(NULL, "gpu_l3_iclk", &gpu_l3_iclk, CK_7XX), CLK(NULL, "l3init_60m_fclk", &l3init_60m_fclk, CK_7XX), CLK(NULL, "l4_root_clk_div", &l4_root_clk_div, CK_7XX), CLK(NULL, "mlb_clk", &mlb_clk, CK_7XX), CLK(NULL, "mlbp_clk", &mlbp_clk, CK_7XX), CLK(NULL, "per_abe_x1_gfclk2_div", &per_abe_x1_gfclk2_div, CK_7XX), CLK(NULL, "timer_sys_clk_div", &timer_sys_clk_div, CK_7XX), CLK(NULL, "video1_clk2_div", &video1_clk2_div, CK_7XX), CLK(NULL, "video1_div_clk", &video1_div_clk, CK_7XX), CLK(NULL, "video1_dpll_clk_mux", &video1_dpll_clk_mux, CK_7XX), CLK(NULL, "video2_clk2_div", &video2_clk2_div, CK_7XX), CLK(NULL, "video2_div_clk", &video2_div_clk, CK_7XX), CLK(NULL, "video2_dpll_clk_mux", &video2_dpll_clk_mux, CK_7XX), CLK(NULL, "wkupaon_iclk_mux", &wkupaon_iclk_mux, CK_7XX), CLK(NULL, "dss_32khz_clk", &dss_32khz_clk, CK_7XX), CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_7XX), CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_7XX), CLK(NULL, "dss_hdmi_clk", &dss_hdmi_clk, CK_7XX), CLK(NULL, "dss_video1_clk", &dss_video1_clk, CK_7XX), CLK(NULL, "dss_video2_clk", &dss_video2_clk, CK_7XX), CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_7XX), CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_7XX), CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_7XX), CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_7XX), CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_7XX), CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_7XX), CLK(NULL, "gpio7_dbclk", &gpio7_dbclk, CK_7XX), CLK(NULL, "gpio8_dbclk", &gpio8_dbclk, CK_7XX), CLK(NULL, "mmc1_clk32k", &mmc1_clk32k, CK_7XX), CLK(NULL, "mmc2_clk32k", &mmc2_clk32k, CK_7XX), CLK(NULL, "mmc3_clk32k", &mmc3_clk32k, CK_7XX), CLK(NULL, "mmc4_clk32k", &mmc4_clk32k, CK_7XX), CLK(NULL, "sata_ref_clk", &sata_ref_clk, CK_7XX), CLK(NULL, "usb_otg_ss1_refclk960m", &usb_otg_ss1_refclk960m, CK_7XX), CLK(NULL, "usb_otg_ss2_refclk960m", &usb_otg_ss2_refclk960m, CK_7XX), CLK(NULL, "usb_phy1_always_on_clk32k", &usb_phy1_always_on_clk32k, CK_7XX), CLK(NULL, "usb_phy2_always_on_clk32k", &usb_phy2_always_on_clk32k, CK_7XX), CLK(NULL, "usb_phy3_always_on_clk32k", &usb_phy3_always_on_clk32k, CK_7XX), CLK(NULL, "atl_dpll_clk_mux", &atl_dpll_clk_mux, CK_7XX), CLK(NULL, "atl_gfclk_mux", &atl_gfclk_mux, CK_7XX), CLK(NULL, "dcan1_sys_clk_mux", &dcan1_sys_clk_mux, CK_7XX), CLK(NULL, "gmac_gmii_ref_clk_div", &gmac_gmii_ref_clk_div, CK_7XX), CLK(NULL, "gmac_rft_clk_mux", &gmac_rft_clk_mux, CK_7XX), CLK(NULL, "gpu_core_gclk_mux", &gpu_core_gclk_mux, CK_7XX), CLK(NULL, "gpu_hyd_gclk_mux", &gpu_hyd_gclk_mux, CK_7XX), CLK(NULL, "ipu1_gfclk_mux", &ipu1_gfclk_mux, CK_7XX), CLK(NULL, "l3instr_ts_gclk_div", &l3instr_ts_gclk_div, CK_7XX), CLK(NULL, "mcasp1_ahclkr_mux", &mcasp1_ahclkr_mux, CK_7XX), CLK(NULL, "mcasp1_ahclkx_mux", &mcasp1_ahclkx_mux, CK_7XX), CLK(NULL, "mcasp1_aux_gfclk_mux", &mcasp1_aux_gfclk_mux, CK_7XX), CLK(NULL, "mcasp2_ahclkr_mux", &mcasp2_ahclkr_mux, CK_7XX), CLK(NULL, "mcasp2_ahclkx_mux", &mcasp2_ahclkx_mux, CK_7XX), CLK(NULL, "mcasp2_aux_gfclk_mux", &mcasp2_aux_gfclk_mux, CK_7XX), CLK(NULL, "mcasp3_ahclkx_mux", &mcasp3_ahclkx_mux, CK_7XX), CLK(NULL, "mcasp3_aux_gfclk_mux", &mcasp3_aux_gfclk_mux, CK_7XX), CLK(NULL, "mcasp4_ahclkx_mux", &mcasp4_ahclkx_mux, CK_7XX), CLK(NULL, "mcasp4_aux_gfclk_mux", &mcasp4_aux_gfclk_mux, CK_7XX), CLK(NULL, "mcasp5_ahclkx_mux", &mcasp5_ahclkx_mux, CK_7XX), CLK(NULL, "mcasp5_aux_gfclk_mux", &mcasp5_aux_gfclk_mux, CK_7XX), CLK(NULL, "mcasp6_ahclkx_mux", &mcasp6_ahclkx_mux, CK_7XX), CLK(NULL, "mcasp6_aux_gfclk_mux", &mcasp6_aux_gfclk_mux, CK_7XX), CLK(NULL, "mcasp7_ahclkx_mux", &mcasp7_ahclkx_mux, CK_7XX), CLK(NULL, "mcasp7_aux_gfclk_mux", &mcasp7_aux_gfclk_mux, CK_7XX), CLK(NULL, "mcasp8_ahclk_mux", &mcasp8_ahclk_mux, CK_7XX), CLK(NULL, "mcasp8_aux_gfclk_mux", &mcasp8_aux_gfclk_mux, CK_7XX), CLK(NULL, "mmc1_fclk_mux", &mmc1_fclk_mux, CK_7XX), CLK(NULL, "mmc1_fclk_div", &mmc1_fclk_div, CK_7XX), CLK(NULL, "mmc2_fclk_mux", &mmc2_fclk_mux, CK_7XX), CLK(NULL, "mmc2_fclk_div", &mmc2_fclk_div, CK_7XX), CLK(NULL, "mmc3_gfclk_mux", &mmc3_gfclk_mux, CK_7XX), CLK(NULL, "mmc3_gfclk_div", &mmc3_gfclk_div, CK_7XX), CLK(NULL, "mmc4_gfclk_mux", &mmc4_gfclk_mux, CK_7XX), CLK(NULL, "mmc4_gfclk_div", &mmc4_gfclk_div, CK_7XX), CLK(NULL, "qspi_gfclk_mux", &qspi_gfclk_mux, CK_7XX), CLK(NULL, "qspi_gfclk_div", &qspi_gfclk_div, CK_7XX), CLK(NULL, "timer10_gfclk_mux", &timer10_gfclk_mux, CK_7XX), CLK(NULL, "timer11_gfclk_mux", &timer11_gfclk_mux, CK_7XX), CLK(NULL, "timer13_gfclk_mux", &timer13_gfclk_mux, CK_7XX), CLK(NULL, "timer14_gfclk_mux", &timer14_gfclk_mux, CK_7XX), CLK(NULL, "timer15_gfclk_mux", &timer15_gfclk_mux, CK_7XX), CLK(NULL, "timer16_gfclk_mux", &timer16_gfclk_mux, CK_7XX), CLK(NULL, "timer1_gfclk_mux", &timer1_gfclk_mux, CK_7XX), CLK(NULL, "timer2_gfclk_mux", &timer2_gfclk_mux, CK_7XX), CLK(NULL, "timer3_gfclk_mux", &timer3_gfclk_mux, CK_7XX), CLK(NULL, "timer4_gfclk_mux", &timer4_gfclk_mux, CK_7XX), CLK(NULL, "timer5_gfclk_mux", &timer5_gfclk_mux, CK_7XX), CLK(NULL, "timer6_gfclk_mux", &timer6_gfclk_mux, CK_7XX), CLK(NULL, "timer7_gfclk_mux", &timer7_gfclk_mux, CK_7XX), CLK(NULL, "timer8_gfclk_mux", &timer8_gfclk_mux, CK_7XX), CLK(NULL, "timer9_gfclk_mux", &timer9_gfclk_mux, CK_7XX), CLK(NULL, "uart10_gfclk_mux", &uart10_gfclk_mux, CK_7XX), CLK(NULL, "uart1_gfclk_mux", &uart1_gfclk_mux, CK_7XX), CLK(NULL, "uart2_gfclk_mux", &uart2_gfclk_mux, CK_7XX), CLK(NULL, "uart3_gfclk_mux", &uart3_gfclk_mux, CK_7XX), CLK(NULL, "uart4_gfclk_mux", &uart4_gfclk_mux, CK_7XX), CLK(NULL, "uart5_gfclk_mux", &uart5_gfclk_mux, CK_7XX), CLK(NULL, "uart6_gfclk_mux", &uart6_gfclk_mux, CK_7XX), CLK(NULL, "uart7_gfclk_mux", &uart7_gfclk_mux, CK_7XX), CLK(NULL, "uart8_gfclk_mux", &uart8_gfclk_mux, CK_7XX), CLK(NULL, "uart9_gfclk_mux", &uart9_gfclk_mux, CK_7XX), CLK(NULL, "vip1_gclk_mux", &vip1_gclk_mux, CK_7XX), CLK(NULL, "vip2_gclk_mux", &vip2_gclk_mux, CK_7XX), CLK(NULL, "vip3_gclk_mux", &vip3_gclk_mux, CK_7XX), CLK(NULL, "gpmc_ck", &dummy_ck, CK_7XX), CLK("omap_i2c.1", "ick", &dummy_ck, CK_7XX), CLK("omap_i2c.2", "ick", &dummy_ck, CK_7XX), CLK("omap_i2c.3", "ick", &dummy_ck, CK_7XX), CLK("omap_i2c.4", "ick", &dummy_ck, CK_7XX), CLK(NULL, "mailboxes_ick", &dummy_ck, CK_7XX), CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_7XX), CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_7XX), CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_7XX), CLK("omap_hsmmc.3", "ick", &dummy_ck, CK_7XX), CLK("omap_hsmmc.4", "ick", &dummy_ck, CK_7XX), CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_7XX), CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_7XX), CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_7XX), CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_7XX), CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_7XX), CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_7XX), CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_7XX), CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_7XX), CLK(NULL, "uart1_ick", &dummy_ck, CK_7XX), CLK(NULL, "uart2_ick", &dummy_ck, CK_7XX), CLK(NULL, "uart3_ick", &dummy_ck, CK_7XX), CLK(NULL, "uart4_ick", &dummy_ck, CK_7XX), CLK("usbhs_omap", "usbhost_ick", &dummy_ck, CK_7XX), CLK("usbhs_omap", "usbtll_fck", &dummy_ck, CK_7XX), CLK("omap_wdt", "ick", &dummy_ck, CK_7XX), CLK(NULL, "timer_32k_ck", &sys_32k_ck, CK_7XX), CLK("4ae18000.timer", "timer_sys_ck", &sys_clkin2, CK_7XX), CLK("48032000.timer", "timer_sys_ck", &sys_clkin2, CK_7XX), CLK("48034000.timer", "timer_sys_ck", &sys_clkin2, CK_7XX), CLK("48036000.timer", "timer_sys_ck", &sys_clkin2, CK_7XX), CLK("4803e000.timer", "timer_sys_ck", &sys_clkin2, CK_7XX), CLK("48086000.timer", "timer_sys_ck", &sys_clkin2, CK_7XX), CLK("48088000.timer", "timer_sys_ck", &sys_clkin2, CK_7XX), CLK("48820000.timer", "timer_sys_ck", &timer_sys_clk_div, CK_7XX), CLK("48822000.timer", "timer_sys_ck", &timer_sys_clk_div, CK_7XX), CLK("48824000.timer", "timer_sys_ck", &timer_sys_clk_div, CK_7XX), CLK("48826000.timer", "timer_sys_ck", &timer_sys_clk_div, CK_7XX), CLK(NULL, "sys_clkin", &sys_clkin1, CK_7XX), }; /* * Prepare and enable a list of clocks. * XXX Deprecated: Only needed until these clocks are properly claimed * and enabled by the drivers or core code thats uses them. */ static const char *enable_init_clks[] = { }; static struct reparent_init_clks reparent_clks[] = { { .name = "abe_dpll_sys_clk_mux", .parent = "sys_clkin2" }, }; static struct rate_init_clks rate_clks[] = { { .name = "dpll_abe_ck", .rate = DRA7_DPLL_ABE_DEFFREQ }, { .name = "dpll_gmac_ck", .rate = DRA7_DPLL_GMAC_DEFFREQ }, }; int __init dra7xx_clk_init(void) { u32 cpu_clkflg; struct omap_clk *c; if (soc_is_dra7xx()) { cpu_mask = RATE_IN_7XX; cpu_clkflg = CK_7XX; } /* * Must stay commented until all OMAP SoC drivers are * converted to runtime PM, or drivers may start crashing * * omap2_clk_disable_clkdm_control(); */ for (c = dra7xx_clks; c < dra7xx_clks + ARRAY_SIZE(dra7xx_clks); c++) { if (c->cpu & cpu_clkflg) { clkdev_add(&c->lk); if (!__clk_init(NULL, c->lk.clk)) omap2_init_clk_hw_omap_clocks(c->lk.clk); } } omap2_clk_disable_autoidle_all(); omap2_clk_reparent_init_clocks(reparent_clks, ARRAY_SIZE(reparent_clks)); omap2_clk_rate_init_clocks(rate_clks, ARRAY_SIZE(rate_clks)); omap2_clk_enable_init_clocks(enable_init_clks, ARRAY_SIZE(enable_init_clks)); return 0; }