Merge branch 'p-ti-linux-3.8.y' into p-ti-android-3.8.y

[android-sdk/kernel-video.git] / arch / arm / boot / compressed / head.S

diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index fe4d9c3ad761c8dfaadce6e214d709417947f396..0ccfd668bd8fd2cde51ad96dc79116e27837142a 100644 (file)
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -548,6 +548,7 @@ cache_on:   mov     r3, #8                  @ cache_on function
  * to cover all 32bit address and cacheable and bufferable.
  */
 __armv4_mpu_cache_on:
+               .arch armv4
                mov     r0, #0x3f               @ 4G, the whole
                mcr     p15, 0, r0, c6, c7, 0   @ PR7 Area Setting
                mcr     p15, 0, r0, c6, c7, 1
@@ -655,6 +656,7 @@ ENDPROC(__setup_mmu)
 @ Enable unaligned access on v6, to allow better code generation
 @ for the decompressor C code:
 __armv6_mmu_cache_on:
+               .arch armv6
                mrc     p15, 0, r0, c1, c0, 0   @ read SCTLR
                bic     r0, r0, #2              @ A (no unaligned access fault)
                orr     r0, r0, #1 << 22        @ U (v6 unaligned access model)
@@ -663,11 +665,13 @@ __armv6_mmu_cache_on:
 
 __arm926ejs_mmu_cache_on:
 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+               .arch armv5
                mov     r0, #4                  @ put dcache in WT mode
                mcr     p15, 7, r0, c15, c0, 0
 #endif
 
 __armv4_mmu_cache_on:
+               .arch armv4
                mov     r12, lr
 #ifdef CONFIG_MMU
                mov     r6, #CB_BITS | 0x12     @ U
@@ -688,6 +692,7 @@ __armv4_mmu_cache_on:
                mov     pc, r12
 
 __armv7_mmu_cache_on:
+               .arch armv7-a
                mov     r12, lr
 #ifdef CONFIG_MMU
                mrc     p15, 0, r11, c0, c1, 4  @ read ID_MMFR0
@@ -716,6 +721,7 @@ __armv7_mmu_cache_on:
                bic     r6, r6, #1 << 31        @ 32-bit translation system
                bic     r6, r6, #3 << 0         @ use only ttbr0
                mcrne   p15, 0, r3, c2, c0, 0   @ load page table pointer
+               mcrne   p15, 0, r0, c8, c7, 0   @ flush I,D TLBs
                mcrne   p15, 0, r1, c3, c0, 0   @ load domain access control
                mcrne   p15, 0, r6, c2, c0, 2   @ load ttb control
 #endif
@@ -805,6 +811,8 @@ call_cache_fn:      adr     r12, proc_types
                .align  2
                .type   proc_types,#object
 proc_types:
+#if !defined(CONFIG_CPU_V7)
+               /* This collides with some V7 IDs, preventing correct detection */
                .word   0x00000000              @ old ARM ID
                .word   0x0000f000
                mov     pc, lr
@@ -813,6 +821,7 @@ proc_types:
  THUMB(                nop                             )
                mov     pc, lr
  THUMB(                nop                             )
+#endif
 
                .word   0x41007000              @ ARM7/710
                .word   0xfff8fe00
@@ -1031,6 +1040,7 @@ cache_clean_flush:
                mov     r3, #16
                b       call_cache_fn
 
+               .arch armv4
 __armv4_mpu_cache_flush:
                mov     r2, #1
                mov     r3, #0
@@ -1056,6 +1066,7 @@ __fa526_cache_flush:
                mov     pc, lr
 
 __armv6_mmu_cache_flush:
+               .arch armv6
                mov     r1, #0
                mcr     p15, 0, r1, c7, c14, 0  @ clean+invalidate D
                mcr     p15, 0, r1, c7, c5, 0   @ invalidate I+BTB
@@ -1063,6 +1074,7 @@ __armv6_mmu_cache_flush:
                mcr     p15, 0, r1, c7, c10, 4  @ drain WB
                mov     pc, lr
 
+               .arch armv7-a
 __armv7_mmu_cache_flush:
                mrc     p15, 0, r10, c0, c1, 5  @ read ID_MMFR1
                tst     r10, #0xf << 16         @ hierarchical cache (ARMv7)
@@ -1123,6 +1135,7 @@ iflush:
                mcr     p15, 0, r10, c7, c5, 4  @ ISB
                mov     pc, lr
 
+               .arch armv5
 __armv5tej_mmu_cache_flush:
 1:             mrc     p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
                bne     1b
@@ -1130,6 +1143,7 @@ __armv5tej_mmu_cache_flush:
                mcr     p15, 0, r0, c7, c10, 4  @ drain WB
                mov     pc, lr
 
+               .arch armv4
 __armv4_mmu_cache_flush:
                mov     r2, #64*1024            @ default: 32K dcache size (*2)
                mov     r11, #32                @ default: 32 byte line size
@@ -1168,6 +1182,8 @@ __armv3_mpu_cache_flush:
                mcr     p15, 0, r1, c7, c0, 0   @ invalidate whole cache v3
                mov     pc, lr
 
+               .arch armv4
+
 /*
  * Various debugging routines for printing hex characters and
  * memory, which again must be relocatable.