index cfe509134d4ae80d36940d4e15a8f8e3b0735dcb..bae190a9d1f7414829cee94097c1152fba6af807 100644 (file)
/dts-v1/;
#include "dra74x.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clk/ti-dra7-atl.h>
/ {
model = "TI DRA742";
reg = <0x80000000 0x60000000>; /* 1536 MB */
};
- reserved-memory {
+ reserved_mem: reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
};
};
+ extcon_usb1: extcon_usb1 {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpios = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ extcon_usb2: extcon_usb2 {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpios = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ evm_3v3_sd: fixedregulator-sd {
+ compatible = "regulator-fixed";
+ regulator-name = "evm_3v3_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&pcf_gpio_21 5 0>;
+ };
+
evm_3v3_sw: fixedregulator-evm_3v3_sw {
compatible = "regulator-fixed";
regulator-name = "evm_3v3_sw";
regulator-max-microvolt = <3300000>;
};
+ aic_dvdd: fixedregulator-aic_dvdd {
+ /* TPS77018DBVT */
+ compatible = "regulator-fixed";
+ regulator-name = "aic_dvdd";
+ vin-supply = <&evm_3v3_sw>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vmmcwl_fixed: fixedregulator-mmcwl {
+ compatible = "regulator-fixed";
+ regulator-name = "vmmcwl_fixed";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&gpio5 8 0>; /* gpio5_8 */
+ startup-delay-us = <70000>;
+ enable-active-high;
+ };
+
+ kim {
+ compatible = "kim";
+ nshutdown_gpio = <132>;
+ dev_name = "/dev/ttyS2";
+ flow_cntrl = <1>;
+ baud_rate = <3686400>;
+ };
+
+ btwilink {
+ compatible = "btwilink";
+ };
+
vtt_fixed: fixedregulator-vtt {
compatible = "regulator-fixed";
regulator-name = "vtt_fixed";
vin-supply = <&sysen2>;
gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
};
+
+ aliases {
+ display0 = &hdmi0;
+ sound0 = &primary_sound;
+ sound1 = &hdmi;
+ };
+
+ hdmi0: connector@1 {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&tpd12s015_out>;
+ };
+ };
+ };
+
+ tpd12s015: encoder@1 {
+ compatible = "ti,dra7evm-tpd12s015";
+
+ pinctrl-names = "i2c", "ddc";
+ pinctrl-0 = <&hdmi_i2c_sel_pin &hdmi_i2c_pins_i2c>;
+ pinctrl-1 = <&hdmi_i2c_sel_pin &hdmi_i2c_pins_ddc>;
+
+ ddc-i2c-bus = <&i2c2>;
+ mcasp-gpio = <&mcasp8>;
+
+ gpios = <&pcf_hdmi 4 0>, /* P4, CT CP HPD */
+ <&pcf_hdmi 5 0>, /* P5, LS OE */
+ <&gpio7 12 0>; /* gpio7_12/sp1_cs2, HPD */
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tpd12s015_in: endpoint@0 {
+ remote-endpoint = <&hdmi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tpd12s015_out: endpoint@0 {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
+
+ ocp {
+ gpu: gpu@0x56000000 {
+ gpu0-voltdm = <&voltdm_gpu>;
+ };
+ };
+
+ primary_sound: primary_sound {
+ compatible = "ti,dra7xx-evm-audio";
+ ti,model = "DRA7xx-EVM";
+ ti,always-on;
+ ti,audio-codec = <&tlv320aic3106>;
+ ti,mcasp-controller = <&mcasp3>;
+ ti,codec-clock-rate = <11289600>;
+ clocks = <&atl_clkin2_ck>;
+ clock-names = "mclk";
+ ti,audio-routing =
+ "Headphone Jack", "HPLOUT",
+ "Headphone Jack", "HPROUT",
+ "Line Out", "LLOUT",
+ "Line Out", "RLOUT",
+ "MIC3L", "Mic Jack",
+ "MIC3R", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "LINE1L", "Line In",
+ "LINE1R", "Line In";
+ };
+
+ btwilink_sound: btwilink_sound {
+ #sound-dai-cells = <0>;
+ compatible = "linux,bt-sco-audio";
+ status = "okay";
+ };
+
+ simple_bt_sco_card: bt_sco_card {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "DRA7xx-WiLink";
+ simple-audio-card,format = "dsp_a";
+ simple-audio-card,frame-master = <&btwilink_codec>;
+ simple-audio-card,bitclock-master = <&btwilink_codec>;
+ simple-audio-card,frame-inversion;
+
+ simple-audio-card,cpu {
+ sound-dai = <&mcasp7>;
+ };
+
+ btwilink_codec: simple-audio-card,codec {
+ sound-dai = <&btwilink_sound>;
+ };
+ };
};
&dra7_pmx_core {
+ hdmi_i2c_sel_pin: pinmux_hdmi_i2c_sel_pin {
+ pinctrl-single,pins = <
+ /* this pin is used as a GPIO via mcasp */
+ 0x2fc (PIN_OUTPUT | MUX_MODE1) /* mcasp8_axr2 */
+ >;
+ };
+
+ hdmi_i2c_pins_i2c: pinmux_hdmi_i2c_pins_default {
+ pinctrl-single,pins = <
+ 0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */
+ 0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */
+ >;
+ };
+
+ hdmi_i2c_pins_ddc: pinmux_hdmi_i2c_pins_ddc {
+ pinctrl-single,pins = <
+ 0x408 (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
+ 0x40c (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
+ >;
+ };
+
+ dcan1_pins_default: dcan1_pins_default {
+ pinctrl-single,pins = <
+ 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
+ 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
+ >;
+ };
+
+ dcan1_pins_sleep: dcan1_pins_sleep {
+ pinctrl-single,pins = <
+ 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
+ 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
+ >;
+ };
+
+ mmc1_pins_default: pinmux_mmc1_default_pins {
+ pinctrl-single,pins = <
+ 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
+ 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+ 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+ 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+ 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+ 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+ 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio187 */
+ >;
+ };
+
+ mmc1_pins_sdr12: pinmux_mmc1_sdr12_pins {
+ pinctrl-single,pins = <
+ 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
+ 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+ 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+ 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+ 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+ 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_hs: pinmux_mmc1_hs_pins {
+ pinctrl-single,pins = <
+ 0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
+ 0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
+ 0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
+ 0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
+ 0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */
+ 0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_sdr25: pinmux_mmc1_sdr25_pins {
+ pinctrl-single,pins = <
+ 0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
+ 0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
+ 0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
+ 0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
+ 0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */
+ 0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_ddr50: pinmux_mmc1_ddr50_pins {
+ pinctrl-single,pins = <
+ 0x354 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_clk.clk */
+ 0x358 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_cmd.cmd */
+ 0x35c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat0.dat0 */
+ 0x360 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat1.dat1 */
+ 0x364 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat2.dat2 */
+ 0x368 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc2_pins_default: mmc2_pins_default {
+ pinctrl-single,pins = <
+ 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+
+ mmc2_pins_hs: pinmux_mmc2_hs_pins {
+ pinctrl-single,pins = <
+ 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+
+ mmc2_pins_ddr_3_3v: pinmux_mmc2_ddr_3_3v_pins {
+ pinctrl-single,pins = <
+ 0x9c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ 0xb0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ 0xa0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ 0xa4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ 0xa8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ 0xac (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ 0x8c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ 0x90 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ 0x94 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ 0x98 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+};
+
+&dra7_iodelay_core {
+ mmc1_iodelay_ddr50_conf: mmc1_iodelay_ddr50_conf {
+ pinctrl-single,pins = <
+ 0x618 (A_DELAY(572) | G_DELAY(540)) /* CFG_MMC1_CLK_IN */
+ 0x624 (A_DELAY(0) | G_DELAY(600)) /* CFG_MMC1_CMD_IN */
+ 0x630 (A_DELAY(403) | G_DELAY(120)) /* CFG_MMC1_DAT0_IN */
+ 0x63c (A_DELAY(23) | G_DELAY(60)) /* CFG_MMC1_DAT1_IN */
+ 0x648 (A_DELAY(25) | G_DELAY(60)) /* CFG_MMC1_DAT2_IN */
+ 0x654 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_IN */
+ 0x620 (A_DELAY(1525) | G_DELAY(0)) /* CFG_MMC1_CLK_IN */
+ 0x628 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OEN */
+ 0x62c (A_DELAY(55) | G_DELAY(0)) /* CFG_MMC1_CMD_OUT */
+ 0x634 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OEN */
+ 0x638 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OUT */
+ 0x640 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OEN */
+ 0x644 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OUT */
+ 0x64c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OEN */
+ 0x650 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OUT */
+ 0x658 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OEN */
+ 0x65c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OUT */
+ >;
+ };
+
+ mmc2_iodelay_ddr_3_3v_conf: mmc2_iodelay_ddr_3_3v_conf {
+ pinctrl-single,pins = <
+ 0x18c (A_DELAY(0) | G_DELAY(120)) /* CFG_GPMC_A19_IN */
+ 0x1a4 (A_DELAY(265) | G_DELAY(360)) /* CFG_GPMC_A20_IN */
+ 0x1b0 (A_DELAY(0) | G_DELAY(120)) /* CFG_GPMC_A21_IN */
+ 0x1bc (A_DELAY(0) | G_DELAY(120)) /* CFG_GPMC_A22_IN */
+ 0x1c8 (A_DELAY(287) | G_DELAY(420)) /* CFG_GPMC_A23_IN */
+ 0x1d4 (A_DELAY(144) | G_DELAY(240)) /* CFG_GPMC_A24_IN */
+ 0x1e0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_IN */
+ 0x1ec (A_DELAY(0) | G_DELAY(120)) /* CFG_GPMC_A26_IN */
+ 0x1f8 (A_DELAY(120) | G_DELAY(180)) /* CFG_GPMC_A27_IN */
+ 0x360 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_IN */
+ 0x190 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A19_OEN */
+ 0x194 (A_DELAY(174) | G_DELAY(0)) /* CFG_GPMC_A19_OUT */
+ 0x1a8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A20_OEN */
+ 0x1ac (A_DELAY(168) | G_DELAY(0)) /* CFG_GPMC_A20_OUT */
+ 0x1b4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A21_OEN */
+ 0x1b8 (A_DELAY(136) | G_DELAY(0)) /* CFG_GPMC_A21_OUT */
+ 0x1c0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A22_OEN */
+ 0x1c4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A22_OUT */
+ 0x1d0 (A_DELAY(879) | G_DELAY(0)) /* CFG_GPMC_A23_OUT */
+ 0x1d8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OEN */
+ 0x1dc (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OUT */
+ 0x1e4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_OEN */
+ 0x1e8 (A_DELAY(34) | G_DELAY(0)) /* CFG_GPMC_A25_OUT */
+ 0x1f0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A26_OEN */
+ 0x1f4 (A_DELAY(120) | G_DELAY(0)) /* CFG_GPMC_A26_OUT */
+ 0x1fc (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_OEN */
+ 0x200 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_OUT */
+ 0x364 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_OEN */
+ 0x368 (A_DELAY(11) | G_DELAY(0)) /* CFG_GPMC_CS1_OUT */
+ >;
+ };
};
&i2c1 {
regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
+ regulator-always-on;
regulator-boot-on;
};
};
};
};
+
+ pcf_lcd: gpio@20 {
+ compatible = "nxp,pcf8575";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ pcf_gpio_21: gpio@21 {
+ compatible = "nxp,pcf8575";
+ reg = <0x21>;
+ lines-initial-states = <0x1408>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+
+ tlv320aic3106: tlv320aic3106@18 {
+ compatible = "ti,tlv320aic3106";
+ reg = <0x18>;
+ adc-settle-ms = <40>;
+ ai3x-micbias-vg = <1>; /* 2.0V */
+ status = "okay";
+
+ /* Regulators */
+ AVDD-supply = <&evm_3v3_sw>;
+ IOVDD-supply = <&evm_3v3_sw>;
+ DRVDD-supply = <&evm_3v3_sw>;
+ DVDD-supply = <&aic_dvdd>;
+ };
};
-&i2c2 {
+i2c_p3_exp: &i2c2 {
status = "okay";
clock-frequency = <400000>;
+
+ pcf_hdmi: gpio@26 {
+ compatible = "nxp,pcf8575";
+ reg = <0x26>;
+ lines-initial-states = <0xffeb>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ ov10633@37 {
+ compatible = "ovti,ov10633";
+ reg = <0x37>;
+
+ mux-gpios = <&pcf_hdmi 3 GPIO_ACTIVE_LOW>; /* CAM_FPD_MUX_S0 */
+ port {
+ onboardLI: endpoint {
+ remote-endpoint = <&vin1a>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ pclk-sample = <0>;
+ };
+ };
+ };
};
&i2c3 {
&uart1 {
status = "okay";
+ interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH
+ &dra7_pmx_core 0x3e0>;
};
&uart2 {
&uart3 {
status = "okay";
+ gpios = <&pcf_gpio_21 14 GPIO_ACTIVE_LOW>;
};
&mmc1 {
status = "okay";
- vmmc-supply = <&ldo1_reg>;
+ pbias-supply = <&pbias_mmc_reg>;
+ vmmc-supply = <&evm_3v3_sd>;
+ vmmc_aux-supply = <&ldo1_reg>;
bus-width = <4>;
+ /*
+ * SDCD signal is not being used here - using the fact that GPIO mode
+ * is always hardwired.
+ */
+ cd-gpios = <&gpio6 27 0>;
+ pinctrl-names = "default", "hs", "sdr12", "sdr25", "ddr50";
+ pinctrl-0 = <&mmc1_pins_default>;
+ pinctrl-1 = <&mmc1_pins_hs>;
+ pinctrl-2 = <&mmc1_pins_sdr12>;
+ pinctrl-3 = <&mmc1_pins_sdr25>;
+ pinctrl-4 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr50_conf>;
+ sd-uhs-ddr50;
+ sd-uhs-sdr25;
+ sd-uhs-sdr12;
};
&mmc2 {
status = "okay";
vmmc-supply = <&evm_3v3_sw>;
bus-width = <8>;
+ pinctrl-names = "default", "hs", "ddr_3_3v";
+ pinctrl-0 = <&mmc2_pins_default>;
+ pinctrl-1 = <&mmc2_pins_hs>;
+ pinctrl-2 = <&mmc2_pins_ddr_3_3v &mmc2_iodelay_ddr_3_3v_conf>;
+ mmc-ddr-1_8v;
+};
+
+&mmc4 {
+ status = "okay";
+ vmmc-supply = <&vmmcwl_fixed>;
+ bus-width = <4>;
+ cap-power-off-card;
+ keep-power-in-suspend;
+ ti,non-removable;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ wlcore: wlcore@0 {
+ compatible = "ti,wl1835";
+ reg = <2>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
&cpu0 {
- cpu0-supply = <&smps123_reg>;
+ cpu0-voltdm = <&voltdm_mpu>;
+ voltage-tolerance = <1>;
+};
+
+&voltdm_mpu {
+ vdd-supply = <&smps123_reg>;
+};
+
+&voltdm_dspeve {
+ vdd-supply = <&smps45_reg>;
+};
+
+&voltdm_gpu {
+ vdd-supply = <&smps6_reg>;
+};
+
+&voltdm_ivahd {
+ vdd-supply = <&smps8_reg>;
+};
+
+&voltdm_core {
+ vdd-supply = <&smps7_reg>;
};
&qspi {
};
partition@5 {
label = "QSPI.u-boot-spl-os";
- reg = <0x00140000 0x00010000>;
+ reg = <0x00140000 0x00080000>;
};
partition@6 {
label = "QSPI.u-boot-env";
- reg = <0x00150000 0x00010000>;
+ reg = <0x001c0000 0x00010000>;
};
partition@7 {
label = "QSPI.u-boot-env.backup1";
- reg = <0x00160000 0x0010000>;
+ reg = <0x001d0000 0x0010000>;
};
partition@8 {
label = "QSPI.kernel";
- reg = <0x00170000 0x0800000>;
+ reg = <0x001e0000 0x0800000>;
};
partition@9 {
label = "QSPI.file-system";
- reg = <0x00970000 0x01690000>;
+ reg = <0x009e0000 0x01620000>;
};
};
};
+&omap_dwc3_1 {
+ extcon = <&extcon_usb1>;
+};
+
+&omap_dwc3_2 {
+ extcon = <&extcon_usb2>;
+};
+
&usb1 {
dr_mode = "peripheral";
};
dr_mode = "host";
};
+&mac {
+ status = "okay";
+ dual_emac;
+ ti,no-idle;
+};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <2>;
+ phy-mode = "rgmii";
+ dual_emac_res_vlan = <1>;
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <3>;
+ phy-mode = "rgmii";
+ dual_emac_res_vlan = <2>;
+};
+
+&elm {
+ status = "okay";
+};
+
+&gpmc {
+ status = "disabled";
+ ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
+ nand@0,0 {
+ reg = <0 0 4>; /* device IO registers */
+ ti,nand-ecc-opt = "bch8";
+ ti,elm-id = <&elm>;
+ nand-bus-width = <16>;
+ gpmc,device-width = <2>;
+ gpmc,sync-clk-ps = <0>;
+ gpmc,cs-on-ns = <0>;
+ gpmc,cs-rd-off-ns = <80>;
+ gpmc,cs-wr-off-ns = <80>;
+ gpmc,adv-on-ns = <0>;
+ gpmc,adv-rd-off-ns = <60>;
+ gpmc,adv-wr-off-ns = <60>;
+ gpmc,we-on-ns = <10>;
+ gpmc,we-off-ns = <50>;
+ gpmc,oe-on-ns = <4>;
+ gpmc,oe-off-ns = <40>;
+ gpmc,access-ns = <40>;
+ gpmc,wr-access-ns = <80>;
+ gpmc,rd-cycle-ns = <80>;
+ gpmc,wr-cycle-ns = <80>;
+ gpmc,bus-turnaround-ns = <0>;
+ gpmc,cycle2cycle-delay-ns = <0>;
+ gpmc,clk-activation-ns = <0>;
+ gpmc,wait-monitoring-ns = <0>;
+ gpmc,wr-data-mux-bus-ns = <0>;
+ /* MTD partition table */
+ /* All SPL-* partitions are sized to minimal length
+ * which can be independently programmable. For
+ * NAND flash this is equal to size of erase-block */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "NAND.SPL";
+ reg = <0x00000000 0x000020000>;
+ };
+ partition@1 {
+ label = "NAND.SPL.backup1";
+ reg = <0x00020000 0x00020000>;
+ };
+ partition@2 {
+ label = "NAND.SPL.backup2";
+ reg = <0x00040000 0x00020000>;
+ };
+ partition@3 {
+ label = "NAND.SPL.backup3";
+ reg = <0x00060000 0x00020000>;
+ };
+ partition@4 {
+ label = "NAND.u-boot-spl-os";
+ reg = <0x00080000 0x00040000>;
+ };
+ partition@5 {
+ label = "NAND.u-boot";
+ reg = <0x000c0000 0x00100000>;
+ };
+ partition@6 {
+ label = "NAND.u-boot-env";
+ reg = <0x001c0000 0x00020000>;
+ };
+ partition@7 {
+ label = "NAND.u-boot-env.backup1";
+ reg = <0x001e0000 0x00020000>;
+ };
+ partition@8 {
+ label = "NAND.kernel";
+ reg = <0x00200000 0x00800000>;
+ };
+ partition@9 {
+ label = "NAND.file-system";
+ reg = <0x00a00000 0x0f600000>;
+ };
+ };
+};
+
&gpio7 {
ti,no-reset-on-init;
ti,no-idle-on-init;
};
+&dss {
+ status = "ok";
+
+ vdda_video-supply = <&ldoln_reg>;
+};
+
+&hdmi {
+ status = "ok";
+ vdda-supply = <&ldo3_reg>;
+
+ port {
+ hdmi_out: endpoint {
+ remote-endpoint = <&tpd12s015_in>;
+ };
+ };
+};
+
+&dcan1 {
+ status = "ok";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&dcan1_pins_default>;
+ pinctrl-1 = <&dcan1_pins_sleep>;
+};
+
&mailbox5 {
status = "okay";
mbox_ipu1_legacy: mbox_ipu1_legacy {
mboxes = <&mailbox6 &mbox_dsp2_legacy>;
timers = <&timer6>;
};
+
+&atl {
+ status = "okay";
+
+ atl2 {
+ bws = <DRA7_ATL_WS_MCASP2_FSX>;
+ aws = <DRA7_ATL_WS_MCASP3_FSX>;
+ };
+};
+
+&mcasp3 {
+ fck_parent = "atl_clkin2_ck";
+
+ status = "okay";
+
+ op-mode = <0>; /* MCASP_IIS_MODE */
+ tdm-slots = <2>;
+ /* 4 serializer */
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 1 2 0 0
+ >;
+ tx-num-evt = <8>;
+ rx-num-evt = <8>;
+};
+
+&mcasp7 {
+ #sound-dai-cells = <0>;
+
+ status = "okay";
+
+ op-mode = <0>; /* MCASP_IIS_MODE */
+ tdm-slots = <4>;
+ /* 4 serializer */
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 2 1 0 0
+ >;
+ tx-num-evt = <8>;
+ rx-num-evt = <8>;
+};
+
+&mcasp8 {
+ /* not used for audio. only the AXR2 pin is used as GPIO */
+ status = "okay";
+};
+
+&usb2_phy1 {
+ phy-supply = <&ldousb_reg>;
+};
+
+&usb2_phy2 {
+ phy-supply = <&ldousb_reg>;
+};
+
+&vip1 {
+ status = "okay";
+};
+
+&vin1a {
+ endpoint@0 {
+ slave-mode;
+ remote-endpoint = <&onboardLI>;
+ };
+};
+
+#include "dra7xx-jamr3.dtsi"