index d126bd52000c01b2f4223be7e26e13d979e497d8..54fed30c38b3aac055a182d0218571ef9dd1cf4a 100644 (file)
/dts-v1/;
#include "dra72x.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clk/ti-dra7-atl.h>
/ {
model = "TI DRA722";
compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
+ aliases {
+ display0 = &hdmi0;
+ sound0 = &primary_sound;
+ sound1 = &hdmi;
+ i2c7 = &disp_ser;
+ };
+
memory {
device_type = "memory";
reg = <0x80000000 0x40000000>; /* 1024 MB */
};
- reserved-memory {
+ tpd12s015: encoder@0 {
+ compatible = "ti,tpd12s015";
+
+ gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
+ <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
+ <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tpd12s015_in: endpoint@0 {
+ remote-endpoint = <&hdmi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tpd12s015_out: endpoint@0 {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
+
+ hdmi0: connector@0 {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&tpd12s015_out>;
+ };
+ };
+ };
+
+ reserved_mem: reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
};
};
- evm_3v3: fixedregulator-evm_3v3 {
+ extcon_usb1: extcon_usb1 {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpios = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ extcon_usb2: extcon_usb2 {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpios = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ evm_3v3_sd: fixedregulator-sd {
+ compatible = "regulator-fixed";
+ regulator-name = "evm_3v3_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&pcf_gpio_21 5 0>;
+ };
+
+ evm_3v3_sw: fixedregulator-evm_3v3 {
compatible = "regulator-fixed";
regulator-name = "evm_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
+
+ aic_dvdd: fixedregulator-aic_dvdd {
+ /* TPS77018DBVT */
+ compatible = "regulator-fixed";
+ regulator-name = "aic_dvdd";
+ vin-supply = <&evm_3v3_sw>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ primary_sound: primary_sound {
+ compatible = "ti,dra7xx-evm-audio";
+ ti,model = "DRA7xx-EVM";
+ ti,always-on;
+ ti,audio-codec = <&tlv320aic3106>;
+ ti,mcasp-controller = <&mcasp3>;
+ ti,codec-clock-rate = <11289600>;
+ clocks = <&atl_clkin2_ck>;
+ clock-names = "mclk";
+ ti,audio-routing =
+ "Headphone Jack", "HPLOUT",
+ "Headphone Jack", "HPROUT",
+ "Line Out", "LLOUT",
+ "Line Out", "RLOUT",
+ "MIC3L", "Mic Jack",
+ "MIC3R", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "LINE1L", "Line In",
+ "LINE1R", "Line In";
+ };
+
+ btwilink_sound: btwilink_sound {
+ #sound-dai-cells = <0>;
+ compatible = "linux,bt-sco-audio";
+ status = "okay";
+ };
+
+ simple_bt_sco_card: bt_sco_card {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "DRA7xx-WiLink";
+ simple-audio-card,format = "dsp_a";
+ simple-audio-card,frame-master = <&btwilink_codec>;
+ simple-audio-card,bitclock-master = <&btwilink_codec>;
+ simple-audio-card,frame-inversion;
+
+ simple-audio-card,cpu {
+ sound-dai = <&mcasp7>;
+ };
+
+ btwilink_codec: simple-audio-card,codec {
+ sound-dai = <&btwilink_sound>;
+ };
+ };
+
+ vmmcwl_fixed: fixedregulator-mmcwl {
+ compatible = "regulator-fixed";
+ regulator-name = "vmmcwl_fixed";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&gpio5 8 GPIO_ACTIVE_HIGH>; /* gpio5_8 */
+ enable-active-high;
+ };
+
+ kim {
+ compatible = "kim";
+ nshutdown_gpio = <132>;
+ dev_name = "/dev/ttyS2";
+ flow_cntrl = <1>;
+ baud_rate = <3686400>;
+ };
+
+ btwilink {
+ compatible = "btwilink";
+ };
};
&dra7_pmx_core {
- i2c1_pins: pinmux_i2c1_pins {
+ tps65917_pins_default: tps65917_pins_default {
pinctrl-single,pins = <
- 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
- 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
+ 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
>;
};
- tps65917_pins_default: tps65917_pins_default {
+ mmc1_pins_default: mmc1_pins_default {
pinctrl-single,pins = <
- 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
+ 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */
+ 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */
+ 0x35C (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */
+ 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */
+ 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */
+ 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */
+ 0x36C (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_sdcd.mmc1_sdcd */
+ >;
+ };
+
+ mmc1_pins_virtual1: mmc1_pins_virtual1 {
+ pinctrl-single,pins = <
+ 0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_clk.mmc1_clk */
+ 0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */
+ 0x35C (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */
+ 0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */
+ 0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */
+ 0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */
+ 0x36C (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_sdcd.mmc1_sdcd */
+ >;
+ };
+
+ mmc1_pins_manual1: mmc1_pins_manual1 {
+ pinctrl-single,pins = <
+ 0x354 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_clk.mmc1_clk */
+ 0x358 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */
+ 0x35C (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */
+ 0x360 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */
+ 0x364 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */
+ 0x368 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */
+ 0x36C (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_sdcd.mmc1_sdcd */
+ >;
+ };
+
+ mmc1_pins_manual2: mmc1_pins_manual2 {
+ pinctrl-single,pins = <
+ 0x354 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_clk.mmc1_clk */
+ 0x358 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */
+ 0x35C (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */
+ 0x360 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */
+ 0x364 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */
+ 0x368 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */
+ 0x36C (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_sdcd.mmc1_sdcd */
>;
};
+
+ mmc2_pins_default: mmc2_pins_default {
+ pinctrl-single,pins = <
+ 0x08C (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ 0x090 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ 0x094 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ 0x098 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ 0x09C (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ 0x0A0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ 0x0A4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ 0x0A8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ 0x0AC (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ 0x0B0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ >;
+ };
+
+ mmc2_pins_manual1: mmc2_pins_manual1 {
+ pinctrl-single,pins = <
+ 0x08C (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ 0x090 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ 0x094 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ 0x098 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ 0x09C (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ 0x0A0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ 0x0A4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ 0x0A8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ 0x0AC (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ 0x0B0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ >;
+ };
+
+ mmc2_pins_manual3: mmc2_pins_manual3 {
+ pinctrl-single,pins = <
+ 0x08C (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ 0x090 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ 0x094 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ 0x098 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ 0x09C (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ 0x0A0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ 0x0A4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ 0x0A8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ 0x0AC (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ 0x0B0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ >;
+ };
+
+ mmc4_pins_default: mmc4_pins_default {
+ pinctrl-single,pins = <
+ 0x3E8 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
+ 0x3EC (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
+ 0x3F0 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
+ 0x3F4 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
+ 0x3F8 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
+ 0x3FC (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
+ >;
+ };
+};
+
+&dra7_iodelay_core {
+ mmc1_iodelay_manual1_conf: mmc1_iodelay_manual1_conf {
+ pinctrl-single,pins = <
+ 0x618 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CLK_IN */
+ 0x620 (A_DELAY(1353) | G_DELAY(0)) /* CFG_MMC1_CLK_OUT */
+ 0x624 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_IN */
+ 0x62C (A_DELAY(1) | G_DELAY(0)) /* CFG_MMC1_CMD_OUT */
+ 0x628 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OEN */
+ 0x630 (A_DELAY(483) | G_DELAY(0)) /* CFG_MMC1_DAT0_IN */
+ 0x638 (A_DELAY(16) | G_DELAY(0)) /* CFG_MMC1_DAT0_OUT */
+ 0x634 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OEN */
+ 0x63C (A_DELAY(126) | G_DELAY(0)) /* CFG_MMC1_DAT1_IN */
+ 0x644 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OUT */
+ 0x640 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OEN */
+ 0x648 (A_DELAY(104) | G_DELAY(0)) /* CFG_MMC1_DAT2_IN */
+ 0x650 (A_DELAY(34) | G_DELAY(0)) /* CFG_MMC1_DAT2_OUT */
+ 0x64C (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OEN */
+ 0x654 (A_DELAY(33) | G_DELAY(0)) /* CFG_MMC1_DAT3_IN */
+ 0x65C (A_DELAY(18) | G_DELAY(0)) /* CFG_MMC1_DAT3_OUT */
+ 0x658 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OEN */
+ >;
+ };
+
+ mmc1_iodelay_manual2_conf: mmc1_iodelay_manual2_conf {
+ pinctrl-single,pins = <
+ 0x620 (A_DELAY(560) | G_DELAY(365)) /* CFG_MMC1_CLK_OUT */
+ 0x62C (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OUT */
+ 0x628 (A_DELAY(125) | G_DELAY(0)) /* CFG_MMC1_CMD_OEN */
+ 0x638 (A_DELAY(29) | G_DELAY(0)) /* CFG_MMC1_DAT0_OUT */
+ 0x634 (A_DELAY(43) | G_DELAY(0)) /* CFG_MMC1_DAT0_OEN */
+ 0x644 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OUT */
+ 0x640 (A_DELAY(433) | G_DELAY(0)) /* CFG_MMC1_DAT1_OEN */
+ 0x650 (A_DELAY(47) | G_DELAY(0)) /* CFG_MMC1_DAT2_OUT */
+ 0x64C (A_DELAY(287) | G_DELAY(0)) /* CFG_MMC1_DAT2_OEN */
+ 0x65C (A_DELAY(30) | G_DELAY(0)) /* CFG_MMC1_DAT3_OUT */
+ 0x658 (A_DELAY(351) | G_DELAY(0)) /* CFG_MMC1_DAT3_OEN */
+ >;
+ };
+
+ mmc2_iodelay_manual1_conf: mmc2_iodelay_manual1_conf {
+ pinctrl-single,pins = <
+ 0x18C (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A19_IN */
+ 0x194 (A_DELAY(100) | G_DELAY(0)) /* CFG_GPMC_A19_OUT */
+ 0x190 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A19_OEN */
+ 0x1A4 (A_DELAY(391) | G_DELAY(0)) /* CFG_GPMC_A20_IN */
+ 0x1AC (A_DELAY(219) | G_DELAY(0)) /* CFG_GPMC_A20_OUT */
+ 0x1A8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A20_OEN */
+ 0x1B0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A21_IN */
+ 0x1B8 (A_DELAY(24) | G_DELAY(0)) /* CFG_GPMC_A21_OUT */
+ 0x1B4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A21_OEN */
+ 0x1BC (A_DELAY(211) | G_DELAY(0)) /* CFG_GPMC_A22_IN */
+ 0x1C4 (A_DELAY(88) | G_DELAY(0)) /* CFG_GPMC_A22_OUT */
+ 0x1C0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A22_OEN */
+ 0x1C8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A23_IN */
+ 0x1D0 (A_DELAY(626) | G_DELAY(0)) /* CFG_GPMC_A23_OUT */
+ 0x1D4 (A_DELAY(320) | G_DELAY(0)) /* CFG_GPMC_A24_IN */
+ 0x1DC (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OUT */
+ 0x1D8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OEN */
+ 0x1E0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_IN */
+ 0x1E8 (A_DELAY(172) | G_DELAY(0)) /* CFG_GPMC_A25_OUT */
+ 0x1E4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_OEN */
+ 0x1EC (A_DELAY(159) | G_DELAY(0)) /* CFG_GPMC_A26_IN */
+ 0x1F4 (A_DELAY(177) | G_DELAY(0)) /* CFG_GPMC_A26_OUT */
+ 0x1F0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A26_OEN */
+ 0x1F8 (A_DELAY(232) | G_DELAY(0)) /* CFG_GPMC_A27_IN */
+ 0x200 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_OUT */
+ 0x1FC (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_OEN */
+ 0x360 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_IN */
+ 0x368 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_OUT */
+ 0x364 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_OEN */
+ >;
+ };
+
+ mmc2_iodelay_manual2_conf: mmc2_iodelay_manual2_conf {
+ pinctrl-single,pins = <
+ 0x18C (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A19_IN */
+ 0x194 (A_DELAY(100) | G_DELAY(0)) /* CFG_GPMC_A19_OUT */
+ 0x190 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A19_OEN */
+ 0x1A4 (A_DELAY(173) | G_DELAY(0)) /* CFG_GPMC_A20_IN */
+ 0x1AC (A_DELAY(219) | G_DELAY(0)) /* CFG_GPMC_A20_OUT */
+ 0x1A8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A20_OEN */
+ 0x1B0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A21_IN */
+ 0x1B8 (A_DELAY(24) | G_DELAY(0)) /* CFG_GPMC_A21_OUT */
+ 0x1B4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A21_OEN */
+ 0x1BC (A_DELAY(40) | G_DELAY(0)) /* CFG_GPMC_A22_IN */
+ 0x1C4 (A_DELAY(88) | G_DELAY(0)) /* CFG_GPMC_A22_OUT */
+ 0x1C0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A22_OEN */
+ 0x1C8 (A_DELAY(716) | G_DELAY(2726)) /* CFG_GPMC_A23_IN */
+ 0x1D0 (A_DELAY(626) | G_DELAY(0)) /* CFG_GPMC_A23_OUT */
+ 0x1D4 (A_DELAY(133) | G_DELAY(0)) /* CFG_GPMC_A24_IN */
+ 0x1DC (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OUT */
+ 0x1D8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OEN */
+ 0x1E0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_IN */
+ 0x1E8 (A_DELAY(172) | G_DELAY(0)) /* CFG_GPMC_A25_OUT */
+ 0x1E4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_OEN */
+ 0x1EC (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A26_IN */
+ 0x1F4 (A_DELAY(177) | G_DELAY(0)) /* CFG_GPMC_A26_OUT */
+ 0x1F0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A26_OEN */
+ 0x1F8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_IN */
+ 0x200 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_OUT */
+ 0x1FC (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_OEN */
+ 0x360 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_IN */
+ 0x368 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_OUT */
+ 0x364 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_OEN */
+ >;
+ };
+
+ mmc2_iodelay_manual3_conf: mmc2_iodelay_manual3_conf {
+ pinctrl-single,pins = <
+ 0x194 (A_DELAY(0) | G_DELAY(95)) /* CFG_GPMC_A19_OUT */
+ 0x190 (A_DELAY(695) | G_DELAY(0)) /* CFG_GPMC_A19_OEN */
+ 0x1AC (A_DELAY(214) | G_DELAY(0)) /* CFG_GPMC_A20_OUT */
+ 0x1A8 (A_DELAY(924) | G_DELAY(0)) /* CFG_GPMC_A20_OEN */
+ 0x1B8 (A_DELAY(19) | G_DELAY(0)) /* CFG_GPMC_A21_OUT */
+ 0x1B4 (A_DELAY(719) | G_DELAY(0)) /* CFG_GPMC_A21_OEN */
+ 0x1C4 (A_DELAY(83) | G_DELAY(0)) /* CFG_GPMC_A22_OUT */
+ 0x1C0 (A_DELAY(824) | G_DELAY(0)) /* CFG_GPMC_A22_OEN */
+ 0x1D0 (A_DELAY(1020) | G_DELAY(416)) /* CFG_GPMC_A23_OUT */
+ 0x1DC (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OUT */
+ 0x1D8 (A_DELAY(877) | G_DELAY(0)) /* CFG_GPMC_A24_OEN */
+ 0x1E8 (A_DELAY(167) | G_DELAY(0)) /* CFG_GPMC_A25_OUT */
+ 0x1E4 (A_DELAY(446) | G_DELAY(0)) /* CFG_GPMC_A25_OEN */
+ 0x1F4 (A_DELAY(172) | G_DELAY(0)) /* CFG_GPMC_A26_OUT */
+ 0x1F0 (A_DELAY(847) | G_DELAY(0)) /* CFG_GPMC_A26_OEN */
+ 0x200 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_OUT */
+ 0x1FC (A_DELAY(586) | G_DELAY(0)) /* CFG_GPMC_A27_OEN */
+ 0x368 (A_DELAY(40) | G_DELAY(0)) /* CFG_GPMC_CS1_OUT */
+ 0x364 (A_DELAY(1039) | G_DELAY(0)) /* CFG_GPMC_CS1_OEN */
+ >;
+ };
+
};
&i2c1 {
status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins>;
clock-frequency = <400000>;
tps65917: tps65917@58 {
/* VDD_MPU */
regulator-name = "smps1";
regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1250000>;
+ regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
};
/* VDD_CORE */
regulator-name = "smps2";
regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1030000>;
+ regulator-max-microvolt = <1500000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_GPU IVA DSPEVE */
regulator-name = "smps3";
regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1250000>;
+ regulator-max-microvolt = <1500000>;
regulator-boot-on;
regulator-always-on;
};
regulator-name = "ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
+ regulator-always-on;
regulator-boot-on;
};
};
};
};
+
+ tps65917_power_button {
+ compatible = "ti,palmas-pwrbutton";
+ interrupt-parent = <&tps65917>;
+ interrupts = <1 IRQ_TYPE_NONE>;
+ wakeup-source;
+ ti,palmas-long-press-seconds = <6>;
+ };
+ };
+
+ pcf_lcd: gpio@20 {
+ compatible = "nxp,pcf8575";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ pcf_lcd_tc3587x: gpio@27 {
+ compatible = "nxp,pcf8575";
+ reg = <0x27>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ pcf_gpio_21: gpio@21 {
+ compatible = "nxp,pcf8575";
+ reg = <0x21>;
+ lines-initial-states = <0x1408>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <11 2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ sel_enet_mux_hog: cpsw_sel_s0 {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_HIGH>;
+ output-low;
+ };
+ };
+
+ tlv320aic3106: tlv320aic3106@19 {
+ compatible = "ti,tlv320aic3106";
+ reg = <0x19>;
+ adc-settle-ms = <40>;
+ ai3x-micbias-vg = <1>; /* 2.0V */
+ status = "okay";
+
+ /* Regulators */
+ AVDD-supply = <&evm_3v3_sw>;
+ IOVDD-supply = <&evm_3v3_sw>;
+ DRVDD-supply = <&evm_3v3_sw>;
+ DVDD-supply = <&aic_dvdd>;
+ };
+};
+
+i2c_p3_exp: &i2c5 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ pcf_hdmi: pcf8575@26 {
+ compatible = "nxp,pcf8575";
+ reg = <0x26>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /*
+ * initial state is used here to keep the mdio interface
+ * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
+ * VIN2_S0 driven high otherwise Ethernet stops working
+ * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
+ */
+ lines-initial-states = <0x0f2b>;
+ };
+
+ ov10633@37 {
+ compatible = "ovti,ov10633";
+ reg = <0x37>;
+
+ mux-gpios = <&pcf_hdmi 2 GPIO_ACTIVE_HIGH>, /* VIN2_S0 */
+ <&pcf_hdmi 6 GPIO_ACTIVE_LOW>; /* VIN2_S2 */
+ port {
+ onboardLI: endpoint {
+ remote-endpoint = <&vin2a>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ pclk-sample = <0>;
+ };
+ };
+ };
+
+ disp_ser: serializer@1b {
+ status = "disabled";
+ compatible = "ti,ds90uh925q";
+ reg = <0x1b>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ranges = <0x2c 0x2c>,
+ <0x1c 0x1c>;
+
+ disp_des: deserializer@2c {
+ compatible = "ti,ds90uh928q";
+ reg = <0x2c>;
+ slave-mode;
+ };
+
+ /* TLC chip for LCD panel power and backlight */
+ fpd_disp: tlc59108@1c {
+ reg = <0x1c>;
+ compatible = "ti,tlc59108-fpddisp";
+ enable-gpios = <&pcf_gpio_21 0 GPIO_ACTIVE_LOW>;
+ /* P0, SEL_GPMC_AD_VID_S0 */
+
+ port@lcd3 {
+ fpd_in: endpoint {
+ remote-endpoint = <&dpi_out3>;
+ };
+ };
+ };
};
};
&uart1 {
+ interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH
+ &dra7_pmx_core 0x3e0>;
+ status = "okay";
+};
+
+&uart3 {
status = "okay";
+ gpios = <&pcf_gpio_21 14 GPIO_ACTIVE_LOW>;
};
&mmc1 {
- /* Using default configured pins */
status = "okay";
- vmmc-supply = <&ldo1_reg>;
+ pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
+ pinctrl-0 = <&mmc1_pins_default>;
+ pinctrl-1 = <&mmc1_pins_default>;
+ pinctrl-2 = <&mmc1_pins_default>;
+ pinctrl-3 = <&mmc1_pins_default>;
+ pinctrl-4 = <&mmc1_pins_virtual1>;
+ pinctrl-5 = <&mmc1_pins_manual1 &mmc1_iodelay_manual1_conf>;
+ pinctrl-6 = <&mmc1_pins_manual2 &mmc1_iodelay_manual2_conf>;
+ pbias-supply = <&pbias_mmc_reg>;
+ vmmc-supply = <&evm_3v3_sd>;
+ vmmc_aux-supply = <&ldo1_reg>;
bus-width = <4>;
/*
* SDCD signal is not being used here - using the fact that GPIO mode
* is always hardwired.
*/
cd-gpios = <&gpio6 27 0>;
+ sd-uhs-sdr104;
+ sd-uhs-sdr50;
+ sd-uhs-ddr50;
+ sd-uhs-sdr25;
+ sd-uhs-sdr12;
+ max-frequency = <192000000>;
};
&mmc2 {
- /* Using default configured pins */
status = "okay";
- vmmc-supply = <&evm_3v3>;
+ pinctrl-names = "default", "hs", "ddr_3_3v", "hs200";
+ pinctrl-0 = <&mmc2_pins_default>;
+ pinctrl-1 = <&mmc2_pins_default>;
+ pinctrl-2 = <&mmc2_pins_manual1 &mmc2_iodelay_manual1_conf>;
+ pinctrl-3 = <&mmc2_pins_manual3 &mmc2_iodelay_manual3_conf>;
+ vmmc-supply = <&evm_3v3_sw>;
bus-width = <8>;
ti,non-removable;
+ mmc-hs200-1_8v;
+ max-frequency = <192000000>;
+};
+
+&mmc4 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc4_pins_default>;
+ vmmc-supply = <&vmmcwl_fixed>;
+ bus-width = <4>;
+ cap-power-off-card;
+ keep-power-in-suspend;
+ ti,non-removable;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ wlcore: wlcore@0 {
+ compatible = "ti,wlcore";
+ reg = <2>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
+
+&mac {
+ status = "okay";
+ slaves = <1>;
+ ti,no-idle;
+};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <3>;
+ phy-mode = "rgmii";
+};
+
+&cpu0 {
+ cpu0-voltdm = <&voltdm_mpu>;
+ voltage-tolerance = <1>;
+};
+
+&voltdm_mpu {
+ vdd-supply = <&smps1_reg>;
+};
+
+&voltdm_core {
+ vdd-supply = <&smps2_reg>;
+};
+
+&voltdm_dspeve {
+ vdd-supply = <&smps3_reg>;
+};
+
+&voltdm_gpu {
+ vdd-supply = <&smps3_reg>;
+};
+
+&voltdm_ivahd {
+ vdd-supply = <&smps3_reg>;
+};
+
+&elm {
+ status = "okay";
+};
+
+&gpmc {
+ status = "okay";
+ ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
+ nand@0,0 {
+ /* To use NAND, DIP switch SW5 must be set like so:
+ * SW5.1 (NAND_SELn) = ON (LOW)
+ * SW5.9 (GPMC_WPN) = OFF (HIGH)
+ */
+ reg = <0 0 4>; /* device IO registers */
+ ti,nand-ecc-opt = "bch8";
+ ti,elm-id = <&elm>;
+ nand-bus-width = <16>;
+ gpmc,device-width = <2>;
+ gpmc,sync-clk-ps = <0>;
+ gpmc,cs-on-ns = <0>;
+ gpmc,cs-rd-off-ns = <80>;
+ gpmc,cs-wr-off-ns = <80>;
+ gpmc,adv-on-ns = <0>;
+ gpmc,adv-rd-off-ns = <60>;
+ gpmc,adv-wr-off-ns = <60>;
+ gpmc,we-on-ns = <10>;
+ gpmc,we-off-ns = <50>;
+ gpmc,oe-on-ns = <4>;
+ gpmc,oe-off-ns = <40>;
+ gpmc,access-ns = <40>;
+ gpmc,wr-access-ns = <80>;
+ gpmc,rd-cycle-ns = <80>;
+ gpmc,wr-cycle-ns = <80>;
+ gpmc,bus-turnaround-ns = <0>;
+ gpmc,cycle2cycle-delay-ns = <0>;
+ gpmc,clk-activation-ns = <0>;
+ gpmc,wait-monitoring-ns = <0>;
+ gpmc,wr-data-mux-bus-ns = <0>;
+ /* MTD partition table */
+ /* All SPL-* partitions are sized to minimal length
+ * which can be independently programmable. For
+ * NAND flash this is equal to size of erase-block */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "NAND.SPL";
+ reg = <0x00000000 0x000020000>;
+ };
+ partition@1 {
+ label = "NAND.SPL.backup1";
+ reg = <0x00020000 0x00020000>;
+ };
+ partition@2 {
+ label = "NAND.SPL.backup2";
+ reg = <0x00040000 0x00020000>;
+ };
+ partition@3 {
+ label = "NAND.SPL.backup3";
+ reg = <0x00060000 0x00020000>;
+ };
+ partition@4 {
+ label = "NAND.u-boot-spl-os";
+ reg = <0x00080000 0x00040000>;
+ };
+ partition@5 {
+ label = "NAND.u-boot";
+ reg = <0x000c0000 0x00100000>;
+ };
+ partition@6 {
+ label = "NAND.u-boot-env";
+ reg = <0x001c0000 0x00020000>;
+ };
+ partition@7 {
+ label = "NAND.u-boot-env.backup1";
+ reg = <0x001e0000 0x00020000>;
+ };
+ partition@8 {
+ label = "NAND.kernel";
+ reg = <0x00200000 0x00800000>;
+ };
+ partition@9 {
+ label = "NAND.file-system";
+ reg = <0x00a00000 0x0f600000>;
+ };
+ };
+};
+
+&dss {
+ status = "ok";
+
+ vdda_video-supply = <&ldo5_reg>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ port@lcd3 {
+ reg = <2>;
+
+ dpi_out3: endpoint {
+ remote-endpoint = <&fpd_in>;
+ data-lines = <24>;
+ };
+ };
+ };
+};
+
+&hdmi {
+ status = "ok";
+ vdda-supply = <&ldo3_reg>;
+
+ port {
+ hdmi_out: endpoint {
+ remote-endpoint = <&tpd12s015_in>;
+ };
+ };
};
&mailbox5 {
timers = <&timer5>;
watchdog-timers = <&timer10>;
};
+
+&atl {
+ status = "okay";
+
+ atl2 {
+ bws = <DRA7_ATL_WS_MCASP2_FSX>;
+ aws = <DRA7_ATL_WS_MCASP3_FSX>;
+ };
+};
+
+&mcasp3 {
+ fck_parent = "atl_clkin2_ck";
+
+ status = "okay";
+
+ op-mode = <0>; /* MCASP_IIS_MODE */
+ tdm-slots = <2>;
+ /* 4 serializer */
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 1 2 0 0
+ >;
+ tx-num-evt = <8>;
+ rx-num-evt = <8>;
+};
+
+&mcasp7 {
+ #sound-dai-cells = <0>;
+
+ status = "okay";
+
+ op-mode = <0>; /* MCASP_IIS_MODE */
+ tdm-slots = <4>;
+ /* 4 serializer */
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 2 1 0 0
+ >;
+ tx-num-evt = <8>;
+ rx-num-evt = <8>;
+};
+
+&omap_dwc3_1 {
+ extcon = <&extcon_usb1>;
+};
+
+&omap_dwc3_2 {
+ extcon = <&extcon_usb2>;
+};
+
+&usb2_phy1 {
+ phy-supply = <&ldo4_reg>;
+};
+
+&usb2_phy2 {
+ phy-supply = <&ldo4_reg>;
+};
+
+&usb1 {
+ dr_mode = "otg";
+};
+
+&usb2 {
+ dr_mode = "host";
+};
+
+&qspi {
+ status = "okay";
+
+ spi-max-frequency = <48000000>;
+ m25p80@0 {
+ compatible = "s25fl256s1";
+ spi-max-frequency = <48000000>;
+ reg = <0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-cpol;
+ spi-cpha;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* MTD partition table.
+ * The ROM checks the first four physical blocks
+ * for a valid file to boot and the flash here is
+ * 64KiB block size.
+ */
+ partition@0 {
+ label = "QSPI.SPL";
+ reg = <0x00000000 0x000010000>;
+ };
+ partition@1 {
+ label = "QSPI.SPL.backup1";
+ reg = <0x00010000 0x00010000>;
+ };
+ partition@2 {
+ label = "QSPI.SPL.backup2";
+ reg = <0x00020000 0x00010000>;
+ };
+ partition@3 {
+ label = "QSPI.SPL.backup3";
+ reg = <0x00030000 0x00010000>;
+ };
+ partition@4 {
+ label = "QSPI.u-boot";
+ reg = <0x00040000 0x00100000>;
+ };
+ partition@5 {
+ label = "QSPI.u-boot-spl-os";
+ reg = <0x00140000 0x00080000>;
+ };
+ partition@6 {
+ label = "QSPI.u-boot-env";
+ reg = <0x001c0000 0x00010000>;
+ };
+ partition@7 {
+ label = "QSPI.u-boot-env.backup1";
+ reg = <0x001d0000 0x0010000>;
+ };
+ partition@8 {
+ label = "QSPI.kernel";
+ reg = <0x001e0000 0x0800000>;
+ };
+ partition@9 {
+ label = "QSPI.file-system";
+ reg = <0x009e0000 0x01620000>;
+ };
+ };
+};
+
+&dcan1 {
+ status = "ok";
+};
+
+&vip1 {
+ status = "okay";
+};
+
+video_in: &vin2a {
+ status = "okay";
+ endpoint@0 {
+ slave-mode;
+ remote-endpoint = <&onboardLI>;
+ };
+};
+
+#include "dra7xx-jamr3.dtsi"
+&cal {
+ status = "okay";
+};
+
+&tvp_5158{
+ mux-gpios = <&pcf_hdmi 2 GPIO_ACTIVE_LOW>, /*VIN2_S0*/
+ <&pcf_jamr3_21 8 GPIO_ACTIVE_LOW>, /*SEL_TVP_FPD*/
+ <&pcf_hdmi 6 GPIO_ACTIVE_HIGH>; /*VIN2_S2*/
+};