index 6cbd8011a1f81e2478d603ac0e61158260a71426..1c7424327c5dc838a6306c918fb4c92658e2f757 100644 (file)
/*
* OMAP3 clock data
*
- * Copyright (C) 2007-2012 Texas Instruments, Inc.
+ G* Copyright (C) 2007-2012 Texas Instruments, Inc.
* Copyright (C) 2007-2011 Nokia Corporation
*
* Written by Paul Walmsley
"omapctrl_ick",
};
+static struct rate_init_clks rate_init_clks[] = {
+ { .name = "dpll5_ck", .rate = 120000000 },
+ { .name = "dpll5_m2_ck", .rate = 120000000 },
+};
+
int __init omap3xxx_clk_init(void)
{
struct omap_clk *c;
- u32 cpu_clkflg = 0;
+ u32 cpu_clkflg = 0, num_rclks = 0;
+ struct rate_init_clks *rclks = NULL;
/*
* 3505 must be tested before 3517, since 3517 returns true
omap2_clk_disable_autoidle_all();
+ if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0)) {
+ rclks = rate_init_clks;
+ num_rclks = ARRAY_SIZE(rate_init_clks);
+ }
+
+ omap2_clk_rate_init_clocks(rclks, num_rclks);
omap2_clk_enable_init_clocks(enable_init_clks,
ARRAY_SIZE(enable_init_clks));
(clk_get_rate(&core_ck) / 1000000),
(clk_get_rate(&arm_fck) / 1000000));
- /*
- * Lock DPLL5 -- here only until other device init code can
- * handle this
- */
- if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0))
- omap3_clk_lock_dpll5();
-
/* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
sdrc_ick_p = clk_get(NULL, "sdrc_ick");
arm_fck_p = clk_get(NULL, "arm_fck");