index 7bd7d91ec24e802198f063b6da7d89df10dcd643..82e0ed1d7daa082c8b3ccae26004819eea0377da 100644 (file)
#define OMAP5XXX_CONTROL_STATUS 0x134
#define OMAP5_DEVICETYPE_MASK (0x7 << 6)
+/* DRA7XX DSP Reset Vector boot register */
+#define DRA7XX_CTRL_CORE_CONTROL_DSP1_RST_VECT 0x55C
+#define DRA7XX_CTRL_CORE_DSP_RST_VECT_MASK (0x3FFFFF << 0)
+#define DRA7XX_CTRL_CORE_DSP_RST_VECT_SHIFT 10
+
/* DRA7XX CONTROL CORE BOOTSTRAP */
#define DRA7_CTRL_CORE_BOOTSTRAP 0x6c4
#define DRA7_SPEEDSELECT_MASK (0x3 << 8)
extern void omap3_ctrl_write_boot_mode(u8 bootmode);
extern void omap_ctrl_write_dsp_boot_addr(u32 bootaddr);
extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode);
+extern void dra7_ctrl_write_dsp_boot_addr(u32 bootaddr, u32 inst);
extern void omap3630_ctrl_disable_rta(void);
extern int omap3_ctrl_save_padconf(void);
extern void omap3_ctrl_set_iva_bootmode_idle(void);