index ee910de0390f8827f71976b60dee3c7e476ead40..77803511fbc7141444d2fdcc46dadcb498e10f1f 100644 (file)
.dev_attr = &dma_dev_attr,
};
+/* tpcc */
+static struct omap_hwmod_class dra7xx_tpcc_hwmod_class = {
+ .name = "tpcc",
+};
+
+struct omap_hwmod dra7xx_tpcc_hwmod = {
+ .name = "tpcc",
+ .class = &dra7xx_tpcc_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'tptc' class */
+static struct omap_hwmod_class dra7xx_tptc_hwmod_class = {
+ .name = "tptc",
+};
+
+/* tptc0 */
+struct omap_hwmod dra7xx_tptc0_hwmod = {
+ .name = "tptc0",
+ .class = &dra7xx_tptc_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
+ HWMOD_NEEDS_REIDLE,
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* tptc1 */
+struct omap_hwmod dra7xx_tptc1_hwmod = {
+ .name = "tptc1",
+ .class = &dra7xx_tptc_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
+ HWMOD_NEEDS_REIDLE,
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* tptc2 */
+struct omap_hwmod dra7xx_tptc2_hwmod = {
+ .name = "tptc2",
+ .class = &dra7xx_tptc_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
+ HWMOD_NEEDS_REIDLE,
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
/*
* 'dsp' class
* dsp sub-system
.name = "dss_core",
.class = &dra7xx_dss_hwmod_class,
.clkdm_name = "dss_clkdm",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.sdma_reqs = dra7xx_dss_sdma_reqs,
.main_clk = "dss_dss_clk",
.prcm = {
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
+ .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
.sysc_fields = &omap_hwmod_sysc_type1,
};
.name = "gpmc",
.class = &dra7xx_gpmc_hwmod_class,
.clkdm_name = "l3main1_clkdm",
- .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
- HWMOD_SWSUP_SIDLE),
.main_clk = "l3_iclk_div",
.prcm = {
.omap4 = {
},
};
+/*
+ * 'gpu' class
+ * 2d/3d graphics accelerator
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_gpu_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+ MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class dra7xx_gpu_hwmod_class = {
+ .name = "gpu",
+ .sysc = &dra7xx_gpu_sysc,
+};
+
+static struct omap_hwmod dra7xx_gpu_hwmod = {
+ .name = "gpu",
+ .class = &dra7xx_gpu_hwmod_class,
+ .clkdm_name = "gpu_clkdm",
+ .main_clk = "gpu_core_gclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_GPU_GPU_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_GPU_GPU_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
/*
* 'hdq1w' class
*
.sysc = &dra7xx_mcasp_sysc,
};
+/* mcasp2 */
+static struct omap_hwmod dra7xx_mcasp2_hwmod = {
+ .name = "mcasp2",
+ .class = &dra7xx_mcasp_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "mcasp2_ahclkx_mux",
+ .flags = HWMOD_SWSUP_SIDLE_ACT,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
/* mcasp3 */
static struct omap_hwmod dra7xx_mcasp3_hwmod = {
.name = "mcasp3",
},
};
+/* mcasp6 */
+static struct omap_hwmod dra7xx_mcasp6_hwmod = {
+ .name = "mcasp6",
+ .class = &dra7xx_mcasp_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "mcasp6_ahclkx_mux",
+ .flags = HWMOD_SWSUP_SIDLE_ACT,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* mcasp7 */
+static struct omap_hwmod dra7xx_mcasp7_hwmod = {
+ .name = "mcasp7",
+ .class = &dra7xx_mcasp_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "mcasp7_ahclkx_mux",
+ .flags = HWMOD_SWSUP_SIDLE_ACT,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* mcasp8 */
+static struct omap_hwmod dra7xx_mcasp8_hwmod = {
+ .name = "mcasp8",
+ .class = &dra7xx_mcasp_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "mcasp8_ahclkx_mux",
+ .flags = HWMOD_SWSUP_SIDLE_ACT,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
/*
* 'mmc' class
*
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+
+/* l4_cfg -> tpcc */
+struct omap_hwmod_ocp_if dra7xx_l4_cfg__tpcc = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_tpcc_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU,
+};
+
+/* l4_cfg -> tptc0 */
+static struct omap_hwmod_addr_space dra7xx_tptc0_addr_space[] = {
+ {
+ .pa_start = 0x43400000,
+ .pa_end = 0x43400212,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+struct omap_hwmod_ocp_if dra7xx_l4_cfg__tptc0 = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_tptc0_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_tptc0_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* l4_cfg -> tptc1 */
+static struct omap_hwmod_addr_space dra7xx_tptc1_addr_space[] = {
+ {
+ .pa_start = 0x43500000,
+ .pa_end = 0x43500212,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+struct omap_hwmod_ocp_if dra7xx_l4_cfg__tptc1 = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_tptc1_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_tptc1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
/* dsp1 -> l3_main_1 */
static struct omap_hwmod_ocp_if dra7xx_dsp1__l3_main_1 = {
.master = &dra7xx_dsp1_hwmod,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* l4_per2 -> mcasp2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp2 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_mcasp2_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU,
+};
+
/* l4_per2 -> mcasp3 */
static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = {
.master = &dra7xx_l4_per2_hwmod,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* l4_per2 -> mcasp6 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_mcasp6_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per2 -> mcasp7 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_mcasp7_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per2 -> mcasp8 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_mcasp8_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = {
{
.pa_start = 0x48078000,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+static struct omap_hwmod_addr_space dra7xx_gpu_addrs[] = {
+ {
+ .name = "klio",
+ .pa_start = 0x56000000,
+ .pa_end = 0x56001fff,
+ },
+ {
+ .name = "hydra2",
+ .pa_start = 0x56004000,
+ .pa_end = 0x56004fff,
+ },
+ {
+ .name = "klio_0",
+ .pa_start = 0x56008000,
+ .pa_end = 0x56009fff,
+ },
+ {
+ .name = "klio_1",
+ .pa_start = 0x5600c000,
+ .pa_end = 0x5600dfff,
+ },
+ {
+ .name = "klio_hl",
+ .pa_start = 0x5600fe00,
+ .pa_end = 0x5600ffff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l3_main_1 -> gpu */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpu = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_gpu_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_gpu_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
{
.pa_start = 0x480b2000,
&dra7xx_l4_per2__cpgmac0,
&dra7xx_gmac__mdio,
&dra7xx_l4_cfg__dma_system,
+ &dra7xx_l4_cfg__tpcc,
+ &dra7xx_l4_cfg__tptc0,
+ &dra7xx_l4_cfg__tptc1,
&dra7xx_l3_main_1__dss,
&dra7xx_l3_main_1__dispc,
&dra7xx_dsp1__l3_main_1,
&dra7xx_l3_main_1__aes1,
&dra7xx_l3_main_1__aes2,
&dra7xx_l3_main_1__sha0,
+ &dra7xx_l4_per2__mcasp2,
&dra7xx_l4_per2__mcasp3,
+ &dra7xx_l4_per2__mcasp6,
+ &dra7xx_l4_per2__mcasp7,
+ &dra7xx_l4_per2__mcasp8,
&dra7xx_l4_per1__elm,
&dra7xx_l4_wkup__gpio1,
&dra7xx_l4_per1__gpio2,
&dra7xx_l4_per1__gpio7,
&dra7xx_l4_per1__gpio8,
&dra7xx_l3_main_1__gpmc,
+ &dra7xx_l3_main_1__gpu,
&dra7xx_l4_per1__hdq1w,
&dra7xx_l4_per1__i2c1,
&dra7xx_l4_per1__i2c2,
&dra7xx_l4_per1__timer9,
&dra7xx_l4_per1__timer10,
&dra7xx_l4_per1__timer11,
- &dra7xx_l4_wkup__timer12,
&dra7xx_l4_per3__timer13,
&dra7xx_l4_per3__timer14,
&dra7xx_l4_per3__timer15,
NULL,
};
+static struct omap_hwmod_ocp_if *dra7xx_gp_hwmod_ocp_ifs[] __initdata = {
+ &dra7xx_l4_wkup__timer12,
+ NULL,
+};
+
int __init dra7xx_hwmod_init(void)
{
int ret;
omap_hwmod_init();
+
+ if (OMAP2_DEVICE_TYPE_GP != omap_type()) {
+ /* AES, DES, SHAM and RNG HWAs are shared between secure and public
+ worlds for a HS/EMU device. In this case the module clocks are
+ already enabled and should not be touched by the kernel driver.
+ */
+ dra7xx_aes_hwmod_class.sysc = NULL;
+ dra7xx_aes_hwmod_class.rev = 0;
+ dra7xx_aes1_hwmod.prcm.omap4.modulemode = 0;
+ dra7xx_aes2_hwmod.prcm.omap4.modulemode = 0;
+
+ dra7xx_des_hwmod_class.sysc = NULL;
+ dra7xx_des_hwmod_class.rev = 0;
+ dra7xx_des_hwmod.prcm.omap4.modulemode = 0;
+
+ dra7xx_sha0_hwmod_class.sysc = NULL;
+ dra7xx_sha0_hwmod_class.rev = 0;
+ dra7xx_sha0_hwmod.prcm.omap4.modulemode = 0;
+
+ dra7xx_rng_hwmod_class.sysc = NULL;
+ dra7xx_rng_hwmod_class.rev = 0;
+ dra7xx_rng_hwmod.prcm.omap4.modulemode = 0;
+ }
+
ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
+ if (!ret && OMAP2_DEVICE_TYPE_GP == omap_type())
+ ret = omap_hwmod_register_links(dra7xx_gp_hwmod_ocp_ifs);
+
if (!ret && soc_is_dra74x())
return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
else if (!ret && soc_is_dra72x())