index 0dc6b7a2060a4053f286e944d1d0c9d7313e3c00..8d40e8eb3bdaa3fd7131116b5611b47f4c82bcda 100644 (file)
{
int cached = 1;
- omap_sram_size -= OMAP4_ERRATA_I688_SIZE;
-
- if (cpu_is_omap34xx()) {
+#ifdef CONFIG_OMAP4_ERRATA_I688
+ if (cpu_is_omap44xx() || soc_is_omap54xx())
+ omap_sram_size -= OMAP4_ERRATA_I688_SIZE;
+#endif
+ if (cpu_is_omap34xx() || soc_is_am33xx()) {
/*
* SRAM must be marked as non-cached on OMAP3 since the
* CORE DPLL M2 divider change code (in SRAM) runs with the
}
#endif /* CONFIG_ARCH_OMAP3 */
+#ifdef CONFIG_SOC_AM33XX
+static inline int am33xx_sram_init(void)
+{
+ am33xx_push_sram_idle();
+ return 0;
+}
+#else
static inline int am33xx_sram_init(void)
{
return 0;
}
+#endif
int __init omap_sram_init(void)
{