| author | Rajendra Nayak <rnayak@ti.com> | |
| Tue, 8 May 2012 05:55:21 +0000 (23:55 -0600) | ||
| committer | Paul Walmsley <paul@pwsan.com> | |
| Tue, 8 May 2012 05:55:21 +0000 (23:55 -0600) | ||
| commit | 4e68f5a79da5b595fc40ceff5ebcfa3e6637bf37 | |
| tree | 1756942d86be26b7790a7fb825e816708f5b197d | tree | snapshot (tar.xz tar.gz zip) |
| parent | 96566043b19ae76d3828ce75cbf28dc6d0bcaaf1 | commit | diff |
ARM: OMAP3: Fix CM register bit masks
The register bits for MPU_CLK_SRC and IVA2_CLK_SRC in CM_CLKSEL1_PLL
register are 3 bits wide. Fix the MASK definition accordingly.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
The register bits for MPU_CLK_SRC and IVA2_CLK_SRC in CM_CLKSEL1_PLL
register are 3 bits wide. Fix the MASK definition accordingly.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
| arch/arm/mach-omap2/cm-regbits-34xx.h | diff | blob | history |