author | Lajos Molnar <lajos@ti.com> | |
Tue, 9 Apr 2013 21:52:13 +0000 (14:52 -0700) | ||
committer | Praneeth Bajjuri <praneeth@ti.com> | |
Fri, 12 Jul 2013 22:54:13 +0000 (17:54 -0500) | ||
commit | 73af561aaa368d596a374cf7765be45b8497f930 | |
tree | 1dfded685e1f5bdfd413b9abcb24c74ad92f917e | tree | snapshot (tar.xz tar.gz zip) |
parent | 0402e5e8698a4c642b408fcde38dd8cf5ef34582 | commit | diff |
gpu: OMAP2: generic Android display configuration setup
Added android_display methods to allow runtime configuration of
Android display resources, such as:
- FB0's vram is dynamically calculated from the number of
buffers SGX requires in VRAM (swap chain and/or composition
buffers), and the FB0 display size.
- OMAP VRAM is calculated from FB0's vram need + any other
specified FB's vram. (If command line is used to specify
FB vrams, omap vram must also be specified.)
- TILER1D area reserved for use as DSS MMU by DSSCOMP is
calculated from default display size. It can be overriden
by board file.
- TILER2D carveout size is reduced by TILER1D area (if coallocated
with TILER2D) and by the TILER2D SGX buffers (swapchain and/or
composition buffers)
- nonsecure TILER2D carveout size is set to the backpages needed
by TILER2D SGX buffers.
All of this is coordinated by omap_android_display_setup. It
takes pointers to the DSS board info, FB platform data, and
optionally to the ION, SGX and DSSCOMP platform data. It should
be called in board_reserve before omap_ion_init.
If SGX data is provided, it is set as the SGX platform data for
FB0. Similarly, if DSSCOMP platform data is provided it is
also set. This can be used to set a preferred tiler1d slot size.
If ION platform data is provided, it is updated with the required
tiler2d carveout sizes.
NOTE:
To maximize TILER2D space, the TILER1D area reserved for android
display is not aligned to 1MB, but is aligned to 32 pages as the
smallest 2D allocation needs a 32-page band. We further reduce
TILER2D space by the container space lost by the SGX buffers,
which may be larger than the actual backpages bneeded for the
SGX buffers.
Therefore the sum of secure + nonsecure + 1D tiler space may
be smaller than the available container space.
Ported to latest SGX DDK by Dima Svetlov.
Change-Id: I5d8858c38efd842452994e3a3476463083d200d7
Signed-off-by: Lajos Molnar <lajos@ti.com>
Signed-off-by: Dima Svetlov <svetlov@ti.com>
Signed-off-by: Muralidhar Dixit <murali.dixit@ti.com>
Signed-off-by: Dandawate Saket <dsaket@ti.com>
Added android_display methods to allow runtime configuration of
Android display resources, such as:
- FB0's vram is dynamically calculated from the number of
buffers SGX requires in VRAM (swap chain and/or composition
buffers), and the FB0 display size.
- OMAP VRAM is calculated from FB0's vram need + any other
specified FB's vram. (If command line is used to specify
FB vrams, omap vram must also be specified.)
- TILER1D area reserved for use as DSS MMU by DSSCOMP is
calculated from default display size. It can be overriden
by board file.
- TILER2D carveout size is reduced by TILER1D area (if coallocated
with TILER2D) and by the TILER2D SGX buffers (swapchain and/or
composition buffers)
- nonsecure TILER2D carveout size is set to the backpages needed
by TILER2D SGX buffers.
All of this is coordinated by omap_android_display_setup. It
takes pointers to the DSS board info, FB platform data, and
optionally to the ION, SGX and DSSCOMP platform data. It should
be called in board_reserve before omap_ion_init.
If SGX data is provided, it is set as the SGX platform data for
FB0. Similarly, if DSSCOMP platform data is provided it is
also set. This can be used to set a preferred tiler1d slot size.
If ION platform data is provided, it is updated with the required
tiler2d carveout sizes.
NOTE:
To maximize TILER2D space, the TILER1D area reserved for android
display is not aligned to 1MB, but is aligned to 32 pages as the
smallest 2D allocation needs a 32-page band. We further reduce
TILER2D space by the container space lost by the SGX buffers,
which may be larger than the actual backpages bneeded for the
SGX buffers.
Therefore the sum of secure + nonsecure + 1D tiler space may
be smaller than the available container space.
Ported to latest SGX DDK by Dima Svetlov.
Change-Id: I5d8858c38efd842452994e3a3476463083d200d7
Signed-off-by: Lajos Molnar <lajos@ti.com>
Signed-off-by: Dima Svetlov <svetlov@ti.com>
Signed-off-by: Muralidhar Dixit <murali.dixit@ti.com>
Signed-off-by: Dandawate Saket <dsaket@ti.com>
arch/arm/plat-omap/Makefile | diff | blob | history |