| author | Nishanth Menon <nm@ti.com> | |
| Fri, 7 Aug 2015 21:55:53 +0000 (16:55 -0500) | ||
| committer | Praneeth Bajjuri <praneeth@ti.com> | |
| Fri, 7 Aug 2015 21:56:55 +0000 (16:56 -0500) | ||
| commit | 906de47bd967029cae5bc95d2d9191cc85376957 | |
| tree | b99075c5809a53a17868890da06b9c761d4390f4 | tree | snapshot (tar.xz tar.gz zip) |
| parent | 34bbc3d77f0ad359608a26006b5d85142cffda00 | commit | diff |
ARM: OMAP: DRA7: powerdomain data: Erratum i892 workaround: Disable core INA
Erratum i892 as will be documented in the upcoming G or later revision
of DRA7xx/ AM57xx errata documentation (SPRZ398F) states that L3 clock
needs to be kept active all the time to ensure that asymmetric aging
degradation is minimal and within the design allowed margin.
by allowing core domain to transition to INA and allowing L3 clock to be
turned off for extended periods of time, there is a risk of functional
issues.
Due to this change, there is a minimal impact on power numbers in low
power state.
Signed-off-by: Nishanth Menon <nm@ti.com>
[cherrypick to 3.14 baseline]
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
Change-Id: I8140ea33686758fc2c03b09a3009e656b4a94294
Erratum i892 as will be documented in the upcoming G or later revision
of DRA7xx/ AM57xx errata documentation (SPRZ398F) states that L3 clock
needs to be kept active all the time to ensure that asymmetric aging
degradation is minimal and within the design allowed margin.
by allowing core domain to transition to INA and allowing L3 clock to be
turned off for extended periods of time, there is a risk of functional
issues.
Due to this change, there is a minimal impact on power numbers in low
power state.
Signed-off-by: Nishanth Menon <nm@ti.com>
[cherrypick to 3.14 baseline]
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
Change-Id: I8140ea33686758fc2c03b09a3009e656b4a94294
| arch/arm/mach-omap2/powerdomains7xx_data.c | diff | blob | history |