| author | Jyri Sarha <jsarha@ti.com> | |
| Mon, 10 Jun 2013 12:41:34 +0000 (15:41 +0300) | ||
| committer | Jyri Sarha <jsarha@ti.com> | |
| Mon, 10 Jun 2013 13:02:35 +0000 (16:02 +0300) | ||
| commit | bff21217cff87b9698bac76ebe078252665a4f6b | |
| tree | e534e647dabf2b8d00a60130a57139c20b72ff5c | tree | snapshot (tar.xz tar.gz zip) |
| parent | 41b605f2887879d5e428928b197e24ffb44d9b82 | commit | diff |
ARM: dts: OMAP5: AESS: Fix AESS L3 Interconnect address
OMAP543x_ES2.0_Public_TRM from May 2013 has this same bug too, but the
right address is 490f1000. Also the bit-wise match to MPU private
access looks better this way.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
OMAP543x_ES2.0_Public_TRM from May 2013 has this same bug too, but the
right address is 490f1000. Also the bit-wise match to MPU private
access looks better this way.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
| arch/arm/boot/dts/omap5.dtsi | diff | blob | history |