ARM: OMAP2+: sleep43xx: Add omap_bus_sync style accesses

According to AM437x Silicon Errata document (SPRZ408, June 2014)
Advisory 11, the SoC also suffers from the potential Asynchronous Bridge
Corruption issues seen on OMAP4, which were corrected by 137d105d5. Add
omap_bus_sync style accesses to DRAM and SRAM to avoid hangs during
suspend/resume by perfoming one strongly ordered write to DRAM and one
to SRAM before calling WFI in the suspend path assembly code.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>

diff --git a/arch/arm/mach-omap2/sleep43xx.S b/arch/arm/mach-omap2/sleep43xx.S
index dde628ba2b98a63aa4bcd681263c23a626ec2af0..9444fd4a5f11729f747429a030b7cfe74493b4ef 100644 (file)
--- a/arch/arm/mach-omap2/sleep43xx.S
+++ b/arch/arm/mach-omap2/sleep43xx.S
@@ -225,8 +225,10 @@ sync:
        orr     r1, r1, #EMIF_POWER_MGMT_SELF_REFRESH_MODE
        str     r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
 
-       ldr     r1, dram_sync_word      @ a dummy access to DDR as per spec
+       ldr     r1, dram_sync_word      @ access DRAM
        ldr     r2, [r1, #0]
+       str     r2, [r1, #0]
+       isb
 
        mov     r1, #EMIF_POWER_MGMT_DELAY_PERIOD       @ Wait for system
 wait_self_refresh:                                     @ to enter SR
@@ -290,6 +292,11 @@ am43xx_deep_sleep_suspend:
        ldr     r1, am43xx_virt_mpu_clkstctrl
        mov     r2, #AM43XX_CM_CLKSTCTRL_CLKTRCTRL_SW_SLEEP
        str     r2, [r1]
+bus_sync:
+       ldr     r1, ddr_start           @ access SRAM
+       str     r1, ddr_start
+
+       isb
 
        /*
         * Execute a barrier instruction to ensure that all cache,
@@ -298,6 +305,7 @@ am43xx_deep_sleep_suspend:
         */
        dsb
        dmb
+       isb
 
        /*
         * Execute a WFI instruction and wait until the