Merge branch 'pm-linux-3.8.y' into ti-linux-3.8.y
authorDan Murphy <dmurphy@ti.com>
Wed, 13 Mar 2013 18:09:47 +0000 (13:09 -0500)
committerDan Murphy <dmurphy@ti.com>
Wed, 13 Mar 2013 18:09:47 +0000 (13:09 -0500)
TI-Feature: power_management
TI-Tree: git://git.ti.com/~kristo/ti-linux-kernel/pm-linux-feature-tree.git
TI-Branch: pm-linux-3.8.y

* pm-linux-3.8.y: (61 commits)
  ARM: OMAP2+: AM33XX: Hookup AM33XX PM code into OMAP builds
  ARM: OMAP2+: AM33XX: Select Mailbox when PM is enabled
  ARM: OMAP2+: AM33XX: Basic suspend resume support
  ARM: OMAP2+: AM33XX: Add assembly code for PM operations
  ARM: OMAP2+: AM33XX: timer: Interchange clkevt and clksrc timers
  ARM: OMAP2+: timer: Add suspend-resume callbacks for clockevent device
  ARM: OMAP2+: Fix selection of clockevent timer when using device-tree
  ARM: OMAP: DTB: Update IRQ data for WKUP_M3
  ARM: OMAP2+: AM33XX: control: Add some control module registers and APIs
  memory: emif: Move EMIF related header file to include/linux/
  ARM: OMAP2: am33xx-hwmod: Fix "register offset NULL check" bug
  ARM: OMAP2+: AM33xx: hwmod: add missing HWMOD_NO_IDLEST flags
  ARM: OMAP: AM33xx hwmod: Add parent-child relationship for PWM subsystem
  ARM: OMAP: AM33xx hwmod: Corrects PWM subsystem HWMOD entries
  ARM: DTS: AM33XX: Add nodes for OCMC RAM and WKUP-M3
  ARM: OMAP2+: AM33XX: Update the hardreset API
  ARM: OMAP2+: AM33XX: hwmod: Update the WKUP-M3 hwmod with reset status bit
  ARM: OMAP2+: AM33XX: hwmod: Fixup cpgmac0 hwmod entry
  ARM: OMAP2+: AM33XX: hwmod: Update TPTC0 hwmod with the right flags
  ARM: OMAP2+: AM33XX: hwmod: Register OCMC RAM hwmod
  ...

Conflicts:
arch/arm/boot/dts/am33xx.dtsi
arch/arm/mach-omap2/omap_hwmod_33xx_data.c

Signed-off-by: Dan Murphy <dmurphy@ti.com>
1  2 
arch/arm/boot/dts/am33xx.dtsi
arch/arm/mach-omap2/Kconfig
arch/arm/mach-omap2/Makefile
arch/arm/mach-omap2/board-generic.c
arch/arm/mach-omap2/common.h
arch/arm/mach-omap2/omap_hwmod.c
arch/arm/mach-omap2/omap_hwmod_33xx_data.c
drivers/memory/emif.c

index ef5f923b086c035157dc19297569c0bf4b0757c8,41abaa2ff4930901e6814878418dcb6d768fa5eb..f01809bc1119f7e0f23995ccef9e718206075701
                        };
                };
  
 +              sham: sham@53100000 {
 +                      compatible = "ti,omap4-sham";
 +                      ti,hwmods = "sham";
 +                      #address-cells = <1>;
 +                      #size-cells = <0>;
 +                      reg = <0x53100000 0x200>;
 +                      interrupt-parent = <&intc>;
 +                      interrupts = <109>;
 +                      dmas = <&edma 36>;
 +                      dma-names = "rx";
 +              };
 +
 +              aes: aes@53500000 {
 +                      compatible = "ti,omap4-aes";
 +                      ti,hwmods = "aes";
 +                      #address-cells = <1>;
 +                      #size-cells = <0>;
 +                      reg = <0x53500000 0xa0>;
 +                      interrupt-parent = <&intc>;
 +                      interrupts = <102>;
 +                      dmas = <&edma 6
 +                              &edma 5>;
 +                      dma-names = "tx", "rx";
 +              };
++
+               ocmcram: ocmcram@40300000 {
+                       compatible = "ti,am3352-ocmcram";
+                       reg = <0x40300000 0x10000>;
+                       ti,hwmods = "ocmcram";
+                       ti,no_idle_on_suspend;
+               };
+               wkup_m3: wkup_m3@44d00000 {
+                       compatible = "ti,am3353-wkup-m3";
+                       reg = <0x44d00000 0x4000        /* M3 UMEM */
+                              0x44d80000 0x2000>;      /* M3 DMEM */
+                       interrupts = <78>;
+                       ti,hwmods = "wkup_m3";
+               };
        };
  };
Simple merge
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Simple merge
index bb78cf07a9b7ff4bc612861433e428512849ba59,f4c2c2b7dc12818adbacc3bb72598cbd5b81336a..1debca32ff11252ec2e8151cd5c90d0dd807b43b
@@@ -417,8 -417,9 +418,7 @@@ static struct omap_hwmod am33xx_adc_tsc
   *    - cEFUSE (doesn't fall under any ocp_if)
   *    - clkdiv32k
   *    - debugss
-  *    - ocmc ram
   *    - ocp watch point
 - *    - aes0
 - *    - sha0
   */
  #if 0
  /*
@@@ -518,21 -500,12 +499,40 @@@ static struct omap_hwmod am33xx_ocpwp_h
                },
        },
  };
 +#endif
 +
++/* ocmcram */
++static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
++      .name = "ocmcram",
++};
++
++static struct omap_hwmod am33xx_ocmcram_hwmod = {
++      .name           = "ocmcram",
++      .class          = &am33xx_ocmcram_hwmod_class,
++      .clkdm_name     = "l3_clkdm",
++      .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
++      .main_clk       = "l3_gclk",
++      .prcm           = {
++              .omap4  = {
++                      .clkctrl_offs   = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
++                      .modulemode     = MODULEMODE_SWCTRL,
++              },
++      },
++};
  /*
 - * 'aes' class
 + * 'aes0' class
   */
 -static struct omap_hwmod_class am33xx_aes_hwmod_class = {
 -      .name           = "aes",
 +static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
 +      .rev_offs       = 0x80,
 +      .sysc_offs      = 0x84,
 +      .syss_offs      = 0x88,
 +      .sysc_flags     = SYSS_HAS_RESET_STATUS,
 +};
 +
 +static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
 +      .name           = "aes0",
 +      .sysc           = &am33xx_aes0_sysc,
  };
  
  static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
@@@ -3388,42 -3445,13 +3486,49 @@@ static struct omap_hwmod_ocp_if am33xx_
        .flags          = OCPIF_SWSUP_IDLE,
  };
  
 +/* l3 main -> sha0 HIB2 */
 +static struct omap_hwmod_addr_space am33xx_sha0_addrs[] = {
 +      {
 +              .pa_start       = 0x53100000,
 +              .pa_end         = 0x53100000 + SZ_512 - 1,
 +              .flags          = ADDR_TYPE_RT
 +      },
 +      { }
 +};
 +
 +static struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = {
 +      .master         = &am33xx_l3_main_hwmod,
 +      .slave          = &am33xx_sha0_hwmod,
 +      .clk            = "sha0_fck",
 +      .addr           = am33xx_sha0_addrs,
 +      .user           = OCP_USER_MPU | OCP_USER_SDMA,
 +};
 +
 +/* l3 main -> AES0 HIB2 */
 +static struct omap_hwmod_addr_space am33xx_aes0_addrs[] = {
 +      {
 +              .pa_start       = 0x53500000,
 +              .pa_end         = 0x53500000 + SZ_1M - 1,
 +              .flags          = ADDR_TYPE_RT
 +      },
 +      { }
 +};
 +
 +static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
 +      .master         = &am33xx_l3_main_hwmod,
 +      .slave          = &am33xx_aes0_hwmod,
 +      .clk            = "aes0_fck",
 +      .addr           = am33xx_aes0_addrs,
 +      .user           = OCP_USER_MPU | OCP_USER_SDMA,
 +};
 +
+ /* l3 main -> ocmc */
+ static struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
+       .master         = &am33xx_l3_main_hwmod,
+       .slave          = &am33xx_ocmcram_hwmod,
+       .user           = OCP_USER_MPU | OCP_USER_SDMA,
+ };
  static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
        &am33xx_l4_fw__emif_fw,
        &am33xx_l3_main__emif,
Simple merge