| author | Praneeth Bajjuri <praneeth@ti.com> | |
| Mon, 8 Jun 2015 17:08:14 +0000 (12:08 -0500) | ||
| committer | Praneeth Bajjuri <praneeth@ti.com> | |
| Mon, 8 Jun 2015 17:08:14 +0000 (12:08 -0500) |
* 'ti-linux-3.14.y' of git://git.ti.com/ti-linux-kernel/ti-linux-kernel: (52 commits)
mmc: host: omap_hsmmc: Fix DTO and DCRC handling
drm/omap: ensure all displays have been probed
ARM: DRA7: hwmod: Fix gpmc hwmod
ARM: OMAP2+: AMX3XX: Add HWMOD_NEEDS_REIDLE to gpmc
ARM: OMAP2+: omap_hwmod: Reidle flagged hwmods when restoring context
ARM: OMAP2+: omap_hwmod: Add softreset to _reidle
ARM: OMAP2+: omap_hwmod: Refactor HWMOD_NEEDS_REIDLE support code
ARM: OMAP2+: omap_hwmod: Always restore saved hardreset context
ARM: DRA7: hwmod: Fix GPMC from preventing core suspend
ARM: DRA7: hwmod: fix gpmc hwmod
media: ti-vpe: vip: Fix input/std/parm reporting
media: ti-vpe: VIP/VPE/VPDMA: Correction of data type label.
media: ti-vpe: vip: Fix format negotiation with sub-device
OMAPDSS: dra7-tpd12s015: fix dependency to mcasp
samples/rpmsg: add support for multiple instances
Revert "ARM: OMAP: DRA7: change IPU1 clk domain to SWSUP for proper boot"
ARM: OMAP2+: use separate IOMMU pdata to fix DRA7 IPU1 boot
iommu/omap: fix boot issue on remoteprocs with AMMU/Unicache
iommu/omap: add pdata ops for setting powerdomain constraint
ARM: dts: am437x-sk-evm: disable DDR regulator in rtc-only/poweroff mode
...
Conflicts:
arch/arm/boot/dts/dra7.dtsi
arch/arm/mach-omap2/omap_hwmod_7xx_data.c
drivers/iommu/omap-iommu.c
drivers/iommu/omap-iommu.h
Change-Id: I45cd013d30f0226f5f1e57b5e7824fc160c94eef
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
mmc: host: omap_hsmmc: Fix DTO and DCRC handling
drm/omap: ensure all displays have been probed
ARM: DRA7: hwmod: Fix gpmc hwmod
ARM: OMAP2+: AMX3XX: Add HWMOD_NEEDS_REIDLE to gpmc
ARM: OMAP2+: omap_hwmod: Reidle flagged hwmods when restoring context
ARM: OMAP2+: omap_hwmod: Add softreset to _reidle
ARM: OMAP2+: omap_hwmod: Refactor HWMOD_NEEDS_REIDLE support code
ARM: OMAP2+: omap_hwmod: Always restore saved hardreset context
ARM: DRA7: hwmod: Fix GPMC from preventing core suspend
ARM: DRA7: hwmod: fix gpmc hwmod
media: ti-vpe: vip: Fix input/std/parm reporting
media: ti-vpe: VIP/VPE/VPDMA: Correction of data type label.
media: ti-vpe: vip: Fix format negotiation with sub-device
OMAPDSS: dra7-tpd12s015: fix dependency to mcasp
samples/rpmsg: add support for multiple instances
Revert "ARM: OMAP: DRA7: change IPU1 clk domain to SWSUP for proper boot"
ARM: OMAP2+: use separate IOMMU pdata to fix DRA7 IPU1 boot
iommu/omap: fix boot issue on remoteprocs with AMMU/Unicache
iommu/omap: add pdata ops for setting powerdomain constraint
ARM: dts: am437x-sk-evm: disable DDR regulator in rtc-only/poweroff mode
...
Conflicts:
arch/arm/boot/dts/dra7.dtsi
arch/arm/mach-omap2/omap_hwmod_7xx_data.c
drivers/iommu/omap-iommu.c
drivers/iommu/omap-iommu.h
Change-Id: I45cd013d30f0226f5f1e57b5e7824fc160c94eef
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
12 files changed:
diff --cc arch/arm/boot/dts/dra7-evm.dts
index 379ca5eb0c90a13e30c51a9e6aaf054460de8cc4,56d0aba0335cdbc0aaebe9a2c88b2b9cd08768a9..f25c2bc0387a7cb8b0d23a8dcd71b54eedaf56aa
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1 2 0 0
>;
+ tx-num-evt = <8>;
+ rx-num-evt = <8>;
+};
+
+&mcasp7 {
+ #sound-dai-cells = <0>;
+
+ status = "okay";
+
+ op-mode = <0>; /* MCASP_IIS_MODE */
+ tdm-slots = <4>;
+ /* 4 serializer */
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 2 1 0 0
+ >;
+ tx-num-evt = <8>;
+ rx-num-evt = <8>;
};
+ &mcasp8 {
+ /* not used for audio. only the AXR2 pin is used as GPIO */
+ status = "okay";
+ };
+
&usb2_phy1 {
phy-supply = <&ldousb_reg>;
};
diff --cc arch/arm/boot/dts/dra7.dtsi
index 0cc93afd7b49514c40b0d712c0056c0755dc3e33,3dcc00d0eec11ae5547f0455e515d092696dd476..12a0c60bc114ef0cbbd5d69c4908cc814aa8dffa
status = "disabled";
};
- dmas = <&sdma 143 &dmacb>, <&sdma 142 &dmacb>;
+ mcasp6: mcasp@48474000 {
+ compatible = "ti,dra7-mcasp-audio";
+ ti,hwmods = "mcasp6";
+ reg = <0x48474000 0x2000>,
+ <0x4844c000 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ dmas = <&sdma_xbar 139>, <&sdma_xbar 138>;
+ dma-names = "tx", "rx";
+ clocks = <&mcasp6_ahclkx_mux>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+
+ mcasp7: mcasp@48478000 {
+ compatible = "ti,dra7-mcasp-audio";
+ ti,hwmods = "mcasp7";
+ reg = <0x48478000 0x2000>,
+ <0x48450000 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ dmas = <&sdma_xbar 141>, <&sdma_xbar 140>;
+ dma-names = "tx", "rx";
+ clocks = <&mcasp7_ahclkx_mux>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+
+ mcasp8: mcasp@4847c000 {
+ compatible = "ti,dra7-mcasp-audio";
+ ti,hwmods = "mcasp8";
+ reg = <0x4847c000 0x2000>,
+ <0x48454000 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
++ dmas = <&sdma_xbar 143>, <&sdma_xbar 142>;
+ dma-names = "tx", "rx";
+ clocks = <&mcasp8_ahclkx_mux>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+
vip1: vip@0x48970000 {
compatible = "ti,vip1";
reg = <0x48970000 0x10000>,
diff --cc arch/arm/boot/dts/dra7xx-clocks.dtsi
Simple merge
index aa2bf0ac8eef1cc8236473906a08715904909b1f,d0967a0846a84dd5f8f96c5417ad3b44d51bbdff..7d756d8e3c6c762b41e100fb145585fc9792c0de
},
};
+/* mcasp6 */
+static struct omap_hwmod dra7xx_mcasp6_hwmod = {
+ .name = "mcasp6",
+ .class = &dra7xx_mcasp_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "mcasp6_ahclkx_mux",
+ .flags = HWMOD_SWSUP_SIDLE_ACT,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* mcasp7 */
+static struct omap_hwmod dra7xx_mcasp7_hwmod = {
+ .name = "mcasp7",
+ .class = &dra7xx_mcasp_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "mcasp7_ahclkx_mux",
+ .flags = HWMOD_SWSUP_SIDLE_ACT,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,
++ .modulemode = MODULEMODE_SWCTRL,
++ },
++ },
++};
++
+ /* mcasp8 */
+ static struct omap_hwmod dra7xx_mcasp8_hwmod = {
+ .name = "mcasp8",
+ .class = &dra7xx_mcasp_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "mcasp8_ahclkx_mux",
+ .flags = HWMOD_SWSUP_SIDLE_ACT,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* l4_per2 -> mcasp6 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_mcasp6_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per2 -> mcasp7 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_mcasp7_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+ /* l4_per2 -> mcasp8 */
+ static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_mcasp8_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = {
{
.pa_start = 0x48078000,
&dra7xx_l3_main_1__aes1,
&dra7xx_l3_main_1__aes2,
&dra7xx_l3_main_1__sha0,
+ &dra7xx_l4_per2__mcasp2,
&dra7xx_l4_per2__mcasp3,
+ &dra7xx_l4_per2__mcasp6,
+ &dra7xx_l4_per2__mcasp7,
+ &dra7xx_l4_per2__mcasp8,
&dra7xx_l4_per1__elm,
&dra7xx_l4_wkup__gpio1,
&dra7xx_l4_per1__gpio2,
diff --cc drivers/clk/ti/clk-7xx.c
Simple merge
diff --cc drivers/gpu/drm/omapdrm/omap_drv.c
Simple merge
diff --cc drivers/iommu/omap-iommu.c
index 11d5d44676df1250685bc0e2e7429349b4793508,1b2c3ac2fe0d2f08db681403f111092fb2acde49..b5548605bb71ddcd4b322f51c8e1d840d07566a8
struct omap_iommu *obj = to_iommu(dev);
int ret = 0;
- if (pdata && pdata->deassert_reset) {
+ if (pdata && pdata->set_pwrdm_constraint) {
+ ret = pdata->set_pwrdm_constraint(pdev, true, &obj->pwrst);
+ if (ret) {
+ dev_warn(dev, "pwrdm_constraint failed to be set, status = %d\n",
+ ret);
+ }
+ }
+
++
+ /* do not deassert reset only during initial boot for late attach */
+ if ((!obj->late_attach || obj->domain) &&
+ pdata && pdata->deassert_reset) {
ret = pdata->deassert_reset(pdev, pdata->reset_name);
if (ret) {
dev_err(dev, "deassert_reset failed: %d\n", ret);
diff --cc drivers/iommu/omap-iommu.h
index 2d9b41c0d494842c82528d241fd0c809ddca96a2,5d76c0844a82c2a21a64d838803bea0eb82f3c9b..a7331a3cf13f9eb27b591de9933c3c992720ceb0
int has_bus_err_back;
u32 id;
+ u32 late_attach;
+ u8 pwrst;
};
struct cr_regs {
diff --cc drivers/mmc/host/omap_hsmmc.c
Simple merge
diff --cc drivers/remoteproc/omap_remoteproc.c
index 1f00ca353ca5515a72f866949cd6a46faa7f368f,d4a0e0d9f475bbf3ebfed94b1eb063efb54ef66e..231dc8f3920ae9753c513ba564711807f8ec40ea
goto put_mbox;
}
- ret = pdata->device_enable(pdev);
- if (ret) {
- dev_err(dev, "omap_device_enable failed: %d\n", ret);
- goto reset_timers;
+ if (!rproc->late_attach) {
+ ret = pdata->device_enable(pdev);
+ if (ret) {
+ dev_err(dev, "omap_device_enable failed: %d\n", ret);
+ goto reset_timers;
+ }
}
+ /*
+ * remote processor is up, so update the runtime pm status and
+ * enable the auto-suspend. The device usage count is incremented
+ * manually for balancing it for auto-suspend
+ */
+ pm_runtime_set_active(dev);
+ pm_runtime_enable(dev);
+ pm_runtime_get_noresume(dev);
+ pm_runtime_set_autosuspend_delay(dev, oproc->autosuspend_delay);
+ pm_runtime_use_autosuspend(dev);
+ pm_runtime_mark_last_busy(dev);
+ pm_runtime_put_autosuspend(dev);
+
return 0;
reset_timers:
ret = omap_rproc_disable_timers(pdev, true);
if (ret)
- return ret;
+ goto enable_device;
+ /*
+ * During late attach, we use non-zeroing dma ops to prevent the kernel
+ * from overwriting already loaded code and data segments. When
+ * shutting down the processor, we restore the normal zeroing dma ops.
+ * This allows the kernel to clear memory when loading a new remoteproc
+ * binary or during error recovery with the current remoteproc binary.
+ */
+ if (rproc->late_attach)
+ set_dma_ops(dev, &arm_dma_ops);
+
mbox_free_channel(oproc->mbox);
+ /*
+ * update the runtime pm states and status now that the remoteproc
+ * has stopped
+ */
+ pm_runtime_dont_use_autosuspend(dev);
+ pm_runtime_put_noidle(dev);
+ pm_runtime_disable(dev);
+ pm_runtime_set_suspended(dev);
+
return 0;
+
+ enable_device:
+ pdata->device_enable(pdev);
+ out:
+ /* schedule the next auto-suspend */
+ pm_runtime_mark_last_busy(dev);
+ pm_runtime_put_autosuspend(dev);
+ return ret;
+
}
static struct rproc_ops omap_rproc_ops = {
diff --cc sound/soc/davinci/davinci-mcasp.c
Simple merge
diff --cc ti_config_fragments/connectivity.cfg
Simple merge