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raw | patch | inline | side by side (parent: 5923e2e)
| author | Jyri Sarha <jsarha@ti.com> | |
| Thu, 2 May 2013 13:18:05 +0000 (16:18 +0300) | ||
| committer | Jyri Sarha <jsarha@ti.com> | |
| Mon, 10 Jun 2013 11:31:56 +0000 (14:31 +0300) |
After this commit the content of sound/soc/omap matches to commit
0769a881 in git://gitorious.org/omap-audio/linux-audio.git with
following exceptions:
These commits not found from LDC tree are not overwritten:
ASoC: omap-abe-core: Call driver_deffered_probe_trigger only if built in
ASoC: OMAP: HDMI: Add support for DT boot
ASoC: HDMI: CPU-DAI: Correct typo
ASoC: OMAP: HDMI: Add config support for OMAP5
These commits from LDC tree are not included:
ASoC: omap: Check regulator enable for DAC on Pandora
ASoC: tlv320aic3x: Convert mic bias to a supply widget
ASoC: omap-pcm: No need to set constraint at open time
This commit is needed to bring the working ABE support from LDC audio
tree to LCPD AV-tree. The history of the old LCPD AV-tree does not
match LDC audio tree history (the "same" commits had different
content) so merge was not possible and this hackish commit was
needed.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
0769a881 in git://gitorious.org/omap-audio/linux-audio.git with
following exceptions:
These commits not found from LDC tree are not overwritten:
ASoC: omap-abe-core: Call driver_deffered_probe_trigger only if built in
ASoC: OMAP: HDMI: Add support for DT boot
ASoC: HDMI: CPU-DAI: Correct typo
ASoC: OMAP: HDMI: Add config support for OMAP5
These commits from LDC tree are not included:
ASoC: omap: Check regulator enable for DAC on Pandora
ASoC: tlv320aic3x: Convert mic bias to a supply widget
ASoC: omap-pcm: No need to set constraint at open time
This commit is needed to bring the working ABE support from LDC audio
tree to LCPD AV-tree. The history of the old LCPD AV-tree does not
match LDC audio tree history (the "same" commits had different
content) so merge was not possible and this hackish commit was
needed.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
28 files changed:
diff --git a/sound/soc/omap/Kconfig b/sound/soc/omap/Kconfig
index 3c9887f4597d9689da6e7eadbeb321729d518f58..9afb392e87e825cb9ac7958ac056c7aeec647517 100644 (file)
--- a/sound/soc/omap/Kconfig
+++ b/sound/soc/omap/Kconfig
config SND_OMAP_SOC_OMAP_ABE_TWL6040
tristate "SoC Audio support for OMAP boards using ABE and twl6040 codec"
- depends on TWL6040_CORE && SND_OMAP_SOC && ARCH_OMAP4
+ depends on TWL6040_CORE && SND_OMAP_SOC && (ARCH_OMAP4 || SOC_OMAP5)
select SND_OMAP_SOC_DMIC
select SND_OMAP_SOC_MCPDM
select SND_SOC_TWL6040
- SDP4430/Blaze boards
- PandaBoard (4430)
- PandaBoardES (4460)
+ - PandaBoard 5 (5432)
config SND_OMAP_SOC_OMAP_HDMI
tristate "SoC Audio support for Texas Instruments OMAP HDMI"
index cb0b4e8c09769fdb58936c407152c81349b4aa99..3963a24349c5dfdf0b06ca875b0125245166307c 100644 (file)
abe_ini.o \
abe_gain.o \
abe_port.o \
- abe_seq.o \
port_mgr.o \
obj-$(CONFIG_SND_OMAP_SOC_ABE) += snd-soc-abe-hal.o
index 0a25f6c9415be18c206e623a7d3d12de09c65db5..058401814775a199c08f44204fe513d40c0545c4 100644 (file)
*
* GPL LICENSE SUMMARY
*
- * Copyright(c) 2010-2012 Texas Instruments Incorporated,
+ * Copyright(c) 2010-2013 Texas Instruments Incorporated,
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
#include <linux/slab.h>
#include <linux/io.h>
-#include "abe_def.h"
-#include "abe_typ.h"
-#include "abe_ext.h"
+#include "aess-fw.h"
#include <linux/debugfs.h>
#define OMAP_ABE_MAX_PORT_ID OMAP_ABE_FE_PORT_MM_DL_LP
-/* ABE copy function IDs */
-#define OMAP_AESS_COPY_FCT_NULL_ID 0
-#define OMAP_AESS_COPY_FCT_S2D_STEREO_16_16_ID 1
-#define OMAP_AESS_COPY_FCT_S2D_MONO_MSB_ID 2
-#define OMAP_AESS_COPY_FCT_S2D_STEREO_MSB_ID 3
-#define OMAP_AESS_COPY_FCT_S2D_STEREO_RSHIFTED_16_ID 4
-#define OMAP_AESS_COPY_FCT_S2D_MONO_RSHIFTED_16_ID 5
-#define OMAP_AESS_COPY_FCT_D2S_STEREO_16_16_ID 6
-#define OMAP_AESS_COPY_FCT_D2S_MONO_MSB_ID 7
-#define OMAP_AESS_COPY_FCT_D2S_MONO_RSHIFTED_16_ID 8
-#define OMAP_AESS_COPY_FCT_D2S_STEREO_RSHIFTED_16_ID 9
-#define OMAP_AESS_COPY_FCT_D2S_STEREO_MSB_ID 10
-#define OMAP_AESS_COPY_FCT_DMIC_ID 11
-#define OMAP_AESS_COPY_FCT_MCPDM_DL_ID 12
-#define OMAP_AESS_COPY_FCT_MM_UL_ID 13
-#define OMAP_AESS_COPY_FCT_SPLIT_SMEM_ID 14
-#define OMAP_AESS_COPY_FCT_MERGE_SMEM_ID 15
-#define OMAP_AESS_COPY_FCT_SPLIT_TDM_ID 16
-#define OMAP_AESS_COPY_FCT_MERGE_TDM_ID 17
-#define OMAP_AESS_COPY_FCT_ROUTE_MM_UL_ID 18
-#define OMAP_AESS_COPY_FCT_IO_IP_ID 19
-#define OMAP_AESS_COPY_FCT_COPY_UNDERFLOW_ID 20
-#define OMAP_AESS_COPY_FCT_COPY_MCPDM_DL_HF_PDL1_ID 21
-#define OMAP_AESS_COPY_FCT_COPY_MCPDM_DL_HF_PDL2_ID 22
-#define OMAP_AESS_COPY_FCT_S2D_MONO_16_16_ID 23
-#define OMAP_AESS_COPY_FCT_D2S_MONO_16_16_ID 24
-#define OMAP_AESS_COPY_FCT_DMIC_NO_PRESCALE_ID 25
-
-/* ABE buffer IDs */
-#define OMAP_AESS_BUFFER_ZERO_ID 0
-#define OMAP_AESS_BUFFER_DMIC1_L_ID 1
-#define OMAP_AESS_BUFFER_DMIC1_R_ID 2
-#define OMAP_AESS_BUFFER_DMIC2_L_ID 3
-#define OMAP_AESS_BUFFER_DMIC2_R_ID 4
-#define OMAP_AESS_BUFFER_DMIC3_L_ID 5
-#define OMAP_AESS_BUFFER_DMIC3_R_ID 6
-#define OMAP_AESS_BUFFER_BT_UL_L_ID 7
-#define OMAP_AESS_BUFFER_BT_UL_R_ID 8
-#define OMAP_AESS_BUFFER_MM_EXT_IN_L_ID 9
-#define OMAP_AESS_BUFFER_MM_EXT_IN_R_ID 10
-#define OMAP_AESS_BUFFER_AMIC_L_ID 11
-#define OMAP_AESS_BUFFER_AMIC_R_ID 12
-#define OMAP_AESS_BUFFER_VX_REC_L_ID 13
-#define OMAP_AESS_BUFFER_VX_REC_R_ID 14
-#define OMAP_AESS_BUFFER_MCU_IRQ_FIFO_PTR_ID 15
-#define OMAP_AESS_BUFFER_DMIC_ATC_PTR_ID 16
-#define OMAP_AESS_BUFFER_MM_EXT_IN_ID 17
-
#define OMAP_ABE_D_MCUIRQFIFO_SIZE 0x40
struct omap_aess_addr *map;
int *fct_id;
int *label_id;
- struct omap_aess_init_task *init_table;
+ int nb_init_task;
+ struct omap_aess_task *init_table;
struct omap_aess_port *port;
struct omap_aess_port *ping_pong;
struct omap_aess_task *dl1_mono_mixer;
struct list_head list;
struct omap_aess *abe;
+ struct snd_pcm_substream *substream;
#ifdef CONFIG_DEBUG_FS
struct dentry *debugfs_lstate;
#endif
};
-struct omap_abe_port *omap_abe_port_open(struct omap_aess *abe, int logical_id);
-void omap_abe_port_close(struct omap_aess *abe, struct omap_abe_port *port);
-int omap_abe_port_enable(struct omap_aess *abe, struct omap_abe_port *port);
-int omap_abe_port_disable(struct omap_aess *abe, struct omap_abe_port *port);
-int omap_abe_port_is_enabled(struct omap_aess *abe, struct omap_abe_port *port);
+struct omap_abe_port *omap_abe_port_open(struct omap_aess *aess, int logical_id);
+void omap_abe_port_close(struct omap_aess *aess, struct omap_abe_port *port);
+int omap_abe_port_enable(struct omap_aess *aess, struct omap_abe_port *port);
+int omap_abe_port_disable(struct omap_aess *aess, struct omap_abe_port *port);
+int omap_abe_port_is_enabled(struct omap_aess *aess, struct omap_abe_port *port);
struct omap_aess *omap_abe_port_mgr_get(void);
-void omap_abe_port_mgr_put(struct omap_aess *abe);
-
-struct omap_aess_seq {
- u32 write_pointer;
- u32 irq_pingpong_player_id;
-};
+void omap_abe_port_mgr_put(struct omap_aess *aess);
/* main ABE structure */
struct omap_aess {
void __iomem *io_base[5];
u32 firmware_version_number;
u16 MultiFrame[25][8];
- u32 compensated_mixer_gain;
u8 muted_gains_indicator[MAX_NBGAIN_CMEM];
u32 desired_gains_decibel[MAX_NBGAIN_CMEM];
u32 muted_gains_decibel[MAX_NBGAIN_CMEM];
u32 size_pingpong;
/* number of ping/pong buffer being used */
u32 nb_pingpong;
- struct snd_pcm_substream *substream_pp;
u32 irq_dbg_read_ptr;
- struct omap_aess_seq seq;
struct omap_aess_mapping *fw_info;
/* List of open ABE logical ports */
#endif
};
-#include "abe_gain.h"
-
struct omap_aess_equ {
/* type of filter */
u32 equ_type;
struct omap_aess_dma {
- /* OCP L3 pointer to the first address of the */
void *data;
- /* destination buffer (either DMA or Ping-Pong read/write pointers). */
- /* address L3 when addressing the DMEM buffer instead of CBPr */
- void *l3_dmem;
- /* address L3 translated to L4 the ARM memory space */
- void *l4_dmem;
- /* number of iterations for the DMA data moves. */
u32 iter;
};
-int omap_aess_set_opp_processing(struct omap_aess *abe, u32 opp);
-int omap_aess_connect_debug_trace(struct omap_aess *abe,
+int omap_aess_set_opp_processing(struct omap_aess *aess, u32 opp);
+int omap_aess_connect_debug_trace(struct omap_aess *aess,
struct omap_aess_dma *dma2);
/* gain */
-int omap_aess_use_compensated_gain(struct omap_aess *abe, int on_off);
-int omap_aess_write_equalizer(struct omap_aess *abe, u32 id,
+int omap_aess_use_compensated_gain(struct omap_aess *aess, int on_off);
+int omap_aess_write_equalizer(struct omap_aess *aess, u32 id,
struct omap_aess_equ *param);
-int omap_aess_disable_gain(struct omap_aess *abe, u32 id);
-int omap_aess_enable_gain(struct omap_aess *abe, u32 id);
-int omap_aess_mute_gain(struct omap_aess *abe, u32 id);
-int omap_aess_unmute_gain(struct omap_aess *abe, u32 id);
-
-int omap_aess_write_gain(struct omap_aess *abe, u32 id, s32 f_g);
-int omap_aess_write_mixer(struct omap_aess *abe, u32 id, s32 f_g);
-int omap_aess_read_gain(struct omap_aess *abe, u32 id, u32 *f_g);
-int omap_aess_read_mixer(struct omap_aess *abe, u32 id, u32 *f_g);
-
-int omap_aess_init_mem(struct omap_aess *abe, struct device *dev,
- void __iomem **_io_base, u32 *fw_header);
-int omap_aess_reset_hal(struct omap_aess *abe);
-int omap_aess_load_fw(struct omap_aess *abe, u32 *firmware);
-int omap_aess_reload_fw(struct omap_aess *abe, u32 *firmware);
+int omap_aess_disable_gain(struct omap_aess *aess, u32 id);
+int omap_aess_enable_gain(struct omap_aess *aess, u32 id);
+int omap_aess_mute_gain(struct omap_aess *aess, u32 id);
+int omap_aess_unmute_gain(struct omap_aess *aess, u32 id);
+
+int omap_aess_write_gain(struct omap_aess *aess, u32 id, s32 f_g);
+int omap_aess_write_mixer(struct omap_aess *aess, u32 id, s32 f_g);
+int omap_aess_read_gain(struct omap_aess *aess, u32 id, u32 *f_g);
+int omap_aess_read_mixer(struct omap_aess *aess, u32 id, u32 *f_g);
+
+int omap_aess_init_mem(struct omap_aess *aess, struct device *dev,
+ void __iomem **_io_base, const void *fw_config);
+int omap_aess_reset_hal(struct omap_aess *aess);
+int omap_aess_load_fw(struct omap_aess *aess, const void *firmware);
+int omap_aess_reload_fw(struct omap_aess *aess, const void *firmware);
u32 omap_abe_get_supported_fw_version(void);
/* port */
-int omap_aess_mono_mixer(struct omap_aess *abe, u32 id, u32 on_off);
-int omap_aess_connect_serial_port(struct omap_aess *abe, u32 id,
+int omap_aess_mono_mixer(struct omap_aess *aess, u32 id, u32 on_off);
+void omap_aess_connect_serial_port(struct omap_aess *aess, u32 id,
struct omap_aess_data_format *f,
- u32 mcbsp_id);
-int omap_aess_connect_cbpr_dmareq_port(struct omap_aess *abe, u32 id,
+ u32 mcbsp_id, struct omap_aess_dma *aess_dma);
+void omap_aess_connect_cbpr_dmareq_port(struct omap_aess *aess, u32 id,
struct omap_aess_data_format *f, u32 d,
- struct omap_aess_dma *returned_dma_t);
-int omap_aess_read_port_address(struct omap_aess *abe,
- u32 port, struct omap_aess_dma *dma2);
-int omap_aess_connect_irq_ping_pong_port(struct omap_aess *abe, u32 id,
+ struct omap_aess_dma *aess_dma);
+int omap_aess_connect_irq_ping_pong_port(struct omap_aess *aess, u32 id,
struct omap_aess_data_format *f,
u32 subroutine_id, u32 size,
u32 *sink, u32 dsp_mcu_flag);
-void omap_aess_write_pdmdl_offset(struct omap_aess *abe, u32 path,
+void omap_aess_write_pdmdl_offset(struct omap_aess *aess, u32 path,
u32 offset_left, u32 offset_right);
-int omap_aess_enable_data_transfer(struct omap_aess *abe, u32 id);
-int omap_aess_disable_data_transfer(struct omap_aess *abe, u32 id);
+int omap_aess_enable_data_transfer(struct omap_aess *aess, u32 id);
+int omap_aess_disable_data_transfer(struct omap_aess *aess, u32 id);
/* core */
-int omap_aess_check_activity(struct omap_aess *abe);
-int omap_aess_wakeup(struct omap_aess *abe);
-int omap_aess_set_router_configuration(struct omap_aess *abe, u32 *param);
-int omap_abe_read_next_ping_pong_buffer(struct omap_aess *abe,
+int omap_aess_check_activity(struct omap_aess *aess);
+int omap_aess_wakeup(struct omap_aess *aess);
+int omap_aess_set_router_configuration(struct omap_aess *aess, u32 *param);
+int omap_abe_read_next_ping_pong_buffer(struct omap_aess *aess,
u32 port, u32 *p, u32 *n);
-int omap_aess_read_next_ping_pong_buffer(struct omap_aess *abe,
+int omap_aess_read_next_ping_pong_buffer(struct omap_aess *aess,
u32 port, u32 *p, u32 *n);
-int omap_aess_irq_processing(struct omap_aess *abe);
-int omap_aess_set_ping_pong_buffer(struct omap_aess *abe,
+int omap_aess_irq_processing(struct omap_aess *aess);
+int omap_aess_set_ping_pong_buffer(struct omap_aess *aess,
u32 port, u32 n_bytes);
-int omap_aess_read_offset_from_ping_buffer(struct omap_aess *abe,
+int omap_aess_read_offset_from_ping_buffer(struct omap_aess *aess,
u32 id, u32 *n);
-/* seq */
-int omap_aess_plug_subroutine(struct omap_aess *abe, u32 *id,
- abe_subroutine2 f, u32 n, u32 *params);
-
#endif /* _ABE_H_ */
index 22f5a669a85620df67fe0afdba4d2696587186c0..bac94a6a329883cc0d84425d91f9d915813101d3 100644 (file)
#include "abe_mem.h"
#include "abe_aess.h"
+#define EVENT_GENERATOR_ON 1
+#define EVENT_GENERATOR_OFF 0
+
+#define EVENT_SOURCE_DMA 0
+#define EVENT_SOURCE_COUNTER 1
+
/**
* omap_aess_hw_configuration
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
*
* Initialize the AESS HW registers for MPU and DMA
* request visibility.
*/
-void omap_aess_hw_configuration(struct omap_aess *abe)
+void omap_aess_hw_configuration(struct omap_aess *aess)
{
/* enable AESS auto gating (required to release all AESS clocks) */
- omap_aess_reg_writel(abe, AESS_AUTO_GATING_ENABLE, 1);
+ omap_aess_reg_writel(aess, OMAP_AESS_AUTO_GATING_ENABLE, 1);
/* enables the DMAreq from AESS AESS_DMAENABLE_SET = 255 */
- omap_aess_reg_writel(abe, AESS_DMAENABLE_SET, DMA_ENABLE_ALL);
+ omap_aess_reg_writel(aess, OMAP_AESS_DMAENABLE_SET, DMA_ENABLE_ALL);
/* enables the MCU IRQ from AESS to Cortex A9 */
- omap_aess_reg_writel(abe, AESS_MCU_IRQENABLE_SET, INT_SET);
+ omap_aess_reg_writel(aess, OMAP_AESS_MCU_IRQENABLE_SET, INT_SET);
}
/**
* omap_aess_clear_irq - clear ABE interrupt
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
*
* This subroutine is called to clear MCU Irq
*/
-int omap_aess_clear_irq(struct omap_aess *abe)
+int omap_aess_clear_irq(struct omap_aess *aess)
{
- omap_aess_reg_writel(abe, ABE_MCU_IRQSTATUS, INT_CLR);
+ omap_aess_reg_writel(aess, OMAP_AESS_MCU_IRQSTATUS, INT_CLR);
return 0;
}
EXPORT_SYMBOL(omap_aess_clear_irq);
/**
* abe_write_event_generator - Selects event generator source
- * @abe: Pointer on abe handle
+ * @aess: Pointer on abe handle
* @e: Event Generation Counter, McPDM, DMIC or default.
*
* Loads the AESS event generator hardware source.
* (1<<1) in order to have the same speed at 50% and 100% OPP
* (only 15 MSB bits are used at OPP50%)
*/
-int omap_aess_write_event_generator(struct omap_aess *abe, u32 e)
+int omap_aess_write_event_generator(struct omap_aess *aess, u32 e)
{
u32 event, selection;
u32 counter = EVENT_GENERATOR_COUNTER_DEFAULT;
aess_err("Bad event generator selection");
return -AESS_EINVAL;
}
- omap_aess_reg_writel(abe, EVENT_GENERATOR_COUNTER, counter);
- omap_aess_reg_writel(abe, EVENT_SOURCE_SELECTION, selection);
- omap_aess_reg_writel(abe, EVENT_GENERATOR_START, EVENT_GENERATOR_ON);
- omap_aess_reg_writel(abe, AUDIO_ENGINE_SCHEDULER, event);
+ omap_aess_reg_writel(aess, OMAP_AESS_EVENT_GENERATOR_COUNTER, counter);
+ omap_aess_reg_writel(aess, OMAP_AESS_EVENT_SOURCE_SELECTION, selection);
+ omap_aess_reg_writel(aess, OMAP_AESS_EVENT_GENERATOR_START, EVENT_GENERATOR_ON);
+ omap_aess_reg_writel(aess, OMAP_AESS_AUDIO_ENGINE_SCHEDULER, event);
return 0;
}
EXPORT_SYMBOL(omap_aess_write_event_generator);
/**
* omap_aess_start_event_generator - Starts event generator source
- * @abe: Pointer on abe handle
+ * @aess: Pointer on abe handle
*
* Start the event genrator of AESS. No more event will be send to AESS engine.
* Upper layer must wait 1/96kHz to be sure that engine reaches
* the IDLE instruction.
*/
-int omap_aess_start_event_generator(struct omap_aess *abe)
+int omap_aess_start_event_generator(struct omap_aess *aess)
{
/* Start the event Generator */
- omap_aess_reg_writel(abe, EVENT_GENERATOR_START, 1);
+ omap_aess_reg_writel(aess, OMAP_AESS_EVENT_GENERATOR_START, 1);
return 0;
}
EXPORT_SYMBOL(omap_aess_start_event_generator);
/**
* omap_aess_stop_event_generator - Stops event generator source
- * @abe: Pointer on abe handle
+ * @aess: Pointer on abe handle
*
* Stop the event genrator of AESS. No more event will be send to AESS engine.
* Upper layer must wait 1/96kHz to be sure that engine reaches
* the IDLE instruction.
*/
-int omap_aess_stop_event_generator(struct omap_aess *abe)
+int omap_aess_stop_event_generator(struct omap_aess *aess)
{
/* Stop the event Generator */
- omap_aess_reg_writel(abe, EVENT_GENERATOR_START, 0);
+ omap_aess_reg_writel(aess, OMAP_AESS_EVENT_GENERATOR_START, 0);
return 0;
}
EXPORT_SYMBOL(omap_aess_stop_event_generator);
/**
* omap_aess_disable_irq - disable MCU/DSP ABE interrupt
- * @abe: Pointer on abe handle
+ * @aess: Pointer on abe handle
*
* This subroutine is disabling ABE MCU/DSP Irq
*/
-int omap_aess_disable_irq(struct omap_aess *abe)
+int omap_aess_disable_irq(struct omap_aess *aess)
{
/* disables the DMAreq from AESS AESS_DMAENABLE_CLR = 127
* DMA_Req7 will still be enabled as it is used for ABE trace */
- omap_aess_reg_writel(abe, AESS_DMAENABLE_CLR, 0x7F);
+ omap_aess_reg_writel(aess, OMAP_AESS_DMAENABLE_CLR, 0x7F);
/* disables the MCU IRQ from AESS to Cortex A9 */
- omap_aess_reg_writel(abe, AESS_MCU_IRQENABLE_CLR, 0x01);
+ omap_aess_reg_writel(aess, OMAP_AESS_MCU_IRQENABLE_CLR, 0x01);
return 0;
}
EXPORT_SYMBOL(omap_aess_disable_irq);
index c109eb7f6097d140e742798fbd361e691dbbf9df..b12f28051310caa5eef3b87a7e6db0a4cca92c3c 100644 (file)
#ifndef _ABE_AESS_H_
#define _ABE_AESS_H_
-#define AESS_REVISION 0x00
-#define AESS_MCU_IRQSTATUS 0x28
-#define AESS_MCU_IRQENABLE_SET 0x3C
-#define AESS_MCU_IRQENABLE_CLR 0x40
-#define AESS_DMAENABLE_SET 0x60
-#define AESS_DMAENABLE_CLR 0x64
-#define EVENT_GENERATOR_COUNTER 0x68
-#define EVENT_GENERATOR_START 0x6C
-#define EVENT_SOURCE_SELECTION 0x70
-#define AUDIO_ENGINE_SCHEDULER 0x74
-#define AESS_AUTO_GATING_ENABLE 0x7C
+#define OMAP_AESS_REVISION 0x00
+#define OMAP_AESS_MCU_IRQSTATUS_RAW 0x24
+#define OMAP_AESS_MCU_IRQSTATUS 0x28
+#define OMAP_AESS_MCU_IRQENABLE_SET 0x3C
+#define OMAP_AESS_MCU_IRQENABLE_CLR 0x40
+#define OMAP_AESS_DSP_IRQSTATUS_RAW 0x4C
+#define OMAP_AESS_DMAENABLE_SET 0x60
+#define OMAP_AESS_DMAENABLE_CLR 0x64
+#define OMAP_AESS_EVENT_GENERATOR_COUNTER 0x68
+#define OMAP_AESS_EVENT_GENERATOR_START 0x6C
+#define OMAP_AESS_EVENT_SOURCE_SELECTION 0x70
+#define OMAP_AESS_AUDIO_ENGINE_SCHEDULER 0x74
+#define OMAP_AESS_AUTO_GATING_ENABLE 0x7C
+#define OMAP_AESS_DMASTATUS_RAW 0x84
/*
* AESS_MCU_IRQSTATUS bit field
#define EVENT_GENERATOR_COUNTER_44100 (2228-1)
-int omap_aess_start_event_generator(struct omap_aess *abe);
-int omap_aess_stop_event_generator(struct omap_aess *abe);
-int omap_aess_write_event_generator(struct omap_aess *abe, u32 e);
+int omap_aess_start_event_generator(struct omap_aess *aess);
+int omap_aess_stop_event_generator(struct omap_aess *aess);
+int omap_aess_write_event_generator(struct omap_aess *aess, u32 e);
-int omap_aess_disable_irq(struct omap_aess *abe);
-int omap_aess_clear_irq(struct omap_aess *abe);
+int omap_aess_disable_irq(struct omap_aess *aess);
+int omap_aess_clear_irq(struct omap_aess *aess);
-void omap_aess_hw_configuration(struct omap_aess *abe);
+void omap_aess_hw_configuration(struct omap_aess *aess);
#endif /* _ABE_AESS_H_ */
index 69fbd3e4eed342f008606af9492b4c8b8d7f581c..c8db67b97d4cd1c74008e54bb3e0e8bf0a86bbb3 100644 (file)
*
* BSD LICENSE
*
- * Copyright(c) 2010-2012 Texas Instruments Incorporated,
+ * Copyright(c) 2010-2013 Texas Instruments Incorporated,
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
#include "abe_port.h"
#include "abe_mem.h"
#include "abe_dbg.h"
-#include "abe_seq.h"
-
-#define IRQtag_COUNT 0x000c
-#define IRQtag_PP 0x000d
-#define OMAP_ABE_IRQ_FIFO_MASK ((OMAP_ABE_D_MCUIRQFIFO_SIZE >> 2) - 1)
/**
- * abe_omap_aess_reset_hal - reset the ABE/HAL
- * @abe: Pointer on aess handle
+ * omap_aess_reset_hal - reset the ABE/HAL
+ * @aess: Pointer on aess handle
*
* Operations : reset the ABE by reloading the static variables and
* default AESS registers.
* Called after a PRCM cold-start reset of ABE
*/
-int omap_aess_reset_hal(struct omap_aess *abe)
+int omap_aess_reset_hal(struct omap_aess *aess)
{
u32 i;
/* IRQ & DBG circular read pointer in DMEM */
- abe->irq_dbg_read_ptr = 0;
-
- /* default = disable the mixer's adaptive gain control */
- omap_aess_use_compensated_gain(abe, 0);
+ aess->irq_dbg_read_ptr = 0;
/* reset the default gain values */
for (i = 0; i < MAX_NBGAIN_CMEM; i++) {
- abe->muted_gains_indicator[i] = 0;
- abe->desired_gains_decibel[i] = (u32) GAIN_MUTE;
- abe->desired_gains_linear[i] = 0;
- abe->desired_ramp_delay_ms[i] = 0;
- abe->muted_gains_decibel[i] = (u32) GAIN_TOOLOW;
+ aess->muted_gains_indicator[i] = 0;
+ aess->desired_gains_decibel[i] = (u32) GAIN_MUTE;
+ aess->desired_gains_linear[i] = 0;
+ aess->desired_ramp_delay_ms[i] = 0;
+ aess->muted_gains_decibel[i] = (u32) GAIN_TOOLOW;
}
- omap_aess_hw_configuration(abe);
+ omap_aess_hw_configuration(aess);
return 0;
}
EXPORT_SYMBOL(omap_aess_reset_hal);
/**
* omap_aess_wakeup - Wakeup ABE
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
*
* Wakeup ABE in case of retention
*/
-int omap_aess_wakeup(struct omap_aess *abe)
+int omap_aess_wakeup(struct omap_aess *aess)
{
/* Restart event generator */
- omap_aess_write_event_generator(abe, EVENT_TIMER);
+ omap_aess_write_event_generator(aess, EVENT_TIMER);
/* reconfigure DMA Req and MCU Irq visibility */
- omap_aess_hw_configuration(abe);
+ omap_aess_hw_configuration(aess);
return 0;
}
EXPORT_SYMBOL(omap_aess_wakeup);
-/**
- * omap_aess_monitoring
- * @abe: Pointer on aess handle
- *
- * checks the internal status of ABE and HAL
- */
-static void omap_aess_monitoring(struct omap_aess *abe)
-{
-
-}
-
-/**
- * omap_aess_irq_processing - Process ABE interrupt
- * @abe: Pointer on aess handle
- *
- * This subroutine is call upon reception of "MA_IRQ_99 ABE_MPU_IRQ" Audio
- * back-end interrupt. This subroutine will check the ATC Hrdware, the
- * IRQ_FIFO from the AE and act accordingly. Some IRQ source are originated
- * for the delivery of "end of time sequenced tasks" notifications, some are
- * originated from the Ping-Pong protocols, some are generated from
- * the embedded debugger when the firmware stops on programmable break-points,
- * etc ...
- */
-int omap_aess_irq_processing(struct omap_aess *abe)
-{
- u32 abe_irq_dbg_write_ptr, i, cmem_src, sm_cm;
- struct omap_aess_irq_data IRQ_data;
- struct omap_aess_addr addr;
-
- /* extract the write pointer index from CMEM memory (INITPTR format) */
- /* CMEM address of the write pointer in bytes */
- cmem_src = abe->fw_info->label_id[OMAP_AESS_BUFFER_MCU_IRQ_FIFO_PTR_ID] << 2;
- omap_abe_mem_read(abe, OMAP_ABE_CMEM, cmem_src,
- &sm_cm, sizeof(abe_irq_dbg_write_ptr));
- /* AESS left-pointer index located on MSBs */
- abe_irq_dbg_write_ptr = sm_cm >> 16;
- abe_irq_dbg_write_ptr &= 0xFF;
- /* loop on the IRQ FIFO content */
- for (i = 0; i < OMAP_ABE_D_MCUIRQFIFO_SIZE; i++) {
- /* stop when the FIFO is empty */
- if (abe_irq_dbg_write_ptr == abe->irq_dbg_read_ptr)
- break;
- /* read the IRQ/DBG FIFO */
- memcpy(&addr, &abe->fw_info->map[OMAP_AESS_DMEM_MCUIRQFIFO_ID],
- sizeof(struct omap_aess_addr));
- addr.offset += (abe->irq_dbg_read_ptr << 2);
- addr.bytes = sizeof(IRQ_data);
- omap_aess_mem_read(abe, addr, (u32 *)&IRQ_data);
- abe->irq_dbg_read_ptr = (abe->irq_dbg_read_ptr + 1) & OMAP_ABE_IRQ_FIFO_MASK;
- /* select the source of the interrupt */
- switch (IRQ_data.tag) {
- case IRQtag_PP:
- omap_aess_irq_ping_pong(abe);
- break;
- case IRQtag_COUNT:
- /*abe_irq_check_for_sequences(IRQ_data.data);*/
- omap_aess_monitoring(abe);
- break;
- default:
- break;
- }
- }
- return 0;
-}
-EXPORT_SYMBOL(omap_aess_irq_processing);
-
/**
* abe_set_router_configuration
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @param: list of output index of the route
*
* The uplink router takes its input from DMIC (6 samples), AMIC (2 samples)
* indexes 14 .. 15 = RESERVED (NULL)
* ZERO_labelID, ZERO_labelID,
*/
-int omap_aess_set_router_configuration(struct omap_aess *abe, u32 *param)
+int omap_aess_set_router_configuration(struct omap_aess *aess, u32 *param)
{
- omap_aess_mem_write(abe,
- abe->fw_info->map[OMAP_AESS_DMEM_AUPLINKROUTING_ID],
+ omap_aess_mem_write(aess,
+ aess->fw_info->map[OMAP_AESS_DMEM_AUPLINKROUTING_ID],
param);
return 0;
}
/**
* abe_set_opp_processing - Set OPP mode for ABE Firmware
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @opp: OOPP mode
*
* New processing network and OPP:
* this switch.
*
*/
-int omap_aess_set_opp_processing(struct omap_aess *abe, u32 opp)
+int omap_aess_set_opp_processing(struct omap_aess *aess, u32 opp)
{
u32 dOppMode32;
break;
}
/* Write Multiframe inside DMEM */
- omap_aess_mem_write(abe,
- abe->fw_info->map[OMAP_AESS_DMEM_MAXTASKBYTESINSLOT_ID],
+ omap_aess_mem_write(aess,
+ aess->fw_info->map[OMAP_AESS_DMEM_MAXTASKBYTESINSLOT_ID],
&dOppMode32);
return 0;
diff --git a/sound/soc/omap/aess/abe_def.h b/sound/soc/omap/aess/abe_def.h
+++ /dev/null
@@ -1,298 +0,0 @@
-/*
- *
- * This file is provided under a dual BSD/GPLv2 license. When using or
- * redistributing this file, you may do so under either license.
- *
- * GPL LICENSE SUMMARY
- *
- * Copyright(c) 2010-2012 Texas Instruments Incorporated,
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of version 2 of the GNU General Public License as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
- * The full GNU General Public License is included in this distribution
- * in the file called LICENSE.GPL.
- *
- * BSD LICENSE
- *
- * Copyright(c) 2010-2012 Texas Instruments Incorporated,
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-
-#ifndef _ABE_DEF_H_
-#define _ABE_DEF_H_
-/*
- * HARDWARE AND PERIPHERAL DEFINITIONS
- */
-/* MM_DL */
-#define ABE_CBPR0_IDX 0
-/* VX_DL */
-#define ABE_CBPR1_IDX 1
-/* VX_UL */
-#define ABE_CBPR2_IDX 2
-/* MM_UL */
-#define ABE_CBPR3_IDX 3
-/* MM_UL2 */
-#define ABE_CBPR4_IDX 4
-/* TONES */
-#define ABE_CBPR5_IDX 5
-/* TDB */
-#define ABE_CBPR6_IDX 6
-/* DEBUG/CTL */
-#define ABE_CBPR7_IDX 7
-#define CIRCULAR_BUFFER_PERIPHERAL_R__0 (0x100 + ABE_CBPR0_IDX*4)
-#define CIRCULAR_BUFFER_PERIPHERAL_R__1 (0x100 + ABE_CBPR1_IDX*4)
-#define CIRCULAR_BUFFER_PERIPHERAL_R__2 (0x100 + ABE_CBPR2_IDX*4)
-#define CIRCULAR_BUFFER_PERIPHERAL_R__3 (0x100 + ABE_CBPR3_IDX*4)
-#define CIRCULAR_BUFFER_PERIPHERAL_R__4 (0x100 + ABE_CBPR4_IDX*4)
-#define CIRCULAR_BUFFER_PERIPHERAL_R__5 (0x100 + ABE_CBPR5_IDX*4)
-#define CIRCULAR_BUFFER_PERIPHERAL_R__6 (0x100 + ABE_CBPR6_IDX*4)
-#define CIRCULAR_BUFFER_PERIPHERAL_R__7 (0x100 + ABE_CBPR7_IDX*4)
-#define PING_PONG_WITH_MCU_IRQ 1
-#define PING_PONG_WITH_DSP_IRQ 2
-/* ID used for LIB memory copy subroutines */
-#define COPY_FROM_ABE_TO_HOST 1
-#define COPY_FROM_HOST_TO_ABE 2
-/*
- * INTERNAL DEFINITIONS
- */
-#define ABE_FIRMWARE_MAX_SIZE 26629
-/* 24 Q6.26 coefficients */
-#define NBEQ1 25
-/* 2x12 Q6.26 coefficients */
-#define NBEQ2 13
-/* TBD APS first set of parameters */
-#define NBAPS1 10
-/* TBD APS second set of parameters */
-#define NBAPS2 10
-/* Mixer used for sending tones to the uplink voice path */
-#define NBMIX_AUDIO_UL 2
-/* Main downlink mixer */
-#define NBMIX_DL1 4
-/* Handsfree downlink mixer */
-#define NBMIX_DL2 4
-/* Side-tone mixer */
-#define NBMIX_SDT 2
-/* Echo reference mixer */
-#define NBMIX_ECHO 2
-/* Voice record mixer */
-#define NBMIX_VXREC 4
-/* unsigned version of (-1) */
-#define CC_M1 0xFF
-#define CS_M1 0xFFFF
-#define CL_M1 0xFFFFFFFFL
-/*
- Mixer ID Input port ID Comments
- DL1_MIXER 0 MMDL path
- 1 MMUL2 path
- 2 VXDL path
- 3 TONES path
- SDT_MIXER 0 Uplink path
- 1 Downlink path
- ECHO_MIXER 0 DL1_MIXER path
- 1 DL2_MIXER path
- AUDUL_MIXER 0 TONES_DL path
- 1 Uplink path
- 2 MM_DL path
- VXREC_MIXER 0 TONES_DL path
- 1 VX_DL path
- 2 MM_DL path
- 3 VX_UL path
-*/
-#define MIX_VXUL_INPUT_MM_DL 0
-#define MIX_VXUL_INPUT_TONES 1
-#define MIX_VXUL_INPUT_VX_UL 2
-#define MIX_VXUL_INPUT_VX_DL 3
-#define MIX_DL1_INPUT_MM_DL 0
-#define MIX_DL1_INPUT_MM_UL2 1
-#define MIX_DL1_INPUT_VX_DL 2
-#define MIX_DL1_INPUT_TONES 3
-#define MIX_DL2_INPUT_MM_DL 0
-#define MIX_DL2_INPUT_MM_UL2 1
-#define MIX_DL2_INPUT_VX_DL 2
-#define MIX_DL2_INPUT_TONES 3
-#define MIX_SDT_INPUT_UP_MIXER 0
-#define MIX_SDT_INPUT_DL1_MIXER 1
-#define MIX_AUDUL_INPUT_MM_DL 0
-#define MIX_AUDUL_INPUT_TONES 1
-#define MIX_AUDUL_INPUT_UPLINK 2
-#define MIX_AUDUL_INPUT_VX_DL 3
-#define MIX_VXREC_INPUT_MM_DL 0
-#define MIX_VXREC_INPUT_TONES 1
-#define MIX_VXREC_INPUT_VX_UL 2
-#define MIX_VXREC_INPUT_VX_DL 3
-#define MIX_ECHO_DL1 0
-#define MIX_ECHO_DL2 1
-/* nb of samples to route */
-#define NBROUTE_UL 16
-/* 10 routing tables max */
-#define NBROUTE_CONFIG_MAX 10
-/* 5 pre-computed routing tables */
-#define NBROUTE_CONFIG 6
-/* AMIC on VX_UL */
-#define UPROUTE_CONFIG_AMIC 0
-/* DMIC first pair on VX_UL */
-#define UPROUTE_CONFIG_DMIC1 1
-/* DMIC second pair on VX_UL */
-#define UPROUTE_CONFIG_DMIC2 2
-/* DMIC last pair on VX_UL */
-#define UPROUTE_CONFIG_DMIC3 3
-/* BT_UL on VX_UL */
-#define UPROUTE_CONFIG_BT 4
-/* ECHO_REF on MM_UL2 */
-#define UPROUTE_ECHO_MMUL2 5
-/* max number of feature associated to a port */
-#define MAXFEATUREPORT 12
-#define SUB_0_PARAM 0
-/* number of parameters per sequence calls */
-#define SUB_1_PARAM 1
-#define SUB_2_PARAM 2
-#define SUB_3_PARAM 3
-#define SUB_4_PARAM 4
-/* active sequence mask = 0 means the line is free */
-#define FREE_LINE 0
-/* no ask for collision protection */
-#define NOMASK (1 << 0)
-/* do not allow a PDM OFF during the execution of this sequence */
-#define MASK_PDM_OFF (1 << 1)
-/* do not allow a PDM ON during the execution of this sequence */
-#define MASK_PDM_ON (1 << 2)
-/* explicit name of the feature */
-#define NBCHARFEATURENAME 16
-/* explicit name of the port */
-#define NBCHARPORTNAME 16
-/* sink / input port from Host point of view (or AESS for DMIC/McPDM/.. */
-#define SNK_P ABE_ATC_DIRECTION_IN
-/* source / ouptut port */
-#define SRC_P ABE_ATC_DIRECTION_OUT
-/* no ASRC applied */
-#define NODRIFT 0
-/* for abe_set_asrc_drift_control */
-#define FORCED_DRIFT_CONTROL 1
-/* for abe_set_asrc_drift_control */
-#define ADPATIVE_DRIFT_CONTROL 2
-/* number of task/slot depending on the OPP value */
-#define DOPPMODE32_OPP100 (0x00000010)
-#define DOPPMODE32_OPP50 (0x0000000C)
-#define DOPPMODE32_OPP25 (0x0000004)
-/*
- * ABE CONST AREA FOR PARAMETERS TRANSLATION
- */
-#define GAIN_MAXIMUM 3000L
-#define GAIN_24dB 2400L
-#define GAIN_18dB 1800L
-#define GAIN_12dB 1200L
-#define GAIN_6dB 600L
-/* default gain = 1 */
-#define GAIN_0dB 0L
-#define GAIN_M6dB -600L
-#define GAIN_M7dB -700L
-#define GAIN_M12dB -1200L
-#define GAIN_M18dB -1800L
-#define GAIN_M24dB -2400L
-#define GAIN_M30dB -3000L
-#define GAIN_M40dB -4000L
-#define GAIN_M50dB -5000L
-/* muted gain = -120 decibels */
-#define MUTE_GAIN -12000L
-#define GAIN_TOOLOW -13000L
-#define GAIN_MUTE MUTE_GAIN
-#define RAMP_MINLENGTH 0L
-/* ramp_t is in milli- seconds */
-#define RAMP_0MS 0L
-#define RAMP_1MS 1L
-#define RAMP_2MS 2L
-#define RAMP_5MS 5L
-#define RAMP_10MS 10L
-#define RAMP_20MS 20L
-#define RAMP_50MS 50L
-#define RAMP_100MS 100L
-#define RAMP_200MS 200L
-#define RAMP_500MS 500L
-#define RAMP_1000MS 1000L
-#define RAMP_MAXLENGTH 10000L
-/* for abe_translate_gain_format */
-#define LINABE_TO_DECIBELS 1
-#define DECIBELS_TO_LINABE 2
-/* for abe_translate_ramp_format */
-#define IIRABE_TO_MICROS 1
-#define MICROS_TO_IIABE 2
-/*
- * ABE CONST AREA FOR PERIPHERAL TUNING
- */
-/* port idled IDLE_P */
-#define OMAP_ABE_PORT_ACTIVITY_IDLE 1
-/* port initialized, ready to be activated */
-#define OMAP_ABE_PORT_INITIALIZED 3
-/* port activated RUN_P */
-#define OMAP_ABE_PORT_ACTIVITY_RUNNING 2
-#define NOCALLBACK 0
-#define NOPARAMETER 0
-/* number of ATC access upon AMIC DMArequests, all the FIFOs are enabled */
-#define MCPDM_UL_ITER 4
-/* All the McPDM FIFOs are enabled simultaneously */
-#define MCPDM_DL_ITER 24
-/* All the DMIC FIFOs are enabled simultaneously */
-#define DMIC_ITER 12
-/* TBD later if needed */
-#define MAX_PINGPONG_BUFFERS 2
-/*
- * Indexes to the subroutines
- */
-#define SUB_WRITE_MIXER 1
-#define SUB_WRITE_PORT_GAIN 2
-/* OLD WAY */
-#define c_feat_init_eq 1
-#define c_feat_read_eq1 2
-#define c_write_eq1 3
-#define c_feat_read_eq2 4
-#define c_write_eq2 5
-#define c_feat_read_eq3 6
-#define c_write_eq3 7
-/* max number of gain to be controlled by HAL */
-#define MAX_NBGAIN_CMEM 36
-/*
- * MACROS
- */
-#define maximum(a, b) (((a) < (b)) ? (b) : (a))
-#define minimum(a, b) (((a) > (b)) ? (b) : (a))
-#define absolute(a) (((a) > 0) ? (a) : ((-1)*(a)))
-#define HAL_VERSIONS 9
-#endif/* _ABE_DEF_H_ */
diff --git a/sound/soc/omap/aess/abe_ext.h b/sound/soc/omap/aess/abe_ext.h
+++ /dev/null
@@ -1,230 +0,0 @@
-/*
- *
- * This file is provided under a dual BSD/GPLv2 license. When using or
- * redistributing this file, you may do so under either license.
- *
- * GPL LICENSE SUMMARY
- *
- * Copyright(c) 2010-2012 Texas Instruments Incorporated,
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of version 2 of the GNU General Public License as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
- * The full GNU General Public License is included in this distribution
- * in the file called LICENSE.GPL.
- *
- * BSD LICENSE
- *
- * Copyright(c) 2010-2012 Texas Instruments Incorporated,
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-
-#ifndef _ABE_EXT_H_
-#define _ABE_EXT_H_
-
-/*
- * HARDWARE AND PERIPHERAL DEFINITIONS
- */
-/* PMEM SIZE in bytes (1024 words of 64 bits: : #32bits words x 4)*/
-#define ABE_PMEM_SIZE 8192
-/* CMEM SIZE in bytes (2048 coeff : #32bits words x 4)*/
-#define ABE_CMEM_SIZE 8192
-/* SMEM SIZE in bytes (3072 stereo samples : #32bits words x 4)*/
-#define ABE_SMEM_SIZE 24576
-/* DMEM SIZE in bytes */
-#define ABE_DMEM_SIZE 65536L
-/* ATC REGISTERS SIZE in bytes */
-#define ABE_ATC_DESC_SIZE 512
-/* holds the MCU Irq signal */
-#define ABE_MCU_IRQSTATUS_RAW 0x24
-/* status : clear the IRQ */
-#define ABE_MCU_IRQSTATUS 0x28
-/* holds the DSP Irq signal */
-#define ABE_DSP_IRQSTATUS_RAW 0x4C
-/* holds the DMA req lines to the sDMA */
-#define ABE_DMASTATUS_RAW 0x84
-#define EVENT_GENERATOR_COUNTER 0x68
-/* PLL output/desired sampling rate = (32768 * 6000)/96000 */
-#define EVENT_GENERATOR_COUNTER_DEFAULT (2048-1)
-/* PLL output/desired sampling rate = (32768 * 6000)/88200 */
-#define EVENT_GENERATOR_COUNTER_44100 (2228-1)
-/* start / stop the EVENT generator */
-#define EVENT_GENERATOR_START 0x6C
-#define EVENT_GENERATOR_ON 1
-#define EVENT_GENERATOR_OFF 0
-/* selection of the EVENT generator source */
-#define EVENT_SOURCE_SELECTION 0x70
-#define EVENT_SOURCE_DMA 0
-#define EVENT_SOURCE_COUNTER 1
-/* selection of the ABE DMA req line from ATC */
-#define AUDIO_ENGINE_SCHEDULER 0x74
-#define ABE_ATC_DMIC_DMA_REQ 1
-#define ABE_ATC_MCPDMDL_DMA_REQ 2
-#define ABE_ATC_MCPDMUL_DMA_REQ 3
-/* Direction=0 means input from ABE point of view */
-#define ABE_ATC_DIRECTION_IN 0
-/* Direction=1 means output from ABE point of view */
-#define ABE_ATC_DIRECTION_OUT 1
-/*
- * DMA requests
- */
-/*Internal connection doesn't connect at ABE boundary */
-#define External_DMA_0 0
-/*Transmit request digital microphone */
-#define DMIC_DMA_REQ 1
-/*Multichannel PDM downlink */
-#define McPDM_DMA_DL 2
-/*Multichannel PDM uplink */
-#define McPDM_DMA_UP 3
-/*MCBSP module 1 - transmit request */
-#define MCBSP1_DMA_TX 4
-/*MCBSP module 1 - receive request */
-#define MCBSP1_DMA_RX 5
-/*MCBSP module 2 - transmit request */
-#define MCBSP2_DMA_TX 6
-/*MCBSP module 2 - receive request */
-#define MCBSP2_DMA_RX 7
-/*MCBSP module 3 - transmit request */
-#define MCBSP3_DMA_TX 8
-/*MCBSP module 3 - receive request */
-#define MCBSP3_DMA_RX 9
-/*SLIMBUS module 1 - transmit request channel 0 */
-#define SLIMBUS1_DMA_TX0 10
-/*SLIMBUS module 1 - transmit request channel 1 */
-#define SLIMBUS1_DMA_TX1 11
-/*SLIMBUS module 1 - transmit request channel 2 */
-#define SLIMBUS1_DMA_TX2 12
-/*SLIMBUS module 1 - transmit request channel 3 */
-#define SLIMBUS1_DMA_TX3 13
-/*SLIMBUS module 1 - transmit request channel 4 */
-#define SLIMBUS1_DMA_TX4 14
-/*SLIMBUS module 1 - transmit request channel 5 */
-#define SLIMBUS1_DMA_TX5 15
-/*SLIMBUS module 1 - transmit request channel 6 */
-#define SLIMBUS1_DMA_TX6 16
-/*SLIMBUS module 1 - transmit request channel 7 */
-#define SLIMBUS1_DMA_TX7 17
-/*SLIMBUS module 1 - receive request channel 0 */
-#define SLIMBUS1_DMA_RX0 18
-/*SLIMBUS module 1 - receive request channel 1 */
-#define SLIMBUS1_DMA_RX1 19
-/*SLIMBUS module 1 - receive request channel 2 */
-#define SLIMBUS1_DMA_RX2 20
-/*SLIMBUS module 1 - receive request channel 3 */
-#define SLIMBUS1_DMA_RX3 21
-/*SLIMBUS module 1 - receive request channel 4 */
-#define SLIMBUS1_DMA_RX4 22
-/*SLIMBUS module 1 - receive request channel 5 */
-#define SLIMBUS1_DMA_RX5 23
-/*SLIMBUS module 1 - receive request channel 6 */
-#define SLIMBUS1_DMA_RX6 24
-/*SLIMBUS module 1 - receive request channel 7 */
-#define SLIMBUS1_DMA_RX7 25
-/*McASP - Data transmit DMA request line */
-#define McASP1_AXEVT 26
-/*McASP - Data receive DMA request line */
-#define McASP1_AREVT 29
-/*DUMMY FIFO @@@ */
-#define _DUMMY_FIFO_ 30
-/*DMA of the Circular buffer peripheral 0 */
-#define CBPr_DMA_RTX0 32
-/*DMA of the Circular buffer peripheral 1 */
-#define CBPr_DMA_RTX1 33
-/*DMA of the Circular buffer peripheral 2 */
-#define CBPr_DMA_RTX2 34
-/*DMA of the Circular buffer peripheral 3 */
-#define CBPr_DMA_RTX3 35
-/*DMA of the Circular buffer peripheral 4 */
-#define CBPr_DMA_RTX4 36
-/*DMA of the Circular buffer peripheral 5 */
-#define CBPr_DMA_RTX5 37
-/*DMA of the Circular buffer peripheral 6 */
-#define CBPr_DMA_RTX6 38
-/*DMA of the Circular buffer peripheral 7 */
-#define CBPr_DMA_RTX7 39
-/*
- * ATC DESCRIPTORS - DESTINATIONS
- */
-#define DEST_DMEM_access 0x00
-#define DEST_MCBSP1_TX 0x01
-#define DEST_MCBSP2_TX 0x02
-#define DEST_MCBSP3_TX 0x03
-#define DEST_SLIMBUS1_TX0 0x04
-#define DEST_SLIMBUS1_TX1 0x05
-#define DEST_SLIMBUS1_TX2 0x06
-#define DEST_SLIMBUS1_TX3 0x07
-#define DEST_SLIMBUS1_TX4 0x08
-#define DEST_SLIMBUS1_TX5 0x09
-#define DEST_SLIMBUS1_TX6 0x0A
-#define DEST_SLIMBUS1_TX7 0x0B
-#define DEST_MCPDM_DL 0x0C
-#define DEST_MCASP_TX0 0x0D
-#define DEST_MCASP_TX1 0x0E
-#define DEST_MCASP_TX2 0x0F
-#define DEST_MCASP_TX3 0x10
-#define DEST_EXTPORT0 0x11
-#define DEST_EXTPORT1 0x12
-#define DEST_EXTPORT2 0x13
-#define DEST_EXTPORT3 0x14
-#define DEST_MCPDM_ON 0x15
-#define DEST_CBP_CBPr 0x3F
-/*
- * ATC DESCRIPTORS - SOURCES
- */
-#define SRC_DMEM_access 0x0
-#define SRC_MCBSP1_RX 0x01
-#define SRC_MCBSP2_RX 0x02
-#define SRC_MCBSP3_RX 0x03
-#define SRC_SLIMBUS1_RX0 0x04
-#define SRC_SLIMBUS1_RX1 0x05
-#define SRC_SLIMBUS1_RX2 0x06
-#define SRC_SLIMBUS1_RX3 0x07
-#define SRC_SLIMBUS1_RX4 0x08
-#define SRC_SLIMBUS1_RX5 0x09
-#define SRC_SLIMBUS1_RX6 0x0A
-#define SRC_SLIMBUS1_RX7 0x0B
-#define SRC_DMIC_UP 0x0C
-#define SRC_MCPDM_UP 0x0D
-#define SRC_MCASP_RX0 0x0E
-#define SRC_MCASP_RX1 0x0F
-#define SRC_MCASP_RX2 0x10
-#define SRC_MCASP_RX3 0x11
-#define SRC_CBP_CBPr 0x3F
-#endif/* _ABE_EXT_H_ */
index c462786b5e8a1ca3ba0088a234f2ca0ddbe58f9b..f016cbe6a9853bdaf5088197b7ccaa0462358d4a 100644 (file)
*
* GPL LICENSE SUMMARY
*
- * Copyright(c) 2010-2012 Texas Instruments Incorporated,
+ * Copyright(c) 2010-2013 Texas Instruments Incorporated,
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
/*
* ABE CONST AREA FOR PARAMETERS TRANSLATION
*/
-#define min_mdb (-12000)
-#define max_mdb (3000)
-#define sizeof_db2lin_table (1 + ((max_mdb - min_mdb)/100))
+#define OMAP_AESS_GAIN_MUTED (0x0001<<0)
+#define OMAP_AESS_GAIN_DISABLED (0x0001<<1)
+
+#define OMAP_AESS_GAIN_MIN_MDB (-12000)
+#define OMAP_AESS_GAIN_MAX_MDB (3000)
+#define OMAP_AESS_GAIN_DB2LIN_SIZE (1 + ((OMAP_AESS_GAIN_MAX_MDB - OMAP_AESS_GAIN_MIN_MDB)/100))
-static const u32 abe_db2lin_table[sizeof_db2lin_table] = {
+static const u32 abe_db2lin_table[OMAP_AESS_GAIN_DB2LIN_SIZE] = {
0x00000000, /* SMEM coding of -120 dB */
0x00000000, /* SMEM coding of -119 dB */
0x00000000, /* SMEM coding of -118 dB */
};
/**
- * abe_use_compensated_gain
- * @abe: Pointer on aess handle
- * @on_off: Enable dynamic gain compensation.
- *
- * Selects the automatic Mixer's gain management
- * on_off = 1 allows the "abe_write_gain" to adjust the overall
- * gains of the mixer to be tuned not to create saturation
- *
- */
-int omap_aess_use_compensated_gain(struct omap_aess *abe, int on_off)
-{
- abe->compensated_mixer_gain = on_off;
- return 0;
-}
-EXPORT_SYMBOL(omap_aess_use_compensated_gain);
-
-/**
- * oamp_abe_write_equalizer
- * @abe: Pointer on aess handle
+ * omap_aess_write_equalizer
+ * @aess: Pointer on aess handle
* @id: name of the equalizer
* @param: equalizer coefficients
*
* Load the coefficients in CMEM.
*/
-int omap_aess_write_equalizer(struct omap_aess *abe,
+int omap_aess_write_equalizer(struct omap_aess *aess,
u32 id, struct omap_aess_equ *param)
{
struct omap_aess_addr equ_addr;
switch (id) {
case OMAP_AESS_CMEM_DL1_COEFS_ID:
memcpy(&equ_addr,
- &abe->fw_info->map[OMAP_AESS_SMEM_DL1_M_EQ_DATA_ID],
+ &aess->fw_info->map[OMAP_AESS_SMEM_DL1_M_EQ_DATA_ID],
sizeof(struct omap_aess_addr));
break;
case OMAP_AESS_CMEM_DL2_L_COEFS_ID:
memcpy(&equ_addr,
- &abe->fw_info->map[OMAP_AESS_SMEM_DL2_M_LR_EQ_DATA_ID],
+ &aess->fw_info->map[OMAP_AESS_SMEM_DL2_M_LR_EQ_DATA_ID],
sizeof(struct omap_aess_addr));
break;
case OMAP_AESS_CMEM_DL2_R_COEFS_ID:
memcpy(&equ_addr,
- &abe->fw_info->map[OMAP_AESS_SMEM_DL2_M_LR_EQ_DATA_ID],
+ &aess->fw_info->map[OMAP_AESS_SMEM_DL2_M_LR_EQ_DATA_ID],
sizeof(struct omap_aess_addr));
break;
case OMAP_AESS_CMEM_SDT_COEFS_ID:
memcpy(&equ_addr,
- &abe->fw_info->map[OMAP_AESS_SMEM_SDT_F_DATA_ID],
+ &aess->fw_info->map[OMAP_AESS_SMEM_SDT_F_DATA_ID],
sizeof(struct omap_aess_addr));
break;
case OMAP_AESS_CMEM_96_48_AMIC_COEFS_ID:
memcpy(&equ_addr,
- &abe->fw_info->map[OMAP_AESS_SMEM_AMIC_96_48_DATA_ID],
+ &aess->fw_info->map[OMAP_AESS_SMEM_AMIC_96_48_DATA_ID],
sizeof(struct omap_aess_addr));
break;
case OMAP_AESS_CMEM_96_48_DMIC_COEFS_ID:
memcpy(&equ_addr,
- &abe->fw_info->map[OMAP_AESS_SMEM_DMIC0_96_48_DATA_ID],
+ &aess->fw_info->map[OMAP_AESS_SMEM_DMIC0_96_48_DATA_ID],
sizeof(struct omap_aess_addr));
/* three DMIC are clear at the same time DMIC0 DMIC1 DMIC2 */
equ_addr.bytes *= 3;
}
/* reset SMEM buffers before the coefficients are loaded */
- omap_aess_reset_mem(abe, equ_addr);
+ omap_aess_reset_mem(aess, equ_addr);
length = param->equ_length;
src = (u32 *)((param->coef).type1);
- omap_aess_mem_write(abe, abe->fw_info->map[id], src);
+ omap_aess_mem_write(aess, aess->fw_info->map[id], src);
/* reset SMEM buffers after the coefficients are loaded */
- omap_aess_reset_mem(abe, equ_addr);
+ omap_aess_reset_mem(aess, equ_addr);
return 0;
}
EXPORT_SYMBOL(omap_aess_write_equalizer);
/**
* omap_aess_disable_gain
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: name of the gain
*
* Set gain to silence if not already mute or disable.
*/
-int omap_aess_disable_gain(struct omap_aess *abe, u32 id)
+int omap_aess_disable_gain(struct omap_aess *aess, u32 id)
{
u32 f_g;
f_g = GAIN_MUTE;
- if (!(abe->muted_gains_indicator[id] & OMAP_ABE_GAIN_DISABLED)) {
+ if (!(aess->muted_gains_indicator[id] & OMAP_AESS_GAIN_DISABLED)) {
/* Check if we are in mute */
- if (!(abe->muted_gains_indicator[id] &
- OMAP_ABE_GAIN_MUTED)) {
- abe->muted_gains_decibel[id] =
- abe->desired_gains_decibel[id];
+ if (!(aess->muted_gains_indicator[id] &
+ OMAP_AESS_GAIN_MUTED)) {
+ aess->muted_gains_decibel[id] =
+ aess->desired_gains_decibel[id];
/* mute the gain */
- omap_aess_write_gain(abe, id, f_g);
+ omap_aess_write_gain(aess, id, f_g);
}
- abe->muted_gains_indicator[id] |= OMAP_ABE_GAIN_DISABLED;
+ aess->muted_gains_indicator[id] |= OMAP_AESS_GAIN_DISABLED;
}
return 0;
}
/**
* omap_aess_enable_gain
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: name of the gain
*
* Restore gain if we are in disable mode.
*/
-int omap_aess_enable_gain(struct omap_aess *abe, u32 id)
+int omap_aess_enable_gain(struct omap_aess *aess, u32 id)
{
u32 f_g;
- if ((abe->muted_gains_indicator[id] & OMAP_ABE_GAIN_DISABLED)) {
+ if ((aess->muted_gains_indicator[id] & OMAP_AESS_GAIN_DISABLED)) {
/* restore the input parameters for mute/unmute */
- f_g = abe->muted_gains_decibel[id];
- abe->muted_gains_indicator[id] &=
- ~OMAP_ABE_GAIN_DISABLED;
+ f_g = aess->muted_gains_decibel[id];
+ aess->muted_gains_indicator[id] &=
+ ~OMAP_AESS_GAIN_DISABLED;
/* unmute the gain */
- omap_aess_write_gain(abe, id, f_g);
+ omap_aess_write_gain(aess, id, f_g);
}
return 0;
}
/**
* omap_aess_mute_gain
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: name of the gain
*
* Set gain to silence if not already mute.
*/
-int omap_aess_mute_gain(struct omap_aess *abe, u32 id)
+int omap_aess_mute_gain(struct omap_aess *aess, u32 id)
{
u32 f_g;
f_g = GAIN_MUTE;
- if (!abe->muted_gains_indicator[id]) {
- abe->muted_gains_decibel[id] =
- abe->desired_gains_decibel[id];
+ if (!aess->muted_gains_indicator[id]) {
+ aess->muted_gains_decibel[id] =
+ aess->desired_gains_decibel[id];
/* mute the gain */
- omap_aess_write_gain(abe, id, f_g);
+ omap_aess_write_gain(aess, id, f_g);
}
- abe->muted_gains_indicator[id] |= OMAP_ABE_GAIN_MUTED;
+ aess->muted_gains_indicator[id] |= OMAP_AESS_GAIN_MUTED;
return 0;
}
EXPORT_SYMBOL(omap_aess_mute_gain);
/**
* omap_aess_unmute_gain
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: name of the gain
*
* Restore gain after mute.
*/
-int omap_aess_unmute_gain(struct omap_aess *abe, u32 id)
+int omap_aess_unmute_gain(struct omap_aess *aess, u32 id)
{
u32 f_g;
- if ((abe->muted_gains_indicator[id] & OMAP_ABE_GAIN_MUTED)) {
+ if ((aess->muted_gains_indicator[id] & OMAP_AESS_GAIN_MUTED)) {
/* restore the input parameters for mute/unmute */
- f_g = abe->muted_gains_decibel[id];
- abe->muted_gains_indicator[id] &=
- ~OMAP_ABE_GAIN_MUTED;
+ f_g = aess->muted_gains_decibel[id];
+ aess->muted_gains_indicator[id] &=
+ ~OMAP_AESS_GAIN_MUTED;
/* unmute the gain */
- omap_aess_write_gain(abe, id, f_g);
+ omap_aess_write_gain(aess, id, f_g);
}
return 0;
}
/**
* omap_aess_write_gain
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: gain name or mixer name
* @f_g: input gain for the mixer
*
* in mute state". A mixer is disabled with a network reconfiguration
* corresponding to an OPP value.
*/
-int omap_aess_write_gain(struct omap_aess *abe,
+int omap_aess_write_gain(struct omap_aess *aess,
u32 id, s32 f_g)
{
u32 lin_g, mixer_target;
s32 gain_index;
- gain_index = ((f_g - min_mdb) / 100);
- gain_index = maximum(gain_index, 0);
- gain_index = minimum(gain_index, sizeof_db2lin_table);
+ gain_index = ((f_g - OMAP_AESS_GAIN_MIN_MDB) / 100);
+ gain_index = max(gain_index, 0);
+ gain_index = min(gain_index, OMAP_AESS_GAIN_DB2LIN_SIZE);
lin_g = abe_db2lin_table[gain_index];
/* save the input parameters for mute/unmute */
- abe->desired_gains_linear[id] = lin_g;
- abe->desired_gains_decibel[id] = f_g;
+ aess->desired_gains_linear[id] = lin_g;
+ aess->desired_gains_decibel[id] = f_g;
/* SMEM address in bytes */
- mixer_target = abe->fw_info->map[OMAP_AESS_SMEM_GTARGET1_ID].offset;
+ mixer_target = aess->fw_info->map[OMAP_AESS_SMEM_GTARGET1_ID].offset;
mixer_target += (id<<2);
- if (!abe->compensated_mixer_gain) {
- if (!abe->muted_gains_indicator[id])
- /* load the S_G_Target SMEM table */
- omap_abe_mem_write(abe, OMAP_ABE_SMEM,
- mixer_target, (u32 *)&lin_g,
- sizeof(lin_g));
- else
- /* update muted gain with new value */
- abe->muted_gains_decibel[id] = f_g;
- }
+ if (!aess->muted_gains_indicator[id])
+ /* load the S_G_Target SMEM table */
+ omap_abe_mem_write(aess, OMAP_ABE_SMEM,
+ mixer_target, (u32 *)&lin_g,
+ sizeof(lin_g));
+ else
+ /* update muted gain with new value */
+ aess->muted_gains_decibel[id] = f_g;
+
return 0;
}
EXPORT_SYMBOL(omap_aess_write_gain);
/**
* omap_aess_write_gain_ramp
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: gain name or mixer name
* @ramp: Gaim ramp time
*
* Loads the gain ramp for the associated gain.
*/
-int omap_aess_write_gain_ramp(struct omap_aess *abe, u32 id, u32 ramp)
+int omap_aess_write_gain_ramp(struct omap_aess *aess, u32 id, u32 ramp)
{
u32 mixer_target;
u32 alpha, beta;
u32 ramp_index;
- abe->desired_ramp_delay_ms[id] = ramp;
+ aess->desired_ramp_delay_ms[id] = ramp;
/* SMEM address in bytes */
- mixer_target = abe->fw_info->map[OMAP_AESS_SMEM_GTARGET1_ID].offset;
+ mixer_target = aess->fw_info->map[OMAP_AESS_SMEM_GTARGET1_ID].offset;
mixer_target += (id<<2);
- ramp = maximum(minimum(RAMP_MAXLENGTH, ramp), RAMP_MINLENGTH);
+ ramp = max(min(RAMP_MAXLENGTH, ramp), RAMP_MINLENGTH);
/* ramp data should be interpolated in the table instead */
ramp_index = 3;
if ((RAMP_2MS <= ramp) && (ramp < RAMP_5MS))
beta = abe_alpha_iir[ramp_index];
alpha = abe_1_alpha_iir[ramp_index];
/* CMEM bytes address */
- mixer_target = abe->fw_info->map[OMAP_AESS_CMEM_1_ALPHA_ID].offset;
+ mixer_target = aess->fw_info->map[OMAP_AESS_CMEM_1_ALPHA_ID].offset;
/* a pair of gains is updated once in the firmware */
mixer_target += ((id) >> 1) << 2;
/* load the ramp delay data */
- omap_abe_mem_write(abe, OMAP_ABE_CMEM, mixer_target,
+ omap_abe_mem_write(aess, OMAP_ABE_CMEM, mixer_target,
(u32 *)&alpha, sizeof(alpha));
/* CMEM bytes address */
- mixer_target = abe->fw_info->map[OMAP_AESS_CMEM_ALPHA_ID].offset;
+ mixer_target = aess->fw_info->map[OMAP_AESS_CMEM_ALPHA_ID].offset;
/* a pair of gains is updated once in the firmware */
mixer_target += ((id) >> 1) << 2;
- omap_abe_mem_write(abe, OMAP_ABE_CMEM, mixer_target,
+ omap_abe_mem_write(aess, OMAP_ABE_CMEM, mixer_target,
(u32 *)&beta, sizeof(beta));
return 0;
}
/**
* omap_aess_write_mixer
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: name of the mixer
* @f_g: input gain for the mixer
*
* gain in mute state". A mixer is disabled with a network reconfiguration
* corresponding to an OPP value.
*/
-int omap_aess_write_mixer(struct omap_aess *abe, u32 id, s32 f_g)
+int omap_aess_write_mixer(struct omap_aess *aess, u32 id, s32 f_g)
{
- omap_aess_write_gain(abe, id, f_g);
+ omap_aess_write_gain(aess, id, f_g);
return 0;
}
EXPORT_SYMBOL(omap_aess_write_mixer);
/**
* omap_aess_read_gain
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: name of the mixer
* @f_g: pointer on the gain for the mixer
*
* gain in mute state". A mixer is disabled with a network reconfiguration
* corresponding to an OPP value.
*/
-int omap_aess_read_gain(struct omap_aess *abe, u32 id, u32 *f_g)
+int omap_aess_read_gain(struct omap_aess *aess, u32 id, u32 *f_g)
{
u32 mixer_target, i;
/* SMEM bytes address */
- mixer_target = abe->fw_info->map[OMAP_AESS_SMEM_GTARGET1_ID].offset;
+ mixer_target = aess->fw_info->map[OMAP_AESS_SMEM_GTARGET1_ID].offset;
mixer_target += (id<<2);
- if (!abe->muted_gains_indicator[id]) {
+ if (!aess->muted_gains_indicator[id]) {
/* load the S_G_Target SMEM table */
- omap_abe_mem_read(abe, OMAP_ABE_SMEM, mixer_target,
+ omap_abe_mem_read(aess, OMAP_ABE_SMEM, mixer_target,
(u32 *)f_g, sizeof(*f_g));
- for (i = 0; i < sizeof_db2lin_table; i++) {
+ for (i = 0; i < OMAP_AESS_GAIN_DB2LIN_SIZE; i++) {
if (abe_db2lin_table[i] == *f_g)
goto found;
}
*f_g = 0;
return -1;
found:
- *f_g = (i * 100) + min_mdb;
+ *f_g = (i * 100) + OMAP_AESS_GAIN_MIN_MDB;
} else {
/* update muted gain with new value */
- *f_g = abe->muted_gains_decibel[id];
+ *f_g = aess->muted_gains_decibel[id];
}
return 0;
}
EXPORT_SYMBOL(omap_aess_read_gain);
/**
- * abe_read_mixer
- * @abe: Pointer on aess handle
+ * omap_aess_read_mixer
+ * @aess: Pointer on aess handle
* @id: name of the mixer
* @f_g: pointer on the gain for the mixer
*
* gain in mute state". A mixer is disabled with a network reconfiguration
* corresponding to an OPP value.
*/
-int omap_aess_read_mixer(struct omap_aess *abe, u32 id, u32 *f_g)
+int omap_aess_read_mixer(struct omap_aess *aess, u32 id, u32 *f_g)
{
- omap_aess_read_gain(abe, id, f_g);
+ omap_aess_read_gain(aess, id, f_g);
return 0;
}
EXPORT_SYMBOL(omap_aess_read_mixer);
/**
- * abe_reset_gain_mixer
- * @abe: Pointer on aess handle
+ * omap_aess_reset_gain_mixer
+ * @aess: Pointer on aess handle
* @id: name of the mixer
*
* restart the working gain value of the mixers when a port is enabled
*/
-void omap_aess_reset_gain_mixer(struct omap_aess *abe, u32 id)
+void omap_aess_reset_gain_mixer(struct omap_aess *aess, u32 id)
{
u32 lin_g, mixer_target;
/* SMEM bytes address for the CURRENT gain values */
- mixer_target = abe->fw_info->map[OMAP_AESS_SMEM_GCURRENT_ID].offset;
+ mixer_target = aess->fw_info->map[OMAP_AESS_SMEM_GCURRENT_ID].offset;
mixer_target += (id<<2);
lin_g = 0;
/* load the S_G_Target SMEM table */
- omap_abe_mem_write(abe, OMAP_ABE_SMEM, mixer_target,
+ omap_abe_mem_write(aess, OMAP_ABE_SMEM, mixer_target,
(u32 *)&lin_g, sizeof(lin_g));
}
index aedef8c5b2da4cbf0f4a23ab8ec89321fdf07b6f..eabf2472208089b4381bebaec1d39587a3776c1d 100644 (file)
*
* BSD LICENSE
*
- * Copyright(c) 2010-2012 Texas Instruments Incorporated,
+ * Copyright(c) 2010-2013 Texas Instruments Incorporated,
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
#ifndef _ABE_GAIN_H_
#define _ABE_GAIN_H_
-#include "abe_typ.h"
-
-#define OMAP_ABE_GAIN_MUTED (0x0001<<0)
-#define OMAP_ABE_GAIN_DISABLED (0x0001<<1)
+#include "aess-fw.h"
-#define OMAP_AESS_GAIN_DMIC1_LEFT 0
-#define OMAP_AESS_GAIN_DMIC1_RIGHT 1
-#define OMAP_AESS_GAIN_DMIC2_LEFT 2
-#define OMAP_AESS_GAIN_DMIC2_RIGHT 3
-#define OMAP_AESS_GAIN_DMIC3_LEFT 4
-#define OMAP_AESS_GAIN_DMIC3_RIGHT 5
-#define OMAP_AESS_GAIN_AMIC_LEFT 6
-#define OMAP_AESS_GAIN_AMIC_RIGHT 7
-#define OMAP_AESS_GAIN_DL1_LEFT 8
-#define OMAP_AESS_GAIN_DL1_RIGHT 9
-#define OMAP_AESS_GAIN_DL2_LEFT 10
-#define OMAP_AESS_GAIN_DL2_RIGHT 11
-#define OMAP_AESS_GAIN_SPLIT_LEFT 12
-#define OMAP_AESS_GAIN_SPLIT_RIGHT 13
-#define OMAP_AESS_MIXDL1_MM_DL 14
-#define OMAP_AESS_MIXDL1_MM_UL2 15
-#define OMAP_AESS_MIXDL1_VX_DL 16
-#define OMAP_AESS_MIXDL1_TONES 17
-#define OMAP_AESS_MIXDL2_MM_DL 18
-#define OMAP_AESS_MIXDL2_MM_UL2 19
-#define OMAP_AESS_MIXDL2_VX_DL 20
-#define OMAP_AESS_MIXDL2_TONES 21
-#define OMAP_AESS_MIXECHO_DL1 22
-#define OMAP_AESS_MIXECHO_DL2 23
-#define OMAP_AESS_MIXSDT_UL 24
-#define OMAP_AESS_MIXSDT_DL 25
-#define OMAP_AESS_MIXVXREC_MM_DL 26
-#define OMAP_AESS_MIXVXREC_TONES 27
-#define OMAP_AESS_MIXVXREC_VX_UL 28
-#define OMAP_AESS_MIXVXREC_VX_DL 29
-#define OMAP_AESS_MIXAUDUL_MM_DL 30
-#define OMAP_AESS_MIXAUDUL_TONES 31
-#define OMAP_AESS_MIXAUDUL_UPLINK 32
-#define OMAP_AESS_MIXAUDUL_VX_DL 33
-#define OMAP_AESS_GAIN_BTUL_LEFT 34
-#define OMAP_AESS_GAIN_BTUL_RIGHT 35
+#define GAIN_MAXIMUM 3000L
+#define GAIN_24dB 2400L
+#define GAIN_18dB 1800L
+#define GAIN_12dB 1200L
+#define GAIN_6dB 600L
+/* default gain = 1 */
+#define GAIN_0dB 0L
+#define GAIN_M6dB -600L
+#define GAIN_M7dB -700L
+#define GAIN_M12dB -1200L
+#define GAIN_M18dB -1800L
+#define GAIN_M24dB -2400L
+#define GAIN_M30dB -3000L
+#define GAIN_M40dB -4000L
+#define GAIN_M50dB -5000L
+/* muted gain = -120 decibels */
+#define MUTE_GAIN -12000L
+#define GAIN_TOOLOW -13000L
+#define GAIN_MUTE MUTE_GAIN
+#define RAMP_MINLENGTH 0L
+/* ramp_t is in milli- seconds */
+#define RAMP_0MS 0L
+#define RAMP_1MS 1L
+#define RAMP_2MS 2L
+#define RAMP_5MS 5L
+#define RAMP_10MS 10L
+#define RAMP_20MS 20L
+#define RAMP_50MS 50L
+#define RAMP_100MS 100L
+#define RAMP_200MS 200L
+#define RAMP_500MS 500L
+#define RAMP_1000MS 1000L
+#define RAMP_MAXLENGTH 10000L
-void omap_aess_reset_gain_mixer(struct omap_aess *abe, u32 id);
-int omap_aess_write_gain_ramp(struct omap_aess *abe, u32 id, u32 ramp);
+void omap_aess_reset_gain_mixer(struct omap_aess *aess, u32 id);
+int omap_aess_write_gain_ramp(struct omap_aess *aess, u32 id, u32 ramp);
#endif /* _ABE_GAIN_H_ */
index edcf86178ebfd9f82623328fc6d408057ff82a00..c15e6597f296067f0b24c3404869758e428ceea2 100644 (file)
#include "abe_gain.h"
#include "abe_mem.h"
#include "abe_port.h"
-#include "abe_seq.h"
/* FW version that this HAL supports.
* We cheat and since we include the FW in the driver atm we can get the
* Memory map of ABE memory space for PMEM/DMEM/SMEM/DMEM
*/
int omap_aess_init_mem(struct omap_aess *abe, struct device *dev,
- void __iomem **_io_base, u32 *fw_header)
+ void __iomem **_io_base, const void *fw_config)
{
+ u32 *fw_header = (u32*) fw_config;
int i, offset = 0;
u32 count;
if (abe->fw_info == NULL)
return -ENOMEM;
- abe->fw_info->init_table = kzalloc(sizeof(struct omap_aess_init_task), GFP_KERNEL);
- if (abe->fw_info->init_table == NULL) {
- kfree(abe->fw_info);
- return -ENOMEM;
- }
-
/* get mapping */
count = fw_header[offset];
dev_dbg(abe->dev, "Map %d items of size 0x%x at offset 0x%x\n", count,
count = fw_header[offset];
dev_dbg(abe->dev, "Tasks %d of size 0x%x at offset 0x%x\n", count,
sizeof(struct omap_aess_task), offset << 2);
- abe->fw_info->init_table->nb_task = count;
- abe->fw_info->init_table->task = (struct omap_aess_task *)&fw_header[++offset];
+ abe->fw_info->nb_init_task = count;
+ abe->fw_info->init_table = (struct omap_aess_task *)&fw_header[++offset];
offset += (sizeof(struct omap_aess_task) * count) / 4;
/* get ports */
*
* Load the different AESS memories PMEM/DMEM/SMEM/DMEM
*/
-static int omap_aess_load_fw_param(struct omap_aess *abe, u32 *data)
+static int omap_aess_load_fw_param(struct omap_aess *abe, const void *data)
{
u32 pmem_size, dmem_size, smem_size, cmem_size;
- u32 *pmem_ptr, *dmem_ptr, *smem_ptr, *cmem_ptr, *fw_ptr;
+ u32 *pmem_ptr, *dmem_ptr, *smem_ptr, *cmem_ptr;
+ u32 *fw_ptr = (u32*) data;
/* Analyze FW memories banks sizes */
- fw_ptr = data;
abe->firmware_version_number = *fw_ptr++;
pmem_size = *fw_ptr++;
cmem_size = *fw_ptr++;
return 0;
}
-EXPORT_SYMBOL(omap_aess_load_fw_param);
/**
* omap_aess_load_fw - Load ABE Firmware and initialize memories
* @firmware: Pointer on the ABE firmware (after the header)
*
*/
-int omap_aess_load_fw(struct omap_aess *abe, u32 *firmware)
+int omap_aess_load_fw(struct omap_aess *abe, const void *firmware)
{
omap_aess_load_fw_param(abe, firmware);
omap_aess_reset_all_ports(abe);
omap_aess_init_gain_ramp(abe);
omap_aess_build_scheduler_table(abe);
- omap_aess_reset_all_sequence(abe);
omap_aess_select_main_port(abe, OMAP_ABE_PDM_DL_PORT);
return 0;
}
* @abe: Pointer on aess handle
* @firmware: Pointer on the ABE firmware (after the header)
*/
-int omap_aess_reload_fw(struct omap_aess *abe, u32 *firmware)
+int omap_aess_reload_fw(struct omap_aess *abe, const void *firmware)
{
omap_aess_load_fw_param(abe, firmware);
omap_aess_init_gain_ramp(abe);
index 3b90ee2a5309a646e502c8ff46c13a0c03ab5b7a..bd162667a85591683f39986b44dc1c0f3ac88e8d 100644 (file)
#ifndef _ABE_MEM_H_
#define _ABE_MEM_H_
-#ifdef __KERNEL__
#include <asm/io.h>
-#endif
-
-#define OMAP_ABE_DMEM 0
-#define OMAP_ABE_CMEM 1
-#define OMAP_ABE_SMEM 2
-#define OMAP_ABE_PMEM 3
-#define OMAP_ABE_AESS 4
-
-struct omap_aess_addr {
- int bank;
- unsigned int offset;
- unsigned int bytes;
-};
-
-#define OMAP_AESS_DMEM_MULTIFRAME_ID 0
-#define OMAP_AESS_DMEM_DMIC_UL_FIFO_ID 1
-#define OMAP_AESS_DMEM_MCPDM_UL_FIFO_ID 2
-#define OMAP_AESS_DMEM_BT_UL_FIFO_ID 3
-#define OMAP_AESS_DMEM_MM_UL_FIFO_ID 4
-#define OMAP_AESS_DMEM_MM_UL2_FIFO_ID 5
-#define OMAP_AESS_DMEM_VX_UL_FIFO_ID 6
-#define OMAP_AESS_DMEM_MM_DL_FIFO_ID 7
-#define OMAP_AESS_DMEM_VX_DL_FIFO_ID 8
-#define OMAP_AESS_DMEM_TONES_DL_FIFO_ID 9
-#define OMAP_AESS_DMEM_MCASP_DL_FIFO_ID 10
-#define OMAP_AESS_DMEM_BT_DL_FIFO_ID 11
-#define OMAP_AESS_DMEM_MCPDM_DL_FIFO_ID 12
-#define OMAP_AESS_DMEM_MM_EXT_OUT_FIFO_ID 13
-#define OMAP_AESS_DMEM_MM_EXT_IN_FIFO_ID 14
-#define OMAP_AESS_SMEM_DMIC0_96_48_DATA_ID 15
-#define OMAP_AESS_SMEM_DMIC1_96_48_DATA_ID 16
-#define OMAP_AESS_SMEM_DMIC2_96_48_DATA_ID 17
-#define OMAP_AESS_SMEM_AMIC_96_48_DATA_ID 18
-#define OMAP_AESS_SMEM_BT_UL_ID 19
-#define OMAP_AESS_SMEM_BT_UL_8_48_HP_DATA_ID 20
-#define OMAP_AESS_SMEM_BT_UL_8_48_LP_DATA_ID 21
-#define OMAP_AESS_SMEM_BT_UL_16_48_HP_DATA_ID 22
-#define OMAP_AESS_SMEM_BT_UL_16_48_LP_DATA_ID 23
-#define OMAP_AESS_SMEM_MM_UL2_ID 24
-#define OMAP_AESS_SMEM_MM_UL_ID 25
-#define OMAP_AESS_SMEM_VX_UL_ID 26
-#define OMAP_AESS_SMEM_VX_UL_48_8_HP_DATA_ID 27
-#define OMAP_AESS_SMEM_VX_UL_48_8_LP_DATA_ID 28
-#define OMAP_AESS_SMEM_VX_UL_48_16_HP_DATA_ID 29
-#define OMAP_AESS_SMEM_VX_UL_48_16_LP_DATA_ID 30
-#define OMAP_AESS_SMEM_MM_DL_ID 31
-#define OMAP_AESS_SMEM_MM_DL_44P1_ID 32
-#define OMAP_AESS_SMEM_MM_DL_44P1_XK_ID 33
-#define OMAP_AESS_SMEM_VX_DL_ID 34
-#define OMAP_AESS_SMEM_VX_DL_8_48_HP_DATA_ID 35
-#define OMAP_AESS_SMEM_VX_DL_8_48_LP_DATA_ID 36
-#define OMAP_AESS_SMEM_VX_DL_8_48_OSR_LP_DATA_ID 37
-#define OMAP_AESS_SMEM_VX_DL_16_48_HP_DATA_ID 38
-#define OMAP_AESS_SMEM_VX_DL_16_48_LP_DATA_ID 39
-#define OMAP_AESS_SMEM_TONES_ID 40
-#define OMAP_AESS_SMEM_TONES_44P1_ID 41
-#define OMAP_AESS_SMEM_TONES_44P1_XK_ID 42
-#define OMAP_AESS_SMEM_MCASP1_ID 43
-#define OMAP_AESS_SMEM_BT_DL_ID 44
-#define OMAP_AESS_SMEM_BT_DL_8_48_OSR_LP_DATA_ID 45
-#define OMAP_AESS_SMEM_BT_DL_48_8_HP_DATA_ID 46
-#define OMAP_AESS_SMEM_BT_DL_48_8_LP_DATA_ID 47
-#define OMAP_AESS_SMEM_BT_DL_48_16_HP_DATA_ID 48
-#define OMAP_AESS_SMEM_BT_DL_48_16_LP_DATA_ID 49
-#define OMAP_AESS_SMEM_DL2_M_LR_EQ_DATA_ID 50
-#define OMAP_AESS_SMEM_DL1_M_EQ_DATA_ID 51
-#define OMAP_AESS_SMEM_EARP_48_96_LP_DATA_ID 52
-#define OMAP_AESS_SMEM_IHF_48_96_LP_DATA_ID 53
-#define OMAP_AESS_SMEM_DC_HS_ID 54
-#define OMAP_AESS_SMEM_DC_HF_ID 55
-#define OMAP_AESS_SMEM_SDT_F_DATA_ID 56
-#define OMAP_AESS_SMEM_GTARGET1_ID 57
-#define OMAP_AESS_SMEM_GCURRENT_ID 58
-#define OMAP_AESS_CMEM_DL1_COEFS_ID 59
-#define OMAP_AESS_CMEM_DL2_L_COEFS_ID 60
-#define OMAP_AESS_CMEM_DL2_R_COEFS_ID 61
-#define OMAP_AESS_CMEM_SDT_COEFS_ID 62
-#define OMAP_AESS_CMEM_96_48_AMIC_COEFS_ID 63
-#define OMAP_AESS_CMEM_96_48_DMIC_COEFS_ID 64
-#define OMAP_AESS_CMEM_1_ALPHA_ID 65
-#define OMAP_AESS_CMEM_ALPHA_ID 66
-#define OMAP_AESS_DMEM_SLOT23_CTRL_ID 67
-#define OMAP_AESS_DMEM_AUPLINKROUTING_ID 68
-#define OMAP_AESS_DMEM_MAXTASKBYTESINSLOT_ID 69
-#define OMAP_AESS_DMEM_PINGPONGDESC_ID 70
-#define OMAP_AESS_DMEM_IODESCR_ID 71
-#define OMAP_AESS_DMEM_MCUIRQFIFO_ID 72
-#define OMAP_AESS_DMEM_PING_ID 73
-#define OMAP_AESS_DMEM_DEBUG_FIFO_ID 74
-#define OMAP_AESS_DMEM_DEBUG_FIFO_HAL_ID 75
-#define OMAP_AESS_DMEM_DEBUG_HAL_TASK_ID 76
-#define OMAP_AESS_DMEM_LOOPCOUNTER_ID 77
-#define OMAP_AESS_DMEM_FWMEMINITDESCR_ID 78
-
-#ifdef __KERNEL__
/* Distinction between Read and Write from/to ABE memory
* is useful for simulation tool */
return memset((void __force *)(abe->io_base[addr.bank] + addr.offset), 0, addr.bytes);
}
-#endif /* __KERNEL__ */
#endif /*_ABE_MEM_H_*/
index 2fcc382471c4bf7178b24028aecf9665c0a83bd3..02a903502a85396278250fecb25e48903cce63d2 100644 (file)
*
* GPL LICENSE SUMMARY
*
- * Copyright(c) 2010-2012 Texas Instruments Incorporated,
+ * Copyright(c) 2010-2013 Texas Instruments Incorporated,
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
#include <linux/err.h>
#include <linux/slab.h>
-#include "abe_typ.h"
+#include "aess-fw.h"
#include "abe.h"
#include "abe_port.h"
#include "abe_dbg.h"
#include "abe_mem.h"
#include "abe_gain.h"
-#include "abe_seq.h"
-
-#include "abe_def.h"
+#include "abe_aess.h"
/*
* GLOBAL DEFINITION
*/
+#define ABE_ATC_DMIC_DMA_REQ 1
+#define ABE_ATC_MCPDMDL_DMA_REQ 2
+#define ABE_ATC_MCPDMUL_DMA_REQ 3
+
+/* nb of samples to route */
+#define NBROUTE_UL 16
+
+/* ATC REGISTERS SIZE in bytes */
+#define ABE_ATC_DESC_SIZE 512
+
#define ATC_SIZE 8 /* 8 bytes per descriptors */
struct omap_abe_atc_desc {
unsigned desen:1;
};
-struct ABE_SPingPongDescriptor {
+struct omap_aess_pingpong_desc {
/* 0: [W] asrc output used for the next ASRC call (+/- 1 / 0) */
u16 drift_ASRC;
/* 2: [W] asrc output used for controlling the number of
static u32 abe_dma_port_iter_factor(struct omap_aess_data_format *f);
static u32 abe_dma_port_iteration(struct omap_aess_data_format *f);
-void omap_aess_decide_main_port(struct omap_aess *abe);
-int omap_aess_init_io_tasks(struct omap_aess *abe, u32 id,
+void omap_aess_decide_main_port(struct omap_aess *aess);
+int omap_aess_init_io_tasks(struct omap_aess *aess, u32 id,
struct omap_aess_data_format *format,
struct omap_aess_port_protocol *prot);
void abe_init_dma_t(u32 id, struct omap_aess_port_protocol *prot);
-extern void omap_aess_init_asrc_vx_dl(struct omap_aess *abe, s32 dppm);
-extern void omap_aess_init_asrc_vx_ul(struct omap_aess *abe, s32 dppm);
+extern void omap_aess_init_asrc_vx_dl(struct omap_aess *aess, s32 dppm);
+extern void omap_aess_init_asrc_vx_ul(struct omap_aess *aess, s32 dppm);
/**
* omap_aess_reset_port
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: ABE port ID
*
* Stop the port activity and reload default parameters on the associated
* processing features.
* Clears the internal AE buffers.
*/
-int omap_aess_reset_port(struct omap_aess *abe, u32 id)
+int omap_aess_reset_port(struct omap_aess *aess, u32 id)
{
- struct omap_aess_port *port = abe->fw_info->port;
+ struct omap_aess_port *port = aess->fw_info->port;
- abe_port[id] = port[id];
+ memcpy(&abe_port[id], &port[id], sizeof(struct omap_aess_port));
return 0;
}
-static void omap_aess_update_scheduling_table(struct omap_aess *abe,
+static void omap_aess_update_scheduling_table(struct omap_aess *aess,
struct omap_aess_init_task *init_task,
int enable)
{
for (i = 0; i < init_task->nb_task; i++) {
task = &init_task->task[i];
if (enable)
- abe->MultiFrame[task->frame][task->slot] = task->task;
- else
- abe->MultiFrame[task->frame][task->slot] = 0;
- }
-}
-
-static void omap_aess_update_scheduling_table1(struct omap_aess *abe,
- struct omap_aess_init_task1 *init_task,
- int enable)
-{
- int i;
- struct omap_aess_task *task;
-
- for (i = 0; i < init_task->nb_task; i++) {
- task = &init_task->task[i];
- if (enable)
- abe->MultiFrame[task->frame][task->slot] = task->task;
+ aess->MultiFrame[task->frame][task->slot] = task->task;
else
- abe->MultiFrame[task->frame][task->slot] = 0;
+ aess->MultiFrame[task->frame][task->slot] = 0;
}
}
-static u32 omap_aess_update_io_task(struct omap_aess *abe,
+static u32 omap_aess_update_io_task(struct omap_aess *aess,
struct omap_aess_io_task *io_task,
int enable)
{
for (i = 0; i < io_task->nb_task; i++) {
task = &io_task->task[i];
if (enable)
- abe->MultiFrame[task->frame][task->slot] = task->task;
+ aess->MultiFrame[task->frame][task->slot] = task->task;
else
- abe->MultiFrame[task->frame][task->slot] = 0;
+ aess->MultiFrame[task->frame][task->slot] = 0;
}
return io_task->smem;
}
-static u32 omap_aess_update_io_task1(struct omap_aess *abe,
+static u32 omap_aess_update_io_task1(struct omap_aess *aess,
struct omap_aess_io_task1 *io_task,
int enable)
{
for (i = 0; i < io_task->nb_task; i++) {
task = &io_task->task[i];
if (enable)
- abe->MultiFrame[task->frame][task->slot] = task->task;
+ aess->MultiFrame[task->frame][task->slot] = task->task;
else
- abe->MultiFrame[task->frame][task->slot] = 0;
+ aess->MultiFrame[task->frame][task->slot] = 0;
}
return io_task->smem;
}
/**
- * abe_build_scheduler_table
- * @abe: Pointer on aess handle
+ * omap_aess_build_scheduler_table
+ * @aess: Pointer on aess handle
*
* Initialize Audio Engine scheduling table for ABE internal
* processing. The content of the scheduling table is provided
* by the firmware header. It can be changed according to the
* ABE graph.
*/
-void omap_aess_build_scheduler_table(struct omap_aess *abe)
+void omap_aess_build_scheduler_table(struct omap_aess *aess)
{
- u16 i, n;
+ struct omap_aess_task *task;
u16 aUplinkMuxing[NBROUTE_UL];
+ int i, n;
/* Initialize default scheduling table */
- memset(abe->MultiFrame, 0, sizeof(abe->MultiFrame));
- omap_aess_update_scheduling_table(abe, abe->fw_info->init_table, 1);
+ memset(aess->MultiFrame, 0, sizeof(aess->MultiFrame));
- omap_aess_mem_write(abe, abe->fw_info->map[OMAP_AESS_DMEM_MULTIFRAME_ID],
- (u32 *)abe->MultiFrame);
+ for (i = 0; i < aess->fw_info->nb_init_task; i++) {
+ task = &aess->fw_info->init_table[i];
+ aess->MultiFrame[task->frame][task->slot] = task->task;
+ }
+
+ omap_aess_mem_write(aess, aess->fw_info->map[OMAP_AESS_DMEM_MULTIFRAME_ID],
+ (u32 *)aess->MultiFrame);
/* reset the uplink router */
- n = abe->fw_info->map[OMAP_AESS_DMEM_AUPLINKROUTING_ID].bytes >> 1;
+ n = aess->fw_info->map[OMAP_AESS_DMEM_AUPLINKROUTING_ID].bytes >> 1;
for (i = 0; i < n; i++)
- aUplinkMuxing[i] = abe->fw_info->label_id[OMAP_AESS_BUFFER_ZERO_ID];
+ aUplinkMuxing[i] = aess->fw_info->label_id[OMAP_AESS_BUFFER_ZERO_ID];
- omap_aess_mem_write(abe,
- abe->fw_info->map[OMAP_AESS_DMEM_AUPLINKROUTING_ID],
+ omap_aess_mem_write(aess,
+ aess->fw_info->map[OMAP_AESS_DMEM_AUPLINKROUTING_ID],
(u32 *)aUplinkMuxing);
}
/**
* abe_dma_port_copy_subroutine_id
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @port_id: ABE port ID
*
* returns the index of the function doing the copy in I/O tasks
*/
-static u32 abe_dma_port_copy_subroutine_id(struct omap_aess *abe, u32 port_id)
+static u32 abe_dma_port_copy_subroutine_id(struct omap_aess *aess, u32 port_id)
{
u32 sub_id;
if (abe_port[port_id].protocol.direction == ABE_ATC_DIRECTION_IN) {
switch (abe_port[port_id].format.samp_format) {
- case MONO_MSB:
- sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_D2S_MONO_MSB_ID];
+ case OMAP_AESS_FORMAT_MONO_MSB:
+ sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_D2S_MONO_MSB_ID];
break;
- case MONO_RSHIFTED_16:
- sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_D2S_MONO_RSHIFTED_16_ID];
+ case OMAP_AESS_FORMAT_MONO_RSHIFTED_16:
+ sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_D2S_MONO_RSHIFTED_16_ID];
break;
- case STEREO_RSHIFTED_16:
- sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_D2S_STEREO_RSHIFTED_16_ID];
+ case OMAP_AESS_FORMAT_STEREO_RSHIFTED_16:
+ sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_D2S_STEREO_RSHIFTED_16_ID];
break;
- case STEREO_16_16:
- sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_D2S_STEREO_16_16_ID];
+ case OMAP_AESS_FORMAT_STEREO_16_16:
+ sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_D2S_STEREO_16_16_ID];
break;
- case MONO_16_16:
- sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_D2S_MONO_16_16_ID];
+ case OMAP_AESS_FORMAT_MONO_16_16:
+ sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_D2S_MONO_16_16_ID];
break;
- case STEREO_MSB:
- sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_D2S_STEREO_MSB_ID];
+ case OMAP_AESS_FORMAT_STEREO_MSB:
+ sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_D2S_STEREO_MSB_ID];
break;
- case SIX_MSB:
+ case OMAP_AESS_FORMAT_SIX_MSB:
if (port_id == OMAP_ABE_DMIC_PORT) {
- sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_DMIC_ID];
+ sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_DMIC_ID];
break;
}
default:
- sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_NULL_ID];
+ sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_NULL_ID];
break;
}
} else {
switch (abe_port[port_id].format.samp_format) {
- case MONO_MSB:
- sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_S2D_MONO_MSB_ID];
+ case OMAP_AESS_FORMAT_MONO_MSB:
+ sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_S2D_MONO_MSB_ID];
break;
- case MONO_RSHIFTED_16:
- sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_S2D_MONO_RSHIFTED_16_ID];
+ case OMAP_AESS_FORMAT_MONO_RSHIFTED_16:
+ sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_S2D_MONO_RSHIFTED_16_ID];
break;
- case STEREO_RSHIFTED_16:
- sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_S2D_STEREO_RSHIFTED_16_ID];
+ case OMAP_AESS_FORMAT_STEREO_RSHIFTED_16:
+ sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_S2D_STEREO_RSHIFTED_16_ID];
break;
- case STEREO_16_16:
- sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_S2D_STEREO_16_16_ID];
+ case OMAP_AESS_FORMAT_STEREO_16_16:
+ sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_S2D_STEREO_16_16_ID];
break;
- case MONO_16_16:
- sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_S2D_MONO_16_16_ID];
+ case OMAP_AESS_FORMAT_MONO_16_16:
+ sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_S2D_MONO_16_16_ID];
break;
- case STEREO_MSB:
- sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_S2D_STEREO_MSB_ID];
+ case OMAP_AESS_FORMAT_STEREO_MSB:
+ sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_S2D_STEREO_MSB_ID];
break;
- case SIX_MSB:
+ case OMAP_AESS_FORMAT_SIX_MSB:
if (port_id == OMAP_ABE_PDM_DL_PORT) {
- sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_MCPDM_DL_ID];
+ sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_MCPDM_DL_ID];
break;
}
if (port_id == OMAP_ABE_MM_UL_PORT) {
- sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_MM_UL_ID];
+ sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_MM_UL_ID];
break;
}
- case THREE_MSB:
- case FOUR_MSB:
- case FIVE_MSB:
- case SEVEN_MSB:
- case EIGHT_MSB:
- case NINE_MSB:
- sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_MM_UL_ID];
+ case OMAP_AESS_FORMAT_THREE_MSB:
+ case OMAP_AESS_FORMAT_FOUR_MSB:
+ case OMAP_AESS_FORMAT_FIVE_MSB:
+ case OMAP_AESS_FORMAT_SEVEN_MSB:
+ case OMAP_AESS_FORMAT_EIGHT_MSB:
+ case OMAP_AESS_FORMAT_NINE_MSB:
+ sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_MM_UL_ID];
break;
default:
- sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_NULL_ID];
+ sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_NULL_ID];
break;
}
}
@@ -415,161 +412,161 @@ static u32 abe_dma_port_copy_subroutine_id(struct omap_aess *abe, u32 port_id)
/**
* abe_clean_temporay buffers
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: ABE port ID
*
* clear temporary buffers according to the port ID.
*/
-static void omap_aess_clean_temporary_buffers(struct omap_aess *abe, u32 id)
+static void omap_aess_clean_temporary_buffers(struct omap_aess *aess, u32 id)
{
switch (id) {
case OMAP_ABE_DMIC_PORT:
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_DMEM_DMIC_UL_FIFO_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_DMIC0_96_48_DATA_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_DMIC1_96_48_DATA_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_DMIC2_96_48_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_DMEM_DMIC_UL_FIFO_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_DMIC0_96_48_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_DMIC1_96_48_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_DMIC2_96_48_DATA_ID]);
/* reset working values of the gain, target gain is preserved */
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_GAIN_DMIC1_LEFT);
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_GAIN_DMIC1_RIGHT);
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_GAIN_DMIC2_LEFT);
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_GAIN_DMIC2_RIGHT);
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_GAIN_DMIC3_LEFT);
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_GAIN_DMIC3_RIGHT);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_GAIN_DMIC1_LEFT);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_GAIN_DMIC1_RIGHT);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_GAIN_DMIC2_LEFT);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_GAIN_DMIC2_RIGHT);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_GAIN_DMIC3_LEFT);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_GAIN_DMIC3_RIGHT);
break;
case OMAP_ABE_PDM_UL_PORT:
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_DMEM_MCPDM_UL_FIFO_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_AMIC_96_48_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_DMEM_MCPDM_UL_FIFO_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_AMIC_96_48_DATA_ID]);
/* reset working values of the gain, target gain is preserved */
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_GAIN_AMIC_LEFT);
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_GAIN_AMIC_RIGHT);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_GAIN_AMIC_LEFT);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_GAIN_AMIC_RIGHT);
break;
case OMAP_ABE_BT_VX_UL_PORT:
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_DMEM_BT_UL_FIFO_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_BT_UL_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_BT_UL_8_48_HP_DATA_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_BT_UL_8_48_LP_DATA_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_BT_UL_16_48_HP_DATA_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_BT_UL_16_48_LP_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_DMEM_BT_UL_FIFO_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_BT_UL_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_BT_UL_8_48_HP_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_BT_UL_8_48_LP_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_BT_UL_16_48_HP_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_BT_UL_16_48_LP_DATA_ID]);
/* reset working values of the gain, target gain is preserved */
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_GAIN_BTUL_LEFT);
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_GAIN_BTUL_RIGHT);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_GAIN_BTUL_LEFT);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_GAIN_BTUL_RIGHT);
break;
case OMAP_ABE_MM_UL_PORT:
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_DMEM_MM_UL_FIFO_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_MM_UL_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_DMEM_MM_UL_FIFO_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_MM_UL_ID]);
break;
case OMAP_ABE_MM_UL2_PORT:
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_DMEM_MM_UL2_FIFO_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_MM_UL2_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_DMEM_MM_UL2_FIFO_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_MM_UL2_ID]);
break;
case OMAP_ABE_VX_UL_PORT:
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_DMEM_VX_UL_FIFO_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_VX_UL_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_VX_UL_48_8_HP_DATA_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_VX_UL_48_8_LP_DATA_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_VX_UL_48_16_HP_DATA_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_VX_UL_48_16_LP_DATA_ID]);
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_MIXAUDUL_UPLINK);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_DMEM_VX_UL_FIFO_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_VX_UL_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_VX_UL_48_8_HP_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_VX_UL_48_8_LP_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_VX_UL_48_16_HP_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_VX_UL_48_16_LP_DATA_ID]);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_MIXAUDUL_UPLINK);
break;
case OMAP_ABE_MM_DL_PORT:
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_DMEM_MM_DL_FIFO_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_MM_DL_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_MM_DL_44P1_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_MM_DL_44P1_XK_ID]);
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_MIXDL1_MM_DL);
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_MIXDL2_MM_DL);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_DMEM_MM_DL_FIFO_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_MM_DL_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_MM_DL_44P1_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_MM_DL_44P1_XK_ID]);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_MIXDL1_MM_DL);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_MIXDL2_MM_DL);
break;
case OMAP_ABE_VX_DL_PORT:
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_DMEM_VX_DL_FIFO_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_VX_DL_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_VX_DL_8_48_HP_DATA_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_VX_DL_8_48_LP_DATA_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_VX_DL_8_48_OSR_LP_DATA_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_VX_DL_16_48_HP_DATA_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_VX_DL_16_48_LP_DATA_ID]);
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_MIXDL1_VX_DL);
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_MIXDL2_VX_DL);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_DMEM_VX_DL_FIFO_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_VX_DL_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_VX_DL_8_48_HP_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_VX_DL_8_48_LP_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_VX_DL_8_48_OSR_LP_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_VX_DL_16_48_HP_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_VX_DL_16_48_LP_DATA_ID]);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_MIXDL1_VX_DL);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_MIXDL2_VX_DL);
break;
case OMAP_ABE_TONES_DL_PORT:
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_DMEM_TONES_DL_FIFO_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_TONES_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_TONES_44P1_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_TONES_44P1_XK_ID]);
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_MIXDL1_TONES);
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_MIXDL2_TONES);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_DMEM_TONES_DL_FIFO_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_TONES_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_TONES_44P1_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_TONES_44P1_XK_ID]);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_MIXDL1_TONES);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_MIXDL2_TONES);
break;
case OMAP_ABE_MCASP_DL_PORT:
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_DMEM_MCASP_DL_FIFO_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_MCASP1_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_DMEM_MCASP_DL_FIFO_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_MCASP1_ID]);
break;
case OMAP_ABE_BT_VX_DL_PORT:
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_DMEM_BT_DL_FIFO_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_BT_DL_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_DMEM_BT_DL_FIFO_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_BT_DL_ID]);
#if !defined(CONFIG_SND_OMAP4_ABE_USE_ALT_FW)
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_BT_DL_8_48_OSR_LP_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_BT_DL_8_48_OSR_LP_DATA_ID]);
#endif
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_BT_DL_48_8_HP_DATA_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_BT_DL_48_8_LP_DATA_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_BT_DL_48_16_HP_DATA_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_BT_DL_48_16_LP_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_BT_DL_48_8_HP_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_BT_DL_48_8_LP_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_BT_DL_48_16_HP_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_BT_DL_48_16_LP_DATA_ID]);
break;
case OMAP_ABE_PDM_DL_PORT:
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_DMEM_MCPDM_DL_FIFO_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_DL2_M_LR_EQ_DATA_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_DL1_M_EQ_DATA_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_EARP_48_96_LP_DATA_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_IHF_48_96_LP_DATA_ID]);
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_GAIN_DL1_LEFT);
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_GAIN_DL1_RIGHT);
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_GAIN_DL2_LEFT);
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_GAIN_DL2_RIGHT);
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_MIXSDT_UL);
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_MIXSDT_DL);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_DMEM_MCPDM_DL_FIFO_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_DL2_M_LR_EQ_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_DL1_M_EQ_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_EARP_48_96_LP_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_IHF_48_96_LP_DATA_ID]);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_GAIN_DL1_LEFT);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_GAIN_DL1_RIGHT);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_GAIN_DL2_LEFT);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_GAIN_DL2_RIGHT);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_MIXSDT_UL);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_MIXSDT_DL);
break;
case OMAP_ABE_MM_EXT_OUT_PORT:
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_DMEM_MM_EXT_OUT_FIFO_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_DMEM_MM_EXT_OUT_FIFO_ID]);
break;
case OMAP_ABE_MM_EXT_IN_PORT:
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_DMEM_MM_EXT_IN_FIFO_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_DMEM_MM_EXT_IN_FIFO_ID]);
break;
}
}
/**
* omap_aess_disable_enable_dma_request
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: ABE port ID
* @on_off: Enable/Disable
*
* Enable/Disable DMA request associated to a port.
*/
-static void omap_aess_disable_enable_dma_request(struct omap_aess *abe, u32 id,
+static void omap_aess_disable_enable_dma_request(struct omap_aess *aess, u32 id,
u32 on_off)
{
u8 desc_third_word[4], irq_dmareq_field;
- struct ABE_SIODescriptor sio_desc;
- struct ABE_SPingPongDescriptor desc_pp;
+ struct omap_aess_io_desc sio_desc;
+ struct omap_aess_pingpong_desc desc_pp;
struct omap_aess_addr addr;
- if (abe_port[id].protocol.protocol_switch == PINGPONG_PORT_PROT) {
+ if (abe_port[id].protocol.protocol_switch == OMAP_AESS_PORT_PINGPONG) {
irq_dmareq_field = (u8) (on_off *
abe_port[id].protocol.p.prot_pingpong.irq_data);
- memcpy(&addr, &abe->fw_info->map[OMAP_AESS_DMEM_PINGPONGDESC_ID],
+ memcpy(&addr, &aess->fw_info->map[OMAP_AESS_DMEM_PINGPONGDESC_ID],
sizeof(struct omap_aess_addr));
addr.offset += (u32)&(desc_pp.data_size) - (u32)&(desc_pp);
addr.bytes = 4;
- omap_aess_mem_read(abe, addr, (u32 *)desc_third_word);
+ omap_aess_mem_read(aess, addr, (u32 *)desc_third_word);
desc_third_word[2] = irq_dmareq_field;
- omap_aess_mem_write(abe, addr, (u32 *)desc_third_word);
+ omap_aess_mem_write(aess, addr, (u32 *)desc_third_word);
} else {
/* serial interface: sync ATC with Firmware activity */
- memcpy(&addr, &abe->fw_info->map[OMAP_AESS_DMEM_IODESCR_ID],
+ memcpy(&addr, &aess->fw_info->map[OMAP_AESS_DMEM_IODESCR_ID],
sizeof(struct omap_aess_addr));
- addr.offset += id * sizeof(struct ABE_SIODescriptor);
- addr.bytes = sizeof(struct ABE_SIODescriptor);
- omap_aess_mem_read(abe, addr, (u32 *)&sio_desc);
+ addr.offset += id * sizeof(struct omap_aess_io_desc);
+ addr.bytes = sizeof(struct omap_aess_io_desc);
+ omap_aess_mem_read(aess, addr, (u32 *)&sio_desc);
if (on_off) {
- if (abe_port[id].protocol.protocol_switch != SERIAL_PORT_PROT)
+ if (abe_port[id].protocol.protocol_switch != OMAP_AESS_PORT_SERIAL)
sio_desc.atc_irq_data =
(u8) abe_port[id].protocol.p.prot_dmareq.
dma_data;
@@ -578,45 +575,45 @@ static void omap_aess_disable_enable_dma_request(struct omap_aess *abe, u32 id,
sio_desc.atc_irq_data = 0;
sio_desc.on_off = 0;
}
- omap_aess_mem_write(abe, addr, (u32 *)&sio_desc);
+ omap_aess_mem_write(aess, addr, (u32 *)&sio_desc);
}
}
/**
* omap_aess_enable_dma_request
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: ABE port ID
*
* Enable DMA request associated to the port ID
*/
-static void omap_aess_enable_dma_request(struct omap_aess *abe, u32 id)
+static void omap_aess_enable_dma_request(struct omap_aess *aess, u32 id)
{
- omap_aess_disable_enable_dma_request(abe, id, 1);
+ omap_aess_disable_enable_dma_request(aess, id, 1);
}
/**
* omap_aess_disable_dma_request
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: ABE port ID
*
* Disable DMA request associated to the port ID
*/
-static void omap_aess_disable_dma_request(struct omap_aess *abe, u32 id)
+static void omap_aess_disable_dma_request(struct omap_aess *aess, u32 id)
{
- omap_aess_disable_enable_dma_request(abe, id, 0);
+ omap_aess_disable_enable_dma_request(aess, id, 0);
}
/**
* omap_aess_init_atc
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: ABE port ID
*
* load the DMEM ATC/AESS descriptor associated to the port ID.
* ATC is describing the internal flexible FIFO inside the DMEM
* connected to HW IP (eg McBSP/DMIC/...)
*/
-static void omap_aess_init_atc(struct omap_aess *abe, u32 id)
+static void omap_aess_init_atc(struct omap_aess *aess, u32 id)
{
u8 iter;
s32 datasize;
atc_desc.wrpt = 0 + ((JITTER_MARGIN+1) * datasize);
switch ((abe_port[id]).protocol.protocol_switch) {
- case SERIAL_PORT_PROT:
+ case OMAP_AESS_PORT_SERIAL:
atc_desc.cbdir = (abe_port[id]).protocol.direction;
atc_desc.cbsize =
(abe_port[id]).protocol.p.prot_serial.buf_size;
atc_desc.destid =
abe_atc_dstid[(abe_port[id]).protocol.p.prot_serial.
desc_addr >> 3];
- omap_abe_mem_write(abe, OMAP_ABE_DMEM,
+ omap_abe_mem_write(aess, OMAP_ABE_DMEM,
(abe_port[id]).protocol.p.prot_serial.desc_addr,
(u32 *)&atc_desc, sizeof(atc_desc));
break;
- case DMIC_PORT_PROT:
+ case OMAP_AESS_PORT_DMIC:
atc_desc.cbdir = ABE_ATC_DIRECTION_IN;
atc_desc.cbsize = (abe_port[id]).protocol.p.prot_dmic.buf_size;
atc_desc.badd =
((abe_port[id]).protocol.p.prot_dmic.buf_addr) >> 4;
atc_desc.iter = DMIC_ITER;
atc_desc.srcid = abe_atc_srcid[ABE_ATC_DMIC_DMA_REQ];
- omap_abe_mem_write(abe, OMAP_ABE_DMEM,
+ omap_abe_mem_write(aess, OMAP_ABE_DMEM,
(ABE_ATC_DMIC_DMA_REQ*ATC_SIZE),
(u32 *)&atc_desc, sizeof(atc_desc));
break;
- case MCPDMDL_PORT_PROT:
+ case OMAP_AESS_PORT_MCPDMDL:
atc_desc.cbdir = ABE_ATC_DIRECTION_OUT;
atc_desc.cbsize =
(abe_port[id]).protocol.p.prot_mcpdmdl.buf_size;
((abe_port[id]).protocol.p.prot_mcpdmdl.buf_addr) >> 4;
atc_desc.iter = MCPDM_DL_ITER;
atc_desc.destid = abe_atc_dstid[ABE_ATC_MCPDMDL_DMA_REQ];
- omap_abe_mem_write(abe, OMAP_ABE_DMEM,
+ omap_abe_mem_write(aess, OMAP_ABE_DMEM,
(ABE_ATC_MCPDMDL_DMA_REQ*ATC_SIZE),
(u32 *)&atc_desc, sizeof(atc_desc));
break;
- case MCPDMUL_PORT_PROT:
+ case OMAP_AESS_PORT_MCPDMUL:
atc_desc.cbdir = ABE_ATC_DIRECTION_IN;
atc_desc.cbsize =
(abe_port[id]).protocol.p.prot_mcpdmul.buf_size;
((abe_port[id]).protocol.p.prot_mcpdmul.buf_addr) >> 4;
atc_desc.iter = MCPDM_UL_ITER;
atc_desc.srcid = abe_atc_srcid[ABE_ATC_MCPDMUL_DMA_REQ];
- omap_abe_mem_write(abe, OMAP_ABE_DMEM,
+ omap_abe_mem_write(aess, OMAP_ABE_DMEM,
(ABE_ATC_MCPDMUL_DMA_REQ*ATC_SIZE),
(u32 *)&atc_desc, sizeof(atc_desc));
break;
- case PINGPONG_PORT_PROT:
+ case OMAP_AESS_PORT_PINGPONG:
/* software protocol, nothing to do on ATC */
break;
- case DMAREQ_PORT_PROT:
+ case OMAP_AESS_PORT_DMAREQ:
atc_desc.cbdir = (abe_port[id]).protocol.direction;
atc_desc.cbsize =
(abe_port[id]).protocol.p.prot_dmareq.buf_size;
[(abe_port[id]).protocol.p.prot_dmareq.
desc_addr >> 3];
}
- omap_abe_mem_write(abe, OMAP_ABE_DMEM,
+ omap_abe_mem_write(aess, OMAP_ABE_DMEM,
(abe_port[id]).protocol.p.prot_dmareq.desc_addr,
(u32 *)&atc_desc, sizeof(atc_desc));
break;
/**
* omap_aess_disable_data_transfer
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: ABE port id
*
* disables the ATC descriptor and stop IO/port activities
* disable the IO task (@f = 0)
* clear ATC DMEM buffer, ATC enabled
*/
-int omap_aess_disable_data_transfer(struct omap_aess *abe, u32 id)
+int omap_aess_disable_data_transfer(struct omap_aess *aess, u32 id)
{
switch (id) {
case OMAP_ABE_MM_DL_PORT:
- abe->MultiFrame[18][1] = 0;
+ aess->MultiFrame[18][1] = 0;
break;
default:
break;
/* local host variable status= "port is running" */
abe_port[id].status = OMAP_ABE_PORT_ACTIVITY_IDLE;
/* disable DMA requests */
- omap_aess_disable_dma_request(abe, id);
+ omap_aess_disable_dma_request(aess, id);
/* disable ATC transfers */
- omap_aess_init_atc(abe, id);
- omap_aess_clean_temporary_buffers(abe, id);
+ omap_aess_init_atc(aess, id);
+ omap_aess_clean_temporary_buffers(aess, id);
/* select the main port based on the desactivation of this port */
- omap_aess_decide_main_port(abe);
+ omap_aess_decide_main_port(aess);
return 0;
}
/**
* omap_aess_enable_data_transfer
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: ABE port id
*
* enables the ATC descriptor
* reset ATC pointers
* enable the IO task (@f <> 0)
*/
-int omap_aess_enable_data_transfer(struct omap_aess *abe, u32 id)
+int omap_aess_enable_data_transfer(struct omap_aess *aess, u32 id)
{
struct omap_aess_port_protocol *protocol;
struct omap_aess_data_format format;
- omap_aess_clean_temporary_buffers(abe, id);
+ omap_aess_clean_temporary_buffers(aess, id);
- omap_aess_update_scheduling_table1(abe, &(abe->fw_info->port[id].task), 1);
+ omap_aess_update_scheduling_table(aess, &(aess->fw_info->port[id].task), 1);
switch (id) {
case OMAP_ABE_PDM_UL_PORT:
/* initializes the ABE ATC descriptors in DMEM for BE ports */
protocol = &(abe_port[id].protocol);
format = abe_port[id].format;
- omap_aess_init_atc(abe, id);
- omap_aess_init_io_tasks(abe, id, &format, protocol);
+ omap_aess_init_atc(aess, id);
+ omap_aess_init_io_tasks(aess, id, &format, protocol);
break;
case OMAP_ABE_MM_DL_PORT:
protocol = &(abe_port[OMAP_ABE_MM_DL_PORT].protocol);
- if (protocol->protocol_switch == PINGPONG_PORT_PROT)
- omap_aess_update_scheduling_table1(abe, &abe->fw_info->ping_pong->task, 1);
+ if (protocol->protocol_switch == OMAP_AESS_PORT_PINGPONG)
+ omap_aess_update_scheduling_table(aess, &aess->fw_info->ping_pong->task, 1);
break;
default:
break;
}
- omap_aess_mem_write(abe, abe->fw_info->map[OMAP_AESS_DMEM_MULTIFRAME_ID],
- (u32 *)abe->MultiFrame);
+ omap_aess_mem_write(aess, aess->fw_info->map[OMAP_AESS_DMEM_MULTIFRAME_ID],
+ (u32 *)aess->MultiFrame);
/* local host variable status= "port is running" */
abe_port[id].status = OMAP_ABE_PORT_ACTIVITY_RUNNING;
/* enable DMA requests */
- omap_aess_enable_dma_request(abe, id);
+ omap_aess_enable_dma_request(aess, id);
/* select the main port based on the activation of this new port */
- omap_aess_decide_main_port(abe);
+ omap_aess_decide_main_port(aess);
return 0;
}
EXPORT_SYMBOL(omap_aess_enable_data_transfer);
+/**
+ * omap_aess_read_port_address
+ * @aess: Pointer on aess handle
+ * @port: port name
+ * @aess_dma: output pointer to the DMA iteration and data destination pointer
+ *
+ * This API returns the address of the DMA register used on this audio port.
+ * Depending on the protocol being used, adds the base address offset L3
+ * (DMA) or MPU (ARM)
+ */
+static void omap_aess_read_port_address(struct omap_aess *aess, u32 port,
+ struct omap_aess_dma *aess_dma)
+{
+ struct omap_aess_dma_offset *dma_offset = &abe_port[port].dma;
+
+ switch (abe_port[port].protocol.protocol_switch) {
+ case OMAP_AESS_PORT_PINGPONG:
+ /* return the base address of the buffer in L3 and L4 spaces */
+ aess_dma->data = (void *)(dma_offset->data +
+ ABE_DEFAULT_BASE_ADDRESS_L3 + ABE_DMEM_BASE_OFFSET_MPU);
+ break;
+ case OMAP_AESS_PORT_DMAREQ:
+ /* return the CBPr(L3), DMEM(L3), DMEM(L4) address */
+ aess_dma->data = (void *)(dma_offset->data +
+ ABE_DEFAULT_BASE_ADDRESS_L3 + ABE_ATC_BASE_OFFSET_MPU);
+ break;
+ default:
+ break;
+ }
+ aess_dma->iter = dma_offset->iter;
+}
+
/**
* omap_aess_connect_cbpr_dmareq_port
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: port name
* @f: desired data format
* @d: desired dma_request line (0..7)
- * @returned_dma_t: returned pointer to the base address of the CBPr register and number of
- * samples to exchange during a DMA_request.
+ * @aess_dma: returned pointer to the base address of the CBPr register and
+ * number of samples to exchange during a DMA_request.
*
* enables the data echange between a DMA and the ABE through the
* CBPr registers of AESS.
*/
-int omap_aess_connect_cbpr_dmareq_port(struct omap_aess *abe,
- u32 id, struct omap_aess_data_format *f,
- u32 d,
- struct omap_aess_dma *returned_dma_t)
+void omap_aess_connect_cbpr_dmareq_port(struct omap_aess *aess, u32 id,
+ struct omap_aess_data_format *f, u32 d,
+ struct omap_aess_dma *aess_dma)
{
- abe_port[id] = ((struct omap_aess_port *)abe->fw_info->port)[id];
- (abe_port[id]).format = (*f);
- abe_port[id].protocol.protocol_switch = DMAREQ_PORT_PROT;
+ omap_aess_reset_port(aess, id);
+
+ memcpy(&abe_port[id].format, f, sizeof(*f));
+
+ abe_port[id].protocol.protocol_switch = OMAP_AESS_PORT_DMAREQ;
abe_port[id].protocol.p.prot_dmareq.iter = abe_dma_port_iteration(f);
- abe_port[id].protocol.p.prot_dmareq.dma_addr = ABE_DMASTATUS_RAW;
+ abe_port[id].protocol.p.prot_dmareq.dma_addr = OMAP_AESS_DMASTATUS_RAW;
abe_port[id].protocol.p.prot_dmareq.dma_data = (1 << d);
+
/* load the dma_t with physical information from AE memory mapping */
- abe_init_dma_t(id, &((abe_port[id]).protocol));
+ abe_init_dma_t(id, &abe_port[id].protocol);
/* load the ATC descriptors - disabled */
- omap_aess_init_atc(abe, id);
+ omap_aess_init_atc(aess, id);
/* load the micro-task parameters */
- omap_aess_init_io_tasks(abe, id, &((abe_port[id]).format),
- &((abe_port[id]).protocol));
+ omap_aess_init_io_tasks(aess, id, &abe_port[id].format,
+ &abe_port[id].protocol);
abe_port[id].status = OMAP_ABE_PORT_INITIALIZED;
- /* return the dma pointer address */
- omap_aess_read_port_address(abe, id, returned_dma_t);
- return 0;
+ if (aess_dma)
+ omap_aess_read_port_address(aess, id, aess_dma);
}
EXPORT_SYMBOL(omap_aess_connect_cbpr_dmareq_port);
/**
* omap_aess_connect_serial_port()
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: port name
* @f: data format
* @mcbsp_id: peripheral ID (McBSP #1, #2, #3)
+ * @aess_dma: returned pointer to the base address of the CBPr register and
+ * number of samples to exchange during a DMA_request.
*
* Operations : enables the data echanges between a McBSP and an ATC buffer in
* DMEM. This API is used connect 48kHz McBSP streams to MM_DL and 8/16kHz
* voice streams to VX_UL, VX_DL, BT_VX_UL, BT_VX_DL. It abstracts the
* abe_write_port API.
*/
-int omap_aess_connect_serial_port(struct omap_aess *abe,
- u32 id, struct omap_aess_data_format *f,
- u32 mcbsp_id)
+void omap_aess_connect_serial_port(struct omap_aess *aess, u32 id,
+ struct omap_aess_data_format *f,
+ u32 mcbsp_id, struct omap_aess_dma *aess_dma)
{
- abe_port[id] = ((struct omap_aess_port *)abe->fw_info->port)[id];
- (abe_port[id]).format = (*f);
- (abe_port[id]).protocol.protocol_switch = SERIAL_PORT_PROT;
+ omap_aess_reset_port(aess, id);
+
+ memcpy(&abe_port[id].format, f, sizeof(*f));
+
+ abe_port[id].protocol.protocol_switch = OMAP_AESS_PORT_SERIAL;
/* McBSP peripheral connected to ATC */
- (abe_port[id]).protocol.p.prot_serial.desc_addr = mcbsp_id*ATC_SIZE;
+ abe_port[id].protocol.p.prot_serial.desc_addr = mcbsp_id * ATC_SIZE;
/* check the iteration of ATC */
- (abe_port[id]).protocol.p.prot_serial.iter =
- abe_dma_port_iter_factor(f);
+ abe_port[id].protocol.p.prot_serial.iter = abe_dma_port_iter_factor(f);
/* load the ATC descriptors - disabled */
- omap_aess_init_atc(abe, id);
+ omap_aess_init_atc(aess, id);
/* load the micro-task parameters */
- omap_aess_init_io_tasks(abe, id, &((abe_port[id]).format),
- &((abe_port[id]).protocol));
+ omap_aess_init_io_tasks(aess, id, &abe_port[id].format,
+ &abe_port[id].protocol);
abe_port[id].status = OMAP_ABE_PORT_INITIALIZED;
- return 0;
+ if (aess_dma)
+ omap_aess_read_port_address(aess, id, aess_dma);
}
EXPORT_SYMBOL(omap_aess_connect_serial_port);
-/**
- * omap_aess_read_port_address
- * @abe: Pointer on aess handle
- * @port: port name
- * @dma2: output pointer to the DMA iteration and data destination pointer
- *
- * This API returns the address of the DMA register used on this audio port.
- * Depending on the protocol being used, adds the base address offset L3
- * (DMA) or MPU (ARM)
- */
-int omap_aess_read_port_address(struct omap_aess *abe,
- u32 port, struct omap_aess_dma *dma2)
-{
- struct omap_aess_dma_offset dma1;
- u32 protocol_switch;
-
- dma1 = (abe_port[port]).dma;
- protocol_switch = abe_port[port].protocol.protocol_switch;
- switch (protocol_switch) {
- case PINGPONG_PORT_PROT:
- /* return the base address of the buffer in L3 and L4 spaces */
- (*dma2).data = (void *)(dma1.data +
- ABE_DEFAULT_BASE_ADDRESS_L3 + ABE_DMEM_BASE_OFFSET_MPU);
- (*dma2).l3_dmem = (void *)(dma1.data +
- ABE_DEFAULT_BASE_ADDRESS_L3 + ABE_DMEM_BASE_OFFSET_MPU);
- (*dma2).l4_dmem = (void *)(dma1.data +
- ABE_DEFAULT_BASE_ADDRESS_L4 + ABE_DMEM_BASE_OFFSET_MPU);
- break;
- case DMAREQ_PORT_PROT:
- /* return the CBPr(L3), DMEM(L3), DMEM(L4) address */
- (*dma2).data = (void *)(dma1.data +
- ABE_DEFAULT_BASE_ADDRESS_L3 + ABE_ATC_BASE_OFFSET_MPU);
- (*dma2).l3_dmem =
- (void *)((abe_port[port]).protocol.p.prot_dmareq.buf_addr +
- ABE_DEFAULT_BASE_ADDRESS_L3 + ABE_DMEM_BASE_OFFSET_MPU);
- (*dma2).l4_dmem =
- (void *)((abe_port[port]).protocol.p.prot_dmareq.buf_addr +
- ABE_DEFAULT_BASE_ADDRESS_L4 + ABE_DMEM_BASE_OFFSET_MPU);
- break;
- default:
- break;
- }
- (*dma2).iter = (dma1.iter);
-
- return 0;
-}
-EXPORT_SYMBOL(omap_aess_read_port_address);
-
/**
* abe_init_dma_t
* @id: ABE port ID
dma.data = 0;
dma.iter = 0;
switch (prot->protocol_switch) {
- case PINGPONG_PORT_PROT:
+ case OMAP_AESS_PORT_PINGPONG:
for (idx = 0; idx < 32; idx++) {
if (((prot->p).prot_pingpong.irq_data) ==
(u32) (1 << idx))
dma.data = (prot->p).prot_pingpong.buf_addr >> 2;
dma.iter = (prot->p).prot_pingpong.buf_size >> 2;
break;
- case DMAREQ_PORT_PROT:
+ case OMAP_AESS_PORT_DMAREQ:
for (idx = 0; idx < 32; idx++) {
if (((prot->p).prot_dmareq.dma_data) ==
(u32) (1 << idx))
(prot->p).prot_dmareq.desc_addr =
((CBPr_DMA_RTX0 + idx)*ATC_SIZE);
break;
- case SLIMBUS_PORT_PROT:
- case SERIAL_PORT_PROT:
- case DMIC_PORT_PROT:
- case MCPDMDL_PORT_PROT:
- case MCPDMUL_PORT_PROT:
+ case OMAP_AESS_PORT_SERIAL:
+ case OMAP_AESS_PORT_DMIC:
+ case OMAP_AESS_PORT_MCPDMDL:
+ case OMAP_AESS_PORT_MCPDMUL:
default:
break;
}
/**
* omap_aess_enable_atc
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: port name
*
* Enable ATC associated to the port ID
*/
-static void omap_aess_enable_atc(struct omap_aess *abe, u32 id)
+static void omap_aess_enable_atc(struct omap_aess *aess, u32 id)
{
struct omap_abe_atc_desc atc_desc;
- omap_abe_mem_read(abe, OMAP_ABE_DMEM,
+ omap_abe_mem_read(aess, OMAP_ABE_DMEM,
(abe_port[id]).protocol.p.prot_dmareq.desc_addr,
(u32 *)&atc_desc, sizeof(atc_desc));
atc_desc.desen = 1;
- omap_abe_mem_write(abe, OMAP_ABE_DMEM,
+ omap_abe_mem_write(aess, OMAP_ABE_DMEM,
(abe_port[id]).protocol.p.prot_dmareq.desc_addr,
(u32 *)&atc_desc, sizeof(atc_desc));
/**
* omap_aess_disable_atc
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: port name
*
* Enable ATC associated to the port ID
*/
-static void omap_aess_disable_atc(struct omap_aess *abe, u32 id)
+static void omap_aess_disable_atc(struct omap_aess *aess, u32 id)
{
struct omap_abe_atc_desc atc_desc;
- omap_abe_mem_read(abe, OMAP_ABE_DMEM,
+ omap_abe_mem_read(aess, OMAP_ABE_DMEM,
(abe_port[id]).protocol.p.prot_dmareq.desc_addr,
(u32 *)&atc_desc, sizeof(atc_desc));
atc_desc.desen = 0;
- omap_abe_mem_write(abe, OMAP_ABE_DMEM,
+ omap_abe_mem_write(aess, OMAP_ABE_DMEM,
(abe_port[id]).protocol.p.prot_dmareq.desc_addr,
(u32 *)&atc_desc, sizeof(atc_desc));
/**
* omap_aess_init_io_tasks
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: port name
* @format: data format being used
* @prot: protocol being used
* For Write to DMEM usually THR1/THR2 = 2/0
* UP_1/2 =X+1/X-1
*/
-int omap_aess_init_io_tasks(struct omap_aess *abe, u32 id,
+int omap_aess_init_io_tasks(struct omap_aess *aess, u32 id,
struct omap_aess_data_format *format,
struct omap_aess_port_protocol *prot)
{
u32 copy_func_index2, atc_desc_address1, atc_desc_address2;
struct omap_aess_addr addr;
- if (prot->protocol_switch == PINGPONG_PORT_PROT) {
- struct ABE_SPingPongDescriptor desc_pp;
+ if (prot->protocol_switch == OMAP_AESS_PORT_PINGPONG) {
+ struct omap_aess_pingpong_desc desc_pp;
memset(&desc_pp, 0, sizeof(desc_pp));
return -AESS_EINVAL;
}
if (abe_port[id].format.f == 44100)
- smem1 = omap_aess_update_io_task1(abe, &(abe->fw_info->ping_pong->tsk_freq[2].task), 1);
+ smem1 = omap_aess_update_io_task1(aess, &(aess->fw_info->ping_pong->tsk_freq[2].task), 1);
else
- smem1 = omap_aess_update_io_task1(abe, &(abe->fw_info->ping_pong->tsk_freq[3].task), 1);
+ smem1 = omap_aess_update_io_task1(aess, &(aess->fw_info->ping_pong->tsk_freq[3].task), 1);
/* able interrupt to be generated at the first frame */
desc_pp.split_addr1 = 1;
- copy_func_index = (u8) abe_dma_port_copy_subroutine_id(abe, id);
+ copy_func_index = (u8) abe_dma_port_copy_subroutine_id(aess, id);
dmareq_addr = abe_port[id].protocol.p.prot_pingpong.irq_addr;
dmareq_field = abe_port[id].protocol.p.prot_pingpong.irq_data;
datasize = abe_dma_port_iter_factor(format);
desc_pp.data_size = (u8) datasize;
/* address comunicated in Bytes */
desc_pp.workbuff_BaseAddr =
- (u16) (abe->base_address_pingpong[1]);
+ (u16) (aess->base_address_pingpong[1]);
/* size comunicated in XIO sample */
desc_pp.workbuff_Samples = 0;
desc_pp.nextbuff0_BaseAddr =
- (u16) (abe->base_address_pingpong[0]);
+ (u16) (aess->base_address_pingpong[0]);
desc_pp.nextbuff1_BaseAddr =
- (u16) (abe->base_address_pingpong[1]);
- if (dmareq_addr == ABE_DMASTATUS_RAW) {
+ (u16) (aess->base_address_pingpong[1]);
+ if (dmareq_addr == OMAP_AESS_DMASTATUS_RAW) {
desc_pp.nextbuff0_Samples =
- (u16) ((abe->size_pingpong >> 2) / datasize);
+ (u16) ((aess->size_pingpong >> 2) / datasize);
desc_pp.nextbuff1_Samples =
- (u16) ((abe->size_pingpong >> 2) / datasize);
+ (u16) ((aess->size_pingpong >> 2) / datasize);
} else {
desc_pp.nextbuff0_Samples = 0;
desc_pp.nextbuff1_Samples = 0;
/* send a DMA req to fill B0 with N samples
abe_block_copy (COPY_FROM_HOST_TO_ABE,
ABE_ATC,
- ABE_DMASTATUS_RAW,
+ OMAP_AESS_DMASTATUS_RAW,
&(abe_port[id].protocol.p.prot_pingpong.irq_data),
4); */
- memcpy(&addr, &abe->fw_info->map[OMAP_AESS_DMEM_PINGPONGDESC_ID],
+ memcpy(&addr, &aess->fw_info->map[OMAP_AESS_DMEM_PINGPONGDESC_ID],
sizeof(struct omap_aess_addr));
addr.bytes = sizeof(desc_pp);
- omap_aess_mem_write(abe, addr, (u32 *)&desc_pp);
+ omap_aess_mem_write(aess, addr, (u32 *)&desc_pp);
} else {
- struct ABE_SIODescriptor sio_desc;
+ struct omap_aess_io_desc sio_desc;
int idx;
switch (abe_port[id].format.f) {
memset(&sio_desc, 0, sizeof(sio_desc));
- io_sub_id = ABE_DMASTATUS_RAW;
- dmareq_addr = ABE_DMASTATUS_RAW;
+ io_sub_id = OMAP_AESS_DMASTATUS_RAW;
+ dmareq_addr = OMAP_AESS_DMASTATUS_RAW;
dmareq_field = 0;
atc_desc_address1 = 0;
atc_desc_address2 = 0;
datasize = abe_dma_port_iter_factor(format);
x_io = (u8) abe_dma_port_iteration(format);
nsamp = (x_io / datasize);
- atc_ptr_saved2 = abe->fw_info->label_id[OMAP_AESS_BUFFER_DMIC_ATC_PTR_ID] + id;
- atc_ptr_saved = abe->fw_info->label_id[OMAP_AESS_BUFFER_DMIC_ATC_PTR_ID] + id;
+ atc_ptr_saved2 = aess->fw_info->label_id[OMAP_AESS_BUFFER_DMIC_ATC_PTR_ID] + id;
+ atc_ptr_saved = aess->fw_info->label_id[OMAP_AESS_BUFFER_DMIC_ATC_PTR_ID] + id;
smem1 = abe_port[id].smem_buffer1;
smem2 = abe_port[id].smem_buffer2;
smem3 = abe_port[id].smem_buffer2;
- copy_func_index1 = (u8) abe_dma_port_copy_subroutine_id(abe, id);
+ copy_func_index1 = (u8) abe_dma_port_copy_subroutine_id(aess, id);
- before_func_index = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_NULL_ID];
- after_func_index = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_NULL_ID];
- copy_func_index2 = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_NULL_ID];
+ before_func_index = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_NULL_ID];
+ after_func_index = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_NULL_ID];
+ copy_func_index2 = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_NULL_ID];
switch (prot->protocol_switch) {
- case DMIC_PORT_PROT:
+ case OMAP_AESS_PORT_DMIC:
/* DMIC port is read in two steps */
x_io = x_io >> 1;
nsamp = nsamp >> 1;
atc_desc_address1 = (ABE_ATC_DMIC_DMA_REQ*ATC_SIZE);
- io_sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_IO_IP_ID];
+ io_sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_IO_IP_ID];
break;
- case MCPDMDL_PORT_PROT:
+ case OMAP_AESS_PORT_MCPDMDL:
/* PDMDL port is written to in two steps */
x_io = x_io >> 1;
atc_desc_address1 = (ABE_ATC_MCPDMDL_DMA_REQ*ATC_SIZE);
- io_sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_IO_IP_ID];
+ io_sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_IO_IP_ID];
break;
- case MCPDMUL_PORT_PROT:
+ case OMAP_AESS_PORT_MCPDMUL:
atc_desc_address1 = (ABE_ATC_MCPDMUL_DMA_REQ*ATC_SIZE);
- io_sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_IO_IP_ID];
- break;
- case SLIMBUS_PORT_PROT:
- atc_desc_address1 = abe_port[id].protocol.p.prot_slimbus.desc_addr1;
- atc_desc_address2 = abe_port[id].protocol.p.prot_slimbus.desc_addr2;
- copy_func_index2 = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_NULL_ID];
- /* @@@@@@
- #define SPLIT_SMEM_CFPID 9
- #define MERGE_SMEM_CFPID 10
- #define SPLIT_TDM_12_CFPID 11
- #define MERGE_TDM_12_CFPID 12
- */
- io_sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_IO_IP_ID];
+ io_sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_IO_IP_ID];
break;
- case SERIAL_PORT_PROT: /* McBSP/McASP */
+ case OMAP_AESS_PORT_SERIAL: /* McBSP/McASP */
atc_desc_address1 = (s16) abe_port[id].protocol.p.prot_serial.desc_addr;
- io_sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_IO_IP_ID];
+ io_sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_IO_IP_ID];
break;
- case DMAREQ_PORT_PROT: /* DMA w/wo CBPr */
+ case OMAP_AESS_PORT_DMAREQ: /* DMA w/wo CBPr */
dmareq_addr = abe_port[id].protocol.p.prot_dmareq.dma_addr;
dmareq_field = 0;
atc_desc_address1 = abe_port[id].protocol.p.prot_dmareq.desc_addr;
- io_sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_IO_IP_ID];
+ io_sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_IO_IP_ID];
break;
}
/* special situation of the PING_PONG protocol which
*/
switch (id) {
case OMAP_ABE_VX_DL_PORT:
- omap_aess_update_scheduling_table1(abe, &(abe->fw_info->port[id].task), 1);
+ omap_aess_update_scheduling_table(aess, &(aess->fw_info->port[id].task), 1);
- smem1 = omap_aess_update_io_task1(abe, &(abe->fw_info->port[id].tsk_freq[idx].task), 1);
+ smem1 = omap_aess_update_io_task1(aess, &(aess->fw_info->port[id].tsk_freq[idx].task), 1);
/* check for 8kHz/16kHz */
if (idx < 2) {
/* ASRC set only for McBSP */
- if ((prot->protocol_switch == SERIAL_PORT_PROT)) {
+ if ((prot->protocol_switch == OMAP_AESS_PORT_SERIAL)) {
if ((abe_port[OMAP_ABE_VX_DL_PORT].status ==
OMAP_ABE_PORT_ACTIVITY_IDLE) &&
(abe_port[OMAP_ABE_VX_UL_PORT].status ==
/* the 1st opened port is VX_DL_PORT
* both VX_UL ASRC and VX_DL ASRC will add/remove sample
* referring to VX_DL flow_counter */
- omap_aess_update_scheduling_table1(abe, &(abe->fw_info->port[id].tsk_freq[idx].asrc.serial), 1);
+ omap_aess_update_scheduling_table(aess, &(aess->fw_info->port[id].tsk_freq[idx].asrc.serial), 1);
/* Init VX_UL ASRC & VX_DL ASRC and enable its adaptation */
- omap_aess_init_asrc_vx_ul(abe, -250);
- omap_aess_init_asrc_vx_dl(abe, 250);
+ omap_aess_init_asrc_vx_ul(aess, -250);
+ omap_aess_init_asrc_vx_dl(aess, 250);
} else {
/* Do nothing, Scheduling Table has already been patched */
}
} else {
/* Enable only ASRC on VXDL port*/
- omap_aess_update_scheduling_table1(abe, &(abe->fw_info->port[id].tsk_freq[idx].asrc.cbpr), 1);
- omap_aess_init_asrc_vx_dl(abe, 0);
+ omap_aess_update_scheduling_table(aess, &(aess->fw_info->port[id].tsk_freq[idx].asrc.cbpr), 1);
+ omap_aess_init_asrc_vx_dl(aess, 0);
}
}
break;
case OMAP_ABE_VX_UL_PORT:
- omap_aess_update_scheduling_table1(abe, &(abe->fw_info->port[id].task), 1);
+ omap_aess_update_scheduling_table(aess, &(aess->fw_info->port[id].task), 1);
- smem1 = omap_aess_update_io_task1(abe, &(abe->fw_info->port[id].tsk_freq[idx].task), 1);
+ smem1 = omap_aess_update_io_task1(aess, &(aess->fw_info->port[id].tsk_freq[idx].task), 1);
/* check for 8kHz/16kHz */
if (idx < 2) {
/* ASRC set only for McBSP */
- if ((prot->protocol_switch == SERIAL_PORT_PROT)) {
+ if ((prot->protocol_switch == OMAP_AESS_PORT_SERIAL)) {
if ((abe_port[OMAP_ABE_VX_DL_PORT].status ==
OMAP_ABE_PORT_ACTIVITY_IDLE) &&
(abe_port[OMAP_ABE_VX_UL_PORT].status ==
/* the 1st opened port is VX_UL_PORT
* both VX_UL ASRC and VX_DL ASRC will add/remove sample
* referring to VX_UL flow_counter */
- omap_aess_update_scheduling_table1(abe, &(abe->fw_info->port[id].tsk_freq[idx].asrc.serial), 1);
+ omap_aess_update_scheduling_table(aess, &(aess->fw_info->port[id].tsk_freq[idx].asrc.serial), 1);
/* Init VX_UL ASRC & VX_DL ASRC and enable its adaptation */
- omap_aess_init_asrc_vx_ul(abe, -250);
- omap_aess_init_asrc_vx_dl(abe, 250);
+ omap_aess_init_asrc_vx_ul(aess, -250);
+ omap_aess_init_asrc_vx_dl(aess, 250);
} else {
/* Do nothing, Scheduling Table has already been patched */
}
} else {
/* Enable only ASRC on VXUL port*/
- omap_aess_update_scheduling_table1(abe, &(abe->fw_info->port[id].tsk_freq[idx].asrc.cbpr), 1);
- omap_aess_init_asrc_vx_ul(abe, 0);
+ omap_aess_update_scheduling_table(aess, &(aess->fw_info->port[id].tsk_freq[idx].asrc.cbpr), 1);
+ omap_aess_init_asrc_vx_ul(aess, 0);
}
}
break;
case OMAP_ABE_BT_VX_UL_PORT:
case OMAP_ABE_MM_DL_PORT:
case OMAP_ABE_TONES_DL_PORT:
- smem1 = omap_aess_update_io_task1(abe, &(abe->fw_info->port[id].tsk_freq[idx].task), 1);
+ smem1 = omap_aess_update_io_task1(aess, &(aess->fw_info->port[id].tsk_freq[idx].task), 1);
break;
case OMAP_ABE_MM_UL_PORT:
- copy_func_index1 = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_MM_UL_ID];
- before_func_index = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_ROUTE_MM_UL_ID];
+ copy_func_index1 = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_MM_UL_ID];
+ before_func_index = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_ROUTE_MM_UL_ID];
break;
case OMAP_ABE_MM_EXT_IN_PORT:
/* set the SMEM buffer -- programming sequence */
- smem1 = abe->fw_info->label_id[OMAP_AESS_BUFFER_MM_EXT_IN_ID];
+ smem1 = aess->fw_info->label_id[OMAP_AESS_BUFFER_MM_EXT_IN_ID];
break;
case OMAP_ABE_PDM_DL_PORT:
case OMAP_ABE_PDM_UL_PORT:
sio_desc.data_size2 = (u8) datasize2;
sio_desc.copy_f_index2 = (u8) copy_func_index2;
- memcpy(&addr, &abe->fw_info->map[OMAP_AESS_DMEM_IODESCR_ID],
+ memcpy(&addr, &aess->fw_info->map[OMAP_AESS_DMEM_IODESCR_ID],
sizeof(struct omap_aess_addr));
- addr.bytes = sizeof(struct ABE_SIODescriptor);
- addr.offset += (id * sizeof(struct ABE_SIODescriptor));
+ addr.bytes = sizeof(struct omap_aess_io_desc);
+ addr.offset += (id * sizeof(struct omap_aess_io_desc));
- omap_aess_mem_write(abe, addr, (u32 *)&sio_desc);
+ omap_aess_mem_write(aess, addr, (u32 *)&sio_desc);
}
- omap_aess_mem_write(abe, abe->fw_info->map[OMAP_AESS_DMEM_MULTIFRAME_ID],
- (u32 *)abe->MultiFrame);
+ omap_aess_mem_write(aess, aess->fw_info->map[OMAP_AESS_DMEM_MULTIFRAME_ID],
+ (u32 *)aess->MultiFrame);
return 0;
}
/**
* omap_aess_select_main_port - Select stynchronization port for Event generator.
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: port name
*
* tells the FW which is the reference stream for adjusting
* the processing on 23/24/25 slots
*/
-int omap_aess_select_main_port(struct omap_aess *abe, u32 id)
+int omap_aess_select_main_port(struct omap_aess *aess, u32 id)
{
u32 selection;
/* flow control */
- selection = abe->fw_info->map[OMAP_AESS_DMEM_IODESCR_ID].offset + id * sizeof(struct ABE_SIODescriptor) +
- offsetof(struct ABE_SIODescriptor, flow_counter);
+ selection = aess->fw_info->map[OMAP_AESS_DMEM_IODESCR_ID].offset + id * sizeof(struct omap_aess_io_desc) +
+ offsetof(struct omap_aess_io_desc, flow_counter);
/* when the main port is a sink port from AESS point of view
the sign the firmware task analysis must be changed */
selection &= 0xFFFFL;
if (abe_port[id].protocol.direction == ABE_ATC_DIRECTION_IN)
selection |= 0x80000;
- omap_aess_mem_write(abe, abe->fw_info->map[OMAP_AESS_DMEM_SLOT23_CTRL_ID],
+ omap_aess_mem_write(aess, aess->fw_info->map[OMAP_AESS_DMEM_SLOT23_CTRL_ID],
&selection);
return 0;
}
*/
static u32 abe_valid_port_for_synchro(u32 id)
{
- if ((abe_port[id].protocol.protocol_switch == DMAREQ_PORT_PROT) ||
- (abe_port[id].protocol.protocol_switch == PINGPONG_PORT_PROT) ||
+ if ((abe_port[id].protocol.protocol_switch == OMAP_AESS_PORT_DMAREQ) ||
+ (abe_port[id].protocol.protocol_switch == OMAP_AESS_PORT_PINGPONG) ||
(abe_port[id].status != OMAP_ABE_PORT_ACTIVITY_RUNNING))
return 0;
else
/**
* omap_aess_decide_main_port() - Decide main port selection for synchronization.
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
*
* Lock up on all ABE port in order to find out the correct port for the
* Audio Engine synchronization.
*/
-void omap_aess_decide_main_port(struct omap_aess *abe)
+void omap_aess_decide_main_port(struct omap_aess *aess)
{
u32 id, id_not_found;
/* if no port is currently activated, the default one is PDM_DL */
if (id_not_found)
- omap_aess_select_main_port(abe, OMAP_ABE_PDM_DL_PORT);
+ omap_aess_select_main_port(aess, OMAP_ABE_PDM_DL_PORT);
else
- omap_aess_select_main_port(abe, abe_port_priority[id]);
+ omap_aess_select_main_port(aess, abe_port_priority[id]);
}
/**
@@ -1468,34 +1441,34 @@ static void abe_format_switch(struct omap_aess_data_format *f, u32 *iter, u32 *m
}
switch (f->samp_format) {
- case MONO_MSB:
- case MONO_RSHIFTED_16:
- case STEREO_16_16:
+ case OMAP_AESS_FORMAT_MONO_MSB:
+ case OMAP_AESS_FORMAT_MONO_RSHIFTED_16:
+ case OMAP_AESS_FORMAT_STEREO_16_16:
*mulfac = 1;
break;
- case STEREO_MSB:
- case STEREO_RSHIFTED_16:
+ case OMAP_AESS_FORMAT_STEREO_MSB:
+ case OMAP_AESS_FORMAT_STEREO_RSHIFTED_16:
*mulfac = 2;
break;
- case THREE_MSB:
+ case OMAP_AESS_FORMAT_THREE_MSB:
*mulfac = 3;
break;
- case FOUR_MSB:
+ case OMAP_AESS_FORMAT_FOUR_MSB:
*mulfac = 4;
break;
- case FIVE_MSB:
+ case OMAP_AESS_FORMAT_FIVE_MSB:
*mulfac = 5;
break;
- case SIX_MSB:
+ case OMAP_AESS_FORMAT_SIX_MSB:
*mulfac = 6;
break;
- case SEVEN_MSB:
+ case OMAP_AESS_FORMAT_SEVEN_MSB:
*mulfac = 7;
break;
- case EIGHT_MSB:
+ case OMAP_AESS_FORMAT_EIGHT_MSB:
*mulfac = 8;
break;
- case NINE_MSB:
+ case OMAP_AESS_FORMAT_NINE_MSB:
*mulfac = 9;
break;
default:
@@ -1503,7 +1476,7 @@ static void abe_format_switch(struct omap_aess_data_format *f, u32 *iter, u32 *m
break;
}
*iter = (n_freq * (*mulfac));
- if (f->samp_format == MONO_16_16)
+ if (f->samp_format == OMAP_AESS_FORMAT_MONO_16_16)
*iter /= 2;
}
/**
* omap_aess_dma_port_iter_factor
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @f: port format
*
* returns the multiplier factor to apply during data move with DMEM
*/
-static u32 omap_aess_dma_port_iter_factor(struct omap_aess *abe, struct omap_aess_data_format *f)
+static u32 omap_aess_dma_port_iter_factor(struct omap_aess *aess, struct omap_aess_data_format *f)
{
u32 iter, mulfac;
@@ -1552,36 +1525,36 @@ static u32 omap_aess_dma_port_iter_factor(struct omap_aess *abe, struct omap_aes
/**
* omap_aess_mono_mixer
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: name of the mixer (MIXDL1, MIXDL2 or MIXAUDUL)
* @on_off: enable/disable flag
*
* This API Programs DL1Mixer or DL2Mixer to output mono data
* on both left and right data paths.
*/
-int omap_aess_mono_mixer(struct omap_aess *abe, u32 id, u32 on_off)
+int omap_aess_mono_mixer(struct omap_aess *aess, u32 id, u32 on_off)
{
struct omap_aess_task *task;
switch (id) {
case MIXDL1:
- task = &abe->fw_info->dl1_mono_mixer[on_off];
+ task = &aess->fw_info->dl1_mono_mixer[on_off];
break;
case MIXDL2:
- task = &abe->fw_info->dl2_mono_mixer[on_off];
+ task = &aess->fw_info->dl2_mono_mixer[on_off];
break;
case MIXAUDUL:
- task = &abe->fw_info->audul_mono_mixer[on_off];
+ task = &aess->fw_info->audul_mono_mixer[on_off];
break;
default:
return 0;
break;
}
- abe->MultiFrame[task->frame][task->slot] = task->task;
+ aess->MultiFrame[task->frame][task->slot] = task->task;
- omap_aess_mem_write(abe, abe->fw_info->map[OMAP_AESS_DMEM_MULTIFRAME_ID],
- (u32 *)abe->MultiFrame);
+ omap_aess_mem_write(aess, aess->fw_info->map[OMAP_AESS_DMEM_MULTIFRAME_ID],
+ (u32 *)aess->MultiFrame);
return 0;
}
/**
* omap_aess_check_activity - Check if some ABE activity.
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
*
* Check if any ABE ports are running.
* return 1: still activity on ABE
* return 0: no more activity on ABE. Event generator can be stopped
*
*/
-int omap_aess_check_activity(struct omap_aess *abe)
+int omap_aess_check_activity(struct omap_aess *aess)
{
int i, ret = 0;
/**
* abe_write_pdmdl_offset - write the desired offset on the DL1/DL2 paths
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @path: DL1 or DL2 port
* @offset_left: integer value that will be added on all PDM left samples
* @offset_right: integer value that will be added on all PDM right samples
* Set ABE internal DC offset cancellation parameter for McPDM IP. Value
* depends on TWL604x triming parameters.
*/
-void omap_aess_write_pdmdl_offset(struct omap_aess *abe, u32 path,
+void omap_aess_write_pdmdl_offset(struct omap_aess *aess, u32 path,
u32 offset_left, u32 offset_right)
{
u32 offset[2];
switch (path) {
case 1:
- omap_aess_mem_write(abe, abe->fw_info->map[OMAP_AESS_SMEM_DC_HS_ID], offset);
+ omap_aess_mem_write(aess, aess->fw_info->map[OMAP_AESS_SMEM_DC_HS_ID], offset);
break;
case 2:
- omap_aess_mem_write(abe, abe->fw_info->map[OMAP_AESS_SMEM_DC_HF_ID], offset);
+ omap_aess_mem_write(aess, aess->fw_info->map[OMAP_AESS_SMEM_DC_HF_ID], offset);
break;
default:
break;
/**
* oamp_abe_set_ping_pong_buffer
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @port: ABE port ID
* @n_bytes: Size of Ping/Pong buffer
*
* Updates the next ping-pong buffer with "size" bytes copied from the
* host processor. This API notifies the FW that the data transfer is done.
*/
-int omap_aess_set_ping_pong_buffer(struct omap_aess *abe, u32 port, u32 n_bytes)
+int omap_aess_set_ping_pong_buffer(struct omap_aess *aess, u32 port, u32 n_bytes)
{
u32 struct_offset, n_samples, datasize, base_and_size;
- struct ABE_SPingPongDescriptor desc_pp;
+ struct omap_aess_pingpong_desc desc_pp;
struct omap_aess_addr addr;
/* ping_pong is only supported on MM_DL */
@@ -1664,14 +1637,14 @@ int omap_aess_set_ping_pong_buffer(struct omap_aess *abe, u32 port, u32 n_bytes)
}
/* translates the number of bytes in samples */
/* data size in DMEM words */
- datasize = omap_aess_dma_port_iter_factor(abe, (struct omap_aess_data_format *)&((abe_port[port]).format));
+ datasize = omap_aess_dma_port_iter_factor(aess, (struct omap_aess_data_format *)&((abe_port[port]).format));
/* data size in bytes */
datasize = datasize << 2;
n_samples = n_bytes / datasize;
- memcpy(&addr, &abe->fw_info->map[OMAP_AESS_DMEM_PINGPONGDESC_ID],
+ memcpy(&addr, &aess->fw_info->map[OMAP_AESS_DMEM_PINGPONGDESC_ID],
sizeof(struct omap_aess_addr));
- addr.bytes = sizeof(struct ABE_SPingPongDescriptor);
- omap_aess_mem_read(abe, addr, (u32 *)&desc_pp);
+ addr.bytes = sizeof(struct omap_aess_pingpong_desc);
+ omap_aess_mem_read(aess, addr, (u32 *)&desc_pp);
/*
* read the port SIO descriptor and extract the current pointer
* address after reading the counter
@@ -1686,14 +1659,14 @@ int omap_aess_set_ping_pong_buffer(struct omap_aess *abe, u32 port, u32 n_bytes)
base_and_size = desc_pp.nextbuff1_BaseAddr;
}
- base_and_size = abe->pp_buf_addr[abe->pp_buf_id_next];
- abe->pp_buf_id_next = (abe->pp_buf_id_next + 1) & 0x03;
+ base_and_size = aess->pp_buf_addr[aess->pp_buf_id_next];
+ aess->pp_buf_id_next = (aess->pp_buf_id_next + 1) & 0x03;
base_and_size = (base_and_size & 0xFFFFL) + (n_samples << 16);
addr.offset += struct_offset;
addr.bytes = 4;
- omap_aess_mem_write(abe, addr, (u32 *)&base_and_size);
+ omap_aess_mem_write(aess, addr, (u32 *)&base_and_size);
return 0;
}
/**
* omap_aess_read_offset_from_ping_buffer
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: ABE port ID
* @n: returned address of the offset
* from the ping buffer start address (in samples)
* Computes the current firmware ping pong read pointer location,
* expressed in samples, as the offset from the start address of ping buffer.
*/
-int omap_aess_read_offset_from_ping_buffer(struct omap_aess *abe,
+int omap_aess_read_offset_from_ping_buffer(struct omap_aess *aess,
u32 id, u32 *n)
{
- struct ABE_SPingPongDescriptor desc_pp;
+ struct omap_aess_pingpong_desc desc_pp;
struct omap_aess_addr addr;
/* ping_pong is only supported on MM_DL */
return -AESS_EINVAL;
} else {
/* read the port SIO ping pong descriptor */
- memcpy(&addr, &abe->fw_info->map[OMAP_AESS_DMEM_PINGPONGDESC_ID],
+ memcpy(&addr, &aess->fw_info->map[OMAP_AESS_DMEM_PINGPONGDESC_ID],
sizeof(struct omap_aess_addr));
- addr.bytes = sizeof(struct ABE_SPingPongDescriptor);
- omap_aess_mem_read(abe, addr, (u32 *)&desc_pp);
+ addr.bytes = sizeof(struct omap_aess_pingpong_desc);
+ omap_aess_mem_read(aess, addr, (u32 *)&desc_pp);
/* extract the current ping pong buffer read pointer based on
the value of the counter */
if ((desc_pp.counter & 0x1) == 0) {
desc_pp.workbuff_Samples;
}
switch (abe_port[OMAP_ABE_MM_DL_PORT].format.samp_format) {
- case MONO_MSB:
- case MONO_RSHIFTED_16:
- case STEREO_16_16:
- *n += abe->pp_buf_id * abe->size_pingpong / 4;
+ case OMAP_AESS_FORMAT_MONO_MSB:
+ case OMAP_AESS_FORMAT_MONO_RSHIFTED_16:
+ case OMAP_AESS_FORMAT_STEREO_16_16:
+ *n += aess->pp_buf_id * aess->size_pingpong / 4;
break;
- case STEREO_MSB:
- case STEREO_RSHIFTED_16:
- *n += abe->pp_buf_id * abe->size_pingpong / 8;
+ case OMAP_AESS_FORMAT_STEREO_MSB:
+ case OMAP_AESS_FORMAT_STEREO_RSHIFTED_16:
+ *n += aess->pp_buf_id * aess->size_pingpong / 8;
break;
default:
aess_err("Bad data format for Ping-pong buffer");
}
EXPORT_SYMBOL(omap_aess_read_offset_from_ping_buffer);
-/**
- * omap_aess_irq_ping_pong
- * @abe: Pointer on aess handle
- *
- * Call the respective subroutine depending on the IRQ FIFO content:
- * APS interrupts : IRQ_FIFO[31:28] = IRQtag_APS,
- * IRQ_FIFO[27:16] = APS_IRQs, IRQ_FIFO[15:0] = loopCounter
- * SEQ interrupts : IRQ_FIFO[31:28] = IRQtag_COUNT,
- * IRQ_FIFO[27:16] = Count_IRQs, IRQ_FIFO[15:0] = loopCounter
- * Ping-Pong Interrupts : IRQ_FIFO[31:28] = IRQtag_PP,
- * IRQ_FIFO[27:16] = PP_MCU_IRQ, IRQ_FIFO[15:0] = loopCounter
- */
-void omap_aess_irq_ping_pong(struct omap_aess *abe)
-{
- /* first IRQ doesn't represent a buffer transference completion */
- if (abe->pp_first_irq)
- abe->pp_first_irq = 0;
- else
- abe->pp_buf_id = (abe->pp_buf_id + 1) & 0x03;
-
- omap_aess_call_subroutine(abe, abe->seq.irq_pingpong_player_id,
- NOPARAMETER, NOPARAMETER,
- NOPARAMETER, NOPARAMETER);
-}
-
/**
* omap_aess_read_next_ping_pong_buffer
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @port: ABE portID
* @p: Next buffer address (pointer)
* @n: Next buffer size (pointer)
*
* Tell the next base address of the next ping_pong Buffer and its size
*/
-int omap_aess_read_next_ping_pong_buffer(struct omap_aess *abe, u32 port,
+int omap_aess_read_next_ping_pong_buffer(struct omap_aess *aess, u32 port,
u32 *p, u32 *n)
{
- struct ABE_SPingPongDescriptor desc_pp;
+ struct omap_aess_pingpong_desc desc_pp;
struct omap_aess_addr addr;
/* ping_pong is only supported on MM_DL */
}
/* read the port SIO descriptor and extract the current pointer
address after reading the counter */
- memcpy(&addr, &abe->fw_info->map[OMAP_AESS_DMEM_PINGPONGDESC_ID],
+ memcpy(&addr, &aess->fw_info->map[OMAP_AESS_DMEM_PINGPONGDESC_ID],
sizeof(struct omap_aess_addr));
- addr.bytes = sizeof(struct ABE_SPingPongDescriptor);
- omap_aess_mem_read(abe, addr, (u32 *)&desc_pp);
+ addr.bytes = sizeof(struct omap_aess_pingpong_desc);
+ omap_aess_mem_read(aess, addr, (u32 *)&desc_pp);
if ((desc_pp.counter & 0x1) == 0)
*p = desc_pp.nextbuff0_BaseAddr;
*p = desc_pp.nextbuff1_BaseAddr;
/* translates the number of samples in bytes */
- *n = abe->size_pingpong;
+ *n = aess->size_pingpong;
return 0;
}
/**
* omap_aess_init_ping_pong_buffer
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: ABE port ID
* @size_bytes:size of the ping pong
* @n_buffers:number of buffers (2 = ping/pong)
*
* Computes the base address of the ping_pong buffers
*/
-static int omap_aess_init_ping_pong_buffer(struct omap_aess *abe,
+static int omap_aess_init_ping_pong_buffer(struct omap_aess *aess,
u32 id, u32 size_bytes,
u32 n_buffers, u32 *p)
{
return -AESS_EINVAL;
}
- memcpy(&addr, &abe->fw_info->map[OMAP_AESS_DMEM_PING_ID],
+ memcpy(&addr, &aess->fw_info->map[OMAP_AESS_DMEM_PING_ID],
sizeof(struct omap_aess_addr));
for (i = 0; i < n_buffers; i++) {
dmem_addr = addr.offset + (i * size_bytes);
/* base addresses of the ping pong buffers in U8 unit */
- abe->base_address_pingpong[i] = dmem_addr;
+ aess->base_address_pingpong[i] = dmem_addr;
}
for (i = 0; i < 4; i++)
- abe->pp_buf_addr[i] = addr.offset + (i * size_bytes);
- abe->pp_buf_id = 0;
- abe->pp_buf_id_next = 0;
- abe->pp_first_irq = 1;
+ aess->pp_buf_addr[i] = addr.offset + (i * size_bytes);
+ aess->pp_buf_id = 0;
+ aess->pp_buf_id_next = 0;
+ aess->pp_first_irq = 1;
/* global data */
- abe->size_pingpong = size_bytes;
+ aess->size_pingpong = size_bytes;
*p = (u32)addr.offset;
return 0;
}
/**
* omap_aess_connect_irq_ping_pong_port
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: port name
* @f: desired data format
* @subroutine_id: index of the call-back subroutine to call
* "abe_set_ping_pong_buffer" to notify the new amount of samples in the
* pong buffer.
*/
-int omap_aess_connect_irq_ping_pong_port(struct omap_aess *abe,
+int omap_aess_connect_irq_ping_pong_port(struct omap_aess *aess,
u32 id, struct omap_aess_data_format *f,
u32 subroutine_id, u32 size,
u32 *sink, u32 dsp_mcu_flag)
return -AESS_EINVAL;
}
- memcpy(&addr, &abe->fw_info->map[OMAP_AESS_DMEM_PING_ID],
+ memcpy(&addr, &aess->fw_info->map[OMAP_AESS_DMEM_PING_ID],
sizeof(struct omap_aess_addr));
- abe_port[id] = ((struct omap_aess_port *)abe->fw_info->port)[id];
+ abe_port[id] = ((struct omap_aess_port *)aess->fw_info->port)[id];
(abe_port[id]).format = (*f);
- (abe_port[id]).protocol.protocol_switch = PINGPONG_PORT_PROT;
+ (abe_port[id]).protocol.protocol_switch = OMAP_AESS_PORT_PINGPONG;
(abe_port[id]).protocol.p.prot_pingpong.buf_addr = addr.offset;
(abe_port[id]).protocol.p.prot_pingpong.buf_size = size;
(abe_port[id]).protocol.p.prot_pingpong.irq_data = (1);
- omap_aess_init_ping_pong_buffer(abe, OMAP_ABE_MM_DL_PORT, size, 2, sink);
+ omap_aess_init_ping_pong_buffer(aess, OMAP_ABE_MM_DL_PORT, size, 2, sink);
if (dsp_mcu_flag == PING_PONG_WITH_MCU_IRQ)
(abe_port[id]).protocol.p.prot_pingpong.irq_addr =
- ABE_MCU_IRQSTATUS_RAW;
+ OMAP_AESS_MCU_IRQSTATUS_RAW;
if (dsp_mcu_flag == PING_PONG_WITH_DSP_IRQ)
(abe_port[id]).protocol.p.prot_pingpong.irq_addr =
- ABE_DSP_IRQSTATUS_RAW;
+ OMAP_AESS_DSP_IRQSTATUS_RAW;
abe_port[id].status = OMAP_ABE_PORT_INITIALIZED;
/* load the ATC descriptors - disabled */
- omap_aess_init_atc(abe, id);
+ omap_aess_init_atc(aess, id);
/* load the micro-task parameters */
- omap_aess_init_io_tasks(abe, id, &((abe_port[id]).format),
+ omap_aess_init_io_tasks(aess, id, &((abe_port[id]).format),
&((abe_port[id]).protocol));
*sink = (abe_port[id]).protocol.p.prot_pingpong.buf_addr;
index 42d31f785698733c9a37b06ee0e097512846d6ea..c80d67d39dc2fcd396a22e22a5b2549e7a0c9cce 100644 (file)
#ifndef _ABE_PORT_H_
#define _ABE_PORT_H_
-struct ABE_STask {
- /* 0 ... Index of called function */
- u16 iF;
- /* 2 ... for INITPTR of A0 */
- u16 A0;
- /* 4 ... for INITPTR of A1 */
- u16 A1;
- /* 6 ... for INITPTR of A2 & A3 */
- u16 A2_3;
- /* 8 ... for INITPTR of A4 & A5 */
- u16 A4_5;
- /* 10 ... for INITREG of R0, R1, R2, R3 */
- u16 R;
- /* 12 */
- u16 misc0;
- /* 14 */
- u16 misc1;
-};
-
-#define ABE_TASK_ID(ID) (OMAP_ABE_D_TASKSLIST_ADDR + sizeof(struct ABE_STask)*(ID))
-
-struct ABE_SIODescriptor {
- /* 0 */
- u16 drift_asrc;
- /* 2 */
- u16 drift_io;
- /* 4 "Function index" of XLS sheet "Functions" */
- u8 io_type_idx;
- /* 5 1 = MONO or Stereo1616, 2= STEREO, ... */
- u8 samp_size;
- /* 6 drift "issues" for ASRC */
- s16 flow_counter;
- /* 8 address for IRQ or DMArequests */
- u16 hw_ctrl_addr;
- /* 10 DMA request bit-field or IRQ (DSP/MCU) */
- u8 atc_irq_data;
- /* 11 0 = Read, 3 = Write */
- u8 direction_rw;
- /* 12 */
- u8 repeat_last_samp;
- /* 13 12 at 48kHz, ... */
- u8 nsamp;
- /* 14 nsamp x samp_size */
- u8 x_io;
- /* 15 ON = 0x80, OFF = 0x00 */
- u8 on_off;
- /* 16 For Slimbus and TDM purpose */
- u16 split_addr1;
- /* 18 */
- u16 split_addr2;
- /* 20 */
- u16 split_addr3;
- /* 22 */
- u8 before_f_index;
- /* 23 */
- u8 after_f_index;
- /* 24 SM/CM INITPTR field */
- u16 smem_addr1;
- /* 26 in bytes */
- u16 atc_address1;
- /* 28 DMIC_ATC_PTR, MCPDM_UL_ATC_PTR, ... */
- u16 atc_pointer_saved1;
- /* 30 samp_size (except in TDM or Slimbus) */
- u8 data_size1;
- /* 31 "Function index" of XLS sheet "Functions" */
- u8 copy_f_index1;
- /* 32 For Slimbus and TDM purpose */
- u16 smem_addr2;
- /* 34 */
- u16 atc_address2;
- /* 36 */
- u16 atc_pointer_saved2;
- /* 38 */
- u8 data_size2;
- /* 39 */
- u8 copy_f_index2;
-};
-
-#ifdef __KERNEL__
int omap_aess_select_main_port(struct omap_aess *abe, u32 id);
void omap_aess_build_scheduler_table(struct omap_aess *abe);
int omap_aess_reset_port(struct omap_aess *abe, u32 id);
void omap_aess_irq_ping_pong(struct omap_aess *abe);
-#endif
#endif /* _ABE_PORT_H_ */
diff --git a/sound/soc/omap/aess/abe_seq.c b/sound/soc/omap/aess/abe_seq.c
+++ /dev/null
@@ -1,259 +0,0 @@
-/*
- *
- * This file is provided under a dual BSD/GPLv2 license. When using or
- * redistributing this file, you may do so under either license.
- *
- * GPL LICENSE SUMMARY
- *
- * Copyright(c) 2010-2012 Texas Instruments Incorporated,
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of version 2 of the GNU General Public License as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
- * The full GNU General Public License is included in this distribution
- * in the file called LICENSE.GPL.
- *
- * BSD LICENSE
- *
- * Copyright(c) 2010-2012 Texas Instruments Incorporated,
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-
-#include "abe.h"
-#include "abe_dbg.h"
-
-/* Maximun subroutines for ABE sequences */
-#define OMAP_ABE_MAX_SUB_ROUTINE 10
-
-struct omap_aess_subroutine {
- u32 sub_id;
- s32 param[4];
-};
-
-
-/* table of new subroutines called in the sequence */
-static abe_subroutine2 abe_all_subsubroutine[OMAP_ABE_MAX_SUB_ROUTINE];
-/* number of parameters per calls */
-static u32 abe_all_subsubroutine_nparam[OMAP_ABE_MAX_SUB_ROUTINE];
-/* paramters of the subroutine (if any) */
-static u32 abe_all_subroutine_params[OMAP_ABE_MAX_SUB_ROUTINE][4];
-
-/**
- * omap_aess_dummy_subroutine
- *
- */
-void omap_aess_dummy_subroutine(void)
-{
-}
-
-/**
- * omap_aess_add_subroutine
- * @abe: Pointer on aess handle
- * @id: ABE port id
- * @f: pointer to the subroutines
- * @nparam: number of parameters
- * @params: pointer to the parameters
- *
- * add one function pointer more and returns the index to it
- */
-int omap_aess_add_subroutine(struct omap_aess *abe, u32 *id, abe_subroutine2 f, u32 nparam, u32 *params)
-{
- u32 i, i_found;
-
- if ((abe->seq.write_pointer >= OMAP_ABE_MAX_SUB_ROUTINE) ||
- ((u32) f == 0)) {
- aess_err("Too many subroutine Plugged");
- return -AESS_EINVAL;
- } else {
- /* search if this subroutine address was not already
- * declared, then return the previous index
- */
- for (i_found = abe->seq.write_pointer, i = 0;
- i < abe->seq.write_pointer; i++) {
- if (f == abe_all_subsubroutine[i])
- i_found = i;
- }
-
- if (i_found == abe->seq.write_pointer) {
- /* Sub routine not listed - Add it */
- *id = abe->seq.write_pointer;
- abe_all_subsubroutine[i_found] = (f);
- for (i = 0; i < nparam; i++)
- abe_all_subroutine_params[i_found][i] = params[i];
- abe_all_subsubroutine_nparam[i_found] = nparam;
- abe->seq.write_pointer++;
- } else {
- /* Sub routine listed - Update parameters */
- for (i = 0; i < nparam; i++)
- abe_all_subroutine_params[i_found][i] = params[i];
- abe_all_subsubroutine_nparam[i_found] = nparam;
- *id = i_found;
- }
- }
- return 0;
-}
-
-/**
- * omap_aess_init_subroutine_table
- * @abe: Pointer on aess handle
- *
- * initializes the default table of pointers to subroutines
- *
- */
-void omap_aess_init_subroutine_table(struct omap_aess *abe)
-{
- u32 id;
-
- /* reset the table's pointers */
- abe->seq.write_pointer = 0;
-
- /* the first index is the NULL task */
- omap_aess_add_subroutine(abe, &id,
- (abe_subroutine2)omap_aess_dummy_subroutine,
- 0, (u32 *)0);
-
- omap_aess_add_subroutine(abe, &abe->seq.irq_pingpong_player_id,
- (abe_subroutine2)omap_aess_dummy_subroutine,
- 0, (u32 *)0);
-}
-
-/**
- * omap_aess_reset_all_sequence
- * @abe: Pointer on aess handle
- *
- * load default configuration for all sequences
- * kill any running activities
- */
-void omap_aess_reset_all_sequence(struct omap_aess *abe)
-{
- omap_aess_init_subroutine_table(abe);
-}
-
-/**
- * omap_aess_call_subroutine
- * @abe: Pointer on aess handle
- * @idx: index to the table of all registered Call-backs and subroutines
- * @p1: first parameter
- * @p2: second parameter
- * @p3: 3rd parameter
- * @p4: 4th parameter
- *
- * run and log a subroutine
- */
-void omap_aess_call_subroutine(struct omap_aess *abe, u32 idx, u32 p1, u32 p2, u32 p3, u32 p4)
-{
- abe_subroutine0 f0;
- abe_subroutine1 f1;
- abe_subroutine2 f2;
- abe_subroutine3 f3;
- abe_subroutine4 f4;
- u32 *params;
-
- if (idx > OMAP_ABE_MAX_SUB_ROUTINE)
- return;
-
- switch (idx) {
- default:
- switch (abe_all_subsubroutine_nparam[idx]) {
- case 0:
- f0 = (abe_subroutine0)abe_all_subsubroutine[idx];
- (*f0)();
- break;
- case 1:
- f1 = (abe_subroutine1)abe_all_subsubroutine[idx];
- params = abe_all_subroutine_params[idx];
- if (params != (u32 *)0)
- p1 = params[0];
- (*f1)(p1);
- break;
- case 2:
- f2 = abe_all_subsubroutine[idx];
- params = abe_all_subroutine_params[idx];
- if (params != (u32 *)0) {
- p1 = params[0];
- p2 = params[1];
- }
- (*f2)(p1, p2);
- break;
- case 3:
- f3 = (abe_subroutine3) abe_all_subsubroutine[idx];
- params = abe_all_subroutine_params[idx];
- if (params != (u32 *)0) {
- p1 = params[0];
- p2 = params[1];
- p3 = params[2];
- }
- (*f3)(p1, p2, p3);
- break;
- case 4:
- f4 = (abe_subroutine4) abe_all_subsubroutine[idx];
- params = abe_all_subroutine_params[idx];
- if (params != (u32 *)0) {
- p1 = params[0];
- p2 = params[1];
- p3 = params[2];
- p4 = params[3];
- }
- (*f4)(p1, p2, p3, p4);
- break;
- default:
- break;
- }
- }
-}
-
-/**
- * omap_aess_plug_subroutine
- * @abe: Pointer on aess handle
- * @id: returned sequence index after plugging a new subroutine
- * @f: subroutine address to be inserted
- * @n: number of parameters of this subroutine
- * @params: pointer on parameters
- *
- * register a list of subroutines for call-back purpose
- */
-int omap_aess_plug_subroutine(struct omap_aess *abe, u32 *id,
- abe_subroutine2 f, u32 n, u32 *params)
-{
- omap_aess_add_subroutine(abe, id, (abe_subroutine2)f, n,
- (u32 *)params);
- return 0;
-}
-EXPORT_SYMBOL(omap_aess_plug_subroutine);
diff --git a/sound/soc/omap/aess/abe_seq.h b/sound/soc/omap/aess/abe_seq.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- *
- * This file is provided under a dual BSD/GPLv2 license. When using or
- * redistributing this file, you may do so under either license.
- *
- * GPL LICENSE SUMMARY
- *
- * Copyright(c) 2010-2012 Texas Instruments Incorporated,
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of version 2 of the GNU General Public License as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
- * The full GNU General Public License is included in this distribution
- * in the file called LICENSE.GPL.
- *
- * BSD LICENSE
- *
- * Copyright(c) 2010-2012 Texas Instruments Incorporated,
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-
-#ifndef _ABE_SEQ_H_
-#define _ABE_SEQ_H_
-
-void omap_aess_reset_all_sequence(struct omap_aess *abe);
-void omap_aess_call_subroutine(struct omap_aess *abe, u32 idx, u32 p1, u32 p2, u32 p3, u32 p4);
-
-#endif /* _ABE_SEQ_H_ */
diff --git a/sound/soc/omap/aess/abe_typ.h b/sound/soc/omap/aess/abe_typ.h
+++ /dev/null
@@ -1,417 +0,0 @@
-/*
- *
- * This file is provided under a dual BSD/GPLv2 license. When using or
- * redistributing this file, you may do so under either license.
- *
- * GPL LICENSE SUMMARY
- *
- * Copyright(c) 2010-2012 Texas Instruments Incorporated,
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of version 2 of the GNU General Public License as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
- * The full GNU General Public License is included in this distribution
- * in the file called LICENSE.GPL.
- *
- * BSD LICENSE
- *
- * Copyright(c) 2010-2012 Texas Instruments Incorporated,
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-
-#include "abe_def.h"
-
-#ifndef _ABE_TYP_H_
-#define _ABE_TYP_H_
-
-/*
- * BASIC TYPES
- */
-#define MAX_UINT8 ((((1L << 7) - 1) << 1) + 1)
-#define MAX_UINT16 ((((1L << 15) - 1) << 1) + 1)
-#define MAX_UINT32 ((((1L << 31) - 1) << 1) + 1)
-#include <linux/types.h>
-
-/* subroutine types */
-typedef void (*abe_subroutine0) (void);
-typedef void (*abe_subroutine1) (u32);
-typedef void (*abe_subroutine2) (u32, u32);
-typedef void (*abe_subroutine3) (u32, u32, u32);
-typedef void (*abe_subroutine4) (u32, u32, u32, u32);
-/*
- * OPP TYPE
- *
- * 0: Ultra Lowest power consumption audio player
- * 1: OPP 25% (simple multimedia features)
- * 2: OPP 50% (multimedia and voice calls)
- * 3: OPP100% (multimedia complex use-cases)
- */
-#define ABE_OPP0 0
-#define ABE_OPP25 1
-#define ABE_OPP50 2
-#define ABE_OPP100 3
-
-/*
- * SAMPLES TYPE
- *
- * mono 16 bit sample LSB aligned, 16 MSB bits are unused;
- * mono right shifted to 16bits LSBs on a 32bits DMEM FIFO for McBSP
- * TX purpose;
- * mono sample MSB aligned (16/24/32bits);
- * two successive mono samples in one 32bits container;
- * Two L/R 16bits samples in a 32bits container;
- * Two channels defined with two MSB aligned samples;
- * Three channels defined with three MSB aligned samples (MIC);
- * Four channels defined with four MSB aligned samples (MIC);
- * . . .
- * Eight channels defined with eight MSB aligned samples (MIC);
- */
-#define MONO_MSB 1
-#define MONO_RSHIFTED_16 2
-#define STEREO_RSHIFTED_16 3
-#define STEREO_16_16 4
-#define STEREO_MSB 5
-#define THREE_MSB 6
-#define FOUR_MSB 7
-#define FIVE_MSB 8
-#define SIX_MSB 9
-#define SEVEN_MSB 10
-#define EIGHT_MSB 11
-#define NINE_MSB 12
-#define TEN_MSB 13
-#define MONO_16_16 14
-
-/*
- * PORT PROTOCOL TYPE - abe_port_protocol_switch_id
- */
-#define SLIMBUS_PORT_PROT 1
-#define SERIAL_PORT_PROT 2
-#define TDM_SERIAL_PORT_PROT 3
-#define DMIC_PORT_PROT 4
-#define MCPDMDL_PORT_PROT 5
-#define MCPDMUL_PORT_PROT 6
-#define PINGPONG_PORT_PROT 7
-#define DMAREQ_PORT_PROT 8
-
-/*
- * PORT IDs, this list is aligned with the FW data mapping
- */
-#define OMAP_ABE_DMIC_PORT 0
-#define OMAP_ABE_PDM_UL_PORT 1
-#define OMAP_ABE_BT_VX_UL_PORT 2
-#define OMAP_ABE_MM_UL_PORT 3
-#define OMAP_ABE_MM_UL2_PORT 4
-#define OMAP_ABE_VX_UL_PORT 5
-#define OMAP_ABE_MM_DL_PORT 6
-#define OMAP_ABE_VX_DL_PORT 7
-#define OMAP_ABE_TONES_DL_PORT 8
-#define OMAP_ABE_MCASP_DL_PORT 9
-#define OMAP_ABE_BT_VX_DL_PORT 10
-#define OMAP_ABE_PDM_DL_PORT 11
-#define OMAP_ABE_MM_EXT_OUT_PORT 12
-#define OMAP_ABE_MM_EXT_IN_PORT 13
-#define TDM_DL_PORT 14
-#define TDM_UL_PORT 15
-#define DEBUG_PORT 16
-#define LAST_PORT_ID 17
-
-#define FEAT_MIXDL1 14
-#define FEAT_MIXDL2 15
-#define FEAT_MIXAUDUL 16
-#define FEAT_GAINS 21
-#define FEAT_GAINS_DMIC1 22
-#define FEAT_GAINS_DMIC2 23
-#define FEAT_GAINS_DMIC3 24
-#define FEAT_GAINS_AMIC 25
-#define FEAT_GAIN_BTUL 29
-
-/* abe_mixer_id */
-#define MIXDL1 FEAT_MIXDL1
-#define MIXDL2 FEAT_MIXDL2
-#define MIXAUDUL FEAT_MIXAUDUL
-/*
- * GAIN IDs
- */
-#define GAINS_DMIC1 FEAT_GAINS_DMIC1
-#define GAINS_DMIC2 FEAT_GAINS_DMIC2
-#define GAINS_DMIC3 FEAT_GAINS_DMIC3
-#define GAINS_AMIC FEAT_GAINS_AMIC
-#define GAINS_BTUL FEAT_GAIN_BTUL
-
-/*
- * EVENT GENERATORS - abe_event_id
- */
-#define EVENT_TIMER 0
-#define EVENT_44100 1
-/*
- * SERIAL PORTS IDs - abe_mcbsp_id
- */
-#define MCBSP1_TX MCBSP1_DMA_TX
-#define MCBSP1_RX MCBSP1_DMA_RX
-#define MCBSP2_TX MCBSP2_DMA_TX
-#define MCBSP2_RX MCBSP2_DMA_RX
-#define MCBSP3_TX MCBSP3_DMA_TX
-#define MCBSP3_RX MCBSP3_DMA_RX
-
-/*
- * SERIAL PORTS IDs - abe_mcasp_id
- */
-#define MCASP1_TX McASP1_AXEVT
-#define MCASP1_RX McASP1_AREVT
-
-/*
- * DATA_FORMAT_T
- *
- * used in port declaration
- */
-struct omap_aess_data_format {
- /* Sampling frequency of the stream */
- u32 f;
- /* Sample format type */
- u32 samp_format;
-};
-
-/*
- * PORT_PROTOCOL_T
- *
- * port declaration
- */
-struct omap_aess_port_protocol {
- /* Direction=0 means input from AESS point of view */
- u32 direction;
- /* Protocol type (switch) during the data transfers */
- u32 protocol_switch;
- union {
- /* Slimbus peripheral connected to ATC */
- struct {
- /* Address of ATC Slimbus descriptor's index */
- u32 desc_addr1;
- /* DMEM address 1 in bytes */
- u32 buf_addr1;
- /* DMEM buffer size size in bytes */
- u32 buf_size;
- /* ITERation on each DMAreq signals */
- u32 iter;
- /* Second ATC index for SlimBus reception (or NULL) */
- u32 desc_addr2;
- /* DMEM address 2 in bytes */
- u32 buf_addr2;
- } prot_slimbus;
- /* McBSP/McASP peripheral connected to ATC */
- struct {
- u32 desc_addr;
- /* Address of ATC McBSP/McASP descriptor's in bytes */
- u32 buf_addr;
- /* DMEM address in bytes */
- u32 buf_size;
- /* ITERation on each DMAreq signals */
- u32 iter;
- } prot_serial;
- /* DMIC peripheral connected to ATC */
- struct {
- /* DMEM address in bytes */
- u32 buf_addr;
- /* DMEM buffer size in bytes */
- u32 buf_size;
- /* Number of activated DMIC */
- u32 nbchan;
- } prot_dmic;
- /* McPDMDL peripheral connected to ATC */
- struct {
- /* DMEM address in bytes */
- u32 buf_addr;
- /* DMEM size in bytes */
- u32 buf_size;
- /* Control allowed on McPDM DL */
- u32 control;
- } prot_mcpdmdl;
- /* McPDMUL peripheral connected to ATC */
- struct {
- /* DMEM address size in bytes */
- u32 buf_addr;
- /* DMEM buffer size size in bytes */
- u32 buf_size;
- } prot_mcpdmul;
- /* Ping-Pong interface to the Host using cache-flush */
- struct {
- /* Address of ATC descriptor's */
- u32 desc_addr;
- /* DMEM buffer base address in bytes */
- u32 buf_addr;
- /* DMEM size in bytes for each ping and pong buffers */
- u32 buf_size;
- /* IRQ address (either DMA (0) MCU (1) or DSP(2)) */
- u32 irq_addr;
- /* IRQ data content loaded in the AESS IRQ register */
- u32 irq_data;
- /* Call-back function upon IRQ reception */
- u32 callback;
- } prot_pingpong;
- /* DMAreq line to CBPr */
- struct {
- /* Address of ATC descriptor's */
- u32 desc_addr;
- /* DMEM buffer address in bytes */
- u32 buf_addr;
- /* DMEM buffer size size in bytes */
- u32 buf_size;
- /* ITERation on each DMAreq signals */
- u32 iter;
- /* DMAreq address */
- u32 dma_addr;
- /* DMA/AESS = 1 << #DMA */
- u32 dma_data;
- } prot_dmareq;
- /* Circular buffer - direct addressing to DMEM */
- struct {
- /* DMEM buffer base address in bytes */
- u32 buf_addr;
- /* DMEM buffer size in bytes */
- u32 buf_size;
- /* DMAreq address */
- u32 dma_addr;
- /* DMA/AESS = 1 << #DMA */
- u32 dma_data;
- } prot_circular_buffer;
- } p;
-};
-
-struct omap_aess_dma_offset {
- /* Offset to the first address of the */
- u32 data;
- /* number of iterations for the DMA data moves. */
- u32 iter;
-};
-
-/*
- * ABE_PORT_T status / format / sampling / protocol(call_back) /
- * features / gain / name ..
- *
- */
-
-struct omap_aess_task {
- u8 frame;
- u8 slot;
- u16 task;
-};
-
-struct omap_aess_init_task1 {
- u32 nb_task;
- struct omap_aess_task task[2];
-};
-
-struct omap_aess_init_task {
- u32 nb_task;
- struct omap_aess_task *task;
-};
-
-struct omap_aess_io_task {
- u32 nb_task;
- u32 smem;
- struct omap_aess_task *task;
-};
-
-struct omap_aess_io_task1 {
- u32 nb_task;
- u32 smem;
- struct omap_aess_task task[2];
-};
-
-struct omap_aess_port_type {
- struct omap_aess_init_task1 serial;
- struct omap_aess_init_task1 cbpr;
-};
-
-struct omap_aess_asrc_port {
- struct omap_aess_io_task1 task;
- struct omap_aess_port_type asrc;
-};
-
-struct omap_aess_port {
- /* running / idled */
- u16 status;
- /* Sample format type */
- struct omap_aess_data_format format;
- /* API : for ASRC */
- s32 drift;
- /* optionnal call-back index for errors and ack */
- u16 callback;
- /* IO tasks buffers */
- u16 smem_buffer1;
- u16 smem_buffer2;
- struct omap_aess_port_protocol protocol;
- /* pointer and iteration counter of the xDMA */
- struct omap_aess_dma_offset dma;
- struct omap_aess_init_task1 task;
- struct omap_aess_asrc_port tsk_freq[4];
-};
-
-/*
- * ROUTER_T
- *
- * table of indexes in unsigned bytes
- */
-typedef u16 abe_router_t;
-/*
- * DRIFT_T abe_drift_t = s32
- *
- * ASRC drift parameter in [ppm] value
- */
-/*
- * -------------------- INTERNAL DATA TYPES ---------------------
- */
-/*
- * ABE_IRQ_DATA_T
- *
- * IRQ FIFO content declaration
- * APS interrupts : IRQ_FIFO[31:28] = IRQtag_APS,
- * IRQ_FIFO[27:16] = APS_IRQs, IRQ_FIFO[15:0] = loopCounter
- * SEQ interrupts : IRQ_FIFO[31:28] IRQtag_COUNT,
- * IRQ_FIFO[27:16] = Count_IRQs, IRQ_FIFO[15:0] = loopCounter
- * Ping-Pong Interrupts : IRQ_FIFO[31:28] = IRQtag_PP,
- * IRQ_FIFO[27:16] = PP_MCU_IRQ, IRQ_FIFO[15:0] = loopCounter
- */
-struct omap_aess_irq_data {
- unsigned int counter:16;
- unsigned int data:12;
- unsigned int tag:4;
-};
-
-#endif /* ifndef _ABE_TYP_H_ */
diff --git a/sound/soc/omap/aess/aess-fw.h b/sound/soc/omap/aess/aess-fw.h
--- /dev/null
@@ -0,0 +1,716 @@
+/*
+ *
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2010-2013 Texas Instruments Incorporated,
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2010-2013 Texas Instruments Incorporated,
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef _AESS_FW_H_
+#define _AESS_FW_H_
+
+/*
+ * HARDWARE AND PERIPHERAL DEFINITIONS
+ */
+/* holds the DMA req lines to the sDMA */
+#define ABE_DMASTATUS_RAW 0x84
+
+/* Direction=0 means input from ABE point of view */
+#define ABE_ATC_DIRECTION_IN 0
+/* Direction=1 means output from ABE point of view */
+#define ABE_ATC_DIRECTION_OUT 1
+
+/*
+ * DMA requests
+ */
+/*Internal connection doesn't connect at ABE boundary */
+#define External_DMA_0 0
+/*Transmit request digital microphone */
+#define DMIC_DMA_REQ 1
+/*Multichannel PDM downlink */
+#define McPDM_DMA_DL 2
+/*Multichannel PDM uplink */
+#define McPDM_DMA_UP 3
+/*MCBSP module 1 - transmit request */
+#define MCBSP1_DMA_TX 4
+/*MCBSP module 1 - receive request */
+#define MCBSP1_DMA_RX 5
+/*MCBSP module 2 - transmit request */
+#define MCBSP2_DMA_TX 6
+/*MCBSP module 2 - receive request */
+#define MCBSP2_DMA_RX 7
+/*MCBSP module 3 - transmit request */
+#define MCBSP3_DMA_TX 8
+/*MCBSP module 3 - receive request */
+#define MCBSP3_DMA_RX 9
+/*McASP - Data transmit DMA request line */
+#define McASP1_AXEVT 26
+/*McASP - Data receive DMA request line */
+#define McASP1_AREVT 29
+/*DUMMY FIFO @@@ */
+#define _DUMMY_FIFO_ 30
+/*DMA of the Circular buffer peripheral 0 */
+#define CBPr_DMA_RTX0 32
+/*DMA of the Circular buffer peripheral 1 */
+#define CBPr_DMA_RTX1 33
+/*DMA of the Circular buffer peripheral 2 */
+#define CBPr_DMA_RTX2 34
+/*DMA of the Circular buffer peripheral 3 */
+#define CBPr_DMA_RTX3 35
+/*DMA of the Circular buffer peripheral 4 */
+#define CBPr_DMA_RTX4 36
+/*DMA of the Circular buffer peripheral 5 */
+#define CBPr_DMA_RTX5 37
+/*DMA of the Circular buffer peripheral 6 */
+#define CBPr_DMA_RTX6 38
+/*DMA of the Circular buffer peripheral 7 */
+#define CBPr_DMA_RTX7 39
+
+/*
+ * HARDWARE AND PERIPHERAL DEFINITIONS
+ */
+/* MM_DL */
+#define ABE_CBPR0_IDX 0
+/* VX_DL */
+#define ABE_CBPR1_IDX 1
+/* VX_UL */
+#define ABE_CBPR2_IDX 2
+/* MM_UL */
+#define ABE_CBPR3_IDX 3
+/* MM_UL2 */
+#define ABE_CBPR4_IDX 4
+/* TONES */
+#define ABE_CBPR5_IDX 5
+/* TDB */
+#define ABE_CBPR6_IDX 6
+/* DEBUG/CTL */
+#define ABE_CBPR7_IDX 7
+#define CIRCULAR_BUFFER_PERIPHERAL_R__0 (0x100 + ABE_CBPR0_IDX*4)
+#define CIRCULAR_BUFFER_PERIPHERAL_R__1 (0x100 + ABE_CBPR1_IDX*4)
+#define CIRCULAR_BUFFER_PERIPHERAL_R__2 (0x100 + ABE_CBPR2_IDX*4)
+#define CIRCULAR_BUFFER_PERIPHERAL_R__3 (0x100 + ABE_CBPR3_IDX*4)
+#define CIRCULAR_BUFFER_PERIPHERAL_R__4 (0x100 + ABE_CBPR4_IDX*4)
+#define CIRCULAR_BUFFER_PERIPHERAL_R__5 (0x100 + ABE_CBPR5_IDX*4)
+#define CIRCULAR_BUFFER_PERIPHERAL_R__6 (0x100 + ABE_CBPR6_IDX*4)
+#define CIRCULAR_BUFFER_PERIPHERAL_R__7 (0x100 + ABE_CBPR7_IDX*4)
+#define PING_PONG_WITH_MCU_IRQ 1
+#define PING_PONG_WITH_DSP_IRQ 2
+/*
+ * INTERNAL DEFINITIONS
+ */
+/* 24 Q6.26 coefficients */
+#define NBEQ1 25
+/* 2x12 Q6.26 coefficients */
+#define NBEQ2 13
+
+/* sink / input port from Host point of view (or AESS for DMIC/McPDM/.. */
+#define SNK_P ABE_ATC_DIRECTION_IN
+/* source / ouptut port */
+#define SRC_P ABE_ATC_DIRECTION_OUT
+
+/* number of task/slot depending on the OPP value */
+#define DOPPMODE32_OPP100 (0x00000010)
+#define DOPPMODE32_OPP50 (0x0000000C)
+#define DOPPMODE32_OPP25 (0x0000004)
+
+/*
+ * ABE CONST AREA FOR PERIPHERAL TUNING
+ */
+/* port idled IDLE_P */
+#define OMAP_ABE_PORT_ACTIVITY_IDLE 1
+/* port initialized, ready to be activated */
+#define OMAP_ABE_PORT_INITIALIZED 3
+/* port activated RUN_P */
+#define OMAP_ABE_PORT_ACTIVITY_RUNNING 2
+
+#define NOPARAMETER 0
+/* number of ATC access upon AMIC DMArequests, all the FIFOs are enabled */
+#define MCPDM_UL_ITER 4
+/* All the McPDM FIFOs are enabled simultaneously */
+#define MCPDM_DL_ITER 24
+/* All the DMIC FIFOs are enabled simultaneously */
+#define DMIC_ITER 12
+/* TBD later if needed */
+#define MAX_PINGPONG_BUFFERS 2
+
+/* OLD WAY */
+#define c_feat_init_eq 1
+#define c_feat_read_eq1 2
+#define c_write_eq1 3
+#define c_feat_read_eq2 4
+#define c_write_eq2 5
+#define c_feat_read_eq3 6
+#define c_write_eq3 7
+/* max number of gain to be controlled by HAL */
+#define MAX_NBGAIN_CMEM 36
+
+
+#define OMAP_ABE_DMEM 0
+#define OMAP_ABE_CMEM 1
+#define OMAP_ABE_SMEM 2
+#define OMAP_ABE_PMEM 3
+#define OMAP_ABE_AESS 4
+
+struct omap_aess_addr {
+ int bank;
+ unsigned int offset;
+ unsigned int bytes;
+};
+
+/* ABE memory IDs */
+#define OMAP_AESS_DMEM_MULTIFRAME_ID 0
+#define OMAP_AESS_DMEM_DMIC_UL_FIFO_ID 1
+#define OMAP_AESS_DMEM_MCPDM_UL_FIFO_ID 2
+#define OMAP_AESS_DMEM_BT_UL_FIFO_ID 3
+#define OMAP_AESS_DMEM_MM_UL_FIFO_ID 4
+#define OMAP_AESS_DMEM_MM_UL2_FIFO_ID 5
+#define OMAP_AESS_DMEM_VX_UL_FIFO_ID 6
+#define OMAP_AESS_DMEM_MM_DL_FIFO_ID 7
+#define OMAP_AESS_DMEM_VX_DL_FIFO_ID 8
+#define OMAP_AESS_DMEM_TONES_DL_FIFO_ID 9
+#define OMAP_AESS_DMEM_MCASP_DL_FIFO_ID 10
+#define OMAP_AESS_DMEM_BT_DL_FIFO_ID 11
+#define OMAP_AESS_DMEM_MCPDM_DL_FIFO_ID 12
+#define OMAP_AESS_DMEM_MM_EXT_OUT_FIFO_ID 13
+#define OMAP_AESS_DMEM_MM_EXT_IN_FIFO_ID 14
+#define OMAP_AESS_SMEM_DMIC0_96_48_DATA_ID 15
+#define OMAP_AESS_SMEM_DMIC1_96_48_DATA_ID 16
+#define OMAP_AESS_SMEM_DMIC2_96_48_DATA_ID 17
+#define OMAP_AESS_SMEM_AMIC_96_48_DATA_ID 18
+#define OMAP_AESS_SMEM_BT_UL_ID 19
+#define OMAP_AESS_SMEM_BT_UL_8_48_HP_DATA_ID 20
+#define OMAP_AESS_SMEM_BT_UL_8_48_LP_DATA_ID 21
+#define OMAP_AESS_SMEM_BT_UL_16_48_HP_DATA_ID 22
+#define OMAP_AESS_SMEM_BT_UL_16_48_LP_DATA_ID 23
+#define OMAP_AESS_SMEM_MM_UL2_ID 24
+#define OMAP_AESS_SMEM_MM_UL_ID 25
+#define OMAP_AESS_SMEM_VX_UL_ID 26
+#define OMAP_AESS_SMEM_VX_UL_48_8_HP_DATA_ID 27
+#define OMAP_AESS_SMEM_VX_UL_48_8_LP_DATA_ID 28
+#define OMAP_AESS_SMEM_VX_UL_48_16_HP_DATA_ID 29
+#define OMAP_AESS_SMEM_VX_UL_48_16_LP_DATA_ID 30
+#define OMAP_AESS_SMEM_MM_DL_ID 31
+#define OMAP_AESS_SMEM_MM_DL_44P1_ID 32
+#define OMAP_AESS_SMEM_MM_DL_44P1_XK_ID 33
+#define OMAP_AESS_SMEM_VX_DL_ID 34
+#define OMAP_AESS_SMEM_VX_DL_8_48_HP_DATA_ID 35
+#define OMAP_AESS_SMEM_VX_DL_8_48_LP_DATA_ID 36
+#define OMAP_AESS_SMEM_VX_DL_8_48_OSR_LP_DATA_ID 37
+#define OMAP_AESS_SMEM_VX_DL_16_48_HP_DATA_ID 38
+#define OMAP_AESS_SMEM_VX_DL_16_48_LP_DATA_ID 39
+#define OMAP_AESS_SMEM_TONES_ID 40
+#define OMAP_AESS_SMEM_TONES_44P1_ID 41
+#define OMAP_AESS_SMEM_TONES_44P1_XK_ID 42
+#define OMAP_AESS_SMEM_MCASP1_ID 43
+#define OMAP_AESS_SMEM_BT_DL_ID 44
+#define OMAP_AESS_SMEM_BT_DL_8_48_OSR_LP_DATA_ID 45
+#define OMAP_AESS_SMEM_BT_DL_48_8_HP_DATA_ID 46
+#define OMAP_AESS_SMEM_BT_DL_48_8_LP_DATA_ID 47
+#define OMAP_AESS_SMEM_BT_DL_48_16_HP_DATA_ID 48
+#define OMAP_AESS_SMEM_BT_DL_48_16_LP_DATA_ID 49
+#define OMAP_AESS_SMEM_DL2_M_LR_EQ_DATA_ID 50
+#define OMAP_AESS_SMEM_DL1_M_EQ_DATA_ID 51
+#define OMAP_AESS_SMEM_EARP_48_96_LP_DATA_ID 52
+#define OMAP_AESS_SMEM_IHF_48_96_LP_DATA_ID 53
+#define OMAP_AESS_SMEM_DC_HS_ID 54
+#define OMAP_AESS_SMEM_DC_HF_ID 55
+#define OMAP_AESS_SMEM_SDT_F_DATA_ID 56
+#define OMAP_AESS_SMEM_GTARGET1_ID 57
+#define OMAP_AESS_SMEM_GCURRENT_ID 58
+#define OMAP_AESS_CMEM_DL1_COEFS_ID 59
+#define OMAP_AESS_CMEM_DL2_L_COEFS_ID 60
+#define OMAP_AESS_CMEM_DL2_R_COEFS_ID 61
+#define OMAP_AESS_CMEM_SDT_COEFS_ID 62
+#define OMAP_AESS_CMEM_96_48_AMIC_COEFS_ID 63
+#define OMAP_AESS_CMEM_96_48_DMIC_COEFS_ID 64
+#define OMAP_AESS_CMEM_1_ALPHA_ID 65
+#define OMAP_AESS_CMEM_ALPHA_ID 66
+#define OMAP_AESS_DMEM_SLOT23_CTRL_ID 67
+#define OMAP_AESS_DMEM_AUPLINKROUTING_ID 68
+#define OMAP_AESS_DMEM_MAXTASKBYTESINSLOT_ID 69
+#define OMAP_AESS_DMEM_PINGPONGDESC_ID 70
+#define OMAP_AESS_DMEM_IODESCR_ID 71
+#define OMAP_AESS_DMEM_MCUIRQFIFO_ID 72
+#define OMAP_AESS_DMEM_PING_ID 73
+#define OMAP_AESS_DMEM_DEBUG_FIFO_ID 74
+#define OMAP_AESS_DMEM_DEBUG_FIFO_HAL_ID 75
+#define OMAP_AESS_DMEM_DEBUG_HAL_TASK_ID 76
+#define OMAP_AESS_DMEM_LOOPCOUNTER_ID 77
+#define OMAP_AESS_DMEM_FWMEMINITDESCR_ID 78
+
+/* ABE copy function IDs */
+#define OMAP_AESS_COPY_FCT_NULL_ID 0
+#define OMAP_AESS_COPY_FCT_S2D_STEREO_16_16_ID 1
+#define OMAP_AESS_COPY_FCT_S2D_MONO_MSB_ID 2
+#define OMAP_AESS_COPY_FCT_S2D_STEREO_MSB_ID 3
+#define OMAP_AESS_COPY_FCT_S2D_STEREO_RSHIFTED_16_ID 4
+#define OMAP_AESS_COPY_FCT_S2D_MONO_RSHIFTED_16_ID 5
+#define OMAP_AESS_COPY_FCT_D2S_STEREO_16_16_ID 6
+#define OMAP_AESS_COPY_FCT_D2S_MONO_MSB_ID 7
+#define OMAP_AESS_COPY_FCT_D2S_MONO_RSHIFTED_16_ID 8
+#define OMAP_AESS_COPY_FCT_D2S_STEREO_RSHIFTED_16_ID 9
+#define OMAP_AESS_COPY_FCT_D2S_STEREO_MSB_ID 10
+#define OMAP_AESS_COPY_FCT_DMIC_ID 11
+#define OMAP_AESS_COPY_FCT_MCPDM_DL_ID 12
+#define OMAP_AESS_COPY_FCT_MM_UL_ID 13
+#define OMAP_AESS_COPY_FCT_SPLIT_SMEM_ID 14
+#define OMAP_AESS_COPY_FCT_MERGE_SMEM_ID 15
+#define OMAP_AESS_COPY_FCT_SPLIT_TDM_ID 16
+#define OMAP_AESS_COPY_FCT_MERGE_TDM_ID 17
+#define OMAP_AESS_COPY_FCT_ROUTE_MM_UL_ID 18
+#define OMAP_AESS_COPY_FCT_IO_IP_ID 19
+#define OMAP_AESS_COPY_FCT_COPY_UNDERFLOW_ID 20
+#define OMAP_AESS_COPY_FCT_COPY_MCPDM_DL_HF_PDL1_ID 21
+#define OMAP_AESS_COPY_FCT_COPY_MCPDM_DL_HF_PDL2_ID 22
+#define OMAP_AESS_COPY_FCT_S2D_MONO_16_16_ID 23
+#define OMAP_AESS_COPY_FCT_D2S_MONO_16_16_ID 24
+#define OMAP_AESS_COPY_FCT_DMIC_NO_PRESCALE_ID 25
+
+/* ABE buffer IDs */
+#define OMAP_AESS_BUFFER_ZERO_ID 0
+#define OMAP_AESS_BUFFER_DMIC1_L_ID 1
+#define OMAP_AESS_BUFFER_DMIC1_R_ID 2
+#define OMAP_AESS_BUFFER_DMIC2_L_ID 3
+#define OMAP_AESS_BUFFER_DMIC2_R_ID 4
+#define OMAP_AESS_BUFFER_DMIC3_L_ID 5
+#define OMAP_AESS_BUFFER_DMIC3_R_ID 6
+#define OMAP_AESS_BUFFER_BT_UL_L_ID 7
+#define OMAP_AESS_BUFFER_BT_UL_R_ID 8
+#define OMAP_AESS_BUFFER_MM_EXT_IN_L_ID 9
+#define OMAP_AESS_BUFFER_MM_EXT_IN_R_ID 10
+#define OMAP_AESS_BUFFER_AMIC_L_ID 11
+#define OMAP_AESS_BUFFER_AMIC_R_ID 12
+#define OMAP_AESS_BUFFER_VX_REC_L_ID 13
+#define OMAP_AESS_BUFFER_VX_REC_R_ID 14
+#define OMAP_AESS_BUFFER_MCU_IRQ_FIFO_PTR_ID 15
+#define OMAP_AESS_BUFFER_DMIC_ATC_PTR_ID 16
+#define OMAP_AESS_BUFFER_MM_EXT_IN_ID 17
+
+struct omap_aess_io_desc {
+ /* 0 */
+ u16 drift_asrc;
+ /* 2 */
+ u16 drift_io;
+ /* 4 "Function index" of XLS sheet "Functions" */
+ u8 io_type_idx;
+ /* 5 1 = MONO or Stereo1616, 2= STEREO, ... */
+ u8 samp_size;
+ /* 6 drift "issues" for ASRC */
+ s16 flow_counter;
+ /* 8 address for IRQ or DMArequests */
+ u16 hw_ctrl_addr;
+ /* 10 DMA request bit-field or IRQ (DSP/MCU) */
+ u8 atc_irq_data;
+ /* 11 0 = Read, 3 = Write */
+ u8 direction_rw;
+ /* 12 */
+ u8 repeat_last_samp;
+ /* 13 12 at 48kHz, ... */
+ u8 nsamp;
+ /* 14 nsamp x samp_size */
+ u8 x_io;
+ /* 15 ON = 0x80, OFF = 0x00 */
+ u8 on_off;
+ /* 16 For TDM purpose */
+ u16 split_addr1;
+ /* 18 */
+ u16 split_addr2;
+ /* 20 */
+ u16 split_addr3;
+ /* 22 */
+ u8 before_f_index;
+ /* 23 */
+ u8 after_f_index;
+ /* 24 SM/CM INITPTR field */
+ u16 smem_addr1;
+ /* 26 in bytes */
+ u16 atc_address1;
+ /* 28 DMIC_ATC_PTR, MCPDM_UL_ATC_PTR, ... */
+ u16 atc_pointer_saved1;
+ /* 30 samp_size (except in TDM) */
+ u8 data_size1;
+ /* 31 "Function index" of XLS sheet "Functions" */
+ u8 copy_f_index1;
+ /* 32 For TDM purpose */
+ u16 smem_addr2;
+ /* 34 */
+ u16 atc_address2;
+ /* 36 */
+ u16 atc_pointer_saved2;
+ /* 38 */
+ u8 data_size2;
+ /* 39 */
+ u8 copy_f_index2;
+};
+
+/*
+ * OPP TYPE
+ *
+ * 0: Ultra Lowest power consumption audio player
+ * 1: OPP 25% (simple multimedia features)
+ * 2: OPP 50% (multimedia and voice calls)
+ * 3: OPP100% (multimedia complex use-cases)
+ */
+#define ABE_OPP0 0
+#define ABE_OPP25 1
+#define ABE_OPP50 2
+#define ABE_OPP100 3
+
+/*
+ * SAMPLES TYPE
+ *
+ * mono 16 bit sample LSB aligned, 16 MSB bits are unused;
+ * mono right shifted to 16bits LSBs on a 32bits DMEM FIFO for McBSP
+ * TX purpose;
+ * mono sample MSB aligned (16/24/32bits);
+ * two successive mono samples in one 32bits container;
+ * Two L/R 16bits samples in a 32bits container;
+ * Two channels defined with two MSB aligned samples;
+ * Three channels defined with three MSB aligned samples (MIC);
+ * Four channels defined with four MSB aligned samples (MIC);
+ * . . .
+ * Eight channels defined with eight MSB aligned samples (MIC);
+ */
+#define OMAP_AESS_FORMAT_MONO_MSB 1
+#define OMAP_AESS_FORMAT_MONO_RSHIFTED_16 2
+#define OMAP_AESS_FORMAT_STEREO_RSHIFTED_16 3
+#define OMAP_AESS_FORMAT_STEREO_16_16 4
+#define OMAP_AESS_FORMAT_STEREO_MSB 5
+#define OMAP_AESS_FORMAT_THREE_MSB 6
+#define OMAP_AESS_FORMAT_FOUR_MSB 7
+#define OMAP_AESS_FORMAT_FIVE_MSB 8
+#define OMAP_AESS_FORMAT_SIX_MSB 9
+#define OMAP_AESS_FORMAT_SEVEN_MSB 10
+#define OMAP_AESS_FORMAT_EIGHT_MSB 11
+#define OMAP_AESS_FORMAT_NINE_MSB 12
+#define OMAP_AESS_FORMAT_TEN_MSB 13
+#define OMAP_AESS_FORMAT_MONO_16_16 14
+
+/*
+ * PORT PROTOCOL TYPE - abe_port_protocol_switch_id
+ */
+#define OMAP_AESS_PORT_SERIAL 2
+#define OMAP_AESS_PORT_TDM 3
+#define OMAP_AESS_PORT_DMIC 4
+#define OMAP_AESS_PORT_MCPDMDL 5
+#define OMAP_AESS_PORT_MCPDMUL 6
+#define OMAP_AESS_PORT_PINGPONG 7
+#define OMAP_AESS_PORT_DMAREQ 8
+
+/*
+ * PORT IDs, this list is aligned with the FW data mapping
+ */
+#define OMAP_ABE_DMIC_PORT 0
+#define OMAP_ABE_PDM_UL_PORT 1
+#define OMAP_ABE_BT_VX_UL_PORT 2
+#define OMAP_ABE_MM_UL_PORT 3
+#define OMAP_ABE_MM_UL2_PORT 4
+#define OMAP_ABE_VX_UL_PORT 5
+#define OMAP_ABE_MM_DL_PORT 6
+#define OMAP_ABE_VX_DL_PORT 7
+#define OMAP_ABE_TONES_DL_PORT 8
+#define OMAP_ABE_MCASP_DL_PORT 9
+#define OMAP_ABE_BT_VX_DL_PORT 10
+#define OMAP_ABE_PDM_DL_PORT 11
+#define OMAP_ABE_MM_EXT_OUT_PORT 12
+#define OMAP_ABE_MM_EXT_IN_PORT 13
+#define TDM_DL_PORT 14
+#define TDM_UL_PORT 15
+#define DEBUG_PORT 16
+#define LAST_PORT_ID 17
+
+#define FEAT_MIXDL1 14
+#define FEAT_MIXDL2 15
+#define FEAT_MIXAUDUL 16
+#define FEAT_GAINS 21
+#define FEAT_GAINS_DMIC1 22
+#define FEAT_GAINS_DMIC2 23
+#define FEAT_GAINS_DMIC3 24
+#define FEAT_GAINS_AMIC 25
+#define FEAT_GAIN_BTUL 29
+
+/* abe_mixer_id */
+#define MIXDL1 FEAT_MIXDL1
+#define MIXDL2 FEAT_MIXDL2
+#define MIXAUDUL FEAT_MIXAUDUL
+/*
+ * GAIN IDs
+ */
+#define GAINS_DMIC1 FEAT_GAINS_DMIC1
+#define GAINS_DMIC2 FEAT_GAINS_DMIC2
+#define GAINS_DMIC3 FEAT_GAINS_DMIC3
+#define GAINS_AMIC FEAT_GAINS_AMIC
+#define GAINS_BTUL FEAT_GAIN_BTUL
+
+/*
+ * EVENT GENERATORS - abe_event_id
+ */
+#define EVENT_TIMER 0
+#define EVENT_44100 1
+/*
+ * SERIAL PORTS IDs - abe_mcbsp_id
+ */
+#define MCBSP1_TX MCBSP1_DMA_TX
+#define MCBSP1_RX MCBSP1_DMA_RX
+#define MCBSP2_TX MCBSP2_DMA_TX
+#define MCBSP2_RX MCBSP2_DMA_RX
+#define MCBSP3_TX MCBSP3_DMA_TX
+#define MCBSP3_RX MCBSP3_DMA_RX
+
+/*
+ * SERIAL PORTS IDs - abe_mcasp_id
+ */
+#define MCASP1_TX McASP1_AXEVT
+#define MCASP1_RX McASP1_AREVT
+
+/*
+ * DATA_FORMAT_T
+ *
+ * used in port declaration
+ */
+struct omap_aess_data_format {
+ /* Sampling frequency of the stream */
+ u32 f;
+ /* Sample format type */
+ u32 samp_format;
+};
+
+/*
+ * PORT_PROTOCOL_T
+ *
+ * port declaration
+ */
+struct omap_aess_port_protocol {
+ /* Direction=0 means input from AESS point of view */
+ u32 direction;
+ /* Protocol type (switch) during the data transfers */
+ u32 protocol_switch;
+ union {
+ /* McBSP/McASP peripheral connected to ATC */
+ struct {
+ u32 desc_addr;
+ /* Address of ATC McBSP/McASP descriptor's in bytes */
+ u32 buf_addr;
+ /* DMEM address in bytes */
+ u32 buf_size;
+ /* ITERation on each DMAreq signals */
+ u32 iter;
+ } prot_serial;
+ /* DMIC peripheral connected to ATC */
+ struct {
+ /* DMEM address in bytes */
+ u32 buf_addr;
+ /* DMEM buffer size in bytes */
+ u32 buf_size;
+ /* Number of activated DMIC */
+ u32 nbchan;
+ } prot_dmic;
+ /* McPDMDL peripheral connected to ATC */
+ struct {
+ /* DMEM address in bytes */
+ u32 buf_addr;
+ /* DMEM size in bytes */
+ u32 buf_size;
+ /* Control allowed on McPDM DL */
+ u32 control;
+ } prot_mcpdmdl;
+ /* McPDMUL peripheral connected to ATC */
+ struct {
+ /* DMEM address size in bytes */
+ u32 buf_addr;
+ /* DMEM buffer size size in bytes */
+ u32 buf_size;
+ } prot_mcpdmul;
+ /* Ping-Pong interface to the Host using cache-flush */
+ struct {
+ /* Address of ATC descriptor's */
+ u32 desc_addr;
+ /* DMEM buffer base address in bytes */
+ u32 buf_addr;
+ /* DMEM size in bytes for each ping and pong buffers */
+ u32 buf_size;
+ /* IRQ address (either DMA (0) MCU (1) or DSP(2)) */
+ u32 irq_addr;
+ /* IRQ data content loaded in the AESS IRQ register */
+ u32 irq_data;
+ /* Call-back function upon IRQ reception */
+ u32 callback;
+ } prot_pingpong;
+ /* DMAreq line to CBPr */
+ struct {
+ /* Address of ATC descriptor's */
+ u32 desc_addr;
+ /* DMEM buffer address in bytes */
+ u32 buf_addr;
+ /* DMEM buffer size size in bytes */
+ u32 buf_size;
+ /* ITERation on each DMAreq signals */
+ u32 iter;
+ /* DMAreq address */
+ u32 dma_addr;
+ /* DMA/AESS = 1 << #DMA */
+ u32 dma_data;
+ } prot_dmareq;
+ /* Circular buffer - direct addressing to DMEM */
+ struct {
+ /* DMEM buffer base address in bytes */
+ u32 buf_addr;
+ /* DMEM buffer size in bytes */
+ u32 buf_size;
+ /* DMAreq address */
+ u32 dma_addr;
+ /* DMA/AESS = 1 << #DMA */
+ u32 dma_data;
+ } prot_circular_buffer;
+ } p;
+};
+
+struct omap_aess_dma_offset {
+ /* Offset to the first address of the */
+ u32 data;
+ /* number of iterations for the DMA data moves. */
+ u32 iter;
+};
+
+/*
+ * ABE_PORT_T status / format / sampling / protocol(call_back) /
+ * features / gain / name ..
+ *
+ */
+
+struct omap_aess_task {
+ u8 frame;
+ u8 slot;
+ u16 task;
+};
+
+struct omap_aess_init_task {
+ u32 nb_task;
+ struct omap_aess_task task[2];
+};
+
+struct omap_aess_io_task {
+ u32 nb_task;
+ u32 smem;
+ struct omap_aess_task *task;
+};
+
+struct omap_aess_io_task1 {
+ u32 nb_task;
+ u32 smem;
+ struct omap_aess_task task[2];
+};
+
+struct omap_aess_port_type {
+ struct omap_aess_init_task serial;
+ struct omap_aess_init_task cbpr;
+};
+
+struct omap_aess_asrc_port {
+ struct omap_aess_io_task1 task;
+ struct omap_aess_port_type asrc;
+};
+
+struct omap_aess_port {
+ /* running / idled */
+ u16 status;
+ /* Sample format type */
+ struct omap_aess_data_format format;
+ /* IO tasks buffers */
+ u16 smem_buffer1;
+ u16 smem_buffer2;
+ struct omap_aess_port_protocol protocol;
+ /* pointer and iteration counter of the xDMA */
+ struct omap_aess_dma_offset dma;
+ struct omap_aess_init_task task;
+ struct omap_aess_asrc_port tsk_freq[4];
+};
+
+#define OMAP_AESS_GAIN_DMIC1_LEFT 0
+#define OMAP_AESS_GAIN_DMIC1_RIGHT 1
+#define OMAP_AESS_GAIN_DMIC2_LEFT 2
+#define OMAP_AESS_GAIN_DMIC2_RIGHT 3
+#define OMAP_AESS_GAIN_DMIC3_LEFT 4
+#define OMAP_AESS_GAIN_DMIC3_RIGHT 5
+#define OMAP_AESS_GAIN_AMIC_LEFT 6
+#define OMAP_AESS_GAIN_AMIC_RIGHT 7
+#define OMAP_AESS_GAIN_DL1_LEFT 8
+#define OMAP_AESS_GAIN_DL1_RIGHT 9
+#define OMAP_AESS_GAIN_DL2_LEFT 10
+#define OMAP_AESS_GAIN_DL2_RIGHT 11
+#define OMAP_AESS_GAIN_SPLIT_LEFT 12
+#define OMAP_AESS_GAIN_SPLIT_RIGHT 13
+#define OMAP_AESS_MIXDL1_MM_DL 14
+#define OMAP_AESS_MIXDL1_MM_UL2 15
+#define OMAP_AESS_MIXDL1_VX_DL 16
+#define OMAP_AESS_MIXDL1_TONES 17
+#define OMAP_AESS_MIXDL2_MM_DL 18
+#define OMAP_AESS_MIXDL2_MM_UL2 19
+#define OMAP_AESS_MIXDL2_VX_DL 20
+#define OMAP_AESS_MIXDL2_TONES 21
+#define OMAP_AESS_MIXECHO_DL1 22
+#define OMAP_AESS_MIXECHO_DL2 23
+#define OMAP_AESS_MIXSDT_UL 24
+#define OMAP_AESS_MIXSDT_DL 25
+#define OMAP_AESS_MIXVXREC_MM_DL 26
+#define OMAP_AESS_MIXVXREC_TONES 27
+#define OMAP_AESS_MIXVXREC_VX_UL 28
+#define OMAP_AESS_MIXVXREC_VX_DL 29
+#define OMAP_AESS_MIXAUDUL_MM_DL 30
+#define OMAP_AESS_MIXAUDUL_TONES 31
+#define OMAP_AESS_MIXAUDUL_UPLINK 32
+#define OMAP_AESS_MIXAUDUL_VX_DL 33
+#define OMAP_AESS_GAIN_BTUL_LEFT 34
+#define OMAP_AESS_GAIN_BTUL_RIGHT 35
+
+#endif /* _AESS_FW_H_ */
index bf346c5075d5eeef94828c5ffc62d65a6abab2c8..23fdb026cf2373c8f685d0e0a60a437ba5cc4b33 100644 (file)
#include <sound/soc.h>
#include <sound/soc-fw.h>
-#include <plat/cpu.h>
#include "../../../arch/arm/mach-omap2/omap-pm.h"
#include "omap-abe-priv.h"
int abe_pm_suspend(struct snd_soc_dai *dai);
int abe_pm_resume(struct snd_soc_dai *dai);
-int abe_mixer_write(struct snd_soc_platform *platform, unsigned int reg,
- unsigned int val);
-unsigned int abe_mixer_read(struct snd_soc_platform *platform,
- unsigned int reg);
irqreturn_t abe_irq_handler(int irq, void *dev_id);
void abe_init_debugfs(struct omap_abe *abe);
void abe_cleanup_debugfs(struct omap_abe *abe);
"mpu"
};
+/* TODO: map IO directly into ABE memories */
+static unsigned int omap_abe_oppwidget_read(struct snd_soc_platform *platform,
+ unsigned int reg)
+{
+ struct omap_abe *abe = snd_soc_platform_get_drvdata(platform);
+
+ if (reg > OMAP_ABE_NUM_DAPM_REG)
+ return 0;
+
+ dev_dbg(platform->dev, "read R%d (Ox%x) = 0x%x\n",
+ reg, reg, abe->opp.widget[reg]);
+ return abe->opp.widget[reg];
+}
+
+static int omap_abe_oppwidget_write(struct snd_soc_platform *platform, unsigned int reg,
+ unsigned int val)
+{
+ struct omap_abe *abe = snd_soc_platform_get_drvdata(platform);
+
+ if (reg > OMAP_ABE_NUM_DAPM_REG)
+ return 0;
+
+ abe->opp.widget[reg] = val;
+ dev_dbg(platform->dev, "write R%d (Ox%x) = 0x%x\n", reg, reg, val);
+ return 0;
+}
+
+
static void abe_init_gains(struct omap_aess *abe)
{
/* Uplink gains */
struct snd_soc_fw_hdr *hdr)
{
struct omap_abe *abe = snd_soc_platform_get_drvdata(platform);
- const u8 *fw_data = snd_soc_fw_get_data(hdr);
+ const void *fw_data = snd_soc_fw_get_data(hdr);
/* get firmware and coefficients header info */
memcpy(&abe->hdr, fw_data, sizeof(struct fw_header));
}
#endif
/* store ABE firmware for later context restore */
- abe->fw_text = kzalloc(hdr->size, GFP_KERNEL);
- if (abe->fw_text == NULL)
- return -ENOMEM;
-
- memcpy(abe->fw_text, fw_data, hdr->size);
+ abe->fw_data = fw_data;
return 0;
}
struct snd_soc_fw_hdr *hdr)
{
struct omap_abe *abe = snd_soc_platform_get_drvdata(platform);
- const u8 *fw_data = snd_soc_fw_get_data(hdr);
+ const void *fw_data = snd_soc_fw_get_data(hdr);
/* store ABE config for later context restore */
- abe->fw_config = kzalloc(hdr->size, GFP_KERNEL);
- if (abe->fw_config == NULL)
- return -ENOMEM;
-
dev_info(abe->dev, "ABE Config size %d bytes\n", hdr->size);
- memcpy(abe->fw_config, fw_data, hdr->size);
+ abe->fw_config = fw_data;
return 0;
}
static void abe_free_fw(struct omap_abe *abe)
{
- kfree(abe->fw_text);
- kfree(abe->fw_config);
-
/* This below should be done in HAL - oposite of init_mem()*/
if (!abe->aess)
return;
if (abe->aess->fw_info) {
- kfree(abe->aess->fw_info->init_table);
kfree(abe->aess->fw_info);
}
}
goto err_fw;
}
- ret = request_threaded_irq(abe->irq, NULL, abe_irq_handler,
- IRQF_ONESHOT, "ABE", (void *)abe);
+ ret = devm_request_threaded_irq(abe->dev, abe->irq, NULL, abe_irq_handler,
+ IRQF_ONESHOT, "ABE", (void *)abe);
if (ret) {
dev_err(platform->dev, "request for ABE IRQ %d failed %d\n",
abe->irq, ret);
for (i = 0; i < OMAP_ABE_ROUTES_UL + 2; i++)
abe->mixer.route_ul[i] = abe->aess->fw_info->label_id[OMAP_AESS_BUFFER_ZERO_ID];
- omap_aess_load_fw(abe->aess, abe->fw_text);
+ omap_aess_load_fw(abe->aess, abe->fw_data);
/* "tick" of the audio engine */
omap_aess_write_event_generator(abe->aess, EVENT_TIMER);
return ret;
-err_opp:
- free_irq(abe->irq, (void *)abe);
err_irq:
abe_free_fw(abe);
err_fw:
struct omap_abe *abe = snd_soc_platform_get_drvdata(platform);
abe_cleanup_debugfs(abe);
- free_irq(abe->irq, (void *)abe);
abe_free_fw(abe);
pm_runtime_disable(abe->dev);
.remove = abe_remove,
.suspend = abe_pm_suspend,
.resume = abe_pm_resume,
- .read = abe_mixer_read,
- .write = abe_mixer_write,
+ .read = omap_abe_oppwidget_read,
+ .write = omap_abe_oppwidget_write,
.stream_event = abe_opp_stream_event,
};
{
struct resource *res;
struct omap_abe *abe;
- int ret = -EINVAL, i;
+ int ret, i;
abe = devm_kzalloc(&pdev->dev, sizeof(struct omap_abe), GFP_KERNEL);
if (abe == NULL)
return -ENOMEM;
- dev_set_drvdata(&pdev->dev, abe);
for (i = 0; i < OMAP_ABE_IO_RESOURCES; i++) {
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
if (res == NULL) {
dev_err(&pdev->dev, "no resource %s\n",
abe_memory_bank[i]);
- goto err;
+ return -ENODEV;
}
- abe->io_base[i] = ioremap(res->start, resource_size(res));
- if (!abe->io_base[i]) {
- ret = -ENOMEM;
- goto err;
+ if (!devm_request_mem_region(&pdev->dev, res->start,
+ resource_size(res), abe_memory_bank[i]))
+ return -EBUSY;
+
+ abe->io_base[i] = devm_ioremap(&pdev->dev, res->start,
+ resource_size(res));
+ if (!abe->io_base[i])
+ return -ENOMEM;
+ }
+
+ for (i = 0; i < OMAP_ABE_DMA_RESOURCES; i++) {
+ char name[8];
+
+ sprintf(name, "fifo%d", i);
+ res = platform_get_resource_byname(pdev, IORESOURCE_DMA, name);
+ if (res == NULL) {
+ dev_err(&pdev->dev, "no resource %s\n", name);
+ return -ENODEV;
}
+ abe->dma_lines[i] = res->start;
}
abe->irq = platform_get_irq(pdev, 0);
- if (abe->irq < 0) {
- ret = abe->irq;
- goto err;
- }
+ if (abe->irq < 0)
+ return abe->irq;
+
+ dev_set_drvdata(&pdev->dev, abe);
#ifdef CONFIG_PM
abe->get_context_lost_count = omap_pm_get_dev_context_loss_count;
abe->device_scale = NULL;
#endif
abe->dev = &pdev->dev;
+
mutex_init(&abe->mutex);
mutex_init(&abe->opp.mutex);
mutex_init(&abe->opp.req_mutex);
put_device(abe->dev);
ret = request_firmware_nowait(THIS_MODULE, 1, "omap4_abe_new", abe->dev,
- GFP_KERNEL, pdev, abe_fw_ready);
- if (ret != 0) {
+ GFP_KERNEL, pdev, abe_fw_ready);
+ if (!ret)
dev_err(abe->dev, "Failed to load firmware %d\n", ret);
- goto err;
- }
-
- return ret;
-
-err:
- for (--i; i >= 0; i--)
- iounmap(abe->io_base[i]);
return ret;
}
static int abe_engine_remove(struct platform_device *pdev)
{
struct omap_abe *abe = dev_get_drvdata(&pdev->dev);
- int i;
snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(omap_abe_dai));
snd_soc_unregister_platform(&pdev->dev);
+
+ abe->fw_data = NULL;
+ abe->fw_config = NULL;
release_firmware(abe->fw);
- for (i = 0; i < OMAP_ABE_IO_RESOURCES; i++)
- iounmap(abe->io_base[i]);
return 0;
}
index 33abb0e9ec98336826601d1d6374e2490bbf5059..3d15c831a4bf44f283924f1cbae809ac558ede90 100644 (file)
#define abe_val_to_gain(val) \
(-OMAP_ABE_MAX_GAIN + (val * OMAP_ABE_GAIN_SCALE))
-/* TODO: map IO directly into ABE memories */
-unsigned int abe_mixer_read(struct snd_soc_platform *platform,
- unsigned int reg)
-{
- struct omap_abe *abe = snd_soc_platform_get_drvdata(platform);
-
- if (reg > OMAP_ABE_NUM_DAPM_REG)
- return 0;
-
- dev_dbg(platform->dev, "read R%d (Ox%x) = 0x%x\n",
- reg, reg, abe->opp.widget[reg]);
- return abe->opp.widget[reg];
-}
-
-int abe_mixer_write(struct snd_soc_platform *platform, unsigned int reg,
- unsigned int val)
-{
- struct omap_abe *abe = snd_soc_platform_get_drvdata(platform);
-
- if (reg > OMAP_ABE_NUM_DAPM_REG)
- return 0;
-
- abe->opp.widget[reg] = val;
- dev_dbg(platform->dev, "write R%d (Ox%x) = 0x%x\n", reg, reg, val);
- return 0;
-}
-
void omap_abe_dc_set_hs_offset(struct snd_soc_platform *platform,
int left, int right, int step_mV)
{
index 86b98c273c851bb99229728f8db9f37f7ce22803..bed4d47556970130d1a70889a58a334c9801d22d 100644 (file)
.buffer_bytes_max = 24 * 1024 * 2,
};
-static void abe_irq_pingpong_subroutine(u32 *sub, u32 *data)
+/*
+ * omap_aess_irq_data
+ *
+ * IRQ FIFO content declaration
+ * APS interrupts : IRQ_FIFO[31:28] = IRQtag_APS,
+ * IRQ_FIFO[27:16] = APS_IRQs, IRQ_FIFO[15:0] = loopCounter
+ * SEQ interrupts : IRQ_FIFO[31:28] OMAP_ABE_IRQTAG_COUNT,
+ * IRQ_FIFO[27:16] = Count_IRQs, IRQ_FIFO[15:0] = loopCounter
+ * Ping-Pong Interrupts : IRQ_FIFO[31:28] = OMAP_ABE_IRQTAG_PP,
+ * IRQ_FIFO[27:16] = PP_MCU_IRQ, IRQ_FIFO[15:0] = loopCounter
+ */
+struct omap_aess_irq_data {
+ unsigned int counter:16;
+ unsigned int data:12;
+ unsigned int tag:4;
+};
+
+#define OMAP_ABE_IRQTAG_COUNT 0x000c
+#define OMAP_ABE_IRQTAG_PP 0x000d
+#define OMAP_ABE_IRQ_FIFO_MASK ((OMAP_ABE_D_MCUIRQFIFO_SIZE >> 2) - 1)
+
+static void abe_irq_pingpong_subroutine(struct snd_pcm_substream *substream, struct omap_abe *abe)
{
- struct snd_pcm_substream *substream = (struct snd_pcm_substream *)sub;
- struct omap_abe *abe = (struct omap_abe *)data;
u32 dst, n_bytes;
omap_aess_read_next_ping_pong_buffer(abe->aess, OMAP_ABE_MM_DL_PORT, &dst, &n_bytes);
}
}
+
irqreturn_t abe_irq_handler(int irq, void *dev_id)
{
struct omap_abe *abe = dev_id;
+ struct omap_aess_addr addr;
+ struct omap_aess *aess = abe->aess;
+ struct omap_aess_irq_data IRQ_data;
+ u32 abe_irq_dbg_write_ptr, i, cmem_src, sm_cm;
pm_runtime_get_sync(abe->dev);
omap_aess_clear_irq(abe->aess);
- omap_aess_irq_processing(abe->aess);
+
+ /* extract the write pointer index from CMEM memory (INITPTR format) */
+ /* CMEM address of the write pointer in bytes */
+ cmem_src = aess->fw_info->label_id[OMAP_AESS_BUFFER_MCU_IRQ_FIFO_PTR_ID] << 2;
+ omap_abe_mem_read(aess, OMAP_ABE_CMEM, cmem_src,
+ &sm_cm, sizeof(abe_irq_dbg_write_ptr));
+ /* AESS left-pointer index located on MSBs */
+ abe_irq_dbg_write_ptr = sm_cm >> 16;
+ abe_irq_dbg_write_ptr &= 0xFF;
+ /* loop on the IRQ FIFO content */
+ for (i = 0; i < OMAP_ABE_D_MCUIRQFIFO_SIZE; i++) {
+ /* stop when the FIFO is empty */
+ if (abe_irq_dbg_write_ptr == aess->irq_dbg_read_ptr)
+ break;
+ /* read the IRQ/DBG FIFO */
+ memcpy(&addr, &aess->fw_info->map[OMAP_AESS_DMEM_MCUIRQFIFO_ID],
+ sizeof(struct omap_aess_addr));
+ addr.offset += (aess->irq_dbg_read_ptr << 2);
+ addr.bytes = sizeof(IRQ_data);
+ omap_aess_mem_read(aess, addr, (u32 *)&IRQ_data);
+ aess->irq_dbg_read_ptr = (aess->irq_dbg_read_ptr + 1) & OMAP_ABE_IRQ_FIFO_MASK;
+ /* select the source of the interrupt */
+ switch (IRQ_data.tag) {
+ case OMAP_ABE_IRQTAG_PP:
+ /* first IRQ doesn't represent a buffer transference completion */
+ if (aess->pp_first_irq)
+ aess->pp_first_irq = 0;
+ else
+ aess->pp_buf_id = (aess->pp_buf_id + 1) & 0x03;
+
+ abe_irq_pingpong_subroutine(abe->dai.port[OMAP_ABE_FE_PORT_MM_DL_LP]->substream,
+ abe);
+
+ break;
+ case OMAP_ABE_IRQTAG_COUNT:
+ /*omap_aess_monitoring(aess);*/
+ break;
+ default:
+ break;
+ }
+
+ }
+
pm_runtime_put_sync_suspend(abe->dev);
return IRQ_HANDLED;
}
-static int omap_abe_hwrule_period_step(struct snd_pcm_hw_params *params,
+static int omap_abe_hwrule_size_step(struct snd_pcm_hw_params *params,
struct snd_pcm_hw_rule *rule)
{
- struct snd_interval *period_size = hw_param_interval(params,
- SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
unsigned int rate = params_rate(params);
/* 44.1kHz has the same iteration number as 48kHz */
rate = (rate == 44100) ? 48000 : rate;
/* ABE requires chunks of 250us worth of data */
- return snd_interval_step(period_size, 0, rate / 4000);
+ return snd_interval_step(hw_param_interval(params, rule->var), 0,
+ rate / 4000);
}
static int aess_open(struct snd_pcm_substream *substream)
break;
default:
/*
- * Period size must be aligned with the Audio Engine
+ * Period and buffer size must be aligned with the Audio Engine
* processing loop which is 250 us long
*/
ret = snd_pcm_hw_rule_add(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
- omap_abe_hwrule_period_step,
+ omap_abe_hwrule_size_step,
NULL,
SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1);
+ ret = snd_pcm_hw_rule_add(substream->runtime, 0,
+ SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
+ omap_abe_hwrule_size_step,
+ NULL,
+ SNDRV_PCM_HW_PARAM_BUFFER_SIZE, -1);
break;
}
struct snd_soc_dai *dai = rtd->cpu_dai;
struct omap_aess_data_format format;
size_t period_size;
- u32 dst, param[2];
+ u32 dst;
int ret = 0;
mutex_lock(&abe->mutex);
format.f = params_rate(params);
if (params_format(params) == SNDRV_PCM_FORMAT_S32_LE)
- format.samp_format = STEREO_MSB;
+ format.samp_format = OMAP_AESS_FORMAT_STEREO_MSB;
else
- format.samp_format = STEREO_16_16;
+ format.samp_format = OMAP_AESS_FORMAT_STEREO_16_16;
period_size = params_period_bytes(params);
- param[0] = (u32)substream;
- param[1] = (u32)abe;
-
- /* Adding ping pong buffer subroutine */
- omap_aess_plug_subroutine(abe->aess, &abe->aess->seq.irq_pingpong_player_id,
- (abe_subroutine2) abe_irq_pingpong_subroutine,
- 2, param);
-
/* Connect a Ping-Pong cache-flush protocol to MM_DL port */
omap_aess_connect_irq_ping_pong_port(abe->aess, OMAP_ABE_MM_DL_PORT, &format,
- abe->aess->seq.irq_pingpong_player_id,
+ 0,
period_size, &dst,
PING_PONG_WITH_MCU_IRQ);
index 0444bc403b942162bcb2c87b1a7fb8c5bba2bc5f..ac16aa644bd58e30a2fbdd77f4631771a810f835 100644 (file)
/* BT_DL connection to McBSP 1 ports */
format.f = 8000;
- format.samp_format = STEREO_RSHIFTED_16;
- omap_aess_connect_serial_port(abe->aess, OMAP_ABE_BT_VX_DL_PORT, &format, MCBSP1_TX);
+ format.samp_format = OMAP_AESS_FORMAT_STEREO_RSHIFTED_16;
+ omap_aess_connect_serial_port(abe->aess, OMAP_ABE_BT_VX_DL_PORT, &format, MCBSP1_TX, NULL);
omap_abe_port_enable(abe->aess,
abe->dai.port[OMAP_ABE_BE_PORT_BT_VX_DL]);
} else {
/* BT_UL connection to McBSP 1 ports */
format.f = 8000;
- format.samp_format = STEREO_RSHIFTED_16;
- omap_aess_connect_serial_port(abe->aess, OMAP_ABE_BT_VX_UL_PORT, &format, MCBSP1_RX);
+ format.samp_format = OMAP_AESS_FORMAT_STEREO_RSHIFTED_16;
+ omap_aess_connect_serial_port(abe->aess, OMAP_ABE_BT_VX_UL_PORT, &format, MCBSP1_RX, NULL);
omap_abe_port_enable(abe->aess,
abe->dai.port[OMAP_ABE_BE_PORT_BT_VX_UL]);
}
/* MM_EXT connection to McBSP 2 ports */
format.f = 48000;
- format.samp_format = STEREO_RSHIFTED_16;
- omap_aess_connect_serial_port(abe->aess, OMAP_ABE_MM_EXT_OUT_PORT, &format, MCBSP2_TX);
+ format.samp_format = OMAP_AESS_FORMAT_STEREO_RSHIFTED_16;
+ omap_aess_connect_serial_port(abe->aess, OMAP_ABE_MM_EXT_OUT_PORT, &format, MCBSP2_TX, NULL);
omap_abe_port_enable(abe->aess,
abe->dai.port[OMAP_ABE_BE_PORT_MM_EXT_DL]);
} else {
/* MM_EXT connection to McBSP 2 ports */
format.f = 48000;
- format.samp_format = STEREO_RSHIFTED_16;
- omap_aess_connect_serial_port(abe->aess, OMAP_ABE_MM_EXT_IN_PORT, &format, MCBSP2_RX);
+ format.samp_format = OMAP_AESS_FORMAT_STEREO_RSHIFTED_16;
+ omap_aess_connect_serial_port(abe->aess, OMAP_ABE_MM_EXT_IN_PORT, &format, MCBSP2_RX, NULL);
omap_abe_port_enable(abe->aess,
abe->dai.port[OMAP_ABE_BE_PORT_MM_EXT_UL]);
}
abe->dai.port[OMAP_ABE_FE_PORT_MM_UL1]);
break;
case OMAP_ABE_FRONTEND_DAI_LP_MEDIA:
- if (stream == SNDRV_PCM_STREAM_PLAYBACK)
+ if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
omap_abe_port_enable(abe->aess,
abe->dai.port[OMAP_ABE_FE_PORT_MM_DL_LP]);
+ abe->dai.port[OMAP_ABE_FE_PORT_MM_DL_LP]->substream = substream;
+ }
break;
case OMAP_ABE_FRONTEND_DAI_MEDIA_CAPTURE:
if (stream == SNDRV_PCM_STREAM_CAPTURE)
struct omap_abe *abe = snd_soc_dai_get_drvdata(dai);
struct omap_pcm_dma_data *dma_data;
struct omap_aess_data_format format;
- struct omap_aess_dma dma_sink;
struct omap_aess_dma dma_params;
dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
switch (params_channels(params)) {
case 1:
if (params_format(params) == SNDRV_PCM_FORMAT_S16_LE)
- format.samp_format = MONO_16_16;
+ format.samp_format = OMAP_AESS_FORMAT_MONO_16_16;
else
- format.samp_format = MONO_MSB;
+ format.samp_format = OMAP_AESS_FORMAT_MONO_MSB;
break;
case 2:
if (params_format(params) == SNDRV_PCM_FORMAT_S16_LE)
- format.samp_format = STEREO_16_16;
+ format.samp_format = OMAP_AESS_FORMAT_STEREO_16_16;
else
- format.samp_format = STEREO_MSB;
+ format.samp_format = OMAP_AESS_FORMAT_STEREO_MSB;
break;
case 3:
- format.samp_format = THREE_MSB;
+ format.samp_format = OMAP_AESS_FORMAT_THREE_MSB;
break;
case 4:
- format.samp_format = FOUR_MSB;
+ format.samp_format = OMAP_AESS_FORMAT_FOUR_MSB;
break;
case 5:
- format.samp_format = FIVE_MSB;
+ format.samp_format = OMAP_AESS_FORMAT_FIVE_MSB;
break;
case 6:
- format.samp_format = SIX_MSB;
+ format.samp_format = OMAP_AESS_FORMAT_SIX_MSB;
break;
case 7:
- format.samp_format = SEVEN_MSB;
+ format.samp_format = OMAP_AESS_FORMAT_SEVEN_MSB;
break;
case 8:
- format.samp_format = EIGHT_MSB;
+ format.samp_format = OMAP_AESS_FORMAT_EIGHT_MSB;
break;
default:
dev_err(dai->dev, "%d channels not supported",
switch (dai->id) {
case OMAP_ABE_FRONTEND_DAI_MEDIA:
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
- omap_aess_connect_cbpr_dmareq_port(abe->aess, OMAP_ABE_MM_DL_PORT, &format, ABE_CBPR0_IDX,
- &dma_sink);
- omap_aess_read_port_address(abe->aess, OMAP_ABE_MM_DL_PORT, &dma_params);
- } else {
- omap_aess_connect_cbpr_dmareq_port(abe->aess, OMAP_ABE_MM_UL_PORT, &format, ABE_CBPR3_IDX,
- &dma_sink);
- omap_aess_read_port_address(abe->aess, OMAP_ABE_MM_UL_PORT, &dma_params);
- }
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ omap_aess_connect_cbpr_dmareq_port(abe->aess,
+ OMAP_ABE_MM_DL_PORT, &format,
+ ABE_CBPR0_IDX, &dma_params);
+ else
+ omap_aess_connect_cbpr_dmareq_port(abe->aess,
+ OMAP_ABE_MM_UL_PORT, &format,
+ ABE_CBPR3_IDX, &dma_params);
break;
case OMAP_ABE_FRONTEND_DAI_LP_MEDIA:
return 0;
case OMAP_ABE_FRONTEND_DAI_MEDIA_CAPTURE:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
return -EINVAL;
- else {
- omap_aess_connect_cbpr_dmareq_port(abe->aess, OMAP_ABE_MM_UL2_PORT, &format, ABE_CBPR4_IDX,
- &dma_sink);
- omap_aess_read_port_address(abe->aess, OMAP_ABE_MM_UL2_PORT, &dma_params);
- }
+ else
+ omap_aess_connect_cbpr_dmareq_port(abe->aess,
+ OMAP_ABE_MM_UL2_PORT, &format,
+ ABE_CBPR4_IDX, &dma_params);
break;
case OMAP_ABE_FRONTEND_DAI_VOICE:
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
- omap_aess_connect_cbpr_dmareq_port(abe->aess, OMAP_ABE_VX_DL_PORT, &format, ABE_CBPR1_IDX,
- &dma_sink);
- omap_aess_read_port_address(abe->aess, OMAP_ABE_VX_DL_PORT, &dma_params);
- } else {
- omap_aess_connect_cbpr_dmareq_port(abe->aess, OMAP_ABE_VX_UL_PORT, &format, ABE_CBPR2_IDX,
- &dma_sink);
- omap_aess_read_port_address(abe->aess, OMAP_ABE_VX_UL_PORT, &dma_params);
- }
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ omap_aess_connect_cbpr_dmareq_port(abe->aess,
+ OMAP_ABE_VX_DL_PORT, &format,
+ ABE_CBPR1_IDX, &dma_params);
+ else
+ omap_aess_connect_cbpr_dmareq_port(abe->aess,
+ OMAP_ABE_VX_UL_PORT, &format,
+ ABE_CBPR2_IDX, &dma_params);
break;
case OMAP_ABE_FRONTEND_DAI_TONES:
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
- omap_aess_connect_cbpr_dmareq_port(abe->aess, OMAP_ABE_TONES_DL_PORT, &format, ABE_CBPR5_IDX,
- &dma_sink);
- omap_aess_read_port_address(abe->aess, OMAP_ABE_TONES_DL_PORT, &dma_params);
- } else
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ omap_aess_connect_cbpr_dmareq_port(abe->aess,
+ OMAP_ABE_TONES_DL_PORT, &format,
+ ABE_CBPR5_IDX, &dma_params);
+ else
return -EINVAL;
break;
case OMAP_ABE_FRONTEND_DAI_MODEM:
/* MODEM is special case where data IO is performed by McBSP2
* directly onto VX_DL and VX_UL (instead of SDMA).
*/
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
- /* Vx_DL connection to McBSP 2 ports */
- format.samp_format = STEREO_RSHIFTED_16;
- omap_aess_connect_serial_port(abe->aess, OMAP_ABE_VX_DL_PORT, &format, MCBSP2_RX);
- omap_aess_read_port_address(abe->aess, OMAP_ABE_VX_DL_PORT, &dma_params);
- } else {
- /* Vx_UL connection to McBSP 2 ports */
- format.samp_format = STEREO_RSHIFTED_16;
- omap_aess_connect_serial_port(abe->aess, OMAP_ABE_VX_UL_PORT, &format, MCBSP2_TX);
- omap_aess_read_port_address(abe->aess, OMAP_ABE_VX_UL_PORT, &dma_params);
- }
+ format.samp_format = OMAP_AESS_FORMAT_STEREO_RSHIFTED_16;
+
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ omap_aess_connect_serial_port(abe->aess,
+ OMAP_ABE_VX_DL_PORT, &format,
+ MCBSP2_RX, &dma_params);
+ else
+ omap_aess_connect_serial_port(abe->aess,
+ OMAP_ABE_VX_UL_PORT, &format,
+ MCBSP2_TX, &dma_params);
break;
default:
dev_err(dai->dev, "port %d not supported\n", dai->id);
index c4cf0a57487d624be3eec444e44dd00b0c285098..284e73fac76eab8d30f2b1d80082a2cc025bd5a9 100644 (file)
}
}
- omap_aess_reload_fw(abe->aess, abe->fw_text);
+ omap_aess_reload_fw(abe->aess, abe->fw_data);
switch (dai->id) {
case OMAP_ABE_DAI_PDM_UL:
index ff0379582d62deac2c5b0970878343fb40c4fc77..d6763c7511d9b5f59890427e0bcad819dc8ff3af 100644 (file)
OMAP_ABE_MIXER_VOLUME, \
SOC_CONTROL_TYPE_VOLSW)
+#define OMAP_ABE_DMA_RESOURCES 8
#ifdef __KERNEL__
struct clk *clk;
void __iomem *io_base[OMAP_ABE_IO_RESOURCES];
+ int dma_lines[OMAP_ABE_DMA_RESOURCES];
int irq;
int active;
struct mutex mutex;
/* firmware */
struct fw_header hdr;
u32 *fw_config;
- u32 *fw_text;
+ const void *fw_data;
const struct firmware *fw;
int num_equ;
index 597e83b2fa430223bfe70b07c3e5003d7b357e19..b7c687a9421f166c8388b5b7aa1c6bb8809b42c9 100644 (file)
static const struct snd_soc_dapm_route dmic_audio_map[] = {
/* Digital Mics: DMic0, DMic1, DMic2 with bias */
- {"DMIC0", NULL, "omap-dmic-abe.0 Capture"},
- {"omap-dmic-abe.0 Capture", NULL, "Digital Mic1 Bias"},
+ {"DMIC0", NULL, "omap-dmic-abe Capture"},
+ {"omap-dmic-abe Capture", NULL, "Digital Mic1 Bias"},
{"Digital Mic1 Bias", NULL, "Digital Mic 0"},
- {"DMIC1", NULL, "omap-dmic-abe.1 Capture"},
- {"omap-dmic-abe.1 Capture", NULL, "Digital Mic1 Bias"},
+ {"DMIC1", NULL, "omap-dmic-abe Capture"},
+ {"omap-dmic-abe Capture", NULL, "Digital Mic1 Bias"},
{"Digital Mic1 Bias", NULL, "Digital Mic 1"},
- {"DMIC2", NULL, "omap-dmic-abe.2 Capture"},
- {"omap-dmic-abe.2 Capture", NULL, "Digital Mic1 Bias"},
+ {"DMIC2", NULL, "omap-dmic-abe Capture"},
+ {"omap-dmic-abe Capture", NULL, "Digital Mic1 Bias"},
{"Digital Mic1 Bias", NULL, "Digital Mic 2"},
};
{
/* McPDM DL1 - Headset */
SND_SOC_DAI_CONNECT("McPDM-DL1", "twl6040-codec", "aess",
- "twl6040-dl1", "mcpdm-dl1"),
+ "twl6040-dl1", "mcpdm-abe"),
SND_SOC_DAI_BE_LINK(OMAP_ABE_DAI_PDM_DL1, mcpdm_be_hw_params_fixup),
SND_SOC_DAI_OPS(&omap_abe_mcpdm_ops, omap_abe_twl6040_init),
SND_SOC_DAI_IGNORE_SUSPEND, SND_SOC_DAI_IGNORE_PMDOWN,
{
/* McPDM UL1 - Analog Capture */
SND_SOC_DAI_CONNECT("McPDM-UL1", "twl6040-codec", "aess",
- "twl6040-ul", "mcpdm-ul1"),
+ "twl6040-ul", "mcpdm-abe"),
SND_SOC_DAI_BE_LINK(OMAP_ABE_DAI_PDM_UL, mcpdm_be_hw_params_fixup),
SND_SOC_DAI_OPS(&omap_abe_mcpdm_ops, NULL),
SND_SOC_DAI_IGNORE_SUSPEND, SND_SOC_DAI_IGNORE_PMDOWN,
{
/* McPDM DL2 - Handsfree */
SND_SOC_DAI_CONNECT("McPDM-DL2", "twl6040-codec", "aess",
- "twl6040-dl2", "mcpdm-dl2"),
+ "twl6040-dl2", "mcpdm-abe"),
SND_SOC_DAI_BE_LINK(OMAP_ABE_DAI_PDM_DL2, mcpdm_be_hw_params_fixup),
SND_SOC_DAI_OPS(&omap_abe_mcpdm_ops, omap_abe_twl6040_dl2_init),
SND_SOC_DAI_IGNORE_SUSPEND, SND_SOC_DAI_IGNORE_PMDOWN,
{
/* DMIC0 */
SND_SOC_DAI_CONNECT("DMIC-0", "dmic-codec", "aess",
- "dmic-hifi", "omap-dmic-abe-dai-0"),
+ "dmic-hifi", "omap-dmic-abe-dai"),
SND_SOC_DAI_BE_LINK(OMAP_ABE_DAI_DMIC0, dmic_be_hw_params_fixup),
SND_SOC_DAI_OPS(&omap_abe_dmic_ops, NULL),
},
{
/* DMIC1 */
SND_SOC_DAI_CONNECT("DMIC-1", "dmic-codec", "aess",
- "dmic-hifi", "omap-dmic-abe-dai-1"),
+ "dmic-hifi", "omap-dmic-abe-dai"),
SND_SOC_DAI_BE_LINK(OMAP_ABE_DAI_DMIC1, dmic_be_hw_params_fixup),
SND_SOC_DAI_OPS(&omap_abe_dmic_ops, NULL),
},
{
/* DMIC2 */
SND_SOC_DAI_CONNECT("DMIC-2", "dmic-codec", "aess",
- "dmic-hifi", "omap-dmic-abe-dai-2"),
+ "dmic-hifi", "omap-dmic-abe-dai"),
SND_SOC_DAI_BE_LINK(OMAP_ABE_DAI_DMIC2, dmic_be_hw_params_fixup),
SND_SOC_DAI_OPS(&omap_abe_dmic_ops, NULL),
},
index 6e5c7b8a9678ff2fc3410f1d1a92f0186714924b..56738100e09fb15ac1e096c4bdd8b6a63d2507a3 100644 (file)
#include "omap-pcm.h"
#include "omap-dmic.h"
-#define OMAP_DMIC_LEGACY_MODE 0x0
-#define OMAP_DMIC_ABE_MODE 0x1
-
-#define OMAP_DMIC_DAI_MODE_MASK 0x0f
+#define OMAP_DMIC_LEGACY_DAI 0
+#define OMAP_DMIC_ABE_DAI 1
struct omap_dmic {
struct device *dev;
int threshold;
u32 ch_enabled;
int active;
- bool abe_mode;
+ bool active_dai;
int running;
struct mutex mutex;
};
struct snd_soc_dai *dai)
{
struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
- int dai_abe_mode = dai->id & OMAP_DMIC_DAI_MODE_MASK;
int ret = 0;
mutex_lock(&dmic->mutex);
if (!dmic->active++) {
- dmic->abe_mode = dai_abe_mode;
+ dmic->active_dai = dai->id;
/* DMIC FIFO configuration */
- if (dmic->abe_mode == OMAP_DMIC_LEGACY_MODE)
+ if (dai->id == OMAP_DMIC_LEGACY_DAI)
dmic->threshold = OMAP_DMIC_THRES_MAX - 3;
else
dmic->threshold = 2;
- } else if (dmic->abe_mode != dai_abe_mode) {
+ } else if (dmic->active_dai != dai->id) {
dev_err(dmic->dev, "Trying %s, while DMIC is in %s.\n",
- dai_abe_mode ? "ABE mode" : "Legacy mode",
- dmic->abe_mode ? "ABE mode" : "Legacy mode");
+ dai->id ? "ABE mode" : "Legacy mode",
+ dmic->active_dai ? "ABE mode" : "Legacy mode");
dmic->active--;
ret = -EINVAL;
}
dmic->ch_enabled = 0;
channels = params_channels(params);
- if (dmic->abe_mode == OMAP_DMIC_LEGACY_MODE)
+ if (dai->id == OMAP_DMIC_LEGACY_DAI)
select_channels = channels;
else
select_channels = 6;
return 0;
}
-#define DMIC_LEGACY_DAI (OMAP_DMIC_LEGACY_MODE | (0 << 4))
-#define DMIC_ABE_DAI_1 (OMAP_DMIC_ABE_MODE | (1 << 4))
-#define DMIC_ABE_DAI_2 (OMAP_DMIC_ABE_MODE | (2 << 4))
-#define DMIC_ABE_DAI_3 (OMAP_DMIC_ABE_MODE | (3 << 4))
-
static struct snd_soc_dai_driver omap_dmic_dai[] = {
{
.name = "omap-dmic",
- .id = DMIC_LEGACY_DAI,
+ .id = OMAP_DMIC_LEGACY_DAI,
.probe = omap_dmic_probe,
.remove = omap_dmic_remove,
.capture = {
.ops = &omap_dmic_dai_ops,
},
{
- .name = "omap-dmic-abe-dai-0",
- .id = DMIC_ABE_DAI_1,
- .capture = {
- .stream_name = "omap-dmic-abe.0 Capture",
- .channels_min = 2,
- .channels_max = 2,
- .rates = SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000,
- .formats = SNDRV_PCM_FMTBIT_S32_LE,
- },
- .ops = &omap_dmic_dai_ops,
-},
-{
- .name = "omap-dmic-abe-dai-1",
- .id = DMIC_ABE_DAI_2,
- .capture = {
- .stream_name = "omap-dmic-abe.1 Capture",
- .channels_min = 2,
- .channels_max = 2,
- .rates = SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000,
- .formats = SNDRV_PCM_FMTBIT_S32_LE,
- },
- .ops = &omap_dmic_dai_ops,
-},
-{
- .name = "omap-dmic-abe-dai-2",
- .id = DMIC_ABE_DAI_3,
+ .name = "omap-dmic-abe-dai",
+ .id = OMAP_DMIC_ABE_DAI,
.capture = {
- .stream_name = "omap-dmic-abe.2 Capture",
+ .stream_name = "omap-dmic-abe Capture",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000,
{
struct omap_dmic *dmic;
struct resource *res;
- int ret;
+ int ret, nr_dai;
dmic = devm_kzalloc(&pdev->dev, sizeof(struct omap_dmic), GFP_KERNEL);
if (!dmic)
goto err_put_clk;
}
- if (!devm_request_mem_region(&pdev->dev, res->start,
- resource_size(res), pdev->name)) {
- dev_err(dmic->dev, "memory region already claimed\n");
- ret = -ENODEV;
- goto err_put_clk;
- }
-
- dmic->io_base = devm_ioremap(&pdev->dev, res->start,
- resource_size(res));
+ dmic->io_base = devm_request_and_ioremap(&pdev->dev, res);
if (!dmic->io_base) {
+ dev_err(&pdev->dev, "cannot remap\n");
ret = -ENOMEM;
goto err_put_clk;
}
- ret = snd_soc_register_dais(&pdev->dev, omap_dmic_dai,
- ARRAY_SIZE(omap_dmic_dai));
+#if defined(CONFIG_SND_OMAP_SOC_ABE) ||\
+ defined(CONFIG_SND_OMAP_SOC_ABE_MODULE)
+ nr_dai = ARRAY_SIZE(omap_dmic_dai);
+#else
+ nr_dai = 1;
+#endif
+ ret = snd_soc_register_dais(&pdev->dev, omap_dmic_dai, nr_dai);
if (ret)
goto err_put_clk;
index 84e16f053bb16f85fb3279d0af7930082b0e47ad..4b0ea194bf745646c8e99a2dce845d9a01fce189 100644 (file)
.ops = &omap_mcasp_dai_ops,
};
-static int omap_mcasp_probe(struct platform_device *pdev)
+static int asoc_mcasp_probe(struct platform_device *pdev)
{
struct omap_mcasp *mcasp;
struct resource *res;
return mcasp->irq;
}
- ret = request_threaded_irq(mcasp->irq, NULL, omap_mcasp_irq_handler,
- IRQF_ONESHOT, "McASP", mcasp);
+ ret = devm_request_threaded_irq(&pdev->dev, mcasp->irq, NULL,
+ omap_mcasp_irq_handler,
+ IRQF_ONESHOT, "McASP", mcasp);
if (ret) {
dev_err(mcasp->dev, "IRQ request failed\n");
return ret;
mcasp->fclk = clk_get(&pdev->dev, "fck");
if (!mcasp->fclk) {
dev_err(mcasp->dev, "cant get fck\n");
- ret = -ENODEV;
- goto err_clk;
+ return -ENODEV;
}
pm_runtime_enable(&pdev->dev);
err_dai:
pm_runtime_put_sync(&pdev->dev);
pm_runtime_disable(&pdev->dev);
-err_clk:
- free_irq(mcasp->irq, (void *)mcasp);
return ret;
}
-static int omap_mcasp_remove(struct platform_device *pdev)
+static int asoc_mcasp_remove(struct platform_device *pdev)
{
struct omap_mcasp *mcasp = dev_get_drvdata(&pdev->dev);
snd_soc_unregister_dai(&pdev->dev);
pm_runtime_disable(&pdev->dev);
clk_put(mcasp->fclk);
- free_irq(mcasp->irq, (void *)mcasp);
return 0;
}
MODULE_DEVICE_TABLE(of, omap_mcasp_of_match);
static struct platform_driver omap_mcasp_driver = {
- .probe = omap_mcasp_probe,
- .remove = omap_mcasp_remove,
.driver = {
.name = "omap-mcasp",
.owner = THIS_MODULE,
.of_match_table = omap_mcasp_of_match,
},
+ .probe = asoc_mcasp_probe,
+ .remove = asoc_mcasp_remove,
};
static int __init omap_mcasp_init(void)
index 4c5345ad976c0fcb3d4c3fa11fc4690daed7640a..ee7fabe9e82c3d8cc314c8454574928fe6443bc5 100644 (file)
#include "omap-abe-priv.h"
-#define MCPDM_LEGACY_MODE 0x0
-#define MCPDM_ABE_MODE 0x1
-
-#define MCPDM_DAI_MODE_MASK 0x0f
+#define OMAP_MCPDM_LEGACY_DAI 0
+#define OMAP_MCPDM_ABE_DAI 1
struct omap_mcpdm {
struct device *dev;
u32 dn_rx_offset;
int active;
- int abe_mode;
+ int active_dai;
- struct omap_aess *abe;
+ struct omap_aess *aess;
struct omap_abe_port *dl_port;
struct omap_abe_port *ul_port;
};
struct snd_soc_dai *dai)
{
struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
- int dai_abe_mode = dai->id & MCPDM_DAI_MODE_MASK;
int ret = 0;
mutex_lock(&mcpdm->mutex);
omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl | MCPDM_WD_EN);
- mcpdm->abe_mode = dai_abe_mode;
+ mcpdm->active_dai = dai->id;
/* McPDM FIFO configuration */
mcpdm->dn_threshold = 2;
- if (mcpdm->abe_mode == MCPDM_LEGACY_MODE)
+ if (dai->id == OMAP_MCPDM_LEGACY_DAI)
mcpdm->up_threshold = MCPDM_UP_THRES_MAX - 3;
else
mcpdm->up_threshold = 2;
- } else if (mcpdm->abe_mode != dai_abe_mode) {
+ } else if (mcpdm->active_dai != dai->id) {
dev_err(mcpdm->dev, "Trying %s, while McPDM is in %s.\n",
- dai_abe_mode ? "ABE mode" : "Legacy mode",
- mcpdm->abe_mode ? "ABE mode" : "Legacy mode");
+ dai->id ? "ABE mode" : "Legacy mode",
+ mcpdm->active_dai ? "ABE mode" : "Legacy mode");
ret = -EINVAL;
}
if (!dai->active) {
if (omap_mcpdm_active(mcpdm)) {
- if (mcpdm->abe_mode == MCPDM_LEGACY_MODE) {
+ if (dai->id == OMAP_MCPDM_LEGACY_DAI) {
omap_mcpdm_stop(mcpdm);
omap_mcpdm_close_streams(mcpdm);
} else {
- omap_abe_port_disable(mcpdm->abe,
+ omap_abe_port_disable(mcpdm->aess,
mcpdm->dl_port);
- omap_abe_port_disable(mcpdm->abe,
+ omap_abe_port_disable(mcpdm->aess,
mcpdm->ul_port);
usleep_range(250, 300);
omap_mcpdm_stop(mcpdm);
dma_data = snd_soc_dai_get_dma_data(dai, substream);
/* ABE DAIs have fixed channels */
- if ((dai->id & MCPDM_DAI_MODE_MASK) == MCPDM_ABE_MODE) {
+ if (dai->id == OMAP_MCPDM_ABE_DAI) {
mcpdm->dn_channels = MCPDM_PDM_DN_MASK | MCPDM_CMD_INT;
mcpdm->up_channels = MCPDM_PDM_UPLINK_EN(1) |
MCPDM_PDM_UPLINK_EN(2);
if (omap_mcpdm_active(mcpdm))
return 0;
- if (mcpdm->abe_mode == MCPDM_ABE_MODE) {
+ if (dai->id == OMAP_MCPDM_ABE_DAI) {
/* Check if ABE McPDM DL is already started */
- if ((omap_abe_port_is_enabled(mcpdm->abe, mcpdm->dl_port)) ||
- (omap_abe_port_is_enabled(mcpdm->abe, mcpdm->ul_port)))
+ if ((omap_abe_port_is_enabled(mcpdm->aess, mcpdm->dl_port)) ||
+ (omap_abe_port_is_enabled(mcpdm->aess, mcpdm->ul_port)))
return 0;
omap_abe_pm_get(platform);
/* start ATC before McPDM IP */
- omap_abe_port_enable(mcpdm->abe, mcpdm->dl_port);
- omap_abe_port_enable(mcpdm->abe, mcpdm->ul_port);
+ omap_abe_port_enable(mcpdm->aess, mcpdm->dl_port);
+ omap_abe_port_enable(mcpdm->aess, mcpdm->ul_port);
/* wait 250us for ABE tick */
usleep_range(250, 300);
struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
int ret;
+ mcpdm->aess = omap_abe_port_mgr_get();
+
+ mcpdm->dl_port = omap_abe_port_open(mcpdm->aess,
+ OMAP_ABE_BE_PORT_PDM_DL1);
+ if (mcpdm->dl_port == NULL) {
+ omap_abe_port_mgr_put(mcpdm->aess);
+ return -EINVAL;
+ }
+
+ mcpdm->ul_port = omap_abe_port_open(mcpdm->aess,
+ OMAP_ABE_BE_PORT_PDM_UL1);
+ if (mcpdm->ul_port == NULL) {
+ omap_abe_port_close(mcpdm->aess, mcpdm->dl_port);
+ omap_abe_port_mgr_put(mcpdm->aess);
+ return -EINVAL;
+ }
+
pm_runtime_enable(mcpdm->dev);
/* Disable lines while request is ongoing */
pm_runtime_get_sync(mcpdm->dev);
omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, 0x00);
- ret = request_irq(mcpdm->irq, omap_mcpdm_irq_handler,
+ ret = devm_request_irq(mcpdm->dev, mcpdm->irq, omap_mcpdm_irq_handler,
0, "McPDM", (void *)mcpdm);
pm_runtime_put_sync(mcpdm->dev);
if (ret) {
dev_err(mcpdm->dev, "Request for IRQ failed\n");
pm_runtime_disable(mcpdm->dev);
+
+ omap_abe_port_close(mcpdm->aess, mcpdm->dl_port);
+ omap_abe_port_close(mcpdm->aess, mcpdm->ul_port);
+ omap_abe_port_mgr_put(mcpdm->aess);
}
/* Configure McPDM threshold values */
{
struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
- free_irq(mcpdm->irq, (void *)mcpdm);
pm_runtime_disable(mcpdm->dev);
+ omap_abe_port_close(mcpdm->aess, mcpdm->dl_port);
+ omap_abe_port_close(mcpdm->aess, mcpdm->ul_port);
+ omap_abe_port_mgr_put(mcpdm->aess);
+
return 0;
}
#define OMAP_MCPDM_RATES (SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
#define OMAP_MCPDM_FORMATS SNDRV_PCM_FMTBIT_S32_LE
-#define MCPDM_LEGACY_DAI (MCPDM_LEGACY_MODE | (0 << 4))
-#define MCPDM_ABE_DAI_DL1 (MCPDM_ABE_MODE | (1 << 4))
-#define MCPDM_ABE_DAI_DL2 (MCPDM_ABE_MODE | (2 << 4))
-#define MCPDM_ABE_DAI_UL1 (MCPDM_ABE_MODE | (4 << 4))
-
static struct snd_soc_dai_driver omap_mcpdm_dai[] = {
{
.name = "mcpdm-legacy",
- .id = MCPDM_LEGACY_DAI,
+ .id = OMAP_MCPDM_LEGACY_DAI,
.probe = omap_mcpdm_probe,
.remove = omap_mcpdm_remove,
.probe_order = SND_SOC_COMP_ORDER_LATE,
},
.ops = &omap_mcpdm_dai_ops,
},
-#if defined(CONFIG_SND_OMAP_SOC_ABE) ||\
- defined(CONFIG_SND_OMAP_SOC_ABE_MODULE)
{
- .name = "mcpdm-dl1",
- .id = MCPDM_ABE_DAI_DL1,
+ .name = "mcpdm-abe",
+ .id = OMAP_MCPDM_ABE_DAI,
.probe_order = SND_SOC_COMP_ORDER_LATE,
.remove_order = SND_SOC_COMP_ORDER_EARLY,
.playback = {
.rates = OMAP_MCPDM_RATES,
.formats = OMAP_MCPDM_FORMATS,
},
- .ops = &omap_mcpdm_dai_ops,
-},
-{
- .name = "mcpdm-dl2",
- .id = MCPDM_ABE_DAI_DL2,
- .probe_order = SND_SOC_COMP_ORDER_LATE,
- .remove_order = SND_SOC_COMP_ORDER_EARLY,
- .playback = {
- .channels_min = 1,
- .channels_max = 2,
- .rates = OMAP_MCPDM_RATES,
- .formats = OMAP_MCPDM_FORMATS,
- },
- .ops = &omap_mcpdm_dai_ops,
-},
-{
- .name = "mcpdm-ul1",
- .id = MCPDM_ABE_DAI_UL1,
- .probe_order = SND_SOC_COMP_ORDER_LATE,
- .remove_order = SND_SOC_COMP_ORDER_EARLY,
.capture = {
.channels_min = 1,
.channels_max = 2,
},
.ops = &omap_mcpdm_dai_ops,
},
-#endif
};
void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd,
{
struct omap_mcpdm *mcpdm;
struct resource *res;
- int ret;
+ int ret, nr_dai;
mcpdm = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcpdm), GFP_KERNEL);
if (!mcpdm)
omap_mcpdm_dai_dma_params[0].port_addr = res->start + MCPDM_REG_DN_DATA;
omap_mcpdm_dai_dma_params[1].port_addr = res->start + MCPDM_REG_UP_DATA;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (res == NULL)
- return -ENOMEM;
-
res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "dn_link");
if (!res)
return -ENODEV;
if (res == NULL)
return -ENOMEM;
- if (!devm_request_mem_region(&pdev->dev, res->start,
- resource_size(res), "McPDM"))
- return -EBUSY;
-
- mcpdm->io_base = devm_ioremap(&pdev->dev, res->start,
- resource_size(res));
- if (!mcpdm->io_base)
+ mcpdm->io_base = devm_request_and_ioremap(&pdev->dev, res);
+ if (!mcpdm->io_base) {
+ dev_err(&pdev->dev, "cannot remap\n");
return -ENOMEM;
+ }
mcpdm->irq = platform_get_irq(pdev, 0);
if (mcpdm->irq < 0)
#if defined(CONFIG_SND_OMAP_SOC_ABE) ||\
defined(CONFIG_SND_OMAP_SOC_ABE_MODULE)
-
- mcpdm->abe = omap_abe_port_mgr_get();
-
- mcpdm->dl_port = omap_abe_port_open(mcpdm->abe,
- OMAP_ABE_BE_PORT_PDM_DL1);
- if (mcpdm->dl_port == NULL) {
- omap_abe_port_mgr_put(mcpdm->abe);
- return -EINVAL;
- }
-
- mcpdm->ul_port = omap_abe_port_open(mcpdm->abe,
- OMAP_ABE_BE_PORT_PDM_UL1);
- if (mcpdm->ul_port == NULL) {
- omap_abe_port_close(mcpdm->abe, mcpdm->dl_port);
- omap_abe_port_mgr_put(mcpdm->abe);
- return -EINVAL;
- }
+ nr_dai = ARRAY_SIZE(omap_mcpdm_dai);
+#else
+ nr_dai = 1;
#endif
- ret = snd_soc_register_dais(&pdev->dev, omap_mcpdm_dai,
- ARRAY_SIZE(omap_mcpdm_dai));
- if (!ret)
- return 0;
+ ret = snd_soc_register_dais(&pdev->dev, omap_mcpdm_dai, nr_dai);
-#if defined(CONFIG_SND_OMAP_SOC_ABE) ||\
- defined(CONFIG_SND_OMAP_SOC_ABE_MODULE)
- omap_abe_port_close(mcpdm->abe, mcpdm->dl_port);
- omap_abe_port_close(mcpdm->abe, mcpdm->ul_port);
- omap_abe_port_mgr_put(mcpdm->abe);
-#endif
return ret;
}
static int asoc_mcpdm_remove(struct platform_device *pdev)
{
- struct omap_mcpdm *mcpdm = platform_get_drvdata(pdev);
-
snd_soc_unregister_dai(&pdev->dev);
-#if defined(CONFIG_SND_OMAP_SOC_ABE) ||\
- defined(CONFIG_SND_OMAP_SOC_ABE_MODULE)
- omap_abe_port_close(mcpdm->abe, mcpdm->dl_port);
- omap_abe_port_close(mcpdm->abe, mcpdm->ul_port);
- omap_abe_port_mgr_put(mcpdm->abe);
-#endif
-
return 0;
}