OMAPDSS: fix programming of the control module

The omapdss driver uses regmap_update_bits to program
CTRL_CORE_DSS_PLL_CONTROL_OFF register, but does not shift the value to
be written properly. This leads to the omapdss always writing 0 to the
bits.

This works, because for PLL enable bits, 0 means "enable", and for the
mux bits 0 means the mux setting that we want to use. So we fail to
disable the PLL, and fail to restore the mux to its original value.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Jyri Sarha <jsarha@ti.com>

diff --git a/drivers/video/fbdev/omap2/dss/dss.c b/drivers/video/fbdev/omap2/dss/dss.c
index abe17f01fa63ee7dad2e3143e6c09fd93a61db3f..11626611efa89cf0afb5d621e46342ca8dae2607 100644 (file)
--- a/drivers/video/fbdev/omap2/dss/dss.c
+++ b/drivers/video/fbdev/omap2/dss/dss.c
@@ -168,7 +168,7 @@ void dss_ctrl_pll_enable(int pll_id, bool enable)
                return;
 
        regmap_update_bits(dss.syscon, CTRL_CORE_DSS_PLL_CONTROL_OFF,
-               1 << pll_id, !enable);
+               1 << pll_id, (!enable) << pll_id);
 }
 
 void dss_ctrl_hdmi_pll_enable(bool enable)
@@ -177,7 +177,7 @@ void dss_ctrl_hdmi_pll_enable(bool enable)
                return;
 
        regmap_update_bits(dss.syscon, CTRL_CORE_DSS_PLL_CONTROL_OFF,
-               1 << 2, !enable);
+               1 << 2, (!enable) << 2);
 }
 
 void dss_ctrl_pll_set_control_mux(int pll_id, enum omap_channel channel)
@@ -240,7 +240,7 @@ void dss_ctrl_pll_set_control_mux(int pll_id, enum omap_channel channel)
        }
 
        regmap_update_bits(dss.syscon, CTRL_CORE_DSS_PLL_CONTROL_OFF,
-               0x3 << shift, val);
+               0x3 << shift, val << shift);
 }
 
 void dss_sdi_init(int datapairs)