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raw | patch | inline | side by side (parent: b3a26e7)
raw | patch | inline | side by side (parent: b3a26e7)
author | Archit Taneja <archit@ti.com> | |
Mon, 6 May 2013 15:36:06 +0000 (17:36 +0200) | ||
committer | Archit Taneja <archit@ti.com> | |
Thu, 30 May 2013 23:03:37 +0000 (04:33 +0530) |
The hdmi driver supports deep color modes. However, there is a specific check
which doesn't allow 1080p timings or higher to be shown 36 bit deep color mode.
The more generic check would be to check if the pixel clock in a deep color mode
is less than the maximum pixel clock the TV overlay manager can support for the
given OMAP. Make this change.
Also, make sure that hdmi.dssdev is assigned by the end of probe, this param is
needed by the deepcolor sysfs attribute file.
Signed-off-by: Archit Taneja <archit@ti.com>
which doesn't allow 1080p timings or higher to be shown 36 bit deep color mode.
The more generic check would be to check if the pixel clock in a deep color mode
is less than the maximum pixel clock the TV overlay manager can support for the
given OMAP. Make this change.
Also, make sure that hdmi.dssdev is assigned by the end of probe, this param is
needed by the deepcolor sysfs attribute file.
Signed-off-by: Archit Taneja <archit@ti.com>
index f69fe0c21afe787d3f186bafb54c2bd8014a8f20..11392f8ecd5e7f02cfaca3d721630aad1960934d 100644 (file)
* scaler cannot scale a image with width more than 768.
*/
[FEAT_PARAM_LINEWIDTH] = { 1, 768 },
+ [FEAT_PARAM_HDMI_PCLK] = { 0, 0 },
};
static const struct dss_param_range omap3_dss_param_range[] = {
[FEAT_PARAM_DSI_FCK] = { 0, 173000000 },
[FEAT_PARAM_DOWNSCALE] = { 1, 4 },
[FEAT_PARAM_LINEWIDTH] = { 1, 1024 },
+ [FEAT_PARAM_HDMI_PCLK] = { 0, 0 },
};
static const struct dss_param_range omap4_dss_param_range[] = {
[FEAT_PARAM_DSI_FCK] = { 0, 170000000 },
[FEAT_PARAM_DOWNSCALE] = { 1, 4 },
[FEAT_PARAM_LINEWIDTH] = { 1, 2048 },
+ [FEAT_PARAM_HDMI_PCLK] = { 1, 185675000 },
};
static const struct dss_param_range omap5_dss_param_range[] = {
[FEAT_PARAM_DSI_FCK] = { 0, 170000000 },
[FEAT_PARAM_DOWNSCALE] = { 1, 4 },
[FEAT_PARAM_LINEWIDTH] = { 1, 2048 },
+ [FEAT_PARAM_HDMI_PCLK] = { 1, 186000000 },
};
static const enum dss_feat_id omap2_dss_feat_list[] = {
index 188ceececf5082a21e261f533948367c14d5542c..0e8fccf79ddede31cdc68bb36fcd2707d0972d79 100644 (file)
FEAT_PARAM_DSI_FCK,
FEAT_PARAM_DOWNSCALE,
FEAT_PARAM_LINEWIDTH,
+ FEAT_PARAM_HDMI_PCLK,
};
/* DSS Feature Functions */
index 6719c2d3d64cce0fcd231c0eae7c41e9d41c8e12..147c0a32671ab3a6037c3d1a07271aaeb62d0036 100644 (file)
phy = (p->pixel_clock * 125) / 100 ;
break;
case HDMI_DEEP_COLOR_36BIT:
- if (p->pixel_clock >= 148500) {
+ phy = (p->pixel_clock * 150) / 100;
+
+ if (phy >= dss_feat_get_param_max(FEAT_PARAM_HDMI_PCLK)) {
DSSERR("36 bit deep color not supported for the pixel clock %d\n",
p->pixel_clock);
goto err_deep_color;
}
- phy = (p->pixel_clock * 150) / 100;
break;
case HDMI_DEEP_COLOR_24BIT:
default:
index 9574f4dbddc9661ef7bd3b4b37c8adf90aa7cbf6..95090f27daaf6c26d363f153900536d5f48021f2 100644 (file)
omapdss_hdmi_display_set_timing(dssdev, &dssdev->panel.timings);
+ hdmi.dssdev = dssdev;
+
return 0;
}