clk: ti: clk-7xx: Configure ATL1 and ATL2 clocks

Set the parent of the atl_gfclk_mux and configure the rate
for atl1 and atl2.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>

diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
index db92379ec18ac8bc6343d16548a9e12777ef721d..fcfc5e8db5ade1a4aedb2779d5a3f6b753c6631f 100644 (file)
--- a/drivers/clk/ti/clk-7xx.c
+++ b/drivers/clk/ti/clk-7xx.c
@@ -18,7 +18,7 @@
 
 #define DRA7_DPLL_ABE_DEFFREQ                          180633600
 #define DRA7_DPLL_GMAC_DEFFREQ                         1000000000
-
+#define DRA7_ATL_DEFFREQ                               5644800
 
 static struct ti_dt_clk dra7xx_clks[] = {
        DT_CLK(NULL, "atl_clkin0_ck", "atl_clkin0_ck"),
@@ -308,6 +308,7 @@ int __init dra7xx_dt_clk_init(void)
 {
        int rc;
        struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck, *dss_deshdcp_ck;
+       struct clk *atl_fck, *atl_parent;
 
        ti_dt_clocks_register(dra7xx_clks);
 
@@ -338,5 +339,21 @@ int __init dra7xx_dt_clk_init(void)
        if (rc)
                pr_err("%s: failed to enable DESHDCP clock\n", __func__);
 
+       atl_fck = clk_get_sys(NULL, "atl_gfclk_mux");
+       atl_parent = clk_get_sys(NULL, "dpll_abe_m2_ck");
+       rc = clk_set_parent(atl_fck, atl_parent);
+       if (rc)
+               pr_err("%s: failed to reparent atl_gfclk_mux\n", __func__);
+
+       atl_fck = clk_get_sys(NULL, "atl_clkin2_ck");
+       rc = clk_set_rate(atl_fck, DRA7_ATL_DEFFREQ);
+       if (rc)
+               pr_err("%s: failed to set atl_clkin2_ck\n", __func__);
+
+       atl_fck = clk_get_sys(NULL, "atl_clkin1_ck");
+       rc = clk_set_rate(atl_fck, DRA7_ATL_DEFFREQ);
+       if (rc)
+               pr_err("%s: failed to set atl_clkin1_ck\n", __func__);
+
        return rc;
 }