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raw | patch | inline | side by side (parent: f103cd7)
raw | patch | inline | side by side (parent: f103cd7)
author | Roger Quadros <rogerq@ti.com> | |
Fri, 29 Aug 2014 16:11:52 +0000 (19:11 +0300) | ||
committer | Sekhar Nori <nsekhar@ti.com> | |
Mon, 1 Sep 2014 08:47:05 +0000 (14:17 +0530) |
Although RESET state of LIMITEDADDRESS bit in GPMC_CONFIG register
is 0 (i.e. A26-A11 enabled), faulty bootloaders might accidentally
set this bit. e.g. u-boot 2014.07 with CONFIG_NOR disabled.
Explicity disable LIMITEDADDRESS bit for non NAND devices so that
they can always work.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
is 0 (i.e. A26-A11 enabled), faulty bootloaders might accidentally
set this bit. e.g. u-boot 2014.07 with CONFIG_NOR disabled.
Explicity disable LIMITEDADDRESS bit for non NAND devices so that
they can always work.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
arch/arm/mach-omap2/gpmc.c | patch | blob | history |
index 7727ad6688b488abcea3f061c5cff602f00ebb65..cf7ed0ff3849fdc8a9eb808afb4d4dd04b069b2e 100644 (file)
#define GPMC_ECC_CTRL_ECCREG8 0x008
#define GPMC_ECC_CTRL_ECCREG9 0x009
+#define GPMC_CONFIG_LIMITEDADDRESS BIT(1)
+
#define GPMC_CONFIG2_CSEXTRADELAY BIT(7)
#define GPMC_CONFIG3_ADVEXTRADELAY BIT(7)
#define GPMC_CONFIG4_OEEXTRADELAY BIT(7)
struct resource res;
unsigned long base;
int ret, cs;
+ u32 val;
if (of_property_read_u32(child, "reg", &cs) < 0) {
dev_err(&pdev->dev, "%s has no 'reg' property\n",
goto err;
}
+ /* Clear limited address i.e. enable A26-A11 */
+ val = gpmc_read_reg(GPMC_CONFIG);
+ val &= ~GPMC_CONFIG_LIMITEDADDRESS;
+ gpmc_write_reg(GPMC_CONFIG, val);
+
no_timings:
if (of_platform_device_create(child, NULL, &pdev->dev))
return 0;