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pinctrl: mvebu: armada-xp: remove non-existing VDD cpu_pd functions
authorThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tue, 9 Jun 2015 16:46:57 +0000 (18:46 +0200)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Mon, 3 Aug 2015 16:29:52 +0000 (09:29 -0700)
commit 80b3d04feab5e69d51cb2375eb989a7165e43e3b upstream.

The latest version of the Armada XP datasheet no longer documents the
VDD cpu_pd functions, which might indicate they are not working and/or
not supported. This commit ensures the pinctrl driver matches the
datasheet.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Fixes: 463e270f766a ("pinctrl: mvebu: add pinctrl driver for Armada XP")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt patch | blob | history
drivers/pinctrl/mvebu/pinctrl-armada-xp.c patch | blob | history

diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
index 797b3d5e2e58d6c7e27b6c648b01592e19fd8fd0..0ba220bdb17f2d051b35a5523f69540a9e3039a8 100644 (file)
--- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
@@ -43,13 +43,13 @@ mpp22         22       gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt)
 mpp23         23       gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt)
 mpp24         24       gpio, lcd(hsync), sata1(prsnt), tdm(rst)
 mpp25         25       gpio, lcd(vsync), sata0(prsnt), tdm(pclk)
-mpp26         26       gpio, lcd(clk), tdm(fsync), vdd(cpu1-pd)
+mpp26         26       gpio, lcd(clk), tdm(fsync)
 mpp27         27       gpio, lcd(e), tdm(dtx), ptp(trig)
 mpp28         28       gpio, lcd(pwm), tdm(drx), ptp(evreq)
-mpp29         29       gpio, lcd(ref-clk), tdm(int0), ptp(clk), vdd(cpu0-pd)
+mpp29         29       gpio, lcd(ref-clk), tdm(int0), ptp(clk)
 mpp30         30       gpio, tdm(int1), sd0(clk)
-mpp31         31       gpio, tdm(int2), sd0(cmd), vdd(cpu0-pd)
-mpp32         32       gpio, tdm(int3), sd0(d0), vdd(cpu1-pd)
+mpp31         31       gpio, tdm(int2), sd0(cmd)
+mpp32         32       gpio, tdm(int3), sd0(d0)
 mpp33         33       gpio, tdm(int4), sd0(d1), mem(bat)
 mpp34         34       gpio, tdm(int5), sd0(d2), sata0(prsnt)
 mpp35         35       gpio, tdm(int6), sd0(d3), sata1(prsnt)
@@ -57,14 +57,11 @@ mpp36         36       gpio, spi(mosi)
 mpp37         37       gpio, spi(miso)
 mpp38         38       gpio, spi(sck)
 mpp39         39       gpio, spi(cs0)
-mpp40         40       gpio, spi(cs1), uart2(cts), lcd(vga-hsync), vdd(cpu1-pd),
-                       pcie(clkreq0)
+mpp40         40       gpio, spi(cs1), uart2(cts), lcd(vga-hsync), pcie(clkreq0)
 mpp41         41       gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt),
                        pcie(clkreq1)
-mpp42         42       gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer),
-                       vdd(cpu0-pd)
-mpp43         43       gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout),
-                       vdd(cpu2-3-pd){1}
+mpp42         42       gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer)
+mpp43         43       gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout)
 mpp44         44       gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2),
                        mem(bat)
 mpp45         45       gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt)
@@ -83,9 +80,9 @@ mpp51         51       gpio, dev(ad16)
 mpp52         52       gpio, dev(ad17)
 mpp53         53       gpio, dev(ad18)
 mpp54         54       gpio, dev(ad19)
-mpp55         55       gpio, dev(ad20), vdd(cpu0-pd)
-mpp56         56       gpio, dev(ad21), vdd(cpu1-pd)
-mpp57         57       gpio, dev(ad22), vdd(cpu2-3-pd){1}
+mpp55         55       gpio, dev(ad20)
+mpp56         56       gpio, dev(ad21)
+mpp57         57       gpio, dev(ad22)
 mpp58         58       gpio, dev(ad23)
 mpp59         59       gpio, dev(ad24)
 mpp60         60       gpio, dev(ad25)
@@ -95,6 +92,3 @@ mpp63         63       gpio, dev(ad28)
 mpp64         64       gpio, dev(ad29)
 mpp65         65       gpio, dev(ad30)
 mpp66         66       gpio, dev(ad31)
-
-Notes:
-* {1} vdd(cpu2-3-pd) only available on mv78460.
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
index 3f8910b292da1803f3767704850466ea2cd5035b..6a7f0c2011f626513b330ab2b7ac2c8e3a714d3a 100644 (file)
--- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
@@ -14,10 +14,7 @@
  * available: mv78230, mv78260 and mv78460. From a pin muxing
  * perspective, the mv78230 has 49 MPP pins. The mv78260 and mv78460
  * both have 67 MPP pins (more GPIOs and address lines for the memory
- * bus mainly). The only difference between the mv78260 and the
- * mv78460 in terms of pin muxing is the addition of two functions on
- * pins 43 and 56 to access the VDD of the CPU2 and 3 (mv78260 has two
- * cores, mv78460 has four cores).
+ * bus mainly).
  */
 
 #include <linux/err.h>
@@ -169,8 +166,7 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
        MPP_MODE(26,
                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
                 MPP_VAR_FUNCTION(0x3, "tdm", "fsync",      V_MV78230_PLUS),
-                MPP_VAR_FUNCTION(0x4, "lcd", "clk",        V_MV78230_PLUS),
-                MPP_VAR_FUNCTION(0x5, "vdd", "cpu1-pd",    V_MV78230_PLUS)),
+                MPP_VAR_FUNCTION(0x4, "lcd", "clk",        V_MV78230_PLUS)),
        MPP_MODE(27,
                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
                 MPP_VAR_FUNCTION(0x1, "ptp", "trig",       V_MV78230_PLUS),
@@ -185,8 +181,7 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
                 MPP_VAR_FUNCTION(0x1, "ptp", "clk",        V_MV78230_PLUS),
                 MPP_VAR_FUNCTION(0x3, "tdm", "int0",       V_MV78230_PLUS),
-                MPP_VAR_FUNCTION(0x4, "lcd", "ref-clk",    V_MV78230_PLUS),
-                MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd",    V_MV78230_PLUS)),
+                MPP_VAR_FUNCTION(0x4, "lcd", "ref-clk",    V_MV78230_PLUS)),
        MPP_MODE(30,
                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
                 MPP_VAR_FUNCTION(0x1, "sd0", "clk",        V_MV78230_PLUS),
@@ -194,13 +189,11 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
        MPP_MODE(31,
                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
                 MPP_VAR_FUNCTION(0x1, "sd0", "cmd",        V_MV78230_PLUS),
-                MPP_VAR_FUNCTION(0x3, "tdm", "int2",       V_MV78230_PLUS),
-                MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd",    V_MV78230_PLUS)),
+                MPP_VAR_FUNCTION(0x3, "tdm", "int2",       V_MV78230_PLUS)),
        MPP_MODE(32,
                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
                 MPP_VAR_FUNCTION(0x1, "sd0", "d0",         V_MV78230_PLUS),
-                MPP_VAR_FUNCTION(0x3, "tdm", "int3",       V_MV78230_PLUS),
-                MPP_VAR_FUNCTION(0x5, "vdd", "cpu1-pd",    V_MV78230_PLUS)),
+                MPP_VAR_FUNCTION(0x3, "tdm", "int3",       V_MV78230_PLUS)),
        MPP_MODE(33,
                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
                 MPP_VAR_FUNCTION(0x1, "sd0", "d1",         V_MV78230_PLUS),
@@ -232,7 +225,6 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
                 MPP_VAR_FUNCTION(0x1, "spi", "cs1",        V_MV78230_PLUS),
                 MPP_VAR_FUNCTION(0x2, "uart2", "cts",      V_MV78230_PLUS),
-                MPP_VAR_FUNCTION(0x3, "vdd", "cpu1-pd",    V_MV78230_PLUS),
                 MPP_VAR_FUNCTION(0x4, "lcd", "vga-hsync",  V_MV78230_PLUS),
                 MPP_VAR_FUNCTION(0x5, "pcie", "clkreq0",   V_MV78230_PLUS)),
        MPP_MODE(41,
@@ -247,15 +239,13 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
                 MPP_VAR_FUNCTION(0x1, "uart2", "rxd",      V_MV78230_PLUS),
                 MPP_VAR_FUNCTION(0x2, "uart0", "cts",      V_MV78230_PLUS),
                 MPP_VAR_FUNCTION(0x3, "tdm", "int7",       V_MV78230_PLUS),
-                MPP_VAR_FUNCTION(0x4, "tdm-1", "timer",    V_MV78230_PLUS),
-                MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd",    V_MV78230_PLUS)),
+                MPP_VAR_FUNCTION(0x4, "tdm-1", "timer",    V_MV78230_PLUS)),
        MPP_MODE(43,
                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
                 MPP_VAR_FUNCTION(0x1, "uart2", "txd",      V_MV78230_PLUS),
                 MPP_VAR_FUNCTION(0x2, "uart0", "rts",      V_MV78230_PLUS),
                 MPP_VAR_FUNCTION(0x3, "spi", "cs3",        V_MV78230_PLUS),
-                MPP_VAR_FUNCTION(0x4, "pcie", "rstout",    V_MV78230_PLUS),
-                MPP_VAR_FUNCTION(0x5, "vdd", "cpu2-3-pd",  V_MV78460)),
+                MPP_VAR_FUNCTION(0x4, "pcie", "rstout",    V_MV78230_PLUS)),
        MPP_MODE(44,
                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
                 MPP_VAR_FUNCTION(0x1, "uart2", "cts",      V_MV78230_PLUS),
@@ -306,16 +296,13 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
                 MPP_VAR_FUNCTION(0x1, "dev", "ad19",       V_MV78260_PLUS)),
        MPP_MODE(55,
                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
-                MPP_VAR_FUNCTION(0x1, "dev", "ad20",       V_MV78260_PLUS),
-                MPP_VAR_FUNCTION(0x2, "vdd", "cpu0-pd",    V_MV78260_PLUS)),
+                MPP_VAR_FUNCTION(0x1, "dev", "ad20",       V_MV78260_PLUS)),
        MPP_MODE(56,
                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
-                MPP_VAR_FUNCTION(0x1, "dev", "ad21",       V_MV78260_PLUS),
-                MPP_VAR_FUNCTION(0x2, "vdd", "cpu1-pd",    V_MV78260_PLUS)),
+                MPP_VAR_FUNCTION(0x1, "dev", "ad21",       V_MV78260_PLUS)),
        MPP_MODE(57,
                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
-                MPP_VAR_FUNCTION(0x1, "dev", "ad22",       V_MV78260_PLUS),
-                MPP_VAR_FUNCTION(0x2, "vdd", "cpu2-3-pd",  V_MV78460)),
+                MPP_VAR_FUNCTION(0x1, "dev", "ad22",       V_MV78260_PLUS)),
        MPP_MODE(58,
                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
                 MPP_VAR_FUNCTION(0x1, "dev", "ad23",       V_MV78260_PLUS)),
Integrated Android Product SDK Hardened Software - Kernel Changes for Android Video and Display Subsystems.