author | Tero Kristo <t-kristo@ti.com> | |
Mon, 27 May 2013 14:06:42 +0000 (17:06 +0300) | ||
committer | Tero Kristo <t-kristo@ti.com> | |
Mon, 27 May 2013 14:06:42 +0000 (17:06 +0300) |
Conflicts:
arch/arm/mach-omap2/clockdomain.h
arch/arm/mach-omap2/control.h
arch/arm/mach-omap2/omap-hotplug.c
arch/arm/mach-omap2/omap-mpuss-lowpower.c
arch/arm/mach-omap2/pm_omap4plus.c
Signed-off-by: Tero Kristo <t-kristo@ti.com>
arch/arm/mach-omap2/clockdomain.h
arch/arm/mach-omap2/control.h
arch/arm/mach-omap2/omap-hotplug.c
arch/arm/mach-omap2/omap-mpuss-lowpower.c
arch/arm/mach-omap2/pm_omap4plus.c
Signed-off-by: Tero Kristo <t-kristo@ti.com>
20 files changed:
diff --cc arch/arm/configs/omap2plus_defconfig
index e5b58cd8d5c0456471c60d651861e3830b8fb13f,dfa2f6d8af2c2f7143c7fcf45c35c89122911927..4a20e7d62cbfa886f3bc2f74ed4bd8cbcc2c645d
CONFIG_GPIO_TWL4030=y
CONFIG_W1=y
CONFIG_POWER_SUPPLY=y
+ CONFIG_SENSORS_LM75=m
CONFIG_WATCHDOG=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_GOV_FAIR_SHARE=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_GOV_USER_SPACE=y
+CONFIG_CPU_THERMAL=y
CONFIG_OMAP_WATCHDOG=y
CONFIG_TWL4030_WATCHDOG=y
CONFIG_MFD_TPS65217=y
+ CONFIG_MFD_TPS65910=y
CONFIG_REGULATOR_TWL4030=y
+CONFIG_MFD_PALMAS=y
+CONFIG_MFD_PALMAS_GPADC=y
+CONFIG_MFD_PALMAS_PWM=y
+CONFIG_MFD_PALMAS_RESOURCE=y
+CONFIG_REGULATOR_PALMAS=y
CONFIG_REGULATOR_TPS65023=y
CONFIG_REGULATOR_TPS6507X=y
CONFIG_REGULATOR_TPS65217=y
diff --cc arch/arm/mach-omap2/Kconfig
index 00d62eaeca4b6889783f49a8dc07ea0c2a07b4c4,5e91009ef16871a6d07fcfa7a81305939c7cae49..d02efdaa8348a10654086413e6698731348e1143
config SOC_HAS_OMAP2_SDRC
bool "OMAP2 SDRAM Controller support"
+config ARCH_HAS_BANDGAP
+ bool
+
config SOC_HAS_REALTIME_COUNTER
bool "Real time free running counter"
- depends on SOC_OMAP5
+ depends on SOC_OMAP5 || SOC_DRA7XX
default y
config ARCH_OMAP2
diff --cc arch/arm/mach-omap2/Makefile
index 7a43c6329af020ff4c6cfb8a01d87ed31611f762,e7108e5a86e879dc47d9f26b3f4fab8b4369e71d..fa3b96c543a3ef114f70241ea4bf463ef764eb7a
obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
obj-$(CONFIG_ARCH_OMAP4) += $(omap4plus-common-pm)
obj-$(CONFIG_SOC_OMAP5) += $(omap4plus-common-pm)
+obj-$(CONFIG_SOC_AM33XX) += pm33xx.o sleep33xx.o
obj-$(CONFIG_PM_DEBUG) += pm-debug.o
+ obj-$(CONFIG_SOC_DRA7XX) += omap-mpuss-lowpower.o
obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o
obj-$(CONFIG_POWER_AVS_OMAP_CLASS3) += smartreflex-class3.o
diff --cc arch/arm/mach-omap2/board-generic.c
Simple merge
diff --cc arch/arm/mach-omap2/cclock33xx_data.c
Simple merge
diff --cc arch/arm/mach-omap2/clock.h
Simple merge
diff --cc arch/arm/mach-omap2/clockdomain.h
index aa800679c80a2f3fa224665ca87b016c924a6fc6,5700924f49a07a3f813928667c9bc5bee3642b66..d767b0199874afe9f2fbf258ef82896b1818281b
extern void __init am33xx_clockdomains_init(void);
extern void __init omap44xx_clockdomains_init(void);
extern void __init omap54xx_clockdomains_init(void);
-extern void _clkdm_add_autodeps(struct clockdomain *clkdm);
-extern void _clkdm_del_autodeps(struct clockdomain *clkdm);
+ extern void __init dra7xx_clockdomains_init(void);
+
+extern void clkdm_add_autodeps(struct clockdomain *clkdm);
+extern void clkdm_del_autodeps(struct clockdomain *clkdm);
extern struct clkdm_ops omap2_clkdm_operations;
extern struct clkdm_ops omap3_clkdm_operations;
diff --cc arch/arm/mach-omap2/common.h
Simple merge
diff --cc arch/arm/mach-omap2/control.h
index 371e9aeb6ae654974f7181ba65a9c2f397006911,17a0128570934cac8b56241bc26107f29cffb516..379b14bab5e3cc2567a73cb77c0d18f129c2c8f1
#define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH 0x2
#define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK (0x3 << 22)
+#define AM33XX_DDR_IO_CTRL 0x0E04
+#define AM33XX_VTP0_CTRL_REG 0x0E0C
+
+/* AM33XX VTP0_CTRL_REG bits */
+#define AM33XX_VTP_CTRL_START_EN (1 << 0)
+#define AM33XX_VTP_CTRL_LOCK_EN (1 << 4)
+#define AM33XX_VTP_CTRL_READY (1 << 5)
+#define AM33XX_VTP_CTRL_ENABLE (1 << 6)
+
+/* AM33XX M3_TXEV_EOI register */
+#define AM33XX_CONTROL_M3_TXEV_EOI 0x1324
+
+#define AM33XX_M3_TXEV_ACK (0x1 << 0)
+#define AM33XX_M3_TXEV_ENABLE (0x0 << 0)
+
+/* AM33XX IPC message registers */
+#define AM33XX_CONTROL_IPC_MSG_REG0 0x1328
+#define AM33XX_CONTROL_IPC_MSG_REG1 0x132C
+#define AM33XX_CONTROL_IPC_MSG_REG2 0x1330
+#define AM33XX_CONTROL_IPC_MSG_REG3 0x1334
+#define AM33XX_CONTROL_IPC_MSG_REG4 0x1338
+#define AM33XX_CONTROL_IPC_MSG_REG5 0x133C
+#define AM33XX_CONTROL_IPC_MSG_REG6 0x1340
+#define AM33XX_CONTROL_IPC_MSG_REG7 0x1344
+
+#define AM33XX_DDR_CMD0_IOCTRL 0x1404
+#define AM33XX_DDR_CMD1_IOCTRL 0x1408
+#define AM33XX_DDR_CMD2_IOCTRL 0x140C
+#define AM33XX_DDR_DATA0_IOCTRL 0x1440
+#define AM33XX_DDR_DATA1_IOCTRL 0x1444
+
+ /* DEV Feature register to identify AM33XX features */
+ #define AM33XX_DEV_FEATURE 0x604
+ #define AM33XX_SGX_SHIFT 29
+ #define AM33XX_SGX_MASK (1 << AM33XX_SGX_SHIFT)
+
/* CONTROL OMAP STATUS register to identify OMAP3 features */
#define OMAP3_CONTROL_OMAP_STATUS 0x044c
diff --cc arch/arm/mach-omap2/io.c
Simple merge
diff --cc arch/arm/mach-omap2/omap-hotplug.c
index 539082a5a991fe017a19a6948211ddf5449f16bf,3a7f50c3d1e2bf14b38db8de364a1ecb357e056a..8a15f77d4f94f9acae8ff6e82094f973d05c6899
/*
* Enter into low power state
*/
- omap4_mpuss_hotplug_cpu(cpu, PWRDM_FUNC_PWRST_OFF);
+ if (soc_is_dra7xx())
- omap4_hotplug_cpu(cpu, PWRDM_POWER_RET);
++ omap4_mpuss_hotplug_cpu(cpu, PWRDM_FUNC_PWRST_CSWR);
+ else
- omap4_hotplug_cpu(cpu, PWRDM_POWER_OFF);
++ omap4_mpuss_hotplug_cpu(cpu, PWRDM_FUNC_PWRST_OFF);
if (omap_secure_apis_support())
boot_cpu = omap_read_auxcoreboot0();
index 8380b3240a61ae7a531e0228cc63585af01e205f,a257d0966be26c63146734d0042c4e4274cb9ba0..d46a2693efbd29ab4bc297b8a9fe48a81bbfc899
{
struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
- __raw_writel(addr, pm_info->wkup_sar_addr);
+ /*
+ * XXX should not be writing directly into another IP block's
+ * address space!
+ */
+ if (pm_info->wkup_sar_addr)
+ __raw_writel(addr, pm_info->wkup_sar_addr);
}
-/*
- * Set the CPUx powerdomain's previous power state
- */
-static inline void set_cpu_next_pwrst(unsigned int cpu_id,
- unsigned int power_state)
-{
- struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
-
- pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
-}
-
-/*
- * Read CPU's previous power state
- */
-static inline unsigned int read_cpu_prev_pwrst(unsigned int cpu_id)
-{
- struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
-
- return pwrdm_read_prev_pwrst(pm_info->pwrdm);
-}
-
-/*
- * Clear the CPUx powerdomain's previous power state
- */
-static inline void clear_cpu_prev_pwrst(unsigned int cpu_id)
-{
- struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
-
- pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
-}
-
/*
* Store the SCU power status value to scratchpad memory
*/
struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
u32 scu_pwr_st;
- switch (cpu_state) {
- case PWRDM_POWER_RET:
+ if (!pm_info->scu_sar_addr)
+ return;
+
+ switch (fpwrst) {
+ case PWRDM_FUNC_PWRST_CSWR:
+ case PWRDM_FUNC_PWRST_OSWR: /* XXX is this accurate? */
scu_pwr_st = SCU_PM_DORMANT;
break;
- case PWRDM_POWER_OFF:
+ case PWRDM_FUNC_PWRST_OFF:
scu_pwr_st = SCU_PM_POWEROFF;
break;
- case PWRDM_POWER_ON:
- case PWRDM_POWER_INACTIVE:
+ case PWRDM_FUNC_PWRST_ON:
+ case PWRDM_FUNC_PWRST_INACTIVE:
default:
scu_pwr_st = SCU_PM_NORMAL;
break;
{
struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
- __raw_writel(save_state, pm_info->l2x0_sar_addr);
+ /*
+ * XXX should not be writing directly into another IP block's
+ * address space!
+ */
+ if (pm_info->l2x0_sar_addr)
+ __raw_writel(save_state, pm_info->l2x0_sar_addr);
}
/*
diff --cc arch/arm/mach-omap2/omap_hwmod.c
Simple merge
diff --cc arch/arm/mach-omap2/pm_omap4plus.c
index 0265ed2802c60ffa02e5f52ea3938790154ec4d6,929e0005d5ddf7126f0b71e6d5e5d7255a8a54ec..2389682d3d8a8e576969c5efe7363ca098d37738
* domain CSWR is not supported by hardware.
* More details can be found in OMAP4430 TRM section 4.3.4.2.
*/
- omap4_mpuss_enter_lowpower(cpu_id, PWRDM_FUNC_PWRST_OFF);
- omap4_enter_lowpower(cpu_id, cpu_suspend_state);
++ omap4_mpuss_enter_lowpower(cpu_id, cpu_suspend_state);
/* Restore next powerdomain state */
list_for_each_entry(pwrst, &pwrst_list, node) {
return -ENOMEM;
pwrst->pwrdm = pwrdm;
- pwrst->next_state = pwrdm_next_state;
+ /*
+ * XXX This should be replaced by explicit lists of
+ * powerdomains with specific powerstates to set
+ */
- pwrst->next_fpwrst = PWRDM_FUNC_PWRST_CSWR;
++ pwrst->next_fpwrst = pwrdm_next_state;
+ if (!pwrdm_supports_fpwrst(pwrdm, pwrst->next_fpwrst))
+ pwrst->next_fpwrst = PWRDM_FUNC_PWRST_ON;
list_add(&pwrst->node, &pwrst_list);
- return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
+ return WARN_ON(pwrdm_set_fpwrst(pwrst->pwrdm, pwrst->next_fpwrst));
}
/**
if (cpu_is_omap44xx() || soc_is_omap54xx())
omap4_idle_init();
- cpu_suspend_state = PWRDM_POWER_ON;
- pwrdm_next_state = PWRDM_POWER_ON;
+ if (soc_is_dra7xx()) {
- cpu_suspend_state = PWRDM_POWER_OFF;
- pwrdm_next_state = PWRDM_POWER_RET;
++ cpu_suspend_state = PWRDM_FUNC_PWRST_ON;
++ pwrdm_next_state = PWRDM_FUNC_PWRST_ON;
+ } else {
++ cpu_suspend_state = PWRDM_FUNC_PWRST_OFF;
++ pwrdm_next_state = PWRDM_FUNC_PWRST_CSWR;
+ }
+
err2:
return ret;
}
diff --cc arch/arm/mach-omap2/powerdomain.c
index 72d6ce042edc2a02da2af948f90328439403fb23,6a1f195c12baabe797e199f663f985eaab09df68..6aa4d572d1461ad9507bebb7c89e81ec6d934f62
pwrdm->voltdm.ptr = voltdm;
INIT_LIST_HEAD(&pwrdm->voltdm_node);
voltdm_add_pwrdm(voltdm, pwrdm);
- spin_lock_init(&pwrdm->_lock);
+ skip_voltdm:
++ spin_lock_init(&pwrdm->_lock);
list_add(&pwrdm->node, &pwrdm_list);
/* Initialize the powerdomain's state counter */
diff --cc arch/arm/mach-omap2/powerdomain.h
Simple merge
diff --cc arch/arm/mach-omap2/sram.c
Simple merge
diff --cc arch/arm/mach-omap2/sram.h
Simple merge
diff --cc arch/arm/mach-omap2/timer.c
Simple merge
diff --cc arch/arm/plat-omap/Kconfig
Simple merge